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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.46 98.71 97.93 100.00 94.23 99.00 99.23 93.11


Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T800 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3759505829 Sep 04 02:21:18 AM UTC 24 Sep 04 02:21:22 AM UTC 24 2033264847 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1112824482 Sep 04 02:21:15 AM UTC 24 Sep 04 02:21:28 AM UTC 24 2057675910 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3395562328 Sep 04 02:21:24 AM UTC 24 Sep 04 02:21:28 AM UTC 24 2117035368 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.25425653 Sep 04 02:21:29 AM UTC 24 Sep 04 02:21:34 AM UTC 24 2966638324 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3763100424 Sep 04 02:21:29 AM UTC 24 Sep 04 02:21:34 AM UTC 24 2214608163 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2139889658 Sep 04 02:22:38 AM UTC 24 Sep 04 02:22:42 AM UTC 24 2036128246 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2147733919 Sep 04 02:21:26 AM UTC 24 Sep 04 02:21:36 AM UTC 24 2891490525 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2174881800 Sep 04 02:21:35 AM UTC 24 Sep 04 02:21:38 AM UTC 24 6430771351 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2024649388 Sep 04 02:21:35 AM UTC 24 Sep 04 02:21:39 AM UTC 24 2032808925 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2268376630 Sep 04 02:21:23 AM UTC 24 Sep 04 02:21:42 AM UTC 24 4012054868 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3854413978 Sep 04 02:21:37 AM UTC 24 Sep 04 02:21:42 AM UTC 24 2055501175 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.497550950 Sep 04 02:21:40 AM UTC 24 Sep 04 02:21:46 AM UTC 24 2064693946 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1100115652 Sep 04 02:21:29 AM UTC 24 Sep 04 02:21:47 AM UTC 24 4628943906 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1059994646 Sep 04 02:21:39 AM UTC 24 Sep 04 02:21:48 AM UTC 24 3005567609 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1667627233 Sep 04 02:21:42 AM UTC 24 Sep 04 02:21:50 AM UTC 24 2010777700 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1959421757 Sep 04 02:21:48 AM UTC 24 Sep 04 02:21:52 AM UTC 24 4102627248 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.4143523530 Sep 04 02:21:48 AM UTC 24 Sep 04 02:21:52 AM UTC 24 2085548727 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1830744273 Sep 04 02:21:42 AM UTC 24 Sep 04 02:21:54 AM UTC 24 2068605731 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.741919038 Sep 04 02:21:30 AM UTC 24 Sep 04 02:21:54 AM UTC 24 42664587109 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.640347066 Sep 04 02:21:51 AM UTC 24 Sep 04 02:21:54 AM UTC 24 2063499978 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.457568820 Sep 04 02:21:49 AM UTC 24 Sep 04 02:21:55 AM UTC 24 2532018694 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1389744199 Sep 04 02:21:51 AM UTC 24 Sep 04 02:21:55 AM UTC 24 2226216717 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1210287137 Sep 04 02:21:53 AM UTC 24 Sep 04 02:21:56 AM UTC 24 2080775832 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1811141891 Sep 04 02:21:39 AM UTC 24 Sep 04 02:21:58 AM UTC 24 4819322815 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2391898408 Sep 04 02:21:54 AM UTC 24 Sep 04 02:22:00 AM UTC 24 6030058050 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2236314272 Sep 04 02:21:56 AM UTC 24 Sep 04 02:22:00 AM UTC 24 5967497410 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1268373086 Sep 04 02:21:54 AM UTC 24 Sep 04 02:22:02 AM UTC 24 2061442745 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2322317777 Sep 04 02:21:42 AM UTC 24 Sep 04 02:22:02 AM UTC 24 22443927787 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.724832320 Sep 04 02:21:54 AM UTC 24 Sep 04 02:22:03 AM UTC 24 2504265073 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.4154908072 Sep 04 02:21:56 AM UTC 24 Sep 04 02:22:06 AM UTC 24 2041648547 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2687718964 Sep 04 02:22:03 AM UTC 24 Sep 04 02:22:08 AM UTC 24 5281687605 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.180577952 Sep 04 02:22:02 AM UTC 24 Sep 04 02:22:09 AM UTC 24 2539863010 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3724617450 Sep 04 02:22:04 AM UTC 24 Sep 04 02:22:10 AM UTC 24 2117206574 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.308327137 Sep 04 02:22:01 AM UTC 24 Sep 04 02:22:10 AM UTC 24 2032273888 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3320090743 Sep 04 02:21:57 AM UTC 24 Sep 04 02:22:10 AM UTC 24 2089955983 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2102718777 Sep 04 02:22:07 AM UTC 24 Sep 04 02:22:11 AM UTC 24 2033710972 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1646864059 Sep 04 02:21:25 AM UTC 24 Sep 04 02:22:11 AM UTC 24 58386000337 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.444127980 Sep 04 02:22:01 AM UTC 24 Sep 04 02:22:13 AM UTC 24 2016365158 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3307721072 Sep 04 02:22:08 AM UTC 24 Sep 04 02:22:14 AM UTC 24 2060178858 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1772909327 Sep 04 02:22:09 AM UTC 24 Sep 04 02:22:15 AM UTC 24 2166422143 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1466964850 Sep 04 02:22:11 AM UTC 24 Sep 04 02:22:16 AM UTC 24 2020614015 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.946464431 Sep 04 02:22:12 AM UTC 24 Sep 04 02:22:17 AM UTC 24 2133376814 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3937615739 Sep 04 02:22:05 AM UTC 24 Sep 04 02:22:18 AM UTC 24 2065422556 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2522441475 Sep 04 02:22:16 AM UTC 24 Sep 04 02:22:20 AM UTC 24 2118026973 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.201029299 Sep 04 02:22:11 AM UTC 24 Sep 04 02:22:20 AM UTC 24 2047795992 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3450803644 Sep 04 02:22:16 AM UTC 24 Sep 04 02:22:20 AM UTC 24 2039571596 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4124263108 Sep 04 02:22:21 AM UTC 24 Sep 04 02:22:34 AM UTC 24 2042824722 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.432308646 Sep 04 02:22:11 AM UTC 24 Sep 04 02:22:21 AM UTC 24 5649490358 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.3493825298 Sep 04 02:22:01 AM UTC 24 Sep 04 02:22:21 AM UTC 24 6032728333 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1676871774 Sep 04 02:22:19 AM UTC 24 Sep 04 02:22:21 AM UTC 24 2147614560 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.675914912 Sep 04 02:22:08 AM UTC 24 Sep 04 02:22:31 AM UTC 24 5144040496 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3447417399 Sep 04 02:22:17 AM UTC 24 Sep 04 02:22:23 AM UTC 24 2121463729 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4134644911 Sep 04 02:21:15 AM UTC 24 Sep 04 02:22:23 AM UTC 24 22201770460 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.822497669 Sep 04 02:22:10 AM UTC 24 Sep 04 02:22:24 AM UTC 24 2036179400 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3420954350 Sep 04 02:22:21 AM UTC 24 Sep 04 02:22:25 AM UTC 24 2087753090 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2179690927 Sep 04 02:22:16 AM UTC 24 Sep 04 02:22:25 AM UTC 24 11250130257 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1700489318 Sep 04 02:22:20 AM UTC 24 Sep 04 02:22:25 AM UTC 24 2073029376 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2901230899 Sep 04 02:22:20 AM UTC 24 Sep 04 02:22:25 AM UTC 24 7950432520 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1167822406 Sep 04 02:22:14 AM UTC 24 Sep 04 02:22:25 AM UTC 24 2011854890 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.393638684 Sep 04 02:22:12 AM UTC 24 Sep 04 02:22:25 AM UTC 24 2117556567 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.716799845 Sep 04 02:22:21 AM UTC 24 Sep 04 02:22:26 AM UTC 24 2050494097 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1666220392 Sep 04 02:22:23 AM UTC 24 Sep 04 02:22:27 AM UTC 24 2069108513 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3830812756 Sep 04 02:22:25 AM UTC 24 Sep 04 02:22:28 AM UTC 24 2234293395 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2805765595 Sep 04 02:22:26 AM UTC 24 Sep 04 02:22:30 AM UTC 24 2079656355 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1990971766 Sep 04 02:22:28 AM UTC 24 Sep 04 02:22:31 AM UTC 24 2054390355 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2566269286 Sep 04 02:22:26 AM UTC 24 Sep 04 02:22:35 AM UTC 24 2053823149 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1366185147 Sep 04 02:22:11 AM UTC 24 Sep 04 02:22:36 AM UTC 24 22447427360 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3389207070 Sep 04 02:21:49 AM UTC 24 Sep 04 02:22:36 AM UTC 24 10335164730 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3163602133 Sep 04 02:22:32 AM UTC 24 Sep 04 02:22:37 AM UTC 24 2454661617 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3202588005 Sep 04 02:22:30 AM UTC 24 Sep 04 02:22:37 AM UTC 24 2041240555 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.618474703 Sep 04 02:22:26 AM UTC 24 Sep 04 02:22:37 AM UTC 24 2086789448 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.522539850 Sep 04 02:22:25 AM UTC 24 Sep 04 02:22:38 AM UTC 24 2014861616 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2554029360 Sep 04 02:22:25 AM UTC 24 Sep 04 02:22:38 AM UTC 24 2041742598 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1340114956 Sep 04 02:22:31 AM UTC 24 Sep 04 02:22:40 AM UTC 24 2044461690 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1527772059 Sep 04 02:22:33 AM UTC 24 Sep 04 02:22:41 AM UTC 24 2014070575 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.919906693 Sep 04 02:22:38 AM UTC 24 Sep 04 02:22:42 AM UTC 24 5005090022 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.501992602 Sep 04 02:22:35 AM UTC 24 Sep 04 02:22:44 AM UTC 24 2066883669 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.815005175 Sep 04 02:22:37 AM UTC 24 Sep 04 02:22:44 AM UTC 24 2079743608 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2222560919 Sep 04 02:22:39 AM UTC 24 Sep 04 02:22:45 AM UTC 24 2089620647 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3544322505 Sep 04 02:22:38 AM UTC 24 Sep 04 02:22:46 AM UTC 24 2055596856 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.638355352 Sep 04 02:22:38 AM UTC 24 Sep 04 02:22:46 AM UTC 24 2052765731 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.122314984 Sep 04 02:22:39 AM UTC 24 Sep 04 02:22:46 AM UTC 24 2098977096 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.422548914 Sep 04 02:22:43 AM UTC 24 Sep 04 02:22:47 AM UTC 24 2080705489 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3981487999 Sep 04 02:22:24 AM UTC 24 Sep 04 02:22:47 AM UTC 24 4750168193 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1297409742 Sep 04 02:22:43 AM UTC 24 Sep 04 02:22:47 AM UTC 24 2093405170 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.426061852 Sep 04 02:22:40 AM UTC 24 Sep 04 02:22:49 AM UTC 24 2013055279 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.108269899 Sep 04 02:22:26 AM UTC 24 Sep 04 02:22:50 AM UTC 24 7703460519 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2405003753 Sep 04 02:22:45 AM UTC 24 Sep 04 02:22:50 AM UTC 24 2246581909 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2161459167 Sep 04 02:22:46 AM UTC 24 Sep 04 02:22:50 AM UTC 24 2018970002 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2578058042 Sep 04 02:22:47 AM UTC 24 Sep 04 02:22:50 AM UTC 24 2339911153 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2085547263 Sep 04 02:22:31 AM UTC 24 Sep 04 02:22:50 AM UTC 24 4570044239 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.700140280 Sep 04 02:22:47 AM UTC 24 Sep 04 02:22:51 AM UTC 24 2153602319 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2487758618 Sep 04 02:22:47 AM UTC 24 Sep 04 02:22:52 AM UTC 24 2512081871 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2564014241 Sep 04 02:22:51 AM UTC 24 Sep 04 02:22:54 AM UTC 24 2336612994 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.895453991 Sep 04 02:22:49 AM UTC 24 Sep 04 02:22:55 AM UTC 24 2012831617 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2671045721 Sep 04 02:22:51 AM UTC 24 Sep 04 02:22:56 AM UTC 24 2076956634 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3273610021 Sep 04 02:22:52 AM UTC 24 Sep 04 02:22:56 AM UTC 24 2150577230 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3320240592 Sep 04 02:22:36 AM UTC 24 Sep 04 02:22:58 AM UTC 24 8887186983 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2525000561 Sep 04 02:21:59 AM UTC 24 Sep 04 02:22:58 AM UTC 24 42385706593 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3758178769 Sep 04 02:22:32 AM UTC 24 Sep 04 02:22:58 AM UTC 24 22509659483 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3747723169 Sep 04 02:22:52 AM UTC 24 Sep 04 02:22:58 AM UTC 24 2077781045 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.4230026163 Sep 04 02:22:51 AM UTC 24 Sep 04 02:22:58 AM UTC 24 2011264884 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1937380955 Sep 04 02:22:50 AM UTC 24 Sep 04 02:22:59 AM UTC 24 2035578996 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.191832060 Sep 04 02:22:57 AM UTC 24 Sep 04 02:23:00 AM UTC 24 2042474579 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3875660319 Sep 04 02:22:57 AM UTC 24 Sep 04 02:23:01 AM UTC 24 2085365065 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3144756506 Sep 04 02:22:39 AM UTC 24 Sep 04 02:23:01 AM UTC 24 43174733263 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3629509294 Sep 04 02:22:52 AM UTC 24 Sep 04 02:23:01 AM UTC 24 5156310906 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2520549151 Sep 04 02:22:59 AM UTC 24 Sep 04 02:23:03 AM UTC 24 2026958305 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2137670732 Sep 04 02:22:58 AM UTC 24 Sep 04 02:23:03 AM UTC 24 2168389007 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.633902657 Sep 04 02:22:43 AM UTC 24 Sep 04 02:23:04 AM UTC 24 8568654639 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1563494599 Sep 04 02:23:01 AM UTC 24 Sep 04 02:23:04 AM UTC 24 2060304780 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.357917805 Sep 04 02:22:54 AM UTC 24 Sep 04 02:23:05 AM UTC 24 2070149571 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3768953516 Sep 04 02:22:21 AM UTC 24 Sep 04 02:23:05 AM UTC 24 42801145125 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4100346231 Sep 04 02:22:47 AM UTC 24 Sep 04 02:23:05 AM UTC 24 4878803515 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.445128203 Sep 04 02:23:01 AM UTC 24 Sep 04 02:23:06 AM UTC 24 2041523488 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1815256472 Sep 04 02:23:03 AM UTC 24 Sep 04 02:23:07 AM UTC 24 2029433160 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1973740877 Sep 04 02:23:02 AM UTC 24 Sep 04 02:23:07 AM UTC 24 2037661347 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2300395695 Sep 04 02:22:57 AM UTC 24 Sep 04 02:23:07 AM UTC 24 2087505221 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.815570355 Sep 04 02:23:03 AM UTC 24 Sep 04 02:23:07 AM UTC 24 2046830999 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1629496028 Sep 04 02:22:45 AM UTC 24 Sep 04 02:23:07 AM UTC 24 22526276757 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.353080783 Sep 04 02:23:00 AM UTC 24 Sep 04 02:23:08 AM UTC 24 2030933146 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3226994284 Sep 04 02:23:03 AM UTC 24 Sep 04 02:23:08 AM UTC 24 2028624753 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3429483431 Sep 04 02:23:00 AM UTC 24 Sep 04 02:23:08 AM UTC 24 2059636332 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3918513596 Sep 04 02:22:57 AM UTC 24 Sep 04 02:23:08 AM UTC 24 7900364471 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3938515727 Sep 04 02:23:05 AM UTC 24 Sep 04 02:23:09 AM UTC 24 2032514210 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1945040184 Sep 04 02:23:12 AM UTC 24 Sep 04 02:23:19 AM UTC 24 2015179999 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.656521044 Sep 04 02:23:06 AM UTC 24 Sep 04 02:23:09 AM UTC 24 2045767288 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1765967962 Sep 04 02:23:02 AM UTC 24 Sep 04 02:23:10 AM UTC 24 2014542070 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.555965102 Sep 04 02:23:07 AM UTC 24 Sep 04 02:23:10 AM UTC 24 2055158922 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.4056094132 Sep 04 02:21:53 AM UTC 24 Sep 04 02:23:11 AM UTC 24 22215354726 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2590503832 Sep 04 02:23:07 AM UTC 24 Sep 04 02:23:11 AM UTC 24 2053139621 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4069510648 Sep 04 02:23:06 AM UTC 24 Sep 04 02:23:11 AM UTC 24 2019151985 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3678730720 Sep 04 02:23:09 AM UTC 24 Sep 04 02:23:11 AM UTC 24 2076570810 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2206726509 Sep 04 02:23:09 AM UTC 24 Sep 04 02:23:11 AM UTC 24 2113164287 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2374753961 Sep 04 02:22:51 AM UTC 24 Sep 04 02:23:12 AM UTC 24 4509772079 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.172316639 Sep 04 02:23:09 AM UTC 24 Sep 04 02:23:16 AM UTC 24 2009835935 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1848322093 Sep 04 02:23:10 AM UTC 24 Sep 04 02:23:19 AM UTC 24 2007661025 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3287682780 Sep 04 02:23:02 AM UTC 24 Sep 04 02:23:12 AM UTC 24 2011451218 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1444932003 Sep 04 02:23:07 AM UTC 24 Sep 04 02:23:12 AM UTC 24 2019429430 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3903710930 Sep 04 02:23:09 AM UTC 24 Sep 04 02:23:12 AM UTC 24 2048754302 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1950577358 Sep 04 02:23:05 AM UTC 24 Sep 04 02:23:12 AM UTC 24 2011614761 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2373311825 Sep 04 02:23:05 AM UTC 24 Sep 04 02:23:13 AM UTC 24 2010290831 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3047294864 Sep 04 02:23:09 AM UTC 24 Sep 04 02:23:13 AM UTC 24 2033642336 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2482272694 Sep 04 02:23:06 AM UTC 24 Sep 04 02:23:13 AM UTC 24 2016343695 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3115388544 Sep 04 02:23:10 AM UTC 24 Sep 04 02:23:13 AM UTC 24 2028480775 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2260885329 Sep 04 02:23:10 AM UTC 24 Sep 04 02:23:13 AM UTC 24 2049398407 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4183620182 Sep 04 02:23:10 AM UTC 24 Sep 04 02:23:13 AM UTC 24 2033261691 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1299027732 Sep 04 02:23:09 AM UTC 24 Sep 04 02:23:14 AM UTC 24 2022877256 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3999001166 Sep 04 02:22:12 AM UTC 24 Sep 04 02:23:14 AM UTC 24 22201673593 ps
T901 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3950729381 Sep 04 02:23:12 AM UTC 24 Sep 04 02:23:15 AM UTC 24 2034604983 ps
T902 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2545849968 Sep 04 02:23:11 AM UTC 24 Sep 04 02:23:16 AM UTC 24 2023859681 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1476771499 Sep 04 02:22:58 AM UTC 24 Sep 04 02:23:17 AM UTC 24 22486531980 ps
T903 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1530847252 Sep 04 02:22:07 AM UTC 24 Sep 04 02:23:21 AM UTC 24 22211073980 ps
T904 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.4089152173 Sep 04 02:22:28 AM UTC 24 Sep 04 02:23:24 AM UTC 24 22216226179 ps
T905 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.493273340 Sep 04 02:21:54 AM UTC 24 Sep 04 02:23:25 AM UTC 24 38836373998 ps
T906 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.355186199 Sep 04 02:22:51 AM UTC 24 Sep 04 02:23:26 AM UTC 24 42798226764 ps
T907 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1020109382 Sep 04 02:22:48 AM UTC 24 Sep 04 02:23:26 AM UTC 24 42918020799 ps
T908 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2402635384 Sep 04 02:23:00 AM UTC 24 Sep 04 02:23:27 AM UTC 24 7934891456 ps
T909 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3180964365 Sep 04 02:22:25 AM UTC 24 Sep 04 02:23:39 AM UTC 24 22212854356 ps
T910 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1046010027 Sep 04 02:22:18 AM UTC 24 Sep 04 02:23:42 AM UTC 24 22171602525 ps
T911 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2820585107 Sep 04 02:22:02 AM UTC 24 Sep 04 02:23:45 AM UTC 24 40487754176 ps
T912 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3791086559 Sep 04 02:22:38 AM UTC 24 Sep 04 02:23:48 AM UTC 24 22188397002 ps
T913 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1586975309 Sep 04 02:21:48 AM UTC 24 Sep 04 02:23:52 AM UTC 24 38394609699 ps
T914 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.195029604 Sep 04 02:22:55 AM UTC 24 Sep 04 02:24:00 AM UTC 24 22194069321 ps
T915 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2634977352 Sep 04 02:21:37 AM UTC 24 Sep 04 02:25:00 AM UTC 24 77252974643 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.558654212
Short name T7
Test name
Test status
Simulation time 2561136955 ps
CPU time 1.93 seconds
Started Sep 04 02:13:11 AM UTC 24
Finished Sep 04 02:13:13 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558654212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.558654212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.4127630511
Short name T52
Test name
Test status
Simulation time 41296505570 ps
CPU time 98.52 seconds
Started Sep 04 02:13:07 AM UTC 24
Finished Sep 04 02:14:48 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127630511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.4127630511
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1674764404
Short name T10
Test name
Test status
Simulation time 3447802161 ps
CPU time 12.09 seconds
Started Sep 04 02:13:20 AM UTC 24
Finished Sep 04 02:13:34 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674764404 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.1674764404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.490027011
Short name T33
Test name
Test status
Simulation time 81475326352 ps
CPU time 41.55 seconds
Started Sep 04 02:13:14 AM UTC 24
Finished Sep 04 02:13:57 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490027011 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.490027011
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2383394516
Short name T24
Test name
Test status
Simulation time 2542298669 ps
CPU time 2.38 seconds
Started Sep 04 02:13:11 AM UTC 24
Finished Sep 04 02:13:14 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383394516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.2383394516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.3528233796
Short name T83
Test name
Test status
Simulation time 6713884529 ps
CPU time 8.15 seconds
Started Sep 04 02:13:37 AM UTC 24
Finished Sep 04 02:13:46 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528233796 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.3528233796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3509799591
Short name T43
Test name
Test status
Simulation time 12805415124 ps
CPU time 12.27 seconds
Started Sep 04 02:13:57 AM UTC 24
Finished Sep 04 02:14:11 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509799591 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.3509799591
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3679981955
Short name T26
Test name
Test status
Simulation time 7528227021 ps
CPU time 5.02 seconds
Started Sep 04 02:13:08 AM UTC 24
Finished Sep 04 02:13:14 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679981955 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.3679981955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.741919038
Short name T317
Test name
Test status
Simulation time 42664587109 ps
CPU time 21.89 seconds
Started Sep 04 02:21:30 AM UTC 24
Finished Sep 04 02:21:54 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741919038 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.741919038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1128574318
Short name T115
Test name
Test status
Simulation time 50101933182 ps
CPU time 18.1 seconds
Started Sep 04 02:16:09 AM UTC 24
Finished Sep 04 02:16:28 AM UTC 24
Peak memory 220856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1128574318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.1128574318
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3070226194
Short name T178
Test name
Test status
Simulation time 35363800260 ps
CPU time 10.44 seconds
Started Sep 04 02:18:53 AM UTC 24
Finished Sep 04 02:19:05 AM UTC 24
Peak memory 220536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3070226194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.3070226194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.3376853738
Short name T194
Test name
Test status
Simulation time 12971582904 ps
CPU time 38.95 seconds
Started Sep 04 02:15:48 AM UTC 24
Finished Sep 04 02:16:28 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376853738 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.3376853738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3978077463
Short name T289
Test name
Test status
Simulation time 56632226346 ps
CPU time 36.59 seconds
Started Sep 04 02:14:16 AM UTC 24
Finished Sep 04 02:14:54 AM UTC 24
Peak memory 210380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978077463 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.3978077463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3936376147
Short name T91
Test name
Test status
Simulation time 12739826142 ps
CPU time 11.42 seconds
Started Sep 04 02:13:15 AM UTC 24
Finished Sep 04 02:13:28 AM UTC 24
Peak memory 226692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3936376147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.3936376147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.2032200737
Short name T268
Test name
Test status
Simulation time 154607082887 ps
CPU time 116.68 seconds
Started Sep 04 02:13:06 AM UTC 24
Finished Sep 04 02:15:05 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032200737 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.2032200737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4269792235
Short name T73
Test name
Test status
Simulation time 841267830693 ps
CPU time 19.2 seconds
Started Sep 04 02:13:35 AM UTC 24
Finished Sep 04 02:13:55 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269792235 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.4269792235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1040697372
Short name T271
Test name
Test status
Simulation time 46507561773 ps
CPU time 37.92 seconds
Started Sep 04 02:14:48 AM UTC 24
Finished Sep 04 02:15:27 AM UTC 24
Peak memory 210524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040697372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_with_pre_cond.1040697372
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.1231217555
Short name T203
Test name
Test status
Simulation time 2878810965 ps
CPU time 2.35 seconds
Started Sep 04 02:15:20 AM UTC 24
Finished Sep 04 02:15:23 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231217555 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.1231217555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.2944511846
Short name T148
Test name
Test status
Simulation time 22052277530 ps
CPU time 18.82 seconds
Started Sep 04 02:13:15 AM UTC 24
Finished Sep 04 02:13:35 AM UTC 24
Peak memory 240348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944511846 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2944511846
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3419147377
Short name T288
Test name
Test status
Simulation time 64960405890 ps
CPU time 93.54 seconds
Started Sep 04 02:15:13 AM UTC 24
Finished Sep 04 02:16:49 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419147377 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.3419147377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.428816323
Short name T305
Test name
Test status
Simulation time 139361194735 ps
CPU time 197.65 seconds
Started Sep 04 02:14:54 AM UTC 24
Finished Sep 04 02:18:14 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428816323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.428816323
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.328624639
Short name T46
Test name
Test status
Simulation time 4338540901 ps
CPU time 8.5 seconds
Started Sep 04 02:14:21 AM UTC 24
Finished Sep 04 02:14:31 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328624639 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.328624639
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.25425653
Short name T36
Test name
Test status
Simulation time 2966638324 ps
CPU time 2.93 seconds
Started Sep 04 02:21:29 AM UTC 24
Finished Sep 04 02:21:34 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25425653 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.25425653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1274437426
Short name T112
Test name
Test status
Simulation time 3429413989 ps
CPU time 9.47 seconds
Started Sep 04 02:15:02 AM UTC 24
Finished Sep 04 02:15:13 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274437426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1274437426
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.911929460
Short name T385
Test name
Test status
Simulation time 212110989782 ps
CPU time 290.6 seconds
Started Sep 04 02:13:25 AM UTC 24
Finished Sep 04 02:18:20 AM UTC 24
Peak memory 213156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911929460 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.911929460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2067485096
Short name T90
Test name
Test status
Simulation time 2530632560 ps
CPU time 4.11 seconds
Started Sep 04 02:13:19 AM UTC 24
Finished Sep 04 02:13:24 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067485096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.2067485096
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.373042047
Short name T381
Test name
Test status
Simulation time 55881386323 ps
CPU time 187.83 seconds
Started Sep 04 02:13:47 AM UTC 24
Finished Sep 04 02:16:58 AM UTC 24
Peak memory 210516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373042047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.373042047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1646864059
Short name T363
Test name
Test status
Simulation time 58386000337 ps
CPU time 44.71 seconds
Started Sep 04 02:21:25 AM UTC 24
Finished Sep 04 02:22:11 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646864059 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.1646864059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.804466718
Short name T446
Test name
Test status
Simulation time 221793153736 ps
CPU time 597.58 seconds
Started Sep 04 02:16:17 AM UTC 24
Finished Sep 04 02:26:21 AM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804466718 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.804466718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.1361162717
Short name T113
Test name
Test status
Simulation time 5094795290 ps
CPU time 5.83 seconds
Started Sep 04 02:16:21 AM UTC 24
Finished Sep 04 02:16:28 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361162717 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.1361162717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.51974649
Short name T380
Test name
Test status
Simulation time 61462948318 ps
CPU time 163.24 seconds
Started Sep 04 02:14:00 AM UTC 24
Finished Sep 04 02:16:46 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51974649 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.51974649
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.899706296
Short name T168
Test name
Test status
Simulation time 681225288165 ps
CPU time 2002.82 seconds
Started Sep 04 02:18:11 AM UTC 24
Finished Sep 04 02:51:54 AM UTC 24
Peak memory 212752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899706296 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.899706296
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.453009744
Short name T54
Test name
Test status
Simulation time 2705827297 ps
CPU time 1.46 seconds
Started Sep 04 02:15:03 AM UTC 24
Finished Sep 04 02:15:06 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453009744 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.453009744
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.4130898885
Short name T179
Test name
Test status
Simulation time 3829113922 ps
CPU time 7.72 seconds
Started Sep 04 02:17:39 AM UTC 24
Finished Sep 04 02:17:48 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130898885 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.4130898885
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3973706608
Short name T25
Test name
Test status
Simulation time 2511004745 ps
CPU time 9.9 seconds
Started Sep 04 02:13:04 AM UTC 24
Finished Sep 04 02:13:15 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973706608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3973706608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2835014367
Short name T192
Test name
Test status
Simulation time 4416108118 ps
CPU time 3.13 seconds
Started Sep 04 02:15:54 AM UTC 24
Finished Sep 04 02:15:58 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835014367 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.2835014367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.1702032031
Short name T248
Test name
Test status
Simulation time 4474115785 ps
CPU time 6.41 seconds
Started Sep 04 02:17:14 AM UTC 24
Finished Sep 04 02:17:22 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702032031 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.1702032031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.80690343
Short name T189
Test name
Test status
Simulation time 68029919828 ps
CPU time 43.33 seconds
Started Sep 04 02:17:06 AM UTC 24
Finished Sep 04 02:17:51 AM UTC 24
Peak memory 210316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80690343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.80690343
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1100115652
Short name T18
Test name
Test status
Simulation time 4628943906 ps
CPU time 16.51 seconds
Started Sep 04 02:21:29 AM UTC 24
Finished Sep 04 02:21:47 AM UTC 24
Peak memory 211068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100115652 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.1100115652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.464841805
Short name T294
Test name
Test status
Simulation time 179151270078 ps
CPU time 104.96 seconds
Started Sep 04 02:13:55 AM UTC 24
Finished Sep 04 02:15:42 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464841805 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.464841805
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.891000620
Short name T415
Test name
Test status
Simulation time 56561737787 ps
CPU time 138.32 seconds
Started Sep 04 02:19:40 AM UTC 24
Finished Sep 04 02:22:01 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891000620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_with_pre_cond.891000620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.232302008
Short name T56
Test name
Test status
Simulation time 50776933407 ps
CPU time 36.54 seconds
Started Sep 04 02:14:16 AM UTC 24
Finished Sep 04 02:14:54 AM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232302008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.232302008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1370891212
Short name T63
Test name
Test status
Simulation time 2931809183 ps
CPU time 10.92 seconds
Started Sep 04 02:13:55 AM UTC 24
Finished Sep 04 02:14:07 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370891212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1370891212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3023123000
Short name T108
Test name
Test status
Simulation time 2012605274 ps
CPU time 8.94 seconds
Started Sep 04 02:13:38 AM UTC 24
Finished Sep 04 02:13:48 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023123000 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.3023123000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1570642321
Short name T398
Test name
Test status
Simulation time 189305127717 ps
CPU time 464.62 seconds
Started Sep 04 02:19:32 AM UTC 24
Finished Sep 04 02:27:22 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570642321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_with_pre_cond.1570642321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1915197595
Short name T29
Test name
Test status
Simulation time 61097947035 ps
CPU time 46.42 seconds
Started Sep 04 02:13:15 AM UTC 24
Finished Sep 04 02:14:03 AM UTC 24
Peak memory 210452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915197595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.1915197595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.4160386988
Short name T308
Test name
Test status
Simulation time 90846180092 ps
CPU time 234.51 seconds
Started Sep 04 02:19:11 AM UTC 24
Finished Sep 04 02:23:09 AM UTC 24
Peak memory 210488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160386988 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.4160386988
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.393638684
Short name T328
Test name
Test status
Simulation time 2117556567 ps
CPU time 11.85 seconds
Started Sep 04 02:22:12 AM UTC 24
Finished Sep 04 02:22:25 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393638684 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.393638684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1662908657
Short name T74
Test name
Test status
Simulation time 7425509696 ps
CPU time 4.12 seconds
Started Sep 04 02:13:55 AM UTC 24
Finished Sep 04 02:14:00 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662908657 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.1662908657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2504430699
Short name T273
Test name
Test status
Simulation time 60731865362 ps
CPU time 39.13 seconds
Started Sep 04 02:15:26 AM UTC 24
Finished Sep 04 02:16:07 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504430699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.2504430699
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.4262545853
Short name T397
Test name
Test status
Simulation time 92492273407 ps
CPU time 87.34 seconds
Started Sep 04 02:20:46 AM UTC 24
Finished Sep 04 02:22:15 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262545853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_with_pre_cond.4262545853
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3064189143
Short name T276
Test name
Test status
Simulation time 2576880043 ps
CPU time 1.44 seconds
Started Sep 04 02:14:19 AM UTC 24
Finished Sep 04 02:14:21 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064189143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3064189143
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.164629266
Short name T396
Test name
Test status
Simulation time 66592490105 ps
CPU time 65.51 seconds
Started Sep 04 02:19:47 AM UTC 24
Finished Sep 04 02:20:54 AM UTC 24
Peak memory 210648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164629266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.164629266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.881888780
Short name T71
Test name
Test status
Simulation time 41559164374 ps
CPU time 118.47 seconds
Started Sep 04 02:13:15 AM UTC 24
Finished Sep 04 02:15:16 AM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881888780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.881888780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.4089152173
Short name T904
Test name
Test status
Simulation time 22216226179 ps
CPU time 54.74 seconds
Started Sep 04 02:22:28 AM UTC 24
Finished Sep 04 02:23:24 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089152173 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.4089152173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.1551252899
Short name T164
Test name
Test status
Simulation time 14459711784 ps
CPU time 42.74 seconds
Started Sep 04 02:13:15 AM UTC 24
Finished Sep 04 02:14:00 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551252899 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.1551252899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.408924200
Short name T96
Test name
Test status
Simulation time 52277626929 ps
CPU time 9.67 seconds
Started Sep 04 02:14:57 AM UTC 24
Finished Sep 04 02:15:08 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408924200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_with_pre_cond.408924200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.3238389784
Short name T383
Test name
Test status
Simulation time 102814772013 ps
CPU time 95.72 seconds
Started Sep 04 02:15:47 AM UTC 24
Finished Sep 04 02:17:24 AM UTC 24
Peak memory 210116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238389784 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.3238389784
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3036150960
Short name T421
Test name
Test status
Simulation time 38531688675 ps
CPU time 31.68 seconds
Started Sep 04 02:19:32 AM UTC 24
Finished Sep 04 02:20:05 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036150960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_with_pre_cond.3036150960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.734995200
Short name T443
Test name
Test status
Simulation time 173608428656 ps
CPU time 467.86 seconds
Started Sep 04 02:20:06 AM UTC 24
Finished Sep 04 02:27:59 AM UTC 24
Peak memory 213240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734995200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_with_pre_cond.734995200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2284202886
Short name T152
Test name
Test status
Simulation time 817991519536 ps
CPU time 8.66 seconds
Started Sep 04 02:16:30 AM UTC 24
Finished Sep 04 02:16:40 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284202886 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.2284202886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.3493825298
Short name T366
Test name
Test status
Simulation time 6032728333 ps
CPU time 18.73 seconds
Started Sep 04 02:22:01 AM UTC 24
Finished Sep 04 02:22:21 AM UTC 24
Peak memory 211064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493825298 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.3493825298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.4294240272
Short name T160
Test name
Test status
Simulation time 2174615829168 ps
CPU time 413.91 seconds
Started Sep 04 02:15:07 AM UTC 24
Finished Sep 04 02:22:06 AM UTC 24
Peak memory 209896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294240272 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.4294240272
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1712009633
Short name T279
Test name
Test status
Simulation time 65594797645 ps
CPU time 192.25 seconds
Started Sep 04 02:13:25 AM UTC 24
Finished Sep 04 02:16:40 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712009633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.1712009633
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3271221664
Short name T379
Test name
Test status
Simulation time 108380392983 ps
CPU time 62.6 seconds
Started Sep 04 02:16:07 AM UTC 24
Finished Sep 04 02:17:12 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271221664 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.3271221664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.760661730
Short name T270
Test name
Test status
Simulation time 54669055502 ps
CPU time 40.85 seconds
Started Sep 04 02:16:07 AM UTC 24
Finished Sep 04 02:16:50 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760661730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_with_pre_cond.760661730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.1964914873
Short name T432
Test name
Test status
Simulation time 107710808188 ps
CPU time 71.03 seconds
Started Sep 04 02:16:42 AM UTC 24
Finished Sep 04 02:17:54 AM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964914873 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.1964914873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3424477886
Short name T413
Test name
Test status
Simulation time 81566812624 ps
CPU time 250.8 seconds
Started Sep 04 02:17:14 AM UTC 24
Finished Sep 04 02:21:28 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424477886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_with_pre_cond.3424477886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1982689176
Short name T114
Test name
Test status
Simulation time 111045545058 ps
CPU time 68.3 seconds
Started Sep 04 02:17:51 AM UTC 24
Finished Sep 04 02:19:00 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982689176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_with_pre_cond.1982689176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.302371780
Short name T130
Test name
Test status
Simulation time 47378091408 ps
CPU time 36.9 seconds
Started Sep 04 02:17:59 AM UTC 24
Finished Sep 04 02:18:37 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302371780 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.302371780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3428254959
Short name T388
Test name
Test status
Simulation time 49697780516 ps
CPU time 145.47 seconds
Started Sep 04 02:18:31 AM UTC 24
Finished Sep 04 02:20:59 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428254959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_with_pre_cond.3428254959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2233833953
Short name T425
Test name
Test status
Simulation time 114269207108 ps
CPU time 72.78 seconds
Started Sep 04 02:19:24 AM UTC 24
Finished Sep 04 02:20:39 AM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233833953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.2233833953
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1818956905
Short name T420
Test name
Test status
Simulation time 119854786700 ps
CPU time 338.95 seconds
Started Sep 04 02:19:32 AM UTC 24
Finished Sep 04 02:25:15 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818956905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with_pre_cond.1818956905
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2885866189
Short name T429
Test name
Test status
Simulation time 72011574562 ps
CPU time 232.51 seconds
Started Sep 04 02:19:37 AM UTC 24
Finished Sep 04 02:23:33 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885866189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_with_pre_cond.2885866189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1634231527
Short name T431
Test name
Test status
Simulation time 47477363539 ps
CPU time 39.51 seconds
Started Sep 04 02:19:40 AM UTC 24
Finished Sep 04 02:20:21 AM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634231527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.1634231527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1015101026
Short name T430
Test name
Test status
Simulation time 76124238065 ps
CPU time 65.23 seconds
Started Sep 04 02:20:07 AM UTC 24
Finished Sep 04 02:21:14 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015101026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.1015101026
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1534155698
Short name T399
Test name
Test status
Simulation time 96204520058 ps
CPU time 280.76 seconds
Started Sep 04 02:20:18 AM UTC 24
Finished Sep 04 02:25:03 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534155698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.1534155698
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1810078022
Short name T408
Test name
Test status
Simulation time 67754340419 ps
CPU time 101.6 seconds
Started Sep 04 02:20:23 AM UTC 24
Finished Sep 04 02:22:06 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810078022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.1810078022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3028993503
Short name T442
Test name
Test status
Simulation time 22081418731 ps
CPU time 81.33 seconds
Started Sep 04 02:20:43 AM UTC 24
Finished Sep 04 02:22:07 AM UTC 24
Peak memory 210452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028993503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.3028993503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1112824482
Short name T34
Test name
Test status
Simulation time 2057675910 ps
CPU time 12.2 seconds
Started Sep 04 02:21:15 AM UTC 24
Finished Sep 04 02:21:28 AM UTC 24
Peak memory 211264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112824482 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.1112824482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1841118168
Short name T67
Test name
Test status
Simulation time 2019480514 ps
CPU time 4.69 seconds
Started Sep 04 02:13:09 AM UTC 24
Finished Sep 04 02:13:15 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841118168 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.1841118168
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.1104628761
Short name T6
Test name
Test status
Simulation time 4026801872 ps
CPU time 8.01 seconds
Started Sep 04 02:13:14 AM UTC 24
Finished Sep 04 02:13:23 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104628761 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.1104628761
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.563940514
Short name T298
Test name
Test status
Simulation time 65905822529 ps
CPU time 51.4 seconds
Started Sep 04 02:20:55 AM UTC 24
Finished Sep 04 02:21:48 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563940514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_with_pre_cond.563940514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2147733919
Short name T38
Test name
Test status
Simulation time 2891490525 ps
CPU time 8.98 seconds
Started Sep 04 02:21:26 AM UTC 24
Finished Sep 04 02:21:36 AM UTC 24
Peak memory 211248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147733919 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.2147733919
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2268376630
Short name T360
Test name
Test status
Simulation time 4012054868 ps
CPU time 17.61 seconds
Started Sep 04 02:21:23 AM UTC 24
Finished Sep 04 02:21:42 AM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268376630 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.2268376630
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3763100424
Short name T37
Test name
Test status
Simulation time 2214608163 ps
CPU time 3.35 seconds
Started Sep 04 02:21:29 AM UTC 24
Finished Sep 04 02:21:34 AM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3763100424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3763100424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3395562328
Short name T35
Test name
Test status
Simulation time 2117035368 ps
CPU time 3.53 seconds
Started Sep 04 02:21:24 AM UTC 24
Finished Sep 04 02:21:28 AM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395562328 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.3395562328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3759505829
Short name T800
Test name
Test status
Simulation time 2033264847 ps
CPU time 3.44 seconds
Started Sep 04 02:21:18 AM UTC 24
Finished Sep 04 02:21:22 AM UTC 24
Peak memory 210824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759505829 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.3759505829
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4134644911
Short name T319
Test name
Test status
Simulation time 22201770460 ps
CPU time 67.08 seconds
Started Sep 04 02:21:15 AM UTC 24
Finished Sep 04 02:22:23 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134644911 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.4134644911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1059994646
Short name T361
Test name
Test status
Simulation time 3005567609 ps
CPU time 7.95 seconds
Started Sep 04 02:21:39 AM UTC 24
Finished Sep 04 02:21:48 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059994646 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.1059994646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2634977352
Short name T915
Test name
Test status
Simulation time 77252974643 ps
CPU time 200.36 seconds
Started Sep 04 02:21:37 AM UTC 24
Finished Sep 04 02:25:00 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634977352 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.2634977352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2174881800
Short name T39
Test name
Test status
Simulation time 6430771351 ps
CPU time 2.78 seconds
Started Sep 04 02:21:35 AM UTC 24
Finished Sep 04 02:21:38 AM UTC 24
Peak memory 211068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174881800 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.2174881800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.497550950
Short name T326
Test name
Test status
Simulation time 2064693946 ps
CPU time 5.09 seconds
Started Sep 04 02:21:40 AM UTC 24
Finished Sep 04 02:21:46 AM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=497550950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
sysrst_ctrl_csr_mem_rw_with_rand_reset.497550950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3854413978
Short name T321
Test name
Test status
Simulation time 2055501175 ps
CPU time 4.12 seconds
Started Sep 04 02:21:37 AM UTC 24
Finished Sep 04 02:21:42 AM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854413978 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.3854413978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2024649388
Short name T802
Test name
Test status
Simulation time 2032808925 ps
CPU time 3.55 seconds
Started Sep 04 02:21:35 AM UTC 24
Finished Sep 04 02:21:39 AM UTC 24
Peak memory 210824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024649388 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.2024649388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1811141891
Short name T20
Test name
Test status
Simulation time 4819322815 ps
CPU time 18.05 seconds
Started Sep 04 02:21:39 AM UTC 24
Finished Sep 04 02:21:58 AM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811141891 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.1811141891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2805765595
Short name T824
Test name
Test status
Simulation time 2079656355 ps
CPU time 2.44 seconds
Started Sep 04 02:22:26 AM UTC 24
Finished Sep 04 02:22:30 AM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2805765595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2805765595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2566269286
Short name T367
Test name
Test status
Simulation time 2053823149 ps
CPU time 7.6 seconds
Started Sep 04 02:22:26 AM UTC 24
Finished Sep 04 02:22:35 AM UTC 24
Peak memory 210872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566269286 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.2566269286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.522539850
Short name T830
Test name
Test status
Simulation time 2014861616 ps
CPU time 11.3 seconds
Started Sep 04 02:22:25 AM UTC 24
Finished Sep 04 02:22:38 AM UTC 24
Peak memory 210752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522539850 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.522539850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.108269899
Short name T844
Test name
Test status
Simulation time 7703460519 ps
CPU time 21.88 seconds
Started Sep 04 02:22:26 AM UTC 24
Finished Sep 04 02:22:50 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108269899 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.108269899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3830812756
Short name T823
Test name
Test status
Simulation time 2234293395 ps
CPU time 2.06 seconds
Started Sep 04 02:22:25 AM UTC 24
Finished Sep 04 02:22:28 AM UTC 24
Peak memory 221416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830812756 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.3830812756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3180964365
Short name T909
Test name
Test status
Simulation time 22212854356 ps
CPU time 71.43 seconds
Started Sep 04 02:22:25 AM UTC 24
Finished Sep 04 02:23:39 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180964365 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.3180964365
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1340114956
Short name T832
Test name
Test status
Simulation time 2044461690 ps
CPU time 7.46 seconds
Started Sep 04 02:22:31 AM UTC 24
Finished Sep 04 02:22:40 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1340114956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1340114956
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3202588005
Short name T828
Test name
Test status
Simulation time 2041240555 ps
CPU time 6.31 seconds
Started Sep 04 02:22:30 AM UTC 24
Finished Sep 04 02:22:37 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202588005 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.3202588005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1990971766
Short name T825
Test name
Test status
Simulation time 2054390355 ps
CPU time 1.99 seconds
Started Sep 04 02:22:28 AM UTC 24
Finished Sep 04 02:22:31 AM UTC 24
Peak memory 210628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990971766 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.1990971766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2085547263
Short name T847
Test name
Test status
Simulation time 4570044239 ps
CPU time 18.36 seconds
Started Sep 04 02:22:31 AM UTC 24
Finished Sep 04 02:22:50 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085547263 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.2085547263
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.618474703
Short name T829
Test name
Test status
Simulation time 2086789448 ps
CPU time 9.39 seconds
Started Sep 04 02:22:26 AM UTC 24
Finished Sep 04 02:22:37 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618474703 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.618474703
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.815005175
Short name T836
Test name
Test status
Simulation time 2079743608 ps
CPU time 6.6 seconds
Started Sep 04 02:22:37 AM UTC 24
Finished Sep 04 02:22:44 AM UTC 24
Peak memory 221240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=815005175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.sysrst_ctrl_csr_mem_rw_with_rand_reset.815005175
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.501992602
Short name T835
Test name
Test status
Simulation time 2066883669 ps
CPU time 7.45 seconds
Started Sep 04 02:22:35 AM UTC 24
Finished Sep 04 02:22:44 AM UTC 24
Peak memory 210948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501992602 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.501992602
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1527772059
Short name T833
Test name
Test status
Simulation time 2014070575 ps
CPU time 6.89 seconds
Started Sep 04 02:22:33 AM UTC 24
Finished Sep 04 02:22:41 AM UTC 24
Peak memory 210680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527772059 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.1527772059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3320240592
Short name T854
Test name
Test status
Simulation time 8887186983 ps
CPU time 20.01 seconds
Started Sep 04 02:22:36 AM UTC 24
Finished Sep 04 02:22:58 AM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320240592 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.3320240592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3163602133
Short name T827
Test name
Test status
Simulation time 2454661617 ps
CPU time 3.65 seconds
Started Sep 04 02:22:32 AM UTC 24
Finished Sep 04 02:22:37 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163602133 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.3163602133
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3758178769
Short name T855
Test name
Test status
Simulation time 22509659483 ps
CPU time 24.55 seconds
Started Sep 04 02:22:32 AM UTC 24
Finished Sep 04 02:22:58 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758178769 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.3758178769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.122314984
Short name T839
Test name
Test status
Simulation time 2098977096 ps
CPU time 6.04 seconds
Started Sep 04 02:22:39 AM UTC 24
Finished Sep 04 02:22:46 AM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=122314984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.sysrst_ctrl_csr_mem_rw_with_rand_reset.122314984
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.638355352
Short name T371
Test name
Test status
Simulation time 2052765731 ps
CPU time 7.08 seconds
Started Sep 04 02:22:38 AM UTC 24
Finished Sep 04 02:22:46 AM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638355352 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.638355352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2139889658
Short name T801
Test name
Test status
Simulation time 2036128246 ps
CPU time 3.15 seconds
Started Sep 04 02:22:38 AM UTC 24
Finished Sep 04 02:22:42 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139889658 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.2139889658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.919906693
Short name T834
Test name
Test status
Simulation time 5005090022 ps
CPU time 2.73 seconds
Started Sep 04 02:22:38 AM UTC 24
Finished Sep 04 02:22:42 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919906693 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.919906693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3544322505
Short name T838
Test name
Test status
Simulation time 2055596856 ps
CPU time 6.84 seconds
Started Sep 04 02:22:38 AM UTC 24
Finished Sep 04 02:22:46 AM UTC 24
Peak memory 221272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544322505 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.3544322505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3791086559
Short name T912
Test name
Test status
Simulation time 22188397002 ps
CPU time 68.98 seconds
Started Sep 04 02:22:38 AM UTC 24
Finished Sep 04 02:23:48 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791086559 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.3791086559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1297409742
Short name T842
Test name
Test status
Simulation time 2093405170 ps
CPU time 3.52 seconds
Started Sep 04 02:22:43 AM UTC 24
Finished Sep 04 02:22:47 AM UTC 24
Peak memory 211020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1297409742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1297409742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.422548914
Short name T840
Test name
Test status
Simulation time 2080705489 ps
CPU time 3.15 seconds
Started Sep 04 02:22:43 AM UTC 24
Finished Sep 04 02:22:47 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422548914 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.422548914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.426061852
Short name T843
Test name
Test status
Simulation time 2013055279 ps
CPU time 7.52 seconds
Started Sep 04 02:22:40 AM UTC 24
Finished Sep 04 02:22:49 AM UTC 24
Peak memory 210872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426061852 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.426061852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.633902657
Short name T863
Test name
Test status
Simulation time 8568654639 ps
CPU time 19.96 seconds
Started Sep 04 02:22:43 AM UTC 24
Finished Sep 04 02:23:04 AM UTC 24
Peak memory 211264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633902657 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.633902657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2222560919
Short name T837
Test name
Test status
Simulation time 2089620647 ps
CPU time 4.64 seconds
Started Sep 04 02:22:39 AM UTC 24
Finished Sep 04 02:22:45 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222560919 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.2222560919
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3144756506
Short name T403
Test name
Test status
Simulation time 43174733263 ps
CPU time 20.69 seconds
Started Sep 04 02:22:39 AM UTC 24
Finished Sep 04 02:23:01 AM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144756506 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.3144756506
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.700140280
Short name T848
Test name
Test status
Simulation time 2153602319 ps
CPU time 3.14 seconds
Started Sep 04 02:22:47 AM UTC 24
Finished Sep 04 02:22:51 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=700140280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.sysrst_ctrl_csr_mem_rw_with_rand_reset.700140280
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2578058042
Short name T368
Test name
Test status
Simulation time 2339911153 ps
CPU time 2.17 seconds
Started Sep 04 02:22:47 AM UTC 24
Finished Sep 04 02:22:50 AM UTC 24
Peak memory 211068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578058042 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.2578058042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2161459167
Short name T846
Test name
Test status
Simulation time 2018970002 ps
CPU time 3.21 seconds
Started Sep 04 02:22:46 AM UTC 24
Finished Sep 04 02:22:50 AM UTC 24
Peak memory 211064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161459167 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.2161459167
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4100346231
Short name T867
Test name
Test status
Simulation time 4878803515 ps
CPU time 17.1 seconds
Started Sep 04 02:22:47 AM UTC 24
Finished Sep 04 02:23:05 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100346231 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.4100346231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2405003753
Short name T845
Test name
Test status
Simulation time 2246581909 ps
CPU time 4.04 seconds
Started Sep 04 02:22:45 AM UTC 24
Finished Sep 04 02:22:50 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405003753 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.2405003753
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1629496028
Short name T873
Test name
Test status
Simulation time 22526276757 ps
CPU time 21.43 seconds
Started Sep 04 02:22:45 AM UTC 24
Finished Sep 04 02:23:07 AM UTC 24
Peak memory 211164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629496028 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.1629496028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2564014241
Short name T850
Test name
Test status
Simulation time 2336612994 ps
CPU time 1.76 seconds
Started Sep 04 02:22:51 AM UTC 24
Finished Sep 04 02:22:54 AM UTC 24
Peak memory 209740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2564014241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2564014241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1937380955
Short name T369
Test name
Test status
Simulation time 2035578996 ps
CPU time 8.71 seconds
Started Sep 04 02:22:50 AM UTC 24
Finished Sep 04 02:22:59 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937380955 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.1937380955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.895453991
Short name T851
Test name
Test status
Simulation time 2012831617 ps
CPU time 5.91 seconds
Started Sep 04 02:22:49 AM UTC 24
Finished Sep 04 02:22:55 AM UTC 24
Peak memory 211000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895453991 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.895453991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2374753961
Short name T887
Test name
Test status
Simulation time 4509772079 ps
CPU time 19.47 seconds
Started Sep 04 02:22:51 AM UTC 24
Finished Sep 04 02:23:12 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374753961 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.2374753961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2487758618
Short name T849
Test name
Test status
Simulation time 2512081871 ps
CPU time 3.37 seconds
Started Sep 04 02:22:47 AM UTC 24
Finished Sep 04 02:22:52 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487758618 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.2487758618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1020109382
Short name T907
Test name
Test status
Simulation time 42918020799 ps
CPU time 36.2 seconds
Started Sep 04 02:22:48 AM UTC 24
Finished Sep 04 02:23:26 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020109382 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.1020109382
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3747723169
Short name T856
Test name
Test status
Simulation time 2077781045 ps
CPU time 4.63 seconds
Started Sep 04 02:22:52 AM UTC 24
Finished Sep 04 02:22:58 AM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3747723169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3747723169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3273610021
Short name T853
Test name
Test status
Simulation time 2150577230 ps
CPU time 3.13 seconds
Started Sep 04 02:22:52 AM UTC 24
Finished Sep 04 02:22:56 AM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273610021 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.3273610021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.4230026163
Short name T857
Test name
Test status
Simulation time 2011264884 ps
CPU time 6.05 seconds
Started Sep 04 02:22:51 AM UTC 24
Finished Sep 04 02:22:58 AM UTC 24
Peak memory 210984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230026163 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.4230026163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3629509294
Short name T860
Test name
Test status
Simulation time 5156310906 ps
CPU time 7.78 seconds
Started Sep 04 02:22:52 AM UTC 24
Finished Sep 04 02:23:01 AM UTC 24
Peak memory 211264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629509294 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.3629509294
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2671045721
Short name T852
Test name
Test status
Simulation time 2076956634 ps
CPU time 4.03 seconds
Started Sep 04 02:22:51 AM UTC 24
Finished Sep 04 02:22:56 AM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671045721 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.2671045721
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.355186199
Short name T906
Test name
Test status
Simulation time 42798226764 ps
CPU time 33.49 seconds
Started Sep 04 02:22:51 AM UTC 24
Finished Sep 04 02:23:26 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355186199 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.355186199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2300395695
Short name T871
Test name
Test status
Simulation time 2087505221 ps
CPU time 8.73 seconds
Started Sep 04 02:22:57 AM UTC 24
Finished Sep 04 02:23:07 AM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2300395695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2300395695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3875660319
Short name T859
Test name
Test status
Simulation time 2085365065 ps
CPU time 2.57 seconds
Started Sep 04 02:22:57 AM UTC 24
Finished Sep 04 02:23:01 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875660319 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.3875660319
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.191832060
Short name T858
Test name
Test status
Simulation time 2042474579 ps
CPU time 1.99 seconds
Started Sep 04 02:22:57 AM UTC 24
Finished Sep 04 02:23:00 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191832060 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.191832060
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3918513596
Short name T877
Test name
Test status
Simulation time 7900364471 ps
CPU time 10.3 seconds
Started Sep 04 02:22:57 AM UTC 24
Finished Sep 04 02:23:08 AM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918513596 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.3918513596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.357917805
Short name T865
Test name
Test status
Simulation time 2070149571 ps
CPU time 10.05 seconds
Started Sep 04 02:22:54 AM UTC 24
Finished Sep 04 02:23:05 AM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357917805 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.357917805
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.195029604
Short name T914
Test name
Test status
Simulation time 22194069321 ps
CPU time 64.1 seconds
Started Sep 04 02:22:55 AM UTC 24
Finished Sep 04 02:24:00 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195029604 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.195029604
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3429483431
Short name T876
Test name
Test status
Simulation time 2059636332 ps
CPU time 7.37 seconds
Started Sep 04 02:23:00 AM UTC 24
Finished Sep 04 02:23:08 AM UTC 24
Peak memory 211020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3429483431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3429483431
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.353080783
Short name T874
Test name
Test status
Simulation time 2030933146 ps
CPU time 7.15 seconds
Started Sep 04 02:23:00 AM UTC 24
Finished Sep 04 02:23:08 AM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353080783 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.353080783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2520549151
Short name T861
Test name
Test status
Simulation time 2026958305 ps
CPU time 2.38 seconds
Started Sep 04 02:22:59 AM UTC 24
Finished Sep 04 02:23:03 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520549151 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.2520549151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2402635384
Short name T908
Test name
Test status
Simulation time 7934891456 ps
CPU time 25.85 seconds
Started Sep 04 02:23:00 AM UTC 24
Finished Sep 04 02:23:27 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402635384 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.2402635384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2137670732
Short name T862
Test name
Test status
Simulation time 2168389007 ps
CPU time 3.62 seconds
Started Sep 04 02:22:58 AM UTC 24
Finished Sep 04 02:23:03 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137670732 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.2137670732
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1476771499
Short name T402
Test name
Test status
Simulation time 22486531980 ps
CPU time 17.87 seconds
Started Sep 04 02:22:58 AM UTC 24
Finished Sep 04 02:23:17 AM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476771499 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.1476771499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.457568820
Short name T376
Test name
Test status
Simulation time 2532018694 ps
CPU time 5.35 seconds
Started Sep 04 02:21:49 AM UTC 24
Finished Sep 04 02:21:55 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457568820 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.457568820
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1586975309
Short name T913
Test name
Test status
Simulation time 38394609699 ps
CPU time 122.5 seconds
Started Sep 04 02:21:48 AM UTC 24
Finished Sep 04 02:23:52 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586975309 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.1586975309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1959421757
Short name T375
Test name
Test status
Simulation time 4102627248 ps
CPU time 3.76 seconds
Started Sep 04 02:21:48 AM UTC 24
Finished Sep 04 02:21:52 AM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959421757 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.1959421757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.640347066
Short name T439
Test name
Test status
Simulation time 2063499978 ps
CPU time 2.1 seconds
Started Sep 04 02:21:51 AM UTC 24
Finished Sep 04 02:21:54 AM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=640347066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
sysrst_ctrl_csr_mem_rw_with_rand_reset.640347066
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.4143523530
Short name T19
Test name
Test status
Simulation time 2085548727 ps
CPU time 3.79 seconds
Started Sep 04 02:21:48 AM UTC 24
Finished Sep 04 02:21:52 AM UTC 24
Peak memory 210940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143523530 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.4143523530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1667627233
Short name T803
Test name
Test status
Simulation time 2010777700 ps
CPU time 6.53 seconds
Started Sep 04 02:21:42 AM UTC 24
Finished Sep 04 02:21:50 AM UTC 24
Peak memory 210600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667627233 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.1667627233
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3389207070
Short name T826
Test name
Test status
Simulation time 10335164730 ps
CPU time 46.01 seconds
Started Sep 04 02:21:49 AM UTC 24
Finished Sep 04 02:22:36 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389207070 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.3389207070
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1830744273
Short name T316
Test name
Test status
Simulation time 2068605731 ps
CPU time 10.1 seconds
Started Sep 04 02:21:42 AM UTC 24
Finished Sep 04 02:21:54 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830744273 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.1830744273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2322317777
Short name T318
Test name
Test status
Simulation time 22443927787 ps
CPU time 19.01 seconds
Started Sep 04 02:21:42 AM UTC 24
Finished Sep 04 02:22:02 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322317777 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.2322317777
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.445128203
Short name T868
Test name
Test status
Simulation time 2041523488 ps
CPU time 3.83 seconds
Started Sep 04 02:23:01 AM UTC 24
Finished Sep 04 02:23:06 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445128203 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.445128203
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1563494599
Short name T864
Test name
Test status
Simulation time 2060304780 ps
CPU time 2.18 seconds
Started Sep 04 02:23:01 AM UTC 24
Finished Sep 04 02:23:04 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563494599 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.1563494599
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1973740877
Short name T870
Test name
Test status
Simulation time 2037661347 ps
CPU time 3.71 seconds
Started Sep 04 02:23:02 AM UTC 24
Finished Sep 04 02:23:07 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973740877 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.1973740877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1765967962
Short name T881
Test name
Test status
Simulation time 2014542070 ps
CPU time 6.62 seconds
Started Sep 04 02:23:02 AM UTC 24
Finished Sep 04 02:23:10 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765967962 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.1765967962
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3287682780
Short name T890
Test name
Test status
Simulation time 2011451218 ps
CPU time 8.39 seconds
Started Sep 04 02:23:02 AM UTC 24
Finished Sep 04 02:23:12 AM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287682780 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.3287682780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.815570355
Short name T872
Test name
Test status
Simulation time 2046830999 ps
CPU time 2.85 seconds
Started Sep 04 02:23:03 AM UTC 24
Finished Sep 04 02:23:07 AM UTC 24
Peak memory 210852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815570355 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.815570355
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3226994284
Short name T875
Test name
Test status
Simulation time 2028624753 ps
CPU time 3.58 seconds
Started Sep 04 02:23:03 AM UTC 24
Finished Sep 04 02:23:08 AM UTC 24
Peak memory 210604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226994284 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.3226994284
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1815256472
Short name T869
Test name
Test status
Simulation time 2029433160 ps
CPU time 2.12 seconds
Started Sep 04 02:23:03 AM UTC 24
Finished Sep 04 02:23:07 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815256472 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.1815256472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2373311825
Short name T894
Test name
Test status
Simulation time 2010290831 ps
CPU time 6.92 seconds
Started Sep 04 02:23:05 AM UTC 24
Finished Sep 04 02:23:13 AM UTC 24
Peak memory 210944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373311825 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.2373311825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1950577358
Short name T893
Test name
Test status
Simulation time 2011614761 ps
CPU time 6.65 seconds
Started Sep 04 02:23:05 AM UTC 24
Finished Sep 04 02:23:12 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950577358 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.1950577358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.724832320
Short name T362
Test name
Test status
Simulation time 2504265073 ps
CPU time 7.54 seconds
Started Sep 04 02:21:54 AM UTC 24
Finished Sep 04 02:22:03 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724832320 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.724832320
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.493273340
Short name T905
Test name
Test status
Simulation time 38836373998 ps
CPU time 88.86 seconds
Started Sep 04 02:21:54 AM UTC 24
Finished Sep 04 02:23:25 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493273340 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.493273340
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2391898408
Short name T805
Test name
Test status
Simulation time 6030058050 ps
CPU time 4.38 seconds
Started Sep 04 02:21:54 AM UTC 24
Finished Sep 04 02:22:00 AM UTC 24
Peak memory 211000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391898408 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.2391898408
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.4154908072
Short name T806
Test name
Test status
Simulation time 2041648547 ps
CPU time 9.08 seconds
Started Sep 04 02:21:56 AM UTC 24
Finished Sep 04 02:22:06 AM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4154908072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_csr_mem_rw_with_rand_reset.4154908072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1268373086
Short name T372
Test name
Test status
Simulation time 2061442745 ps
CPU time 6.36 seconds
Started Sep 04 02:21:54 AM UTC 24
Finished Sep 04 02:22:02 AM UTC 24
Peak memory 210940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268373086 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.1268373086
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1210287137
Short name T804
Test name
Test status
Simulation time 2080775832 ps
CPU time 2.17 seconds
Started Sep 04 02:21:53 AM UTC 24
Finished Sep 04 02:21:56 AM UTC 24
Peak memory 210596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210287137 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.1210287137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2236314272
Short name T21
Test name
Test status
Simulation time 5967497410 ps
CPU time 3.68 seconds
Started Sep 04 02:21:56 AM UTC 24
Finished Sep 04 02:22:00 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236314272 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.2236314272
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1389744199
Short name T324
Test name
Test status
Simulation time 2226216717 ps
CPU time 3.15 seconds
Started Sep 04 02:21:51 AM UTC 24
Finished Sep 04 02:21:55 AM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389744199 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.1389744199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.4056094132
Short name T404
Test name
Test status
Simulation time 22215354726 ps
CPU time 75.83 seconds
Started Sep 04 02:21:53 AM UTC 24
Finished Sep 04 02:23:11 AM UTC 24
Peak memory 211160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056094132 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.4056094132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3938515727
Short name T878
Test name
Test status
Simulation time 2032514210 ps
CPU time 3.02 seconds
Started Sep 04 02:23:05 AM UTC 24
Finished Sep 04 02:23:09 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938515727 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.3938515727
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.656521044
Short name T880
Test name
Test status
Simulation time 2045767288 ps
CPU time 2.05 seconds
Started Sep 04 02:23:06 AM UTC 24
Finished Sep 04 02:23:09 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656521044 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.656521044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2482272694
Short name T896
Test name
Test status
Simulation time 2016343695 ps
CPU time 5.99 seconds
Started Sep 04 02:23:06 AM UTC 24
Finished Sep 04 02:23:13 AM UTC 24
Peak memory 210540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482272694 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.2482272694
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4069510648
Short name T884
Test name
Test status
Simulation time 2019151985 ps
CPU time 3.97 seconds
Started Sep 04 02:23:06 AM UTC 24
Finished Sep 04 02:23:11 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069510648 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.4069510648
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.555965102
Short name T882
Test name
Test status
Simulation time 2055158922 ps
CPU time 1.8 seconds
Started Sep 04 02:23:07 AM UTC 24
Finished Sep 04 02:23:10 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555965102 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.555965102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1444932003
Short name T891
Test name
Test status
Simulation time 2019429430 ps
CPU time 3.41 seconds
Started Sep 04 02:23:07 AM UTC 24
Finished Sep 04 02:23:12 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444932003 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.1444932003
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2590503832
Short name T883
Test name
Test status
Simulation time 2053139621 ps
CPU time 2.37 seconds
Started Sep 04 02:23:07 AM UTC 24
Finished Sep 04 02:23:11 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590503832 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.2590503832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1299027732
Short name T900
Test name
Test status
Simulation time 2022877256 ps
CPU time 4.12 seconds
Started Sep 04 02:23:09 AM UTC 24
Finished Sep 04 02:23:14 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299027732 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.1299027732
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3678730720
Short name T885
Test name
Test status
Simulation time 2076570810 ps
CPU time 1.42 seconds
Started Sep 04 02:23:09 AM UTC 24
Finished Sep 04 02:23:11 AM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678730720 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.3678730720
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3903710930
Short name T892
Test name
Test status
Simulation time 2048754302 ps
CPU time 2.47 seconds
Started Sep 04 02:23:09 AM UTC 24
Finished Sep 04 02:23:12 AM UTC 24
Peak memory 210604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903710930 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.3903710930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.180577952
Short name T807
Test name
Test status
Simulation time 2539863010 ps
CPU time 5.61 seconds
Started Sep 04 02:22:02 AM UTC 24
Finished Sep 04 02:22:09 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180577952 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.180577952
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2820585107
Short name T911
Test name
Test status
Simulation time 40487754176 ps
CPU time 100.35 seconds
Started Sep 04 02:22:02 AM UTC 24
Finished Sep 04 02:23:45 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820585107 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.2820585107
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3724617450
Short name T327
Test name
Test status
Simulation time 2117206574 ps
CPU time 3.83 seconds
Started Sep 04 02:22:04 AM UTC 24
Finished Sep 04 02:22:10 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3724617450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3724617450
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.308327137
Short name T374
Test name
Test status
Simulation time 2032273888 ps
CPU time 8.15 seconds
Started Sep 04 02:22:01 AM UTC 24
Finished Sep 04 02:22:10 AM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308327137 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.308327137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.444127980
Short name T809
Test name
Test status
Simulation time 2016365158 ps
CPU time 11.42 seconds
Started Sep 04 02:22:01 AM UTC 24
Finished Sep 04 02:22:13 AM UTC 24
Peak memory 210536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444127980 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.444127980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2687718964
Short name T373
Test name
Test status
Simulation time 5281687605 ps
CPU time 3.7 seconds
Started Sep 04 02:22:03 AM UTC 24
Finished Sep 04 02:22:08 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687718964 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.2687718964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3320090743
Short name T325
Test name
Test status
Simulation time 2089955983 ps
CPU time 12.51 seconds
Started Sep 04 02:21:57 AM UTC 24
Finished Sep 04 02:22:10 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320090743 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.3320090743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2525000561
Short name T401
Test name
Test status
Simulation time 42385706593 ps
CPU time 57.51 seconds
Started Sep 04 02:21:59 AM UTC 24
Finished Sep 04 02:22:58 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525000561 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.2525000561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.172316639
Short name T888
Test name
Test status
Simulation time 2009835935 ps
CPU time 6.15 seconds
Started Sep 04 02:23:09 AM UTC 24
Finished Sep 04 02:23:16 AM UTC 24
Peak memory 210548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172316639 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.172316639
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3047294864
Short name T895
Test name
Test status
Simulation time 2033642336 ps
CPU time 2.94 seconds
Started Sep 04 02:23:09 AM UTC 24
Finished Sep 04 02:23:13 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047294864 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.3047294864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2206726509
Short name T886
Test name
Test status
Simulation time 2113164287 ps
CPU time 1.72 seconds
Started Sep 04 02:23:09 AM UTC 24
Finished Sep 04 02:23:11 AM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206726509 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.2206726509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4183620182
Short name T899
Test name
Test status
Simulation time 2033261691 ps
CPU time 2.43 seconds
Started Sep 04 02:23:10 AM UTC 24
Finished Sep 04 02:23:13 AM UTC 24
Peak memory 210828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183620182 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.4183620182
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1848322093
Short name T889
Test name
Test status
Simulation time 2007661025 ps
CPU time 7.89 seconds
Started Sep 04 02:23:10 AM UTC 24
Finished Sep 04 02:23:19 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848322093 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.1848322093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3115388544
Short name T897
Test name
Test status
Simulation time 2028480775 ps
CPU time 1.99 seconds
Started Sep 04 02:23:10 AM UTC 24
Finished Sep 04 02:23:13 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115388544 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.3115388544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2260885329
Short name T898
Test name
Test status
Simulation time 2049398407 ps
CPU time 2.16 seconds
Started Sep 04 02:23:10 AM UTC 24
Finished Sep 04 02:23:13 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260885329 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.2260885329
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2545849968
Short name T902
Test name
Test status
Simulation time 2023859681 ps
CPU time 3.32 seconds
Started Sep 04 02:23:11 AM UTC 24
Finished Sep 04 02:23:16 AM UTC 24
Peak memory 210604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545849968 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.2545849968
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1945040184
Short name T879
Test name
Test status
Simulation time 2015179999 ps
CPU time 5.98 seconds
Started Sep 04 02:23:12 AM UTC 24
Finished Sep 04 02:23:19 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945040184 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.1945040184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3950729381
Short name T901
Test name
Test status
Simulation time 2034604983 ps
CPU time 2 seconds
Started Sep 04 02:23:12 AM UTC 24
Finished Sep 04 02:23:15 AM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950729381 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.3950729381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1772909327
Short name T810
Test name
Test status
Simulation time 2166422143 ps
CPU time 4.26 seconds
Started Sep 04 02:22:09 AM UTC 24
Finished Sep 04 02:22:15 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1772909327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_csr_mem_rw_with_rand_reset.1772909327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3307721072
Short name T364
Test name
Test status
Simulation time 2060178858 ps
CPU time 5.37 seconds
Started Sep 04 02:22:08 AM UTC 24
Finished Sep 04 02:22:14 AM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307721072 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.3307721072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2102718777
Short name T808
Test name
Test status
Simulation time 2033710972 ps
CPU time 3.33 seconds
Started Sep 04 02:22:07 AM UTC 24
Finished Sep 04 02:22:11 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102718777 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.2102718777
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.675914912
Short name T815
Test name
Test status
Simulation time 5144040496 ps
CPU time 22.06 seconds
Started Sep 04 02:22:08 AM UTC 24
Finished Sep 04 02:22:31 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675914912 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.675914912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3937615739
Short name T330
Test name
Test status
Simulation time 2065422556 ps
CPU time 11.38 seconds
Started Sep 04 02:22:05 AM UTC 24
Finished Sep 04 02:22:18 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937615739 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.3937615739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1530847252
Short name T903
Test name
Test status
Simulation time 22211073980 ps
CPU time 72.22 seconds
Started Sep 04 02:22:07 AM UTC 24
Finished Sep 04 02:23:21 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530847252 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.1530847252
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.946464431
Short name T440
Test name
Test status
Simulation time 2133376814 ps
CPU time 3.11 seconds
Started Sep 04 02:22:12 AM UTC 24
Finished Sep 04 02:22:17 AM UTC 24
Peak memory 210976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=946464431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
sysrst_ctrl_csr_mem_rw_with_rand_reset.946464431
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.201029299
Short name T365
Test name
Test status
Simulation time 2047795992 ps
CPU time 7.45 seconds
Started Sep 04 02:22:11 AM UTC 24
Finished Sep 04 02:22:20 AM UTC 24
Peak memory 211080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201029299 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.201029299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1466964850
Short name T811
Test name
Test status
Simulation time 2020614015 ps
CPU time 3.19 seconds
Started Sep 04 02:22:11 AM UTC 24
Finished Sep 04 02:22:16 AM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466964850 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.1466964850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.432308646
Short name T813
Test name
Test status
Simulation time 5649490358 ps
CPU time 8.05 seconds
Started Sep 04 02:22:11 AM UTC 24
Finished Sep 04 02:22:21 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432308646 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.432308646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.822497669
Short name T816
Test name
Test status
Simulation time 2036179400 ps
CPU time 12.33 seconds
Started Sep 04 02:22:10 AM UTC 24
Finished Sep 04 02:22:24 AM UTC 24
Peak memory 211124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822497669 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.822497669
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1366185147
Short name T400
Test name
Test status
Simulation time 22447427360 ps
CPU time 23.37 seconds
Started Sep 04 02:22:11 AM UTC 24
Finished Sep 04 02:22:36 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366185147 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.1366185147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2522441475
Short name T329
Test name
Test status
Simulation time 2118026973 ps
CPU time 2.82 seconds
Started Sep 04 02:22:16 AM UTC 24
Finished Sep 04 02:22:20 AM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2522441475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2522441475
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3450803644
Short name T812
Test name
Test status
Simulation time 2039571596 ps
CPU time 3.43 seconds
Started Sep 04 02:22:16 AM UTC 24
Finished Sep 04 02:22:20 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450803644 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.3450803644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1167822406
Short name T820
Test name
Test status
Simulation time 2011854890 ps
CPU time 9.06 seconds
Started Sep 04 02:22:14 AM UTC 24
Finished Sep 04 02:22:25 AM UTC 24
Peak memory 210668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167822406 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.1167822406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2179690927
Short name T818
Test name
Test status
Simulation time 11250130257 ps
CPU time 7.83 seconds
Started Sep 04 02:22:16 AM UTC 24
Finished Sep 04 02:22:25 AM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179690927 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.2179690927
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3999001166
Short name T405
Test name
Test status
Simulation time 22201673593 ps
CPU time 60.44 seconds
Started Sep 04 02:22:12 AM UTC 24
Finished Sep 04 02:23:14 AM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999001166 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.3999001166
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.716799845
Short name T821
Test name
Test status
Simulation time 2050494097 ps
CPU time 3.48 seconds
Started Sep 04 02:22:21 AM UTC 24
Finished Sep 04 02:22:26 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=716799845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
sysrst_ctrl_csr_mem_rw_with_rand_reset.716799845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1700489318
Short name T370
Test name
Test status
Simulation time 2073029376 ps
CPU time 3.48 seconds
Started Sep 04 02:22:20 AM UTC 24
Finished Sep 04 02:22:25 AM UTC 24
Peak memory 210716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700489318 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.1700489318
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1676871774
Short name T814
Test name
Test status
Simulation time 2147614560 ps
CPU time 1.2 seconds
Started Sep 04 02:22:19 AM UTC 24
Finished Sep 04 02:22:21 AM UTC 24
Peak memory 210684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676871774 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.1676871774
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2901230899
Short name T819
Test name
Test status
Simulation time 7950432520 ps
CPU time 3.58 seconds
Started Sep 04 02:22:20 AM UTC 24
Finished Sep 04 02:22:25 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901230899 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.2901230899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3447417399
Short name T323
Test name
Test status
Simulation time 2121463729 ps
CPU time 5.26 seconds
Started Sep 04 02:22:17 AM UTC 24
Finished Sep 04 02:22:23 AM UTC 24
Peak memory 221276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447417399 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.3447417399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1046010027
Short name T910
Test name
Test status
Simulation time 22171602525 ps
CPU time 82.51 seconds
Started Sep 04 02:22:18 AM UTC 24
Finished Sep 04 02:23:42 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046010027 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.1046010027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2554029360
Short name T831
Test name
Test status
Simulation time 2041742598 ps
CPU time 11.85 seconds
Started Sep 04 02:22:25 AM UTC 24
Finished Sep 04 02:22:38 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2554029360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2554029360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1666220392
Short name T822
Test name
Test status
Simulation time 2069108513 ps
CPU time 2.67 seconds
Started Sep 04 02:22:23 AM UTC 24
Finished Sep 04 02:22:27 AM UTC 24
Peak memory 210940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666220392 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.1666220392
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3420954350
Short name T817
Test name
Test status
Simulation time 2087753090 ps
CPU time 1.92 seconds
Started Sep 04 02:22:21 AM UTC 24
Finished Sep 04 02:22:25 AM UTC 24
Peak memory 210000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420954350 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.3420954350
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3981487999
Short name T841
Test name
Test status
Simulation time 4750168193 ps
CPU time 21.46 seconds
Started Sep 04 02:22:24 AM UTC 24
Finished Sep 04 02:22:47 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981487999 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.3981487999
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4124263108
Short name T322
Test name
Test status
Simulation time 2042824722 ps
CPU time 11.76 seconds
Started Sep 04 02:22:21 AM UTC 24
Finished Sep 04 02:22:34 AM UTC 24
Peak memory 221252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124263108 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.4124263108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3768953516
Short name T866
Test name
Test status
Simulation time 42801145125 ps
CPU time 41.61 seconds
Started Sep 04 02:22:21 AM UTC 24
Finished Sep 04 02:23:05 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768953516 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.3768953516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.4214554477
Short name T16
Test name
Test status
Simulation time 3339998566 ps
CPU time 6.52 seconds
Started Sep 04 02:13:06 AM UTC 24
Finished Sep 04 02:13:13 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214554477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.4214554477
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4177425828
Short name T1
Test name
Test status
Simulation time 2446912543 ps
CPU time 2.47 seconds
Started Sep 04 02:13:00 AM UTC 24
Finished Sep 04 02:13:04 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177425828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.4177425828
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1790063359
Short name T5
Test name
Test status
Simulation time 2358813410 ps
CPU time 3.4 seconds
Started Sep 04 02:13:00 AM UTC 24
Finished Sep 04 02:13:05 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790063359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1790063359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.110627966
Short name T272
Test name
Test status
Simulation time 54108613319 ps
CPU time 154.77 seconds
Started Sep 04 02:13:07 AM UTC 24
Finished Sep 04 02:15:44 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110627966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.110627966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1828061610
Short name T78
Test name
Test status
Simulation time 2530953069 ps
CPU time 11.84 seconds
Started Sep 04 02:13:05 AM UTC 24
Finished Sep 04 02:13:18 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828061610 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.1828061610
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2097816577
Short name T3
Test name
Test status
Simulation time 5464644399 ps
CPU time 3.22 seconds
Started Sep 04 02:13:06 AM UTC 24
Finished Sep 04 02:13:10 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097816577 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.2097816577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1824141713
Short name T15
Test name
Test status
Simulation time 2617801528 ps
CPU time 5.06 seconds
Started Sep 04 02:13:05 AM UTC 24
Finished Sep 04 02:13:11 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824141713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1824141713
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2935546100
Short name T14
Test name
Test status
Simulation time 2483775168 ps
CPU time 9.22 seconds
Started Sep 04 02:12:59 AM UTC 24
Finished Sep 04 02:13:10 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935546100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.2935546100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.1018500351
Short name T4
Test name
Test status
Simulation time 2104759008 ps
CPU time 2.14 seconds
Started Sep 04 02:13:02 AM UTC 24
Finished Sep 04 02:13:05 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018500351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1018500351
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.857942733
Short name T332
Test name
Test status
Simulation time 42012484596 ps
CPU time 112.89 seconds
Started Sep 04 02:13:09 AM UTC 24
Finished Sep 04 02:15:04 AM UTC 24
Peak memory 240204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857942733 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.857942733
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.425889114
Short name T13
Test name
Test status
Simulation time 2113662400 ps
CPU time 7.97 seconds
Started Sep 04 02:12:59 AM UTC 24
Finished Sep 04 02:13:08 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425889114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.425889114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3361366924
Short name T9
Test name
Test status
Simulation time 13901374186 ps
CPU time 9.91 seconds
Started Sep 04 02:13:08 AM UTC 24
Finished Sep 04 02:13:19 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3361366924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.3361366924
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2490582313
Short name T2
Test name
Test status
Simulation time 6930345672 ps
CPU time 2.12 seconds
Started Sep 04 02:13:06 AM UTC 24
Finished Sep 04 02:13:09 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490582313 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.2490582313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.122914870
Short name T121
Test name
Test status
Simulation time 2049107659 ps
CPU time 2.79 seconds
Started Sep 04 02:13:16 AM UTC 24
Finished Sep 04 02:13:19 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122914870 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.122914870
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.212427987
Short name T27
Test name
Test status
Simulation time 3626438051 ps
CPU time 4.29 seconds
Started Sep 04 02:13:12 AM UTC 24
Finished Sep 04 02:13:17 AM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212427987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.212427987
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2360525789
Short name T8
Test name
Test status
Simulation time 2423889455 ps
CPU time 3.2 seconds
Started Sep 04 02:13:11 AM UTC 24
Finished Sep 04 02:13:15 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360525789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2360525789
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2803376299
Short name T80
Test name
Test status
Simulation time 4566392789 ps
CPU time 17.14 seconds
Started Sep 04 02:13:12 AM UTC 24
Finished Sep 04 02:13:30 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803376299 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.2803376299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1707569171
Short name T89
Test name
Test status
Simulation time 2612285794 ps
CPU time 7.59 seconds
Started Sep 04 02:13:11 AM UTC 24
Finished Sep 04 02:13:19 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707569171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.1707569171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3598775148
Short name T22
Test name
Test status
Simulation time 2483503096 ps
CPU time 3.35 seconds
Started Sep 04 02:13:11 AM UTC 24
Finished Sep 04 02:13:15 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598775148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3598775148
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.158306610
Short name T68
Test name
Test status
Simulation time 2174180779 ps
CPU time 5.69 seconds
Started Sep 04 02:13:11 AM UTC 24
Finished Sep 04 02:13:17 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158306610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.158306610
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.671201577
Short name T66
Test name
Test status
Simulation time 2133430639 ps
CPU time 3.04 seconds
Started Sep 04 02:13:10 AM UTC 24
Finished Sep 04 02:13:15 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671201577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.671201577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2926839897
Short name T239
Test name
Test status
Simulation time 2013444579 ps
CPU time 8.72 seconds
Started Sep 04 02:14:25 AM UTC 24
Finished Sep 04 02:14:34 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926839897 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.2926839897
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1621629420
Short name T70
Test name
Test status
Simulation time 3595587226 ps
CPU time 3.83 seconds
Started Sep 04 02:14:20 AM UTC 24
Finished Sep 04 02:14:25 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621629420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.1621629420
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.2560279301
Short name T103
Test name
Test status
Simulation time 27159784923 ps
CPU time 23.09 seconds
Started Sep 04 02:14:21 AM UTC 24
Finished Sep 04 02:14:45 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560279301 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.2560279301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1773085315
Short name T97
Test name
Test status
Simulation time 83460901190 ps
CPU time 60.93 seconds
Started Sep 04 02:14:21 AM UTC 24
Finished Sep 04 02:15:24 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773085315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_with_pre_cond.1773085315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2821220163
Short name T246
Test name
Test status
Simulation time 2781307415 ps
CPU time 7.22 seconds
Started Sep 04 02:14:20 AM UTC 24
Finished Sep 04 02:14:28 AM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821220163 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.2821220163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.874967430
Short name T242
Test name
Test status
Simulation time 2635326925 ps
CPU time 3.41 seconds
Started Sep 04 02:14:20 AM UTC 24
Finished Sep 04 02:14:24 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874967430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.874967430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.1630156831
Short name T243
Test name
Test status
Simulation time 2477564267 ps
CPU time 4.88 seconds
Started Sep 04 02:14:19 AM UTC 24
Finished Sep 04 02:14:25 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630156831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1630156831
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.2567921021
Short name T234
Test name
Test status
Simulation time 2167698878 ps
CPU time 10.91 seconds
Started Sep 04 02:14:19 AM UTC 24
Finished Sep 04 02:14:31 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567921021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.2567921021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.2482523149
Short name T245
Test name
Test status
Simulation time 2113298567 ps
CPU time 6.25 seconds
Started Sep 04 02:14:19 AM UTC 24
Finished Sep 04 02:14:26 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482523149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.2482523149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.271739535
Short name T339
Test name
Test status
Simulation time 11402246938 ps
CPU time 30.45 seconds
Started Sep 04 02:14:22 AM UTC 24
Finished Sep 04 02:14:54 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271739535 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.271739535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1173905824
Short name T311
Test name
Test status
Simulation time 3226435325 ps
CPU time 15.19 seconds
Started Sep 04 02:14:22 AM UTC 24
Finished Sep 04 02:14:39 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1173905824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1173905824
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.713880093
Short name T244
Test name
Test status
Simulation time 4333220529 ps
CPU time 3.29 seconds
Started Sep 04 02:14:21 AM UTC 24
Finished Sep 04 02:14:25 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713880093 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.713880093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.2198908345
Short name T240
Test name
Test status
Simulation time 2046826642 ps
CPU time 2.19 seconds
Started Sep 04 02:14:32 AM UTC 24
Finished Sep 04 02:14:35 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198908345 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.2198908345
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2031107038
Short name T119
Test name
Test status
Simulation time 3139637535 ps
CPU time 17.53 seconds
Started Sep 04 02:14:28 AM UTC 24
Finished Sep 04 02:14:47 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031107038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2031107038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.939753352
Short name T703
Test name
Test status
Simulation time 141805582563 ps
CPU time 258.06 seconds
Started Sep 04 02:14:29 AM UTC 24
Finished Sep 04 02:18:51 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939753352 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.939753352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.237509783
Short name T95
Test name
Test status
Simulation time 21095748168 ps
CPU time 24.77 seconds
Started Sep 04 02:14:30 AM UTC 24
Finished Sep 04 02:14:56 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237509783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_with_pre_cond.237509783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2225122959
Short name T235
Test name
Test status
Simulation time 3700307451 ps
CPU time 3.02 seconds
Started Sep 04 02:14:27 AM UTC 24
Finished Sep 04 02:14:31 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225122959 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.2225122959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.2528432426
Short name T47
Test name
Test status
Simulation time 5070008255 ps
CPU time 4.56 seconds
Started Sep 04 02:14:30 AM UTC 24
Finished Sep 04 02:14:36 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528432426 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.2528432426
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1574117040
Short name T241
Test name
Test status
Simulation time 2608876258 ps
CPU time 8.85 seconds
Started Sep 04 02:14:27 AM UTC 24
Finished Sep 04 02:14:37 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574117040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1574117040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.1540551410
Short name T237
Test name
Test status
Simulation time 2468364144 ps
CPU time 6.16 seconds
Started Sep 04 02:14:26 AM UTC 24
Finished Sep 04 02:14:33 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540551410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1540551410
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.3177051848
Short name T455
Test name
Test status
Simulation time 2044605349 ps
CPU time 3.15 seconds
Started Sep 04 02:14:26 AM UTC 24
Finished Sep 04 02:14:30 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177051848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.3177051848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2719868230
Short name T451
Test name
Test status
Simulation time 2548114838 ps
CPU time 2.48 seconds
Started Sep 04 02:14:26 AM UTC 24
Finished Sep 04 02:14:29 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719868230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2719868230
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.3501301282
Short name T238
Test name
Test status
Simulation time 2112868616 ps
CPU time 7.34 seconds
Started Sep 04 02:14:26 AM UTC 24
Finished Sep 04 02:14:34 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501301282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.3501301282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.1284849467
Short name T350
Test name
Test status
Simulation time 7072555840 ps
CPU time 22.56 seconds
Started Sep 04 02:14:32 AM UTC 24
Finished Sep 04 02:14:55 AM UTC 24
Peak memory 209736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284849467 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.1284849467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3065069397
Short name T283
Test name
Test status
Simulation time 4226392873 ps
CPU time 14.87 seconds
Started Sep 04 02:14:32 AM UTC 24
Finished Sep 04 02:14:48 AM UTC 24
Peak memory 220400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3065069397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.3065069397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1045788069
Short name T280
Test name
Test status
Simulation time 2015948092 ps
CPU time 4.78 seconds
Started Sep 04 02:14:41 AM UTC 24
Finished Sep 04 02:14:47 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045788069 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.1045788069
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1477151633
Short name T118
Test name
Test status
Simulation time 3224001962 ps
CPU time 3.13 seconds
Started Sep 04 02:14:36 AM UTC 24
Finished Sep 04 02:14:40 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477151633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1477151633
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2515106577
Short name T386
Test name
Test status
Simulation time 97353084399 ps
CPU time 289.3 seconds
Started Sep 04 02:14:37 AM UTC 24
Finished Sep 04 02:19:31 AM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515106577 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.2515106577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.336866557
Short name T456
Test name
Test status
Simulation time 3373791589 ps
CPU time 5.96 seconds
Started Sep 04 02:14:36 AM UTC 24
Finished Sep 04 02:14:43 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336866557 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.336866557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3023462483
Short name T51
Test name
Test status
Simulation time 3238465278 ps
CPU time 5.95 seconds
Started Sep 04 02:14:37 AM UTC 24
Finished Sep 04 02:14:44 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023462483 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.3023462483
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.18943077
Short name T285
Test name
Test status
Simulation time 2611811526 ps
CPU time 12.85 seconds
Started Sep 04 02:14:35 AM UTC 24
Finished Sep 04 02:14:49 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18943077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.18943077
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2567634295
Short name T310
Test name
Test status
Simulation time 2458449270 ps
CPU time 4.9 seconds
Started Sep 04 02:14:33 AM UTC 24
Finished Sep 04 02:14:39 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567634295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2567634295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.3782780341
Short name T282
Test name
Test status
Simulation time 2232346779 ps
CPU time 12.07 seconds
Started Sep 04 02:14:34 AM UTC 24
Finished Sep 04 02:14:47 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782780341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.3782780341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3100280485
Short name T313
Test name
Test status
Simulation time 2516204439 ps
CPU time 5.57 seconds
Started Sep 04 02:14:35 AM UTC 24
Finished Sep 04 02:14:42 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100280485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3100280485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.1719544659
Short name T312
Test name
Test status
Simulation time 2116000787 ps
CPU time 5.21 seconds
Started Sep 04 02:14:33 AM UTC 24
Finished Sep 04 02:14:39 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719544659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1719544659
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3075748039
Short name T389
Test name
Test status
Simulation time 226673607302 ps
CPU time 560.68 seconds
Started Sep 04 02:14:40 AM UTC 24
Finished Sep 04 02:24:06 AM UTC 24
Peak memory 213148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075748039 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.3075748039
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3479066998
Short name T341
Test name
Test status
Simulation time 5179456417 ps
CPU time 12.31 seconds
Started Sep 04 02:14:40 AM UTC 24
Finished Sep 04 02:14:53 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3479066998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3479066998
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1246011837
Short name T466
Test name
Test status
Simulation time 2013978311 ps
CPU time 10.06 seconds
Started Sep 04 02:14:48 AM UTC 24
Finished Sep 04 02:14:59 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246011837 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.1246011837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3792126753
Short name T286
Test name
Test status
Simulation time 3209618304 ps
CPU time 3.71 seconds
Started Sep 04 02:14:45 AM UTC 24
Finished Sep 04 02:14:50 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792126753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.3792126753
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.4217186212
Short name T436
Test name
Test status
Simulation time 116578248015 ps
CPU time 349.37 seconds
Started Sep 04 02:14:46 AM UTC 24
Finished Sep 04 02:20:40 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217186212 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.4217186212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.214802712
Short name T462
Test name
Test status
Simulation time 4628676366 ps
CPU time 6.13 seconds
Started Sep 04 02:14:45 AM UTC 24
Finished Sep 04 02:14:52 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214802712 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.214802712
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1532103472
Short name T53
Test name
Test status
Simulation time 3135297772 ps
CPU time 9.4 seconds
Started Sep 04 02:14:46 AM UTC 24
Finished Sep 04 02:14:57 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532103472 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.1532103472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3376129758
Short name T348
Test name
Test status
Simulation time 2610626074 ps
CPU time 8.54 seconds
Started Sep 04 02:14:44 AM UTC 24
Finished Sep 04 02:14:54 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376129758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.3376129758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.750880804
Short name T284
Test name
Test status
Simulation time 2477333459 ps
CPU time 3.9 seconds
Started Sep 04 02:14:43 AM UTC 24
Finished Sep 04 02:14:48 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750880804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.750880804
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.3278282885
Short name T281
Test name
Test status
Simulation time 2158037677 ps
CPU time 2.63 seconds
Started Sep 04 02:14:43 AM UTC 24
Finished Sep 04 02:14:47 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278282885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.3278282885
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.173121611
Short name T463
Test name
Test status
Simulation time 2512027826 ps
CPU time 12.36 seconds
Started Sep 04 02:14:43 AM UTC 24
Finished Sep 04 02:14:56 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173121611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.173121611
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.493232513
Short name T458
Test name
Test status
Simulation time 2122498899 ps
CPU time 2.8 seconds
Started Sep 04 02:14:41 AM UTC 24
Finished Sep 04 02:14:44 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493232513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.493232513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.3616582191
Short name T228
Test name
Test status
Simulation time 64867392088 ps
CPU time 18.21 seconds
Started Sep 04 02:14:48 AM UTC 24
Finished Sep 04 02:15:07 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616582191 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.3616582191
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3986417405
Short name T465
Test name
Test status
Simulation time 2976165413 ps
CPU time 9.95 seconds
Started Sep 04 02:14:48 AM UTC 24
Finished Sep 04 02:14:59 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3986417405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3986417405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3393623739
Short name T464
Test name
Test status
Simulation time 3027790986 ps
CPU time 11.43 seconds
Started Sep 04 02:14:45 AM UTC 24
Finished Sep 04 02:14:58 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393623739 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.3393623739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.3461106466
Short name T470
Test name
Test status
Simulation time 2021426993 ps
CPU time 6.86 seconds
Started Sep 04 02:14:54 AM UTC 24
Finished Sep 04 02:15:02 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461106466 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.3461106466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.976642404
Short name T333
Test name
Test status
Simulation time 3466941689 ps
CPU time 3.74 seconds
Started Sep 04 02:14:51 AM UTC 24
Finished Sep 04 02:14:56 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976642404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.976642404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.41115178
Short name T382
Test name
Test status
Simulation time 109448488454 ps
CPU time 130.75 seconds
Started Sep 04 02:14:52 AM UTC 24
Finished Sep 04 02:17:05 AM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41115178 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.41115178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3271420638
Short name T338
Test name
Test status
Simulation time 2718726257 ps
CPU time 9.2 seconds
Started Sep 04 02:14:50 AM UTC 24
Finished Sep 04 02:15:00 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271420638 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.3271420638
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.625901689
Short name T204
Test name
Test status
Simulation time 3274077603 ps
CPU time 4.51 seconds
Started Sep 04 02:14:52 AM UTC 24
Finished Sep 04 02:14:58 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625901689 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.625901689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3503251539
Short name T460
Test name
Test status
Simulation time 2761056857 ps
CPU time 1.59 seconds
Started Sep 04 02:14:49 AM UTC 24
Finished Sep 04 02:14:52 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503251539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.3503251539
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.1233309025
Short name T469
Test name
Test status
Simulation time 2447865893 ps
CPU time 10.83 seconds
Started Sep 04 02:14:49 AM UTC 24
Finished Sep 04 02:15:01 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233309025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.1233309025
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.3036121273
Short name T459
Test name
Test status
Simulation time 2134367894 ps
CPU time 1.27 seconds
Started Sep 04 02:14:49 AM UTC 24
Finished Sep 04 02:14:51 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036121273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3036121273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.436925419
Short name T349
Test name
Test status
Simulation time 2530631511 ps
CPU time 3.8 seconds
Started Sep 04 02:14:49 AM UTC 24
Finished Sep 04 02:14:54 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436925419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.436925419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.1189492916
Short name T461
Test name
Test status
Simulation time 2131757029 ps
CPU time 3.13 seconds
Started Sep 04 02:14:48 AM UTC 24
Finished Sep 04 02:14:52 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189492916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.1189492916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1373487493
Short name T233
Test name
Test status
Simulation time 9725890061 ps
CPU time 15.03 seconds
Started Sep 04 02:14:54 AM UTC 24
Finished Sep 04 02:15:10 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1373487493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.1373487493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.1428371816
Short name T110
Test name
Test status
Simulation time 7236390303 ps
CPU time 1.47 seconds
Started Sep 04 02:14:52 AM UTC 24
Finished Sep 04 02:14:55 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428371816 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.1428371816
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1743231022
Short name T472
Test name
Test status
Simulation time 2029499584 ps
CPU time 2.98 seconds
Started Sep 04 02:14:59 AM UTC 24
Finished Sep 04 02:15:03 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743231022 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.1743231022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2644013689
Short name T120
Test name
Test status
Simulation time 3713993728 ps
CPU time 13.63 seconds
Started Sep 04 02:14:56 AM UTC 24
Finished Sep 04 02:15:11 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644013689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2644013689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1032025532
Short name T315
Test name
Test status
Simulation time 156059140051 ps
CPU time 77.24 seconds
Started Sep 04 02:14:57 AM UTC 24
Finished Sep 04 02:16:16 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032025532 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.1032025532
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.1658487736
Short name T231
Test name
Test status
Simulation time 3395051564 ps
CPU time 11.92 seconds
Started Sep 04 02:14:56 AM UTC 24
Finished Sep 04 02:15:09 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658487736 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.1658487736
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1069435403
Short name T180
Test name
Test status
Simulation time 4318192662 ps
CPU time 6.14 seconds
Started Sep 04 02:14:57 AM UTC 24
Finished Sep 04 02:15:05 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069435403 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.1069435403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2451943174
Short name T468
Test name
Test status
Simulation time 2619375462 ps
CPU time 4.29 seconds
Started Sep 04 02:14:55 AM UTC 24
Finished Sep 04 02:15:00 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451943174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.2451943174
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1149306302
Short name T473
Test name
Test status
Simulation time 2443245358 ps
CPU time 7.23 seconds
Started Sep 04 02:14:55 AM UTC 24
Finished Sep 04 02:15:03 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149306302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1149306302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1813267617
Short name T267
Test name
Test status
Simulation time 2187094608 ps
CPU time 8.67 seconds
Started Sep 04 02:14:55 AM UTC 24
Finished Sep 04 02:15:05 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813267617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.1813267617
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2586745153
Short name T467
Test name
Test status
Simulation time 2524532021 ps
CPU time 3.77 seconds
Started Sep 04 02:14:55 AM UTC 24
Finished Sep 04 02:15:00 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586745153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2586745153
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.2807863361
Short name T471
Test name
Test status
Simulation time 2114347443 ps
CPU time 6.42 seconds
Started Sep 04 02:14:55 AM UTC 24
Finished Sep 04 02:15:02 AM UTC 24
Peak memory 209816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807863361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.2807863361
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3530523167
Short name T770
Test name
Test status
Simulation time 286262695245 ps
CPU time 351.83 seconds
Started Sep 04 02:14:59 AM UTC 24
Finished Sep 04 02:20:54 AM UTC 24
Peak memory 209956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530523167 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.3530523167
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.376204556
Short name T138
Test name
Test status
Simulation time 11206961028 ps
CPU time 16.37 seconds
Started Sep 04 02:14:59 AM UTC 24
Finished Sep 04 02:15:16 AM UTC 24
Peak memory 226968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=376204556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.376204556
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2635350757
Short name T145
Test name
Test status
Simulation time 4832513654 ps
CPU time 3.43 seconds
Started Sep 04 02:14:57 AM UTC 24
Finished Sep 04 02:15:02 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635350757 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.2635350757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2198594532
Short name T232
Test name
Test status
Simulation time 2009331553 ps
CPU time 6.82 seconds
Started Sep 04 02:15:05 AM UTC 24
Finished Sep 04 02:15:13 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198594532 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.2198594532
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1196736299
Short name T124
Test name
Test status
Simulation time 99289827609 ps
CPU time 55.51 seconds
Started Sep 04 02:15:02 AM UTC 24
Finished Sep 04 02:15:59 AM UTC 24
Peak memory 210232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196736299 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.1196736299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1441161116
Short name T441
Test name
Test status
Simulation time 39877925910 ps
CPU time 126.86 seconds
Started Sep 04 02:15:03 AM UTC 24
Finished Sep 04 02:17:13 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441161116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.1441161116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1283377951
Short name T793
Test name
Test status
Simulation time 903355923668 ps
CPU time 550.33 seconds
Started Sep 04 02:15:01 AM UTC 24
Finished Sep 04 02:24:17 AM UTC 24
Peak memory 212600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283377951 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.1283377951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2517992792
Short name T478
Test name
Test status
Simulation time 2610789347 ps
CPU time 10.04 seconds
Started Sep 04 02:15:01 AM UTC 24
Finished Sep 04 02:15:12 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517992792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.2517992792
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.4126961837
Short name T269
Test name
Test status
Simulation time 2477412317 ps
CPU time 4.71 seconds
Started Sep 04 02:15:00 AM UTC 24
Finished Sep 04 02:15:05 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126961837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.4126961837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.3521205145
Short name T474
Test name
Test status
Simulation time 2045964303 ps
CPU time 2.6 seconds
Started Sep 04 02:15:00 AM UTC 24
Finished Sep 04 02:15:03 AM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521205145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3521205145
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2750241459
Short name T475
Test name
Test status
Simulation time 2534535160 ps
CPU time 2.31 seconds
Started Sep 04 02:15:01 AM UTC 24
Finished Sep 04 02:15:04 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750241459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2750241459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1270758651
Short name T227
Test name
Test status
Simulation time 2115822372 ps
CPU time 5.36 seconds
Started Sep 04 02:15:00 AM UTC 24
Finished Sep 04 02:15:06 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270758651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1270758651
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2646238934
Short name T141
Test name
Test status
Simulation time 7466434688 ps
CPU time 11.13 seconds
Started Sep 04 02:15:05 AM UTC 24
Finished Sep 04 02:15:17 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646238934 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.2646238934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2614616354
Short name T342
Test name
Test status
Simulation time 7843984690 ps
CPU time 24.64 seconds
Started Sep 04 02:15:03 AM UTC 24
Finished Sep 04 02:15:29 AM UTC 24
Peak memory 220476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2614616354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.2614616354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3149133412
Short name T146
Test name
Test status
Simulation time 8995871103 ps
CPU time 4.27 seconds
Started Sep 04 02:15:02 AM UTC 24
Finished Sep 04 02:15:07 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149133412 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.3149133412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.4017105525
Short name T481
Test name
Test status
Simulation time 2014409424 ps
CPU time 7.48 seconds
Started Sep 04 02:15:10 AM UTC 24
Finished Sep 04 02:15:19 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017105525 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.4017105525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4165246309
Short name T139
Test name
Test status
Simulation time 3609126686 ps
CPU time 9.41 seconds
Started Sep 04 02:15:06 AM UTC 24
Finished Sep 04 02:15:17 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165246309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.4165246309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2527162037
Short name T377
Test name
Test status
Simulation time 74989114114 ps
CPU time 89.68 seconds
Started Sep 04 02:15:07 AM UTC 24
Finished Sep 04 02:16:39 AM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527162037 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.2527162037
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2371683004
Short name T123
Test name
Test status
Simulation time 26087953958 ps
CPU time 40.39 seconds
Started Sep 04 02:15:08 AM UTC 24
Finished Sep 04 02:15:50 AM UTC 24
Peak memory 210644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371683004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_with_pre_cond.2371683004
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3085704991
Short name T482
Test name
Test status
Simulation time 3672193716 ps
CPU time 12.28 seconds
Started Sep 04 02:15:06 AM UTC 24
Finished Sep 04 02:15:19 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085704991 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.3085704991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.1953287576
Short name T137
Test name
Test status
Simulation time 5112559976 ps
CPU time 5.51 seconds
Started Sep 04 02:15:08 AM UTC 24
Finished Sep 04 02:15:15 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953287576 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.1953287576
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.290027958
Short name T477
Test name
Test status
Simulation time 2636091557 ps
CPU time 3.81 seconds
Started Sep 04 02:15:06 AM UTC 24
Finished Sep 04 02:15:11 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290027958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.290027958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3057160289
Short name T230
Test name
Test status
Simulation time 2472567147 ps
CPU time 2.85 seconds
Started Sep 04 02:15:05 AM UTC 24
Finished Sep 04 02:15:09 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057160289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.3057160289
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.3491437246
Short name T476
Test name
Test status
Simulation time 2062600652 ps
CPU time 3.35 seconds
Started Sep 04 02:15:06 AM UTC 24
Finished Sep 04 02:15:10 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491437246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3491437246
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.4019490027
Short name T135
Test name
Test status
Simulation time 2512445645 ps
CPU time 6.68 seconds
Started Sep 04 02:15:06 AM UTC 24
Finished Sep 04 02:15:14 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019490027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.4019490027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.1469541470
Short name T229
Test name
Test status
Simulation time 2135268412 ps
CPU time 2.6 seconds
Started Sep 04 02:15:05 AM UTC 24
Finished Sep 04 02:15:09 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469541470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.1469541470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.3547941309
Short name T357
Test name
Test status
Simulation time 7086620034 ps
CPU time 20.68 seconds
Started Sep 04 02:15:10 AM UTC 24
Finished Sep 04 02:15:32 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547941309 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.3547941309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1522641770
Short name T334
Test name
Test status
Simulation time 13332134878 ps
CPU time 10.91 seconds
Started Sep 04 02:15:10 AM UTC 24
Finished Sep 04 02:15:22 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1522641770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.1522641770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2897824247
Short name T483
Test name
Test status
Simulation time 2087275315 ps
CPU time 1.9 seconds
Started Sep 04 02:15:17 AM UTC 24
Finished Sep 04 02:15:20 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897824247 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.2897824247
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.4130853406
Short name T142
Test name
Test status
Simulation time 3515233980 ps
CPU time 2.89 seconds
Started Sep 04 02:15:13 AM UTC 24
Finished Sep 04 02:15:17 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130853406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.4130853406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.618154276
Short name T278
Test name
Test status
Simulation time 57803247038 ps
CPU time 68.51 seconds
Started Sep 04 02:15:15 AM UTC 24
Finished Sep 04 02:16:25 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618154276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.618154276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1953093110
Short name T484
Test name
Test status
Simulation time 4665332614 ps
CPU time 5.94 seconds
Started Sep 04 02:15:12 AM UTC 24
Finished Sep 04 02:15:20 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953093110 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.1953093110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2226609478
Short name T171
Test name
Test status
Simulation time 3723595204 ps
CPU time 2.18 seconds
Started Sep 04 02:15:14 AM UTC 24
Finished Sep 04 02:15:18 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226609478 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.2226609478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.8634676
Short name T480
Test name
Test status
Simulation time 2625755145 ps
CPU time 4.54 seconds
Started Sep 04 02:15:12 AM UTC 24
Finished Sep 04 02:15:18 AM UTC 24
Peak memory 209240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8634676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_
TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.8634676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.2804949408
Short name T490
Test name
Test status
Simulation time 2477955094 ps
CPU time 9.6 seconds
Started Sep 04 02:15:11 AM UTC 24
Finished Sep 04 02:15:22 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804949408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.2804949408
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.3559663839
Short name T136
Test name
Test status
Simulation time 2335194564 ps
CPU time 1.64 seconds
Started Sep 04 02:15:11 AM UTC 24
Finished Sep 04 02:15:14 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559663839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3559663839
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.1734925933
Short name T488
Test name
Test status
Simulation time 2510407714 ps
CPU time 9.03 seconds
Started Sep 04 02:15:11 AM UTC 24
Finished Sep 04 02:15:22 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734925933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1734925933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.264503766
Short name T140
Test name
Test status
Simulation time 2113646854 ps
CPU time 5.73 seconds
Started Sep 04 02:15:10 AM UTC 24
Finished Sep 04 02:15:17 AM UTC 24
Peak memory 209816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264503766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.264503766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1177776106
Short name T116
Test name
Test status
Simulation time 8897624499 ps
CPU time 11.46 seconds
Started Sep 04 02:15:16 AM UTC 24
Finished Sep 04 02:15:28 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177776106 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.1177776106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.4178135593
Short name T486
Test name
Test status
Simulation time 23750109325 ps
CPU time 5.35 seconds
Started Sep 04 02:15:15 AM UTC 24
Finished Sep 04 02:15:21 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4178135593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.4178135593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.4132222917
Short name T479
Test name
Test status
Simulation time 8268514594 ps
CPU time 3.04 seconds
Started Sep 04 02:15:13 AM UTC 24
Finished Sep 04 02:15:18 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132222917 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.4132222917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.53817233
Short name T497
Test name
Test status
Simulation time 2012843508 ps
CPU time 11.68 seconds
Started Sep 04 02:15:21 AM UTC 24
Finished Sep 04 02:15:34 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53817233 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.53817233
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1137944151
Short name T144
Test name
Test status
Simulation time 3439047503 ps
CPU time 9.5 seconds
Started Sep 04 02:15:18 AM UTC 24
Finished Sep 04 02:15:29 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137944151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1137944151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.1423264262
Short name T218
Test name
Test status
Simulation time 146367495179 ps
CPU time 110.54 seconds
Started Sep 04 02:15:19 AM UTC 24
Finished Sep 04 02:17:12 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423264262 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.1423264262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2993227809
Short name T125
Test name
Test status
Simulation time 53045662865 ps
CPU time 37.24 seconds
Started Sep 04 02:15:21 AM UTC 24
Finished Sep 04 02:15:59 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993227809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_with_pre_cond.2993227809
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.838907044
Short name T491
Test name
Test status
Simulation time 4118000267 ps
CPU time 5.89 seconds
Started Sep 04 02:15:18 AM UTC 24
Finished Sep 04 02:15:25 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838907044 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.838907044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3299586972
Short name T493
Test name
Test status
Simulation time 2609285989 ps
CPU time 8.71 seconds
Started Sep 04 02:15:18 AM UTC 24
Finished Sep 04 02:15:28 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299586972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.3299586972
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.1039507763
Short name T355
Test name
Test status
Simulation time 2469464937 ps
CPU time 12.37 seconds
Started Sep 04 02:15:18 AM UTC 24
Finished Sep 04 02:15:32 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039507763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1039507763
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.1565750209
Short name T487
Test name
Test status
Simulation time 2243954587 ps
CPU time 2.51 seconds
Started Sep 04 02:15:18 AM UTC 24
Finished Sep 04 02:15:22 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565750209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.1565750209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3696693438
Short name T489
Test name
Test status
Simulation time 2526685907 ps
CPU time 2.44 seconds
Started Sep 04 02:15:18 AM UTC 24
Finished Sep 04 02:15:22 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696693438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3696693438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.1317442797
Short name T485
Test name
Test status
Simulation time 2135734753 ps
CPU time 2.14 seconds
Started Sep 04 02:15:17 AM UTC 24
Finished Sep 04 02:15:20 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317442797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.1317442797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3905565604
Short name T435
Test name
Test status
Simulation time 78080050426 ps
CPU time 216.85 seconds
Started Sep 04 02:15:21 AM UTC 24
Finished Sep 04 02:19:01 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905565604 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.3905565604
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1304222484
Short name T337
Test name
Test status
Simulation time 6416852601 ps
CPU time 24.33 seconds
Started Sep 04 02:15:21 AM UTC 24
Finished Sep 04 02:15:46 AM UTC 24
Peak memory 222820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1304222484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.1304222484
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2665080401
Short name T111
Test name
Test status
Simulation time 3648188367 ps
CPU time 6.29 seconds
Started Sep 04 02:15:19 AM UTC 24
Finished Sep 04 02:15:27 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665080401 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.2665080401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.1283411606
Short name T149
Test name
Test status
Simulation time 2015427709 ps
CPU time 9.01 seconds
Started Sep 04 02:13:28 AM UTC 24
Finished Sep 04 02:13:38 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283411606 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.1283411606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1030647724
Short name T58
Test name
Test status
Simulation time 3183464303 ps
CPU time 12.49 seconds
Started Sep 04 02:13:20 AM UTC 24
Finished Sep 04 02:13:34 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030647724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1030647724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.1650919379
Short name T40
Test name
Test status
Simulation time 97199099889 ps
CPU time 61.32 seconds
Started Sep 04 02:13:21 AM UTC 24
Finished Sep 04 02:14:24 AM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650919379 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.1650919379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.4128409484
Short name T57
Test name
Test status
Simulation time 2169182635 ps
CPU time 5.67 seconds
Started Sep 04 02:13:17 AM UTC 24
Finished Sep 04 02:13:23 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128409484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.4128409484
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.829658405
Short name T28
Test name
Test status
Simulation time 2277835559 ps
CPU time 11.63 seconds
Started Sep 04 02:13:18 AM UTC 24
Finished Sep 04 02:13:31 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829658405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.829658405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.349031090
Short name T79
Test name
Test status
Simulation time 2831543784 ps
CPU time 2.8 seconds
Started Sep 04 02:13:20 AM UTC 24
Finished Sep 04 02:13:24 AM UTC 24
Peak memory 209704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349031090 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.349031090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.1610258516
Short name T11
Test name
Test status
Simulation time 3708090125 ps
CPU time 8.25 seconds
Started Sep 04 02:13:25 AM UTC 24
Finished Sep 04 02:13:34 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610258516 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.1610258516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2793609787
Short name T92
Test name
Test status
Simulation time 2614165813 ps
CPU time 9.36 seconds
Started Sep 04 02:13:20 AM UTC 24
Finished Sep 04 02:13:31 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793609787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.2793609787
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2084621075
Short name T23
Test name
Test status
Simulation time 2499237178 ps
CPU time 2.87 seconds
Started Sep 04 02:13:17 AM UTC 24
Finished Sep 04 02:13:21 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084621075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2084621075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.3956696770
Short name T182
Test name
Test status
Simulation time 2057020234 ps
CPU time 8.57 seconds
Started Sep 04 02:13:18 AM UTC 24
Finished Sep 04 02:13:28 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956696770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.3956696770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.1948578295
Short name T162
Test name
Test status
Simulation time 22030660209 ps
CPU time 29.23 seconds
Started Sep 04 02:13:25 AM UTC 24
Finished Sep 04 02:13:56 AM UTC 24
Peak memory 238300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948578295 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1948578295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.1439900961
Short name T181
Test name
Test status
Simulation time 2118697547 ps
CPU time 6.44 seconds
Started Sep 04 02:13:17 AM UTC 24
Finished Sep 04 02:13:24 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439900961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1439900961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.274286118
Short name T17
Test name
Test status
Simulation time 17559034299 ps
CPU time 15.81 seconds
Started Sep 04 02:13:25 AM UTC 24
Finished Sep 04 02:13:42 AM UTC 24
Peak memory 220412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=274286118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.274286118
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.1222725630
Short name T359
Test name
Test status
Simulation time 2038741457 ps
CPU time 3.83 seconds
Started Sep 04 02:15:28 AM UTC 24
Finished Sep 04 02:15:33 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222725630 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.1222725630
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2982421277
Short name T494
Test name
Test status
Simulation time 3379167761 ps
CPU time 4.38 seconds
Started Sep 04 02:15:23 AM UTC 24
Finished Sep 04 02:15:29 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982421277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.2982421277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.290143161
Short name T378
Test name
Test status
Simulation time 156857854474 ps
CPU time 93.91 seconds
Started Sep 04 02:15:24 AM UTC 24
Finished Sep 04 02:17:00 AM UTC 24
Peak memory 210484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290143161 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.290143161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3008050073
Short name T352
Test name
Test status
Simulation time 3220485344 ps
CPU time 6.43 seconds
Started Sep 04 02:15:22 AM UTC 24
Finished Sep 04 02:15:30 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008050073 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.3008050073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.4093550668
Short name T212
Test name
Test status
Simulation time 3835578494 ps
CPU time 5.47 seconds
Started Sep 04 02:15:25 AM UTC 24
Finished Sep 04 02:15:31 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093550668 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.4093550668
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3856308078
Short name T358
Test name
Test status
Simulation time 2608278833 ps
CPU time 8.75 seconds
Started Sep 04 02:15:22 AM UTC 24
Finished Sep 04 02:15:32 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856308078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.3856308078
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.1008912850
Short name T354
Test name
Test status
Simulation time 2461455153 ps
CPU time 7.2 seconds
Started Sep 04 02:15:22 AM UTC 24
Finished Sep 04 02:15:31 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008912850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1008912850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.227488335
Short name T492
Test name
Test status
Simulation time 2207867937 ps
CPU time 3.31 seconds
Started Sep 04 02:15:22 AM UTC 24
Finished Sep 04 02:15:27 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227488335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.227488335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.3761780554
Short name T353
Test name
Test status
Simulation time 2520847604 ps
CPU time 6.89 seconds
Started Sep 04 02:15:22 AM UTC 24
Finished Sep 04 02:15:30 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761780554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.3761780554
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.224247821
Short name T356
Test name
Test status
Simulation time 2110311580 ps
CPU time 9.55 seconds
Started Sep 04 02:15:21 AM UTC 24
Finished Sep 04 02:15:32 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224247821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.224247821
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.988933903
Short name T292
Test name
Test status
Simulation time 86246297153 ps
CPU time 186.15 seconds
Started Sep 04 02:15:28 AM UTC 24
Finished Sep 04 02:18:37 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988933903 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.988933903
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3410252702
Short name T336
Test name
Test status
Simulation time 5325048332 ps
CPU time 10.8 seconds
Started Sep 04 02:15:28 AM UTC 24
Finished Sep 04 02:15:40 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3410252702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.3410252702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.3475781442
Short name T448
Test name
Test status
Simulation time 158142161449 ps
CPU time 16.96 seconds
Started Sep 04 02:15:23 AM UTC 24
Finished Sep 04 02:15:42 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475781442 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.3475781442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.3783497405
Short name T501
Test name
Test status
Simulation time 2027111781 ps
CPU time 2.64 seconds
Started Sep 04 02:15:34 AM UTC 24
Finished Sep 04 02:15:38 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783497405 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.3783497405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1110514291
Short name T498
Test name
Test status
Simulation time 3136218586 ps
CPU time 3 seconds
Started Sep 04 02:15:31 AM UTC 24
Finished Sep 04 02:15:35 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110514291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1110514291
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.653754021
Short name T291
Test name
Test status
Simulation time 121554121922 ps
CPU time 112.93 seconds
Started Sep 04 02:15:33 AM UTC 24
Finished Sep 04 02:17:28 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653754021 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.653754021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1425774092
Short name T122
Test name
Test status
Simulation time 79340906833 ps
CPU time 13.9 seconds
Started Sep 04 02:15:33 AM UTC 24
Finished Sep 04 02:15:48 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425774092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.1425774092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2015337069
Short name T507
Test name
Test status
Simulation time 3845730307 ps
CPU time 12.49 seconds
Started Sep 04 02:15:30 AM UTC 24
Finished Sep 04 02:15:44 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015337069 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.2015337069
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.2779591687
Short name T169
Test name
Test status
Simulation time 4791040216 ps
CPU time 2.39 seconds
Started Sep 04 02:15:33 AM UTC 24
Finished Sep 04 02:15:36 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779591687 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.2779591687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3553096219
Short name T503
Test name
Test status
Simulation time 2607875094 ps
CPU time 9.29 seconds
Started Sep 04 02:15:30 AM UTC 24
Finished Sep 04 02:15:41 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553096219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.3553096219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.701933308
Short name T502
Test name
Test status
Simulation time 2436279267 ps
CPU time 7.71 seconds
Started Sep 04 02:15:29 AM UTC 24
Finished Sep 04 02:15:38 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701933308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.701933308
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1413207284
Short name T496
Test name
Test status
Simulation time 2094083959 ps
CPU time 2.28 seconds
Started Sep 04 02:15:30 AM UTC 24
Finished Sep 04 02:15:34 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413207284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1413207284
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.2071837467
Short name T499
Test name
Test status
Simulation time 2519971474 ps
CPU time 4.37 seconds
Started Sep 04 02:15:30 AM UTC 24
Finished Sep 04 02:15:36 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071837467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2071837467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.2023157407
Short name T495
Test name
Test status
Simulation time 2135366694 ps
CPU time 2.91 seconds
Started Sep 04 02:15:29 AM UTC 24
Finished Sep 04 02:15:33 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023157407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2023157407
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3933850313
Short name T151
Test name
Test status
Simulation time 11069713645 ps
CPU time 11.87 seconds
Started Sep 04 02:15:33 AM UTC 24
Finished Sep 04 02:15:46 AM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933850313 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.3933850313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1594690286
Short name T260
Test name
Test status
Simulation time 5652871520 ps
CPU time 20.71 seconds
Started Sep 04 02:15:33 AM UTC 24
Finished Sep 04 02:15:55 AM UTC 24
Peak memory 220804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1594690286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.1594690286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1535932031
Short name T340
Test name
Test status
Simulation time 2863578895 ps
CPU time 5.05 seconds
Started Sep 04 02:15:32 AM UTC 24
Finished Sep 04 02:15:38 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535932031 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.1535932031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.847778806
Short name T510
Test name
Test status
Simulation time 2026619277 ps
CPU time 5.44 seconds
Started Sep 04 02:15:42 AM UTC 24
Finished Sep 04 02:15:48 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847778806 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.847778806
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2374655234
Short name T505
Test name
Test status
Simulation time 3482366930 ps
CPU time 3.04 seconds
Started Sep 04 02:15:37 AM UTC 24
Finished Sep 04 02:15:42 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374655234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2374655234
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.2296084470
Short name T188
Test name
Test status
Simulation time 158533440424 ps
CPU time 129.56 seconds
Started Sep 04 02:15:39 AM UTC 24
Finished Sep 04 02:17:50 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296084470 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.2296084470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.503230498
Short name T411
Test name
Test status
Simulation time 311799309734 ps
CPU time 291.56 seconds
Started Sep 04 02:15:39 AM UTC 24
Finished Sep 04 02:20:34 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503230498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_with_pre_cond.503230498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.92847508
Short name T721
Test name
Test status
Simulation time 90152431520 ps
CPU time 201.6 seconds
Started Sep 04 02:15:37 AM UTC 24
Finished Sep 04 02:19:02 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92847508 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.92847508
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1514945166
Short name T170
Test name
Test status
Simulation time 3972394723 ps
CPU time 12.7 seconds
Started Sep 04 02:15:39 AM UTC 24
Finished Sep 04 02:15:53 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514945166 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.1514945166
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1978980048
Short name T506
Test name
Test status
Simulation time 2625778015 ps
CPU time 4.23 seconds
Started Sep 04 02:15:36 AM UTC 24
Finished Sep 04 02:15:42 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978980048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.1978980048
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3320643282
Short name T509
Test name
Test status
Simulation time 2444651315 ps
CPU time 10.75 seconds
Started Sep 04 02:15:34 AM UTC 24
Finished Sep 04 02:15:46 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320643282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3320643282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.2144482862
Short name T508
Test name
Test status
Simulation time 2223457686 ps
CPU time 10.3 seconds
Started Sep 04 02:15:35 AM UTC 24
Finished Sep 04 02:15:47 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144482862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.2144482862
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.47888888
Short name T504
Test name
Test status
Simulation time 2529392839 ps
CPU time 3.74 seconds
Started Sep 04 02:15:36 AM UTC 24
Finished Sep 04 02:15:41 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47888888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.47888888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.506459292
Short name T500
Test name
Test status
Simulation time 2122158999 ps
CPU time 2.3 seconds
Started Sep 04 02:15:34 AM UTC 24
Finished Sep 04 02:15:37 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506459292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.506459292
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.4117288736
Short name T251
Test name
Test status
Simulation time 11180694801 ps
CPU time 4.32 seconds
Started Sep 04 02:15:42 AM UTC 24
Finished Sep 04 02:15:47 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117288736 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.4117288736
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2598217881
Short name T255
Test name
Test status
Simulation time 3453112943 ps
CPU time 11.4 seconds
Started Sep 04 02:15:41 AM UTC 24
Finished Sep 04 02:15:53 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2598217881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2598217881
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2639236990
Short name T166
Test name
Test status
Simulation time 3395607426 ps
CPU time 3.52 seconds
Started Sep 04 02:15:39 AM UTC 24
Finished Sep 04 02:15:43 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639236990 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.2639236990
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.1897343796
Short name T254
Test name
Test status
Simulation time 2040921516 ps
CPU time 3.02 seconds
Started Sep 04 02:15:49 AM UTC 24
Finished Sep 04 02:15:53 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897343796 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.1897343796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2232805879
Short name T511
Test name
Test status
Simulation time 3626184255 ps
CPU time 2.03 seconds
Started Sep 04 02:15:46 AM UTC 24
Finished Sep 04 02:15:49 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232805879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2232805879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1384434971
Short name T172
Test name
Test status
Simulation time 3815655299 ps
CPU time 3.87 seconds
Started Sep 04 02:15:48 AM UTC 24
Finished Sep 04 02:15:53 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384434971 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.1384434971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3501365199
Short name T262
Test name
Test status
Simulation time 2611466974 ps
CPU time 11.4 seconds
Started Sep 04 02:15:44 AM UTC 24
Finished Sep 04 02:15:57 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501365199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.3501365199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.102501364
Short name T514
Test name
Test status
Simulation time 2460626924 ps
CPU time 7.94 seconds
Started Sep 04 02:15:42 AM UTC 24
Finished Sep 04 02:15:51 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102501364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.102501364
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.1335615636
Short name T256
Test name
Test status
Simulation time 2094232722 ps
CPU time 9.17 seconds
Started Sep 04 02:15:43 AM UTC 24
Finished Sep 04 02:15:53 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335615636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1335615636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.2995188969
Short name T512
Test name
Test status
Simulation time 2517699982 ps
CPU time 5.42 seconds
Started Sep 04 02:15:43 AM UTC 24
Finished Sep 04 02:15:50 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995188969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2995188969
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3798600274
Short name T513
Test name
Test status
Simulation time 2109774541 ps
CPU time 7.57 seconds
Started Sep 04 02:15:42 AM UTC 24
Finished Sep 04 02:15:51 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798600274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3798600274
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.4177823845
Short name T259
Test name
Test status
Simulation time 3363819423 ps
CPU time 6.8 seconds
Started Sep 04 02:15:47 AM UTC 24
Finished Sep 04 02:15:55 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177823845 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.4177823845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.2890834431
Short name T517
Test name
Test status
Simulation time 2092545394 ps
CPU time 1.96 seconds
Started Sep 04 02:15:55 AM UTC 24
Finished Sep 04 02:15:58 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890834431 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.2890834431
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2881262845
Short name T714
Test name
Test status
Simulation time 235488575635 ps
CPU time 181.83 seconds
Started Sep 04 02:15:54 AM UTC 24
Finished Sep 04 02:18:59 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881262845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2881262845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.3179013618
Short name T127
Test name
Test status
Simulation time 19548177635 ps
CPU time 54.14 seconds
Started Sep 04 02:15:54 AM UTC 24
Finished Sep 04 02:16:49 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179013618 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.3179013618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2022178759
Short name T299
Test name
Test status
Simulation time 25089395736 ps
CPU time 57.85 seconds
Started Sep 04 02:15:54 AM UTC 24
Finished Sep 04 02:16:53 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022178759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_with_pre_cond.2022178759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1192746337
Short name T521
Test name
Test status
Simulation time 4300547854 ps
CPU time 8.89 seconds
Started Sep 04 02:15:52 AM UTC 24
Finished Sep 04 02:16:02 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192746337 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.1192746337
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.628723010
Short name T515
Test name
Test status
Simulation time 2619652263 ps
CPU time 5.27 seconds
Started Sep 04 02:15:52 AM UTC 24
Finished Sep 04 02:15:58 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628723010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.628723010
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.1297902426
Short name T261
Test name
Test status
Simulation time 2484578299 ps
CPU time 4.51 seconds
Started Sep 04 02:15:49 AM UTC 24
Finished Sep 04 02:15:55 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297902426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.1297902426
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3330787938
Short name T258
Test name
Test status
Simulation time 2267159883 ps
CPU time 2.95 seconds
Started Sep 04 02:15:50 AM UTC 24
Finished Sep 04 02:15:54 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330787938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3330787938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2511944295
Short name T524
Test name
Test status
Simulation time 2512933731 ps
CPU time 9.5 seconds
Started Sep 04 02:15:52 AM UTC 24
Finished Sep 04 02:16:02 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511944295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2511944295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.2369294124
Short name T257
Test name
Test status
Simulation time 2118012238 ps
CPU time 3.54 seconds
Started Sep 04 02:15:49 AM UTC 24
Finished Sep 04 02:15:54 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369294124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.2369294124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.1762936693
Short name T529
Test name
Test status
Simulation time 7923035846 ps
CPU time 10.86 seconds
Started Sep 04 02:15:55 AM UTC 24
Finished Sep 04 02:16:07 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762936693 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.1762936693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2027211569
Short name T542
Test name
Test status
Simulation time 6258701845 ps
CPU time 19 seconds
Started Sep 04 02:15:55 AM UTC 24
Finished Sep 04 02:16:15 AM UTC 24
Peak memory 220464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2027211569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.2027211569
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.267944525
Short name T156
Test name
Test status
Simulation time 2685872273 ps
CPU time 6.43 seconds
Started Sep 04 02:15:54 AM UTC 24
Finished Sep 04 02:16:01 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267944525 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.267944525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2136420684
Short name T532
Test name
Test status
Simulation time 2020270678 ps
CPU time 4.7 seconds
Started Sep 04 02:16:03 AM UTC 24
Finished Sep 04 02:16:08 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136420684 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.2136420684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2869420961
Short name T523
Test name
Test status
Simulation time 3441061525 ps
CPU time 2.16 seconds
Started Sep 04 02:15:59 AM UTC 24
Finished Sep 04 02:16:02 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869420961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.2869420961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.1784283779
Short name T302
Test name
Test status
Simulation time 100407140352 ps
CPU time 70.02 seconds
Started Sep 04 02:15:59 AM UTC 24
Finished Sep 04 02:17:11 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784283779 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.1784283779
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3763987235
Short name T447
Test name
Test status
Simulation time 34000940939 ps
CPU time 121.28 seconds
Started Sep 04 02:16:00 AM UTC 24
Finished Sep 04 02:18:04 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763987235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_with_pre_cond.3763987235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.4065191959
Short name T533
Test name
Test status
Simulation time 3910669627 ps
CPU time 9.61 seconds
Started Sep 04 02:15:58 AM UTC 24
Finished Sep 04 02:16:09 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065191959 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.4065191959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.2068947658
Short name T538
Test name
Test status
Simulation time 2884878940 ps
CPU time 11.8 seconds
Started Sep 04 02:16:00 AM UTC 24
Finished Sep 04 02:16:13 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068947658 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.2068947658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.2538072384
Short name T531
Test name
Test status
Simulation time 2612943426 ps
CPU time 9.07 seconds
Started Sep 04 02:15:58 AM UTC 24
Finished Sep 04 02:16:08 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538072384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.2538072384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.1159569251
Short name T519
Test name
Test status
Simulation time 2467269964 ps
CPU time 4.46 seconds
Started Sep 04 02:15:55 AM UTC 24
Finished Sep 04 02:16:01 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159569251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1159569251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.4134971968
Short name T520
Test name
Test status
Simulation time 2048251297 ps
CPU time 3.66 seconds
Started Sep 04 02:15:57 AM UTC 24
Finished Sep 04 02:16:01 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134971968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.4134971968
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.1933037666
Short name T518
Test name
Test status
Simulation time 2533078211 ps
CPU time 2.48 seconds
Started Sep 04 02:15:57 AM UTC 24
Finished Sep 04 02:16:00 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933037666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.1933037666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.3278465329
Short name T522
Test name
Test status
Simulation time 2112261687 ps
CPU time 5.51 seconds
Started Sep 04 02:15:55 AM UTC 24
Finished Sep 04 02:16:02 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278465329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.3278465329
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.1905326112
Short name T539
Test name
Test status
Simulation time 12183554195 ps
CPU time 10.88 seconds
Started Sep 04 02:16:01 AM UTC 24
Finished Sep 04 02:16:13 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905326112 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.1905326112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3628768945
Short name T541
Test name
Test status
Simulation time 6194952030 ps
CPU time 11.76 seconds
Started Sep 04 02:16:01 AM UTC 24
Finished Sep 04 02:16:14 AM UTC 24
Peak memory 209728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3628768945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.3628768945
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3461296564
Short name T525
Test name
Test status
Simulation time 2888198538 ps
CPU time 5.57 seconds
Started Sep 04 02:15:59 AM UTC 24
Finished Sep 04 02:16:06 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461296564 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.3461296564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.450974388
Short name T537
Test name
Test status
Simulation time 2015794023 ps
CPU time 3.48 seconds
Started Sep 04 02:16:09 AM UTC 24
Finished Sep 04 02:16:13 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450974388 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.450974388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3456626976
Short name T551
Test name
Test status
Simulation time 3353867389 ps
CPU time 12.53 seconds
Started Sep 04 02:16:06 AM UTC 24
Finished Sep 04 02:16:20 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456626976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.3456626976
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2200976489
Short name T528
Test name
Test status
Simulation time 3457621711 ps
CPU time 1.8 seconds
Started Sep 04 02:16:04 AM UTC 24
Finished Sep 04 02:16:07 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200976489 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.2200976489
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1031128810
Short name T173
Test name
Test status
Simulation time 5718706123 ps
CPU time 4.15 seconds
Started Sep 04 02:16:07 AM UTC 24
Finished Sep 04 02:16:13 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031128810 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.1031128810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3769116097
Short name T527
Test name
Test status
Simulation time 2638209573 ps
CPU time 2.87 seconds
Started Sep 04 02:16:03 AM UTC 24
Finished Sep 04 02:16:07 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769116097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3769116097
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.4152335347
Short name T534
Test name
Test status
Simulation time 2469930921 ps
CPU time 5.83 seconds
Started Sep 04 02:16:03 AM UTC 24
Finished Sep 04 02:16:10 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152335347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.4152335347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1449537453
Short name T526
Test name
Test status
Simulation time 2144810596 ps
CPU time 2.3 seconds
Started Sep 04 02:16:03 AM UTC 24
Finished Sep 04 02:16:06 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449537453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.1449537453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.2638394947
Short name T530
Test name
Test status
Simulation time 2527017536 ps
CPU time 3.93 seconds
Started Sep 04 02:16:03 AM UTC 24
Finished Sep 04 02:16:08 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638394947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.2638394947
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2827848713
Short name T535
Test name
Test status
Simulation time 2117554709 ps
CPU time 6.24 seconds
Started Sep 04 02:16:03 AM UTC 24
Finished Sep 04 02:16:10 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827848713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.2827848713
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.1532918791
Short name T559
Test name
Test status
Simulation time 11121961772 ps
CPU time 29.68 seconds
Started Sep 04 02:16:09 AM UTC 24
Finished Sep 04 02:16:40 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532918791 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.1532918791
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.754652522
Short name T547
Test name
Test status
Simulation time 3035004244 ps
CPU time 10.92 seconds
Started Sep 04 02:16:07 AM UTC 24
Finished Sep 04 02:16:19 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754652522 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.754652522
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.1627659930
Short name T554
Test name
Test status
Simulation time 2015514140 ps
CPU time 5.84 seconds
Started Sep 04 02:16:17 AM UTC 24
Finished Sep 04 02:16:24 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627659930 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.1627659930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2168092786
Short name T549
Test name
Test status
Simulation time 3281853219 ps
CPU time 5.36 seconds
Started Sep 04 02:16:13 AM UTC 24
Finished Sep 04 02:16:20 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168092786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2168092786
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1700077056
Short name T767
Test name
Test status
Simulation time 154399473215 ps
CPU time 250.69 seconds
Started Sep 04 02:16:14 AM UTC 24
Finished Sep 04 02:20:28 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700077056 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.1700077056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2874754117
Short name T406
Test name
Test status
Simulation time 82692176800 ps
CPU time 59.65 seconds
Started Sep 04 02:16:15 AM UTC 24
Finished Sep 04 02:17:16 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874754117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.2874754117
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3182524089
Short name T546
Test name
Test status
Simulation time 3715574564 ps
CPU time 4.5 seconds
Started Sep 04 02:16:13 AM UTC 24
Finished Sep 04 02:16:19 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182524089 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.3182524089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.345060730
Short name T193
Test name
Test status
Simulation time 3591514799 ps
CPU time 4.85 seconds
Started Sep 04 02:16:14 AM UTC 24
Finished Sep 04 02:16:20 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345060730 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.345060730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.813018827
Short name T548
Test name
Test status
Simulation time 2614411377 ps
CPU time 7.39 seconds
Started Sep 04 02:16:11 AM UTC 24
Finished Sep 04 02:16:19 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813018827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.813018827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.2163613543
Short name T540
Test name
Test status
Simulation time 2462444168 ps
CPU time 3.12 seconds
Started Sep 04 02:16:10 AM UTC 24
Finished Sep 04 02:16:14 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163613543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2163613543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.586836032
Short name T536
Test name
Test status
Simulation time 2084997431 ps
CPU time 1.66 seconds
Started Sep 04 02:16:10 AM UTC 24
Finished Sep 04 02:16:12 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586836032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.586836032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.4147573108
Short name T545
Test name
Test status
Simulation time 2514300158 ps
CPU time 7.42 seconds
Started Sep 04 02:16:10 AM UTC 24
Finished Sep 04 02:16:18 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147573108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.4147573108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.2142560453
Short name T550
Test name
Test status
Simulation time 2114971185 ps
CPU time 9.92 seconds
Started Sep 04 02:16:09 AM UTC 24
Finished Sep 04 02:16:20 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142560453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.2142560453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3544984147
Short name T216
Test name
Test status
Simulation time 4591194935 ps
CPU time 13.08 seconds
Started Sep 04 02:16:16 AM UTC 24
Finished Sep 04 02:16:30 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3544984147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.3544984147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2429099738
Short name T543
Test name
Test status
Simulation time 3554556644 ps
CPU time 2.37 seconds
Started Sep 04 02:16:14 AM UTC 24
Finished Sep 04 02:16:18 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429099738 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.2429099738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2646872677
Short name T222
Test name
Test status
Simulation time 2013134089 ps
CPU time 8.11 seconds
Started Sep 04 02:16:25 AM UTC 24
Finished Sep 04 02:16:34 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646872677 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.2646872677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.1719322873
Short name T129
Test name
Test status
Simulation time 33980534995 ps
CPU time 114.24 seconds
Started Sep 04 02:16:21 AM UTC 24
Finished Sep 04 02:18:18 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719322873 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.1719322873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1534180538
Short name T394
Test name
Test status
Simulation time 48302981742 ps
CPU time 115.86 seconds
Started Sep 04 02:16:23 AM UTC 24
Finished Sep 04 02:18:20 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534180538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.1534180538
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2992863798
Short name T553
Test name
Test status
Simulation time 2656296548 ps
CPU time 2.13 seconds
Started Sep 04 02:16:20 AM UTC 24
Finished Sep 04 02:16:23 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992863798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2992863798
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.2156500428
Short name T555
Test name
Test status
Simulation time 2456420279 ps
CPU time 4.86 seconds
Started Sep 04 02:16:19 AM UTC 24
Finished Sep 04 02:16:25 AM UTC 24
Peak memory 209712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156500428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.2156500428
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.4195573724
Short name T516
Test name
Test status
Simulation time 2229338649 ps
CPU time 6.01 seconds
Started Sep 04 02:16:19 AM UTC 24
Finished Sep 04 02:16:26 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195573724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.4195573724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.2810107587
Short name T217
Test name
Test status
Simulation time 2512717009 ps
CPU time 8.61 seconds
Started Sep 04 02:16:20 AM UTC 24
Finished Sep 04 02:16:30 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810107587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2810107587
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.2485752439
Short name T552
Test name
Test status
Simulation time 2123583226 ps
CPU time 2.02 seconds
Started Sep 04 02:16:19 AM UTC 24
Finished Sep 04 02:16:22 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485752439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.2485752439
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.2106534429
Short name T437
Test name
Test status
Simulation time 88289329000 ps
CPU time 236.06 seconds
Started Sep 04 02:16:24 AM UTC 24
Finished Sep 04 02:20:23 AM UTC 24
Peak memory 210232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106534429 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.2106534429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3149083108
Short name T557
Test name
Test status
Simulation time 8518972899 ps
CPU time 13.99 seconds
Started Sep 04 02:16:24 AM UTC 24
Finished Sep 04 02:16:39 AM UTC 24
Peak memory 226616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3149083108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.3149083108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2139667558
Short name T219
Test name
Test status
Simulation time 4401591563 ps
CPU time 9.94 seconds
Started Sep 04 02:16:20 AM UTC 24
Finished Sep 04 02:16:31 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139667558 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.2139667558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.744134978
Short name T558
Test name
Test status
Simulation time 2039470658 ps
CPU time 3.06 seconds
Started Sep 04 02:16:35 AM UTC 24
Finished Sep 04 02:16:39 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744134978 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.744134978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2410609835
Short name T563
Test name
Test status
Simulation time 3682438662 ps
CPU time 10.79 seconds
Started Sep 04 02:16:30 AM UTC 24
Finished Sep 04 02:16:42 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410609835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.2410609835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1385776641
Short name T290
Test name
Test status
Simulation time 24919835927 ps
CPU time 19.35 seconds
Started Sep 04 02:16:31 AM UTC 24
Finished Sep 04 02:16:51 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385776641 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.1385776641
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.4220932608
Short name T423
Test name
Test status
Simulation time 97868583140 ps
CPU time 314.03 seconds
Started Sep 04 02:16:32 AM UTC 24
Finished Sep 04 02:21:50 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220932608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.4220932608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.4012850110
Short name T556
Test name
Test status
Simulation time 2548352802 ps
CPU time 7.11 seconds
Started Sep 04 02:16:29 AM UTC 24
Finished Sep 04 02:16:38 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012850110 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.4012850110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1488781956
Short name T562
Test name
Test status
Simulation time 3233352693 ps
CPU time 9.19 seconds
Started Sep 04 02:16:32 AM UTC 24
Finished Sep 04 02:16:42 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488781956 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.1488781956
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2657607622
Short name T224
Test name
Test status
Simulation time 2620520771 ps
CPU time 5.39 seconds
Started Sep 04 02:16:29 AM UTC 24
Finished Sep 04 02:16:36 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657607622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.2657607622
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.3286679941
Short name T221
Test name
Test status
Simulation time 2464792037 ps
CPU time 6.17 seconds
Started Sep 04 02:16:26 AM UTC 24
Finished Sep 04 02:16:33 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286679941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.3286679941
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.3354609850
Short name T223
Test name
Test status
Simulation time 2032333685 ps
CPU time 6.29 seconds
Started Sep 04 02:16:27 AM UTC 24
Finished Sep 04 02:16:34 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354609850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.3354609850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.298236653
Short name T220
Test name
Test status
Simulation time 2532549048 ps
CPU time 3.94 seconds
Started Sep 04 02:16:28 AM UTC 24
Finished Sep 04 02:16:33 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298236653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.298236653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.80275510
Short name T544
Test name
Test status
Simulation time 2123692316 ps
CPU time 2.35 seconds
Started Sep 04 02:16:26 AM UTC 24
Finished Sep 04 02:16:29 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80275510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.80275510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.619576782
Short name T560
Test name
Test status
Simulation time 9131928803 ps
CPU time 5.68 seconds
Started Sep 04 02:16:34 AM UTC 24
Finished Sep 04 02:16:41 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619576782 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.619576782
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2553541221
Short name T574
Test name
Test status
Simulation time 4413011863 ps
CPU time 16.11 seconds
Started Sep 04 02:16:34 AM UTC 24
Finished Sep 04 02:16:51 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2553541221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2553541221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2839188768
Short name T60
Test name
Test status
Simulation time 3395572457 ps
CPU time 6.67 seconds
Started Sep 04 02:13:35 AM UTC 24
Finished Sep 04 02:13:42 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839188768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.2839188768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1988321428
Short name T32
Test name
Test status
Simulation time 37893574286 ps
CPU time 9.41 seconds
Started Sep 04 02:13:35 AM UTC 24
Finished Sep 04 02:13:45 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988321428 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.1988321428
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3501061652
Short name T59
Test name
Test status
Simulation time 2160094455 ps
CPU time 9.25 seconds
Started Sep 04 02:13:30 AM UTC 24
Finished Sep 04 02:13:41 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501061652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.3501061652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4074593749
Short name T12
Test name
Test status
Simulation time 2552680250 ps
CPU time 5.06 seconds
Started Sep 04 02:13:31 AM UTC 24
Finished Sep 04 02:13:38 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074593749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4074593749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.275179281
Short name T30
Test name
Test status
Simulation time 35819054156 ps
CPU time 30.4 seconds
Started Sep 04 02:13:36 AM UTC 24
Finished Sep 04 02:14:08 AM UTC 24
Peak memory 210328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275179281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with_pre_cond.275179281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2398441322
Short name T150
Test name
Test status
Simulation time 3251410054 ps
CPU time 3.63 seconds
Started Sep 04 02:13:34 AM UTC 24
Finished Sep 04 02:13:39 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398441322 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.2398441322
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.656999671
Short name T798
Test name
Test status
Simulation time 483387703401 ps
CPU time 1326.6 seconds
Started Sep 04 02:13:36 AM UTC 24
Finished Sep 04 02:35:56 AM UTC 24
Peak memory 212524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656999671 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.656999671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.1475473972
Short name T94
Test name
Test status
Simulation time 2614970648 ps
CPU time 7.33 seconds
Started Sep 04 02:13:34 AM UTC 24
Finished Sep 04 02:13:43 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475473972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.1475473972
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.245589857
Short name T82
Test name
Test status
Simulation time 2488013279 ps
CPU time 2.62 seconds
Started Sep 04 02:13:29 AM UTC 24
Finished Sep 04 02:13:33 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245589857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.245589857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2786759731
Short name T147
Test name
Test status
Simulation time 2104530654 ps
CPU time 2.46 seconds
Started Sep 04 02:13:31 AM UTC 24
Finished Sep 04 02:13:35 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786759731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2786759731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.3926970620
Short name T93
Test name
Test status
Simulation time 2514626888 ps
CPU time 8.26 seconds
Started Sep 04 02:13:31 AM UTC 24
Finished Sep 04 02:13:41 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926970620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.3926970620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3660066277
Short name T314
Test name
Test status
Simulation time 42184813611 ps
CPU time 62.16 seconds
Started Sep 04 02:13:38 AM UTC 24
Finished Sep 04 02:14:42 AM UTC 24
Peak memory 240284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660066277 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3660066277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.716118751
Short name T335
Test name
Test status
Simulation time 2131087256 ps
CPU time 3 seconds
Started Sep 04 02:13:29 AM UTC 24
Finished Sep 04 02:13:33 AM UTC 24
Peak memory 209700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716118751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.716118751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3476997835
Short name T161
Test name
Test status
Simulation time 9114642732 ps
CPU time 17.61 seconds
Started Sep 04 02:13:36 AM UTC 24
Finished Sep 04 02:13:55 AM UTC 24
Peak memory 226668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3476997835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.3476997835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.2695840192
Short name T570
Test name
Test status
Simulation time 2029237368 ps
CPU time 3.27 seconds
Started Sep 04 02:16:44 AM UTC 24
Finished Sep 04 02:16:48 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695840192 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.2695840192
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.318768834
Short name T587
Test name
Test status
Simulation time 4018143688 ps
CPU time 18.3 seconds
Started Sep 04 02:16:41 AM UTC 24
Finished Sep 04 02:17:00 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318768834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.318768834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1006462459
Short name T387
Test name
Test status
Simulation time 47916489162 ps
CPU time 127.78 seconds
Started Sep 04 02:16:43 AM UTC 24
Finished Sep 04 02:18:53 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006462459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_with_pre_cond.1006462459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3663329919
Short name T568
Test name
Test status
Simulation time 2544544716 ps
CPU time 4.51 seconds
Started Sep 04 02:16:39 AM UTC 24
Finished Sep 04 02:16:45 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663329919 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.3663329919
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.3573701829
Short name T174
Test name
Test status
Simulation time 3225555281 ps
CPU time 5.72 seconds
Started Sep 04 02:16:42 AM UTC 24
Finished Sep 04 02:16:48 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573701829 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.3573701829
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1410966798
Short name T566
Test name
Test status
Simulation time 2620913599 ps
CPU time 3.66 seconds
Started Sep 04 02:16:39 AM UTC 24
Finished Sep 04 02:16:44 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410966798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1410966798
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.2071814933
Short name T564
Test name
Test status
Simulation time 2473468124 ps
CPU time 5.42 seconds
Started Sep 04 02:16:36 AM UTC 24
Finished Sep 04 02:16:43 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071814933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.2071814933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.516207087
Short name T565
Test name
Test status
Simulation time 2270006778 ps
CPU time 4.15 seconds
Started Sep 04 02:16:38 AM UTC 24
Finished Sep 04 02:16:43 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516207087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.516207087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3453423413
Short name T567
Test name
Test status
Simulation time 2535943334 ps
CPU time 3.64 seconds
Started Sep 04 02:16:39 AM UTC 24
Finished Sep 04 02:16:44 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453423413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3453423413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1188864637
Short name T561
Test name
Test status
Simulation time 2118223448 ps
CPU time 5.64 seconds
Started Sep 04 02:16:35 AM UTC 24
Finished Sep 04 02:16:42 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188864637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1188864637
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1549530073
Short name T612
Test name
Test status
Simulation time 11379907366 ps
CPU time 38.16 seconds
Started Sep 04 02:16:43 AM UTC 24
Finished Sep 04 02:17:22 AM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549530073 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.1549530073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.126899163
Short name T583
Test name
Test status
Simulation time 4668355069 ps
CPU time 14.54 seconds
Started Sep 04 02:16:43 AM UTC 24
Finished Sep 04 02:16:59 AM UTC 24
Peak memory 209148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=126899163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.126899163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2206287660
Short name T157
Test name
Test status
Simulation time 4388884135 ps
CPU time 5.07 seconds
Started Sep 04 02:16:42 AM UTC 24
Finished Sep 04 02:16:48 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206287660 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.2206287660
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3037853688
Short name T589
Test name
Test status
Simulation time 2011268066 ps
CPU time 9.76 seconds
Started Sep 04 02:16:51 AM UTC 24
Finished Sep 04 02:17:02 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037853688 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.3037853688
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3283672839
Short name T576
Test name
Test status
Simulation time 3191689317 ps
CPU time 2.61 seconds
Started Sep 04 02:16:49 AM UTC 24
Finished Sep 04 02:16:52 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283672839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3283672839
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.3231613143
Short name T434
Test name
Test status
Simulation time 182513023562 ps
CPU time 465.48 seconds
Started Sep 04 02:16:50 AM UTC 24
Finished Sep 04 02:24:41 AM UTC 24
Peak memory 213092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231613143 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.3231613143
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4124645373
Short name T424
Test name
Test status
Simulation time 65969654151 ps
CPU time 28.71 seconds
Started Sep 04 02:16:50 AM UTC 24
Finished Sep 04 02:17:20 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124645373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.4124645373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.4179713365
Short name T591
Test name
Test status
Simulation time 3238777587 ps
CPU time 15.51 seconds
Started Sep 04 02:16:48 AM UTC 24
Finished Sep 04 02:17:04 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179713365 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.4179713365
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3551227211
Short name T175
Test name
Test status
Simulation time 3852129867 ps
CPU time 11.37 seconds
Started Sep 04 02:16:50 AM UTC 24
Finished Sep 04 02:17:03 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551227211 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.3551227211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.731011188
Short name T572
Test name
Test status
Simulation time 2643010797 ps
CPU time 2.23 seconds
Started Sep 04 02:16:46 AM UTC 24
Finished Sep 04 02:16:50 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731011188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.731011188
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.4288287363
Short name T577
Test name
Test status
Simulation time 2452346864 ps
CPU time 8.3 seconds
Started Sep 04 02:16:45 AM UTC 24
Finished Sep 04 02:16:55 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288287363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.4288287363
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1743984302
Short name T573
Test name
Test status
Simulation time 2101631370 ps
CPU time 3.87 seconds
Started Sep 04 02:16:45 AM UTC 24
Finished Sep 04 02:16:50 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743984302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1743984302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.1356664776
Short name T578
Test name
Test status
Simulation time 2510361742 ps
CPU time 9.04 seconds
Started Sep 04 02:16:45 AM UTC 24
Finished Sep 04 02:16:55 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356664776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.1356664776
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.2411557182
Short name T569
Test name
Test status
Simulation time 2144346679 ps
CPU time 2 seconds
Started Sep 04 02:16:44 AM UTC 24
Finished Sep 04 02:16:47 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411557182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.2411557182
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2945752422
Short name T732
Test name
Test status
Simulation time 153996556393 ps
CPU time 136.47 seconds
Started Sep 04 02:16:51 AM UTC 24
Finished Sep 04 02:19:10 AM UTC 24
Peak memory 210416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945752422 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.2945752422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.484521759
Short name T585
Test name
Test status
Simulation time 2100262131 ps
CPU time 6.88 seconds
Started Sep 04 02:16:51 AM UTC 24
Finished Sep 04 02:16:59 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=484521759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.484521759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.710751181
Short name T575
Test name
Test status
Simulation time 6246412614 ps
CPU time 1.82 seconds
Started Sep 04 02:16:49 AM UTC 24
Finished Sep 04 02:16:52 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710751181 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.710751181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.807778202
Short name T594
Test name
Test status
Simulation time 2012850737 ps
CPU time 7.96 seconds
Started Sep 04 02:16:59 AM UTC 24
Finished Sep 04 02:17:08 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807778202 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.807778202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.528033657
Short name T598
Test name
Test status
Simulation time 3498552573 ps
CPU time 14.37 seconds
Started Sep 04 02:16:56 AM UTC 24
Finished Sep 04 02:17:11 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528033657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.528033657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.1943858527
Short name T791
Test name
Test status
Simulation time 142792461819 ps
CPU time 402.04 seconds
Started Sep 04 02:16:58 AM UTC 24
Finished Sep 04 02:23:45 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943858527 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.1943858527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2865780819
Short name T183
Test name
Test status
Simulation time 59592404182 ps
CPU time 49.77 seconds
Started Sep 04 02:16:58 AM UTC 24
Finished Sep 04 02:17:49 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865780819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.2865780819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1951873671
Short name T584
Test name
Test status
Simulation time 3602610891 ps
CPU time 2.88 seconds
Started Sep 04 02:16:55 AM UTC 24
Finished Sep 04 02:16:59 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951873671 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.1951873671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.11414137
Short name T588
Test name
Test status
Simulation time 2620626106 ps
CPU time 1.88 seconds
Started Sep 04 02:16:58 AM UTC 24
Finished Sep 04 02:17:01 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11414137 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.11414137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3303009224
Short name T586
Test name
Test status
Simulation time 2631346412 ps
CPU time 4.11 seconds
Started Sep 04 02:16:54 AM UTC 24
Finished Sep 04 02:16:59 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303009224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3303009224
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.3044844632
Short name T580
Test name
Test status
Simulation time 2466456882 ps
CPU time 3.82 seconds
Started Sep 04 02:16:52 AM UTC 24
Finished Sep 04 02:16:57 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044844632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3044844632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.574189008
Short name T579
Test name
Test status
Simulation time 2117916989 ps
CPU time 3.29 seconds
Started Sep 04 02:16:52 AM UTC 24
Finished Sep 04 02:16:57 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574189008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.574189008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2272065040
Short name T581
Test name
Test status
Simulation time 2519099902 ps
CPU time 4.09 seconds
Started Sep 04 02:16:52 AM UTC 24
Finished Sep 04 02:16:58 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272065040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2272065040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.2087896478
Short name T582
Test name
Test status
Simulation time 2112036643 ps
CPU time 6.15 seconds
Started Sep 04 02:16:51 AM UTC 24
Finished Sep 04 02:16:58 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087896478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2087896478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.902665916
Short name T395
Test name
Test status
Simulation time 94964648077 ps
CPU time 89.26 seconds
Started Sep 04 02:16:59 AM UTC 24
Finished Sep 04 02:18:30 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902665916 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.902665916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3767930556
Short name T601
Test name
Test status
Simulation time 5182092180 ps
CPU time 13.17 seconds
Started Sep 04 02:16:59 AM UTC 24
Finished Sep 04 02:17:14 AM UTC 24
Peak memory 220396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3767930556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.3767930556
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1672077173
Short name T159
Test name
Test status
Simulation time 915773571348 ps
CPU time 199.85 seconds
Started Sep 04 02:16:56 AM UTC 24
Finished Sep 04 02:20:19 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672077173 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.1672077173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.676696188
Short name T609
Test name
Test status
Simulation time 2014636732 ps
CPU time 9.31 seconds
Started Sep 04 02:17:09 AM UTC 24
Finished Sep 04 02:17:20 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676696188 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.676696188
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.477235980
Short name T596
Test name
Test status
Simulation time 9026183988 ps
CPU time 5.92 seconds
Started Sep 04 02:17:03 AM UTC 24
Finished Sep 04 02:17:10 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477235980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.477235980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.1790897199
Short name T392
Test name
Test status
Simulation time 118532092534 ps
CPU time 371.71 seconds
Started Sep 04 02:17:05 AM UTC 24
Finished Sep 04 02:23:21 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790897199 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.1790897199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3757785642
Short name T597
Test name
Test status
Simulation time 3562237301 ps
CPU time 7.07 seconds
Started Sep 04 02:17:02 AM UTC 24
Finished Sep 04 02:17:10 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757785642 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.3757785642
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.551414979
Short name T605
Test name
Test status
Simulation time 2362883423 ps
CPU time 11.33 seconds
Started Sep 04 02:17:05 AM UTC 24
Finished Sep 04 02:17:17 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551414979 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.551414979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1845870894
Short name T599
Test name
Test status
Simulation time 2612999173 ps
CPU time 9.64 seconds
Started Sep 04 02:17:01 AM UTC 24
Finished Sep 04 02:17:11 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845870894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.1845870894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.2647405812
Short name T595
Test name
Test status
Simulation time 2456504076 ps
CPU time 7.17 seconds
Started Sep 04 02:17:00 AM UTC 24
Finished Sep 04 02:17:09 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647405812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2647405812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2037938328
Short name T593
Test name
Test status
Simulation time 2209566916 ps
CPU time 6.2 seconds
Started Sep 04 02:17:01 AM UTC 24
Finished Sep 04 02:17:08 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037938328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.2037938328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.1628540428
Short name T600
Test name
Test status
Simulation time 2510729564 ps
CPU time 11.64 seconds
Started Sep 04 02:17:01 AM UTC 24
Finished Sep 04 02:17:13 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628540428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1628540428
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1792392451
Short name T590
Test name
Test status
Simulation time 2118988641 ps
CPU time 3.22 seconds
Started Sep 04 02:16:59 AM UTC 24
Finished Sep 04 02:17:04 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792392451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1792392451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1941162295
Short name T797
Test name
Test status
Simulation time 156833661235 ps
CPU time 510.01 seconds
Started Sep 04 02:17:08 AM UTC 24
Finished Sep 04 02:25:44 AM UTC 24
Peak memory 212824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941162295 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.1941162295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2655586020
Short name T320
Test name
Test status
Simulation time 10934147964 ps
CPU time 8.18 seconds
Started Sep 04 02:17:08 AM UTC 24
Finished Sep 04 02:17:18 AM UTC 24
Peak memory 220536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2655586020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.2655586020
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1299811985
Short name T592
Test name
Test status
Simulation time 3111968733 ps
CPU time 2.62 seconds
Started Sep 04 02:17:04 AM UTC 24
Finished Sep 04 02:17:08 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299811985 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.1299811985
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.3952882767
Short name T607
Test name
Test status
Simulation time 2029896827 ps
CPU time 3.17 seconds
Started Sep 04 02:17:15 AM UTC 24
Finished Sep 04 02:17:19 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952882767 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.3952882767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.968945355
Short name T613
Test name
Test status
Simulation time 3516885070 ps
CPU time 8.74 seconds
Started Sep 04 02:17:13 AM UTC 24
Finished Sep 04 02:17:23 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968945355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.968945355
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1492370250
Short name T293
Test name
Test status
Simulation time 31615048646 ps
CPU time 90.6 seconds
Started Sep 04 02:17:13 AM UTC 24
Finished Sep 04 02:18:46 AM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492370250 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.1492370250
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2516956418
Short name T617
Test name
Test status
Simulation time 3634024975 ps
CPU time 12.24 seconds
Started Sep 04 02:17:13 AM UTC 24
Finished Sep 04 02:17:26 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516956418 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.2516956418
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.773657294
Short name T604
Test name
Test status
Simulation time 2631238940 ps
CPU time 3.86 seconds
Started Sep 04 02:17:12 AM UTC 24
Finished Sep 04 02:17:17 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773657294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.773657294
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.4215266151
Short name T614
Test name
Test status
Simulation time 2440252145 ps
CPU time 12.71 seconds
Started Sep 04 02:17:09 AM UTC 24
Finished Sep 04 02:17:24 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215266151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.4215266151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.2870419598
Short name T603
Test name
Test status
Simulation time 2096751915 ps
CPU time 3.18 seconds
Started Sep 04 02:17:11 AM UTC 24
Finished Sep 04 02:17:15 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870419598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2870419598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.1701656073
Short name T606
Test name
Test status
Simulation time 2510774755 ps
CPU time 6.74 seconds
Started Sep 04 02:17:11 AM UTC 24
Finished Sep 04 02:17:19 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701656073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.1701656073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.2582246418
Short name T602
Test name
Test status
Simulation time 2130130455 ps
CPU time 3.46 seconds
Started Sep 04 02:17:09 AM UTC 24
Finished Sep 04 02:17:14 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582246418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.2582246418
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.750595122
Short name T214
Test name
Test status
Simulation time 14564167519 ps
CPU time 21.67 seconds
Started Sep 04 02:17:15 AM UTC 24
Finished Sep 04 02:17:38 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750595122 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.750595122
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1396431360
Short name T128
Test name
Test status
Simulation time 18569572546 ps
CPU time 15 seconds
Started Sep 04 02:17:14 AM UTC 24
Finished Sep 04 02:17:30 AM UTC 24
Peak memory 220548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1396431360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.1396431360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1804410572
Short name T610
Test name
Test status
Simulation time 4894372087 ps
CPU time 6.18 seconds
Started Sep 04 02:17:13 AM UTC 24
Finished Sep 04 02:17:20 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804410572 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.1804410572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.2552086243
Short name T621
Test name
Test status
Simulation time 2016376118 ps
CPU time 5.4 seconds
Started Sep 04 02:17:24 AM UTC 24
Finished Sep 04 02:17:30 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552086243 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.2552086243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.770836737
Short name T625
Test name
Test status
Simulation time 3538078900 ps
CPU time 12.12 seconds
Started Sep 04 02:17:20 AM UTC 24
Finished Sep 04 02:17:33 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770836737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.770836737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2081789108
Short name T303
Test name
Test status
Simulation time 55021003383 ps
CPU time 43.11 seconds
Started Sep 04 02:17:21 AM UTC 24
Finished Sep 04 02:18:06 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081789108 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.2081789108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3791600513
Short name T417
Test name
Test status
Simulation time 103719283771 ps
CPU time 76.29 seconds
Started Sep 04 02:17:21 AM UTC 24
Finished Sep 04 02:18:39 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791600513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.3791600513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2810055868
Short name T622
Test name
Test status
Simulation time 3331283880 ps
CPU time 9.89 seconds
Started Sep 04 02:17:20 AM UTC 24
Finished Sep 04 02:17:31 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810055868 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.2810055868
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.3665638663
Short name T213
Test name
Test status
Simulation time 3793482565 ps
CPU time 8.2 seconds
Started Sep 04 02:17:21 AM UTC 24
Finished Sep 04 02:17:30 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665638663 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.3665638663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2811222072
Short name T619
Test name
Test status
Simulation time 2610066754 ps
CPU time 7.18 seconds
Started Sep 04 02:17:20 AM UTC 24
Finished Sep 04 02:17:28 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811222072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2811222072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.1530246406
Short name T611
Test name
Test status
Simulation time 2503164298 ps
CPU time 2.17 seconds
Started Sep 04 02:17:18 AM UTC 24
Finished Sep 04 02:17:21 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530246406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1530246406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.3722732601
Short name T615
Test name
Test status
Simulation time 2160441264 ps
CPU time 4.3 seconds
Started Sep 04 02:17:19 AM UTC 24
Finished Sep 04 02:17:24 AM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722732601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.3722732601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.2129945646
Short name T616
Test name
Test status
Simulation time 2521849071 ps
CPU time 4.5 seconds
Started Sep 04 02:17:19 AM UTC 24
Finished Sep 04 02:17:24 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129945646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2129945646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.2303516607
Short name T608
Test name
Test status
Simulation time 2160489837 ps
CPU time 2.03 seconds
Started Sep 04 02:17:16 AM UTC 24
Finished Sep 04 02:17:19 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303516607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2303516607
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.4107136832
Short name T186
Test name
Test status
Simulation time 101775989758 ps
CPU time 25.24 seconds
Started Sep 04 02:17:23 AM UTC 24
Finished Sep 04 02:17:50 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107136832 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.4107136832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1213875384
Short name T343
Test name
Test status
Simulation time 16971779102 ps
CPU time 15.23 seconds
Started Sep 04 02:17:22 AM UTC 24
Finished Sep 04 02:17:39 AM UTC 24
Peak memory 226792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1213875384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1213875384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3853506714
Short name T450
Test name
Test status
Simulation time 509098624835 ps
CPU time 21.07 seconds
Started Sep 04 02:17:21 AM UTC 24
Finished Sep 04 02:17:43 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853506714 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.3853506714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2235601412
Short name T626
Test name
Test status
Simulation time 2032345360 ps
CPU time 2.66 seconds
Started Sep 04 02:17:32 AM UTC 24
Finished Sep 04 02:17:35 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235601412 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.2235601412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3219687656
Short name T627
Test name
Test status
Simulation time 3198290474 ps
CPU time 5.23 seconds
Started Sep 04 02:17:29 AM UTC 24
Finished Sep 04 02:17:35 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219687656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3219687656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.91775893
Short name T309
Test name
Test status
Simulation time 144796292042 ps
CPU time 379.26 seconds
Started Sep 04 02:17:29 AM UTC 24
Finished Sep 04 02:23:53 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91775893 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.91775893
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4236254121
Short name T709
Test name
Test status
Simulation time 116617875893 ps
CPU time 83.19 seconds
Started Sep 04 02:17:30 AM UTC 24
Finished Sep 04 02:18:55 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236254121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_with_pre_cond.4236254121
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2283837805
Short name T628
Test name
Test status
Simulation time 2787072178 ps
CPU time 9.45 seconds
Started Sep 04 02:17:27 AM UTC 24
Finished Sep 04 02:17:37 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283837805 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.2283837805
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3737118246
Short name T185
Test name
Test status
Simulation time 499949219084 ps
CPU time 19.39 seconds
Started Sep 04 02:17:29 AM UTC 24
Finished Sep 04 02:17:50 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737118246 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.3737118246
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2278094584
Short name T623
Test name
Test status
Simulation time 2622825663 ps
CPU time 4.18 seconds
Started Sep 04 02:17:26 AM UTC 24
Finished Sep 04 02:17:31 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278094584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.2278094584
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3744335047
Short name T624
Test name
Test status
Simulation time 2486322300 ps
CPU time 5.89 seconds
Started Sep 04 02:17:25 AM UTC 24
Finished Sep 04 02:17:32 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744335047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3744335047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.1941302009
Short name T620
Test name
Test status
Simulation time 2178649376 ps
CPU time 2.79 seconds
Started Sep 04 02:17:25 AM UTC 24
Finished Sep 04 02:17:28 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941302009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1941302009
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.764052710
Short name T629
Test name
Test status
Simulation time 2512727020 ps
CPU time 11.79 seconds
Started Sep 04 02:17:25 AM UTC 24
Finished Sep 04 02:17:38 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764052710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.764052710
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1943402005
Short name T618
Test name
Test status
Simulation time 2146347608 ps
CPU time 2.34 seconds
Started Sep 04 02:17:25 AM UTC 24
Finished Sep 04 02:17:28 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943402005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1943402005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.2256062544
Short name T654
Test name
Test status
Simulation time 10775793401 ps
CPU time 37.09 seconds
Started Sep 04 02:17:31 AM UTC 24
Finished Sep 04 02:18:10 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256062544 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.2256062544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1762180162
Short name T344
Test name
Test status
Simulation time 3699649408 ps
CPU time 10.54 seconds
Started Sep 04 02:17:31 AM UTC 24
Finished Sep 04 02:17:43 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1762180162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.1762180162
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2769123409
Short name T158
Test name
Test status
Simulation time 7359170315 ps
CPU time 2.71 seconds
Started Sep 04 02:17:29 AM UTC 24
Finished Sep 04 02:17:33 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769123409 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.2769123409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.1351960911
Short name T187
Test name
Test status
Simulation time 2019068706 ps
CPU time 5.26 seconds
Started Sep 04 02:17:44 AM UTC 24
Finished Sep 04 02:17:50 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351960911 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.1351960911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2070048923
Short name T636
Test name
Test status
Simulation time 3513994668 ps
CPU time 7.62 seconds
Started Sep 04 02:17:38 AM UTC 24
Finished Sep 04 02:17:47 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070048923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2070048923
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.2131050496
Short name T304
Test name
Test status
Simulation time 56653002739 ps
CPU time 97.83 seconds
Started Sep 04 02:17:39 AM UTC 24
Finished Sep 04 02:19:19 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131050496 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.2131050496
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4165092551
Short name T410
Test name
Test status
Simulation time 72623836802 ps
CPU time 43.53 seconds
Started Sep 04 02:17:40 AM UTC 24
Finished Sep 04 02:18:25 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165092551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_with_pre_cond.4165092551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2963301509
Short name T633
Test name
Test status
Simulation time 2986467648 ps
CPU time 6.48 seconds
Started Sep 04 02:17:36 AM UTC 24
Finished Sep 04 02:17:44 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963301509 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.2963301509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.4212331662
Short name T634
Test name
Test status
Simulation time 2607766208 ps
CPU time 7.39 seconds
Started Sep 04 02:17:36 AM UTC 24
Finished Sep 04 02:17:45 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212331662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.4212331662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.4183206629
Short name T630
Test name
Test status
Simulation time 2461723434 ps
CPU time 6.17 seconds
Started Sep 04 02:17:33 AM UTC 24
Finished Sep 04 02:17:40 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183206629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.4183206629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.968003854
Short name T635
Test name
Test status
Simulation time 2188244713 ps
CPU time 10.32 seconds
Started Sep 04 02:17:34 AM UTC 24
Finished Sep 04 02:17:45 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968003854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.968003854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2964258760
Short name T631
Test name
Test status
Simulation time 2517463997 ps
CPU time 5.94 seconds
Started Sep 04 02:17:34 AM UTC 24
Finished Sep 04 02:17:41 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964258760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2964258760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1725543170
Short name T632
Test name
Test status
Simulation time 2108776079 ps
CPU time 10.53 seconds
Started Sep 04 02:17:32 AM UTC 24
Finished Sep 04 02:17:43 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725543170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1725543170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.3558430994
Short name T655
Test name
Test status
Simulation time 11944138255 ps
CPU time 25.36 seconds
Started Sep 04 02:17:44 AM UTC 24
Finished Sep 04 02:18:10 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558430994 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.3558430994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1793711991
Short name T648
Test name
Test status
Simulation time 16912959765 ps
CPU time 20.55 seconds
Started Sep 04 02:17:41 AM UTC 24
Finished Sep 04 02:18:03 AM UTC 24
Peak memory 220476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1793711991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.1793711991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2043332891
Short name T637
Test name
Test status
Simulation time 10233550078 ps
CPU time 14.23 seconds
Started Sep 04 02:17:38 AM UTC 24
Finished Sep 04 02:17:53 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043332891 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.2043332891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.637287960
Short name T640
Test name
Test status
Simulation time 2018289051 ps
CPU time 3.34 seconds
Started Sep 04 02:17:53 AM UTC 24
Finished Sep 04 02:17:57 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637287960 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.637287960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1652920212
Short name T643
Test name
Test status
Simulation time 3653085112 ps
CPU time 8.13 seconds
Started Sep 04 02:17:50 AM UTC 24
Finished Sep 04 02:18:00 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652920212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.1652920212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.1473675552
Short name T390
Test name
Test status
Simulation time 115355479450 ps
CPU time 175.39 seconds
Started Sep 04 02:17:50 AM UTC 24
Finished Sep 04 02:20:48 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473675552 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.1473675552
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.918310357
Short name T641
Test name
Test status
Simulation time 5616948366 ps
CPU time 7.23 seconds
Started Sep 04 02:17:49 AM UTC 24
Finished Sep 04 02:17:57 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918310357 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.918310357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.2444194791
Short name T167
Test name
Test status
Simulation time 4664119684 ps
CPU time 10 seconds
Started Sep 04 02:17:50 AM UTC 24
Finished Sep 04 02:18:02 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444194791 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.2444194791
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.608529502
Short name T191
Test name
Test status
Simulation time 2631068399 ps
CPU time 2.67 seconds
Started Sep 04 02:17:48 AM UTC 24
Finished Sep 04 02:17:52 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608529502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.608529502
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.2552764632
Short name T184
Test name
Test status
Simulation time 2480363536 ps
CPU time 3.68 seconds
Started Sep 04 02:17:45 AM UTC 24
Finished Sep 04 02:17:49 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552764632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.2552764632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.621268614
Short name T642
Test name
Test status
Simulation time 2121456897 ps
CPU time 10.64 seconds
Started Sep 04 02:17:46 AM UTC 24
Finished Sep 04 02:17:58 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621268614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.621268614
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.2362898627
Short name T638
Test name
Test status
Simulation time 2509936698 ps
CPU time 7.78 seconds
Started Sep 04 02:17:46 AM UTC 24
Finished Sep 04 02:17:55 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362898627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.2362898627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.1682575568
Short name T190
Test name
Test status
Simulation time 2114646567 ps
CPU time 5.79 seconds
Started Sep 04 02:17:45 AM UTC 24
Finished Sep 04 02:17:52 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682575568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1682575568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.366108566
Short name T384
Test name
Test status
Simulation time 93521921448 ps
CPU time 75.31 seconds
Started Sep 04 02:17:52 AM UTC 24
Finished Sep 04 02:19:09 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366108566 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.366108566
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2039049031
Short name T263
Test name
Test status
Simulation time 15234754885 ps
CPU time 13.53 seconds
Started Sep 04 02:17:52 AM UTC 24
Finished Sep 04 02:18:06 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2039049031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.2039049031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2832827473
Short name T153
Test name
Test status
Simulation time 6920869903 ps
CPU time 4.47 seconds
Started Sep 04 02:17:50 AM UTC 24
Finished Sep 04 02:17:56 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832827473 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.2832827473
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2043101959
Short name T651
Test name
Test status
Simulation time 2041773040 ps
CPU time 2.63 seconds
Started Sep 04 02:18:03 AM UTC 24
Finished Sep 04 02:18:07 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043101959 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.2043101959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1979115727
Short name T649
Test name
Test status
Simulation time 3325024214 ps
CPU time 4.83 seconds
Started Sep 04 02:17:58 AM UTC 24
Finished Sep 04 02:18:04 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979115727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1979115727
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2200718024
Short name T762
Test name
Test status
Simulation time 51813009969 ps
CPU time 120.78 seconds
Started Sep 04 02:18:01 AM UTC 24
Finished Sep 04 02:20:04 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200718024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.2200718024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.4278665558
Short name T647
Test name
Test status
Simulation time 3176521727 ps
CPU time 4.42 seconds
Started Sep 04 02:17:57 AM UTC 24
Finished Sep 04 02:18:03 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278665558 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.4278665558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.2667669758
Short name T658
Test name
Test status
Simulation time 3356303185 ps
CPU time 12.35 seconds
Started Sep 04 02:18:01 AM UTC 24
Finished Sep 04 02:18:14 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667669758 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.2667669758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.639254690
Short name T645
Test name
Test status
Simulation time 2637483606 ps
CPU time 3.56 seconds
Started Sep 04 02:17:56 AM UTC 24
Finished Sep 04 02:18:01 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639254690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.639254690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.1001115944
Short name T646
Test name
Test status
Simulation time 2472723419 ps
CPU time 6.42 seconds
Started Sep 04 02:17:54 AM UTC 24
Finished Sep 04 02:18:01 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001115944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.1001115944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2963292833
Short name T652
Test name
Test status
Simulation time 2071225003 ps
CPU time 10.7 seconds
Started Sep 04 02:17:55 AM UTC 24
Finished Sep 04 02:18:07 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963292833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2963292833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.26085618
Short name T644
Test name
Test status
Simulation time 2524560652 ps
CPU time 3.7 seconds
Started Sep 04 02:17:55 AM UTC 24
Finished Sep 04 02:18:00 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26085618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.26085618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.624016455
Short name T639
Test name
Test status
Simulation time 2141417332 ps
CPU time 2.95 seconds
Started Sep 04 02:17:53 AM UTC 24
Finished Sep 04 02:17:57 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624016455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.624016455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.1848001100
Short name T684
Test name
Test status
Simulation time 9542764149 ps
CPU time 34.96 seconds
Started Sep 04 02:18:02 AM UTC 24
Finished Sep 04 02:18:38 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848001100 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.1848001100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1736925736
Short name T661
Test name
Test status
Simulation time 9311557197 ps
CPU time 13.21 seconds
Started Sep 04 02:18:02 AM UTC 24
Finished Sep 04 02:18:16 AM UTC 24
Peak memory 220536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1736925736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.1736925736
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2285413833
Short name T650
Test name
Test status
Simulation time 3119971980 ps
CPU time 4.89 seconds
Started Sep 04 02:17:58 AM UTC 24
Finished Sep 04 02:18:04 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285413833 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.2285413833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.425533925
Short name T163
Test name
Test status
Simulation time 2015381011 ps
CPU time 7.8 seconds
Started Sep 04 02:13:48 AM UTC 24
Finished Sep 04 02:13:57 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425533925 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.425533925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.4267162575
Short name T61
Test name
Test status
Simulation time 3123355297 ps
CPU time 7.24 seconds
Started Sep 04 02:13:44 AM UTC 24
Finished Sep 04 02:13:52 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267162575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.4267162575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2190571933
Short name T287
Test name
Test status
Simulation time 103098600557 ps
CPU time 149.69 seconds
Started Sep 04 02:13:46 AM UTC 24
Finished Sep 04 02:16:18 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190571933 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.2190571933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3922640366
Short name T69
Test name
Test status
Simulation time 2525916463 ps
CPU time 3.67 seconds
Started Sep 04 02:13:41 AM UTC 24
Finished Sep 04 02:13:46 AM UTC 24
Peak memory 209844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922640366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3922640366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1494377503
Short name T297
Test name
Test status
Simulation time 2931755157 ps
CPU time 14.62 seconds
Started Sep 04 02:13:44 AM UTC 24
Finished Sep 04 02:14:00 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494377503 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.1494377503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.4161219031
Short name T48
Test name
Test status
Simulation time 4807757904 ps
CPU time 5.43 seconds
Started Sep 04 02:13:47 AM UTC 24
Finished Sep 04 02:13:54 AM UTC 24
Peak memory 209432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161219031 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.4161219031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2672149938
Short name T107
Test name
Test status
Simulation time 2627612532 ps
CPU time 4.18 seconds
Started Sep 04 02:13:43 AM UTC 24
Finished Sep 04 02:13:48 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672149938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2672149938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.1512715465
Short name T84
Test name
Test status
Simulation time 2460770496 ps
CPU time 6.37 seconds
Started Sep 04 02:13:40 AM UTC 24
Finished Sep 04 02:13:48 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512715465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1512715465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.3798806499
Short name T104
Test name
Test status
Simulation time 2117542251 ps
CPU time 3.95 seconds
Started Sep 04 02:13:41 AM UTC 24
Finished Sep 04 02:13:46 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798806499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3798806499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2312975330
Short name T105
Test name
Test status
Simulation time 2562020156 ps
CPU time 2.71 seconds
Started Sep 04 02:13:43 AM UTC 24
Finished Sep 04 02:13:47 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312975330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.2312975330
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.1363688209
Short name T331
Test name
Test status
Simulation time 22011243915 ps
CPU time 61.82 seconds
Started Sep 04 02:13:48 AM UTC 24
Finished Sep 04 02:14:52 AM UTC 24
Peak memory 240348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363688209 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.1363688209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.2874638864
Short name T106
Test name
Test status
Simulation time 2107516759 ps
CPU time 6.55 seconds
Started Sep 04 02:13:39 AM UTC 24
Finished Sep 04 02:13:47 AM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874638864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2874638864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.3439814888
Short name T86
Test name
Test status
Simulation time 7062090473 ps
CPU time 15.18 seconds
Started Sep 04 02:13:47 AM UTC 24
Finished Sep 04 02:14:04 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439814888 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.3439814888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1692104858
Short name T226
Test name
Test status
Simulation time 2782762738 ps
CPU time 9.8 seconds
Started Sep 04 02:13:47 AM UTC 24
Finished Sep 04 02:13:58 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1692104858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.1692104858
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3915809763
Short name T72
Test name
Test status
Simulation time 7648461154 ps
CPU time 4.47 seconds
Started Sep 04 02:13:44 AM UTC 24
Finished Sep 04 02:13:50 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915809763 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.3915809763
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.1268025578
Short name T664
Test name
Test status
Simulation time 2012432523 ps
CPU time 6 seconds
Started Sep 04 02:18:12 AM UTC 24
Finished Sep 04 02:18:19 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268025578 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.1268025578
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1611809213
Short name T657
Test name
Test status
Simulation time 3052464978 ps
CPU time 2.89 seconds
Started Sep 04 02:18:08 AM UTC 24
Finished Sep 04 02:18:12 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611809213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.1611809213
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.851898876
Short name T306
Test name
Test status
Simulation time 185061280794 ps
CPU time 51.18 seconds
Started Sep 04 02:18:08 AM UTC 24
Finished Sep 04 02:19:00 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851898876 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.851898876
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3153561800
Short name T445
Test name
Test status
Simulation time 24036337886 ps
CPU time 15.96 seconds
Started Sep 04 02:18:11 AM UTC 24
Finished Sep 04 02:18:28 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153561800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_with_pre_cond.3153561800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.747115805
Short name T663
Test name
Test status
Simulation time 2658207108 ps
CPU time 11.42 seconds
Started Sep 04 02:18:06 AM UTC 24
Finished Sep 04 02:18:19 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747115805 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.747115805
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.3014794656
Short name T176
Test name
Test status
Simulation time 3094713880 ps
CPU time 3.43 seconds
Started Sep 04 02:18:11 AM UTC 24
Finished Sep 04 02:18:15 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014794656 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.3014794656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.43851743
Short name T656
Test name
Test status
Simulation time 2629007615 ps
CPU time 4.01 seconds
Started Sep 04 02:18:05 AM UTC 24
Finished Sep 04 02:18:10 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43851743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.43851743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.2452919146
Short name T662
Test name
Test status
Simulation time 2473982372 ps
CPU time 11.72 seconds
Started Sep 04 02:18:04 AM UTC 24
Finished Sep 04 02:18:17 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452919146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2452919146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.4006428482
Short name T653
Test name
Test status
Simulation time 2262229971 ps
CPU time 3.5 seconds
Started Sep 04 02:18:05 AM UTC 24
Finished Sep 04 02:18:10 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006428482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.4006428482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2420211744
Short name T660
Test name
Test status
Simulation time 2507374675 ps
CPU time 9.54 seconds
Started Sep 04 02:18:05 AM UTC 24
Finished Sep 04 02:18:16 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420211744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2420211744
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.1035299090
Short name T659
Test name
Test status
Simulation time 2110142955 ps
CPU time 10.31 seconds
Started Sep 04 02:18:04 AM UTC 24
Finished Sep 04 02:18:15 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035299090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.1035299090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2108957677
Short name T669
Test name
Test status
Simulation time 6816305007 ps
CPU time 10.29 seconds
Started Sep 04 02:18:11 AM UTC 24
Finished Sep 04 02:18:22 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2108957677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.2108957677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.669797507
Short name T449
Test name
Test status
Simulation time 1817542202496 ps
CPU time 24.08 seconds
Started Sep 04 02:18:08 AM UTC 24
Finished Sep 04 02:18:33 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669797507 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.669797507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.4030801959
Short name T674
Test name
Test status
Simulation time 2015854085 ps
CPU time 8.44 seconds
Started Sep 04 02:18:21 AM UTC 24
Finished Sep 04 02:18:31 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030801959 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.4030801959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3071483395
Short name T672
Test name
Test status
Simulation time 3570495860 ps
CPU time 8.71 seconds
Started Sep 04 02:18:17 AM UTC 24
Finished Sep 04 02:18:27 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071483395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.3071483395
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.1363887140
Short name T433
Test name
Test status
Simulation time 80136082319 ps
CPU time 51.4 seconds
Started Sep 04 02:18:19 AM UTC 24
Finished Sep 04 02:19:11 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363887140 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.1363887140
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2041681060
Short name T416
Test name
Test status
Simulation time 93847360654 ps
CPU time 74.42 seconds
Started Sep 04 02:18:20 AM UTC 24
Finished Sep 04 02:19:36 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041681060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.2041681060
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1318995981
Short name T670
Test name
Test status
Simulation time 3615126354 ps
CPU time 6.82 seconds
Started Sep 04 02:18:16 AM UTC 24
Finished Sep 04 02:18:24 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318995981 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.1318995981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2116443472
Short name T264
Test name
Test status
Simulation time 2706028438 ps
CPU time 11.19 seconds
Started Sep 04 02:18:20 AM UTC 24
Finished Sep 04 02:18:32 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116443472 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.2116443472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3032875241
Short name T675
Test name
Test status
Simulation time 2611165718 ps
CPU time 13.2 seconds
Started Sep 04 02:18:16 AM UTC 24
Finished Sep 04 02:18:31 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032875241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.3032875241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.182308181
Short name T665
Test name
Test status
Simulation time 2475611897 ps
CPU time 3.3 seconds
Started Sep 04 02:18:15 AM UTC 24
Finished Sep 04 02:18:19 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182308181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.182308181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.3649816544
Short name T666
Test name
Test status
Simulation time 2234686964 ps
CPU time 3.33 seconds
Started Sep 04 02:18:16 AM UTC 24
Finished Sep 04 02:18:21 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649816544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.3649816544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.397530784
Short name T667
Test name
Test status
Simulation time 2537338436 ps
CPU time 3.8 seconds
Started Sep 04 02:18:16 AM UTC 24
Finished Sep 04 02:18:21 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397530784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.397530784
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.4283811377
Short name T671
Test name
Test status
Simulation time 2110196018 ps
CPU time 8.3 seconds
Started Sep 04 02:18:15 AM UTC 24
Finished Sep 04 02:18:25 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283811377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.4283811377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.4020775808
Short name T133
Test name
Test status
Simulation time 64393646452 ps
CPU time 180.62 seconds
Started Sep 04 02:18:21 AM UTC 24
Finished Sep 04 02:21:24 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020775808 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.4020775808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.437143270
Short name T351
Test name
Test status
Simulation time 7312753126 ps
CPU time 18.3 seconds
Started Sep 04 02:18:21 AM UTC 24
Finished Sep 04 02:18:40 AM UTC 24
Peak memory 220484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=437143270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.437143270
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1996224138
Short name T668
Test name
Test status
Simulation time 3440521583 ps
CPU time 3.06 seconds
Started Sep 04 02:18:18 AM UTC 24
Finished Sep 04 02:18:22 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996224138 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.1996224138
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1712263458
Short name T683
Test name
Test status
Simulation time 2019002054 ps
CPU time 4.36 seconds
Started Sep 04 02:18:32 AM UTC 24
Finished Sep 04 02:18:38 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712263458 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.1712263458
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3935038203
Short name T686
Test name
Test status
Simulation time 3349789182 ps
CPU time 10.87 seconds
Started Sep 04 02:18:27 AM UTC 24
Finished Sep 04 02:18:39 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935038203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.3935038203
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.122550202
Short name T307
Test name
Test status
Simulation time 75813168668 ps
CPU time 50.33 seconds
Started Sep 04 02:18:29 AM UTC 24
Finished Sep 04 02:19:21 AM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122550202 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.122550202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3119523796
Short name T679
Test name
Test status
Simulation time 3939650492 ps
CPU time 7.58 seconds
Started Sep 04 02:18:26 AM UTC 24
Finished Sep 04 02:18:34 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119523796 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.3119523796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.3773683443
Short name T249
Test name
Test status
Simulation time 3310349983 ps
CPU time 3.44 seconds
Started Sep 04 02:18:29 AM UTC 24
Finished Sep 04 02:18:33 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773683443 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.3773683443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3024280136
Short name T680
Test name
Test status
Simulation time 2608838356 ps
CPU time 9.29 seconds
Started Sep 04 02:18:26 AM UTC 24
Finished Sep 04 02:18:36 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024280136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.3024280136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.3066727313
Short name T678
Test name
Test status
Simulation time 2450899207 ps
CPU time 8.76 seconds
Started Sep 04 02:18:22 AM UTC 24
Finished Sep 04 02:18:32 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066727313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.3066727313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.495677460
Short name T677
Test name
Test status
Simulation time 2153434235 ps
CPU time 8.4 seconds
Started Sep 04 02:18:22 AM UTC 24
Finished Sep 04 02:18:32 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495677460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.495677460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.420496143
Short name T681
Test name
Test status
Simulation time 2513274083 ps
CPU time 11.75 seconds
Started Sep 04 02:18:23 AM UTC 24
Finished Sep 04 02:18:36 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420496143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.420496143
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.1507454859
Short name T673
Test name
Test status
Simulation time 2115024893 ps
CPU time 5.68 seconds
Started Sep 04 02:18:21 AM UTC 24
Finished Sep 04 02:18:28 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507454859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1507454859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.1048168103
Short name T265
Test name
Test status
Simulation time 12638466171 ps
CPU time 5.35 seconds
Started Sep 04 02:18:31 AM UTC 24
Finished Sep 04 02:18:38 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048168103 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.1048168103
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2700118494
Short name T688
Test name
Test status
Simulation time 7074529273 ps
CPU time 6.94 seconds
Started Sep 04 02:18:31 AM UTC 24
Finished Sep 04 02:18:39 AM UTC 24
Peak memory 220408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2700118494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2700118494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1634824850
Short name T676
Test name
Test status
Simulation time 3006874239 ps
CPU time 2.22 seconds
Started Sep 04 02:18:28 AM UTC 24
Finished Sep 04 02:18:31 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634824850 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.1634824850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.2514108953
Short name T696
Test name
Test status
Simulation time 2021697169 ps
CPU time 4.6 seconds
Started Sep 04 02:18:39 AM UTC 24
Finished Sep 04 02:18:45 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514108953 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.2514108953
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2738931866
Short name T691
Test name
Test status
Simulation time 3359337501 ps
CPU time 3.18 seconds
Started Sep 04 02:18:37 AM UTC 24
Finished Sep 04 02:18:41 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738931866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2738931866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.37482598
Short name T794
Test name
Test status
Simulation time 121063710518 ps
CPU time 341.94 seconds
Started Sep 04 02:18:38 AM UTC 24
Finished Sep 04 02:24:24 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37482598 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.37482598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3253316693
Short name T782
Test name
Test status
Simulation time 75939479367 ps
CPU time 208.41 seconds
Started Sep 04 02:18:38 AM UTC 24
Finished Sep 04 02:22:10 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253316693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_with_pre_cond.3253316693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2688645116
Short name T689
Test name
Test status
Simulation time 4195134739 ps
CPU time 4.25 seconds
Started Sep 04 02:18:35 AM UTC 24
Finished Sep 04 02:18:40 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688645116 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.2688645116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1190108681
Short name T704
Test name
Test status
Simulation time 2769814758 ps
CPU time 11.21 seconds
Started Sep 04 02:18:38 AM UTC 24
Finished Sep 04 02:18:51 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190108681 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.1190108681
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.357353930
Short name T695
Test name
Test status
Simulation time 2611442870 ps
CPU time 9.48 seconds
Started Sep 04 02:18:35 AM UTC 24
Finished Sep 04 02:18:45 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357353930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.357353930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.4229232227
Short name T687
Test name
Test status
Simulation time 2478363309 ps
CPU time 4.16 seconds
Started Sep 04 02:18:34 AM UTC 24
Finished Sep 04 02:18:39 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229232227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.4229232227
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.477268879
Short name T692
Test name
Test status
Simulation time 2056605844 ps
CPU time 7.66 seconds
Started Sep 04 02:18:34 AM UTC 24
Finished Sep 04 02:18:43 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477268879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.477268879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.2533490354
Short name T685
Test name
Test status
Simulation time 2521793144 ps
CPU time 3.3 seconds
Started Sep 04 02:18:34 AM UTC 24
Finished Sep 04 02:18:38 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533490354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.2533490354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2604441843
Short name T682
Test name
Test status
Simulation time 2125463172 ps
CPU time 2.98 seconds
Started Sep 04 02:18:32 AM UTC 24
Finished Sep 04 02:18:37 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604441843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2604441843
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3076757883
Short name T347
Test name
Test status
Simulation time 16666796125 ps
CPU time 17.11 seconds
Started Sep 04 02:18:38 AM UTC 24
Finished Sep 04 02:18:57 AM UTC 24
Peak memory 220408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3076757883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.3076757883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.871930602
Short name T690
Test name
Test status
Simulation time 5077151095 ps
CPU time 2.04 seconds
Started Sep 04 02:18:37 AM UTC 24
Finished Sep 04 02:18:40 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871930602 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.871930602
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.639470445
Short name T708
Test name
Test status
Simulation time 2013182399 ps
CPU time 7.6 seconds
Started Sep 04 02:18:46 AM UTC 24
Finished Sep 04 02:18:55 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639470445 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.639470445
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.276960100
Short name T711
Test name
Test status
Simulation time 3249190795 ps
CPU time 14.37 seconds
Started Sep 04 02:18:41 AM UTC 24
Finished Sep 04 02:18:57 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276960100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.276960100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.1148344147
Short name T792
Test name
Test status
Simulation time 85032515440 ps
CPU time 307.02 seconds
Started Sep 04 02:18:42 AM UTC 24
Finished Sep 04 02:23:53 AM UTC 24
Peak memory 210232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148344147 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.1148344147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.504886944
Short name T699
Test name
Test status
Simulation time 3549201652 ps
CPU time 5.11 seconds
Started Sep 04 02:18:41 AM UTC 24
Finished Sep 04 02:18:47 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504886944 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.504886944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.462808317
Short name T250
Test name
Test status
Simulation time 3969383643 ps
CPU time 3.97 seconds
Started Sep 04 02:18:44 AM UTC 24
Finished Sep 04 02:18:49 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462808317 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.462808317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.94746891
Short name T693
Test name
Test status
Simulation time 2751874321 ps
CPU time 1.38 seconds
Started Sep 04 02:18:41 AM UTC 24
Finished Sep 04 02:18:43 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94746891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.94746891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.2488591786
Short name T705
Test name
Test status
Simulation time 2463400764 ps
CPU time 11.56 seconds
Started Sep 04 02:18:39 AM UTC 24
Finished Sep 04 02:18:52 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488591786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.2488591786
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3384301928
Short name T702
Test name
Test status
Simulation time 2184600284 ps
CPU time 8.57 seconds
Started Sep 04 02:18:41 AM UTC 24
Finished Sep 04 02:18:51 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384301928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3384301928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3723119902
Short name T698
Test name
Test status
Simulation time 2520003682 ps
CPU time 5.24 seconds
Started Sep 04 02:18:41 AM UTC 24
Finished Sep 04 02:18:47 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723119902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3723119902
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.128935444
Short name T694
Test name
Test status
Simulation time 2122399645 ps
CPU time 3.78 seconds
Started Sep 04 02:18:39 AM UTC 24
Finished Sep 04 02:18:45 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128935444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.128935444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.3224379732
Short name T758
Test name
Test status
Simulation time 12995778312 ps
CPU time 54.8 seconds
Started Sep 04 02:18:46 AM UTC 24
Finished Sep 04 02:19:43 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224379732 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.3224379732
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1210220137
Short name T706
Test name
Test status
Simulation time 2126209396 ps
CPU time 7.39 seconds
Started Sep 04 02:18:45 AM UTC 24
Finished Sep 04 02:18:54 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1210220137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.1210220137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3159076333
Short name T697
Test name
Test status
Simulation time 11974535893 ps
CPU time 2.87 seconds
Started Sep 04 02:18:42 AM UTC 24
Finished Sep 04 02:18:46 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159076333 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.3159076333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2286346765
Short name T715
Test name
Test status
Simulation time 2029234770 ps
CPU time 3.06 seconds
Started Sep 04 02:18:55 AM UTC 24
Finished Sep 04 02:19:00 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286346765 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.2286346765
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3964378683
Short name T713
Test name
Test status
Simulation time 3713583570 ps
CPU time 4.43 seconds
Started Sep 04 02:18:52 AM UTC 24
Finished Sep 04 02:18:58 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964378683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.3964378683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.986974350
Short name T796
Test name
Test status
Simulation time 194241952393 ps
CPU time 406.36 seconds
Started Sep 04 02:18:52 AM UTC 24
Finished Sep 04 02:25:44 AM UTC 24
Peak memory 210428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986974350 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.986974350
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4191968785
Short name T760
Test name
Test status
Simulation time 38961104839 ps
CPU time 63.03 seconds
Started Sep 04 02:18:53 AM UTC 24
Finished Sep 04 02:19:58 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191968785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.4191968785
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3641856959
Short name T710
Test name
Test status
Simulation time 3211683737 ps
CPU time 3.69 seconds
Started Sep 04 02:18:51 AM UTC 24
Finished Sep 04 02:18:56 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641856959 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.3641856959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2297156866
Short name T723
Test name
Test status
Simulation time 2415244114 ps
CPU time 9.44 seconds
Started Sep 04 02:18:52 AM UTC 24
Finished Sep 04 02:19:03 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297156866 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.2297156866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2361390658
Short name T718
Test name
Test status
Simulation time 2611258162 ps
CPU time 10.38 seconds
Started Sep 04 02:18:50 AM UTC 24
Finished Sep 04 02:19:01 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361390658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.2361390658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1375507113
Short name T712
Test name
Test status
Simulation time 2470080249 ps
CPU time 9.84 seconds
Started Sep 04 02:18:46 AM UTC 24
Finished Sep 04 02:18:58 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375507113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.1375507113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.3165034237
Short name T701
Test name
Test status
Simulation time 2112747750 ps
CPU time 2 seconds
Started Sep 04 02:18:48 AM UTC 24
Finished Sep 04 02:18:51 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165034237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.3165034237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.2972047372
Short name T700
Test name
Test status
Simulation time 2569686989 ps
CPU time 1.33 seconds
Started Sep 04 02:18:48 AM UTC 24
Finished Sep 04 02:18:50 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972047372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2972047372
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.1493032138
Short name T707
Test name
Test status
Simulation time 2112554163 ps
CPU time 7.11 seconds
Started Sep 04 02:18:46 AM UTC 24
Finished Sep 04 02:18:55 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493032138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.1493032138
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.4167992321
Short name T716
Test name
Test status
Simulation time 6721780354 ps
CPU time 5.05 seconds
Started Sep 04 02:18:54 AM UTC 24
Finished Sep 04 02:19:00 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167992321 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.4167992321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.453294066
Short name T154
Test name
Test status
Simulation time 8381561281 ps
CPU time 7.1 seconds
Started Sep 04 02:18:52 AM UTC 24
Finished Sep 04 02:19:00 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453294066 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.453294066
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.1137958220
Short name T733
Test name
Test status
Simulation time 2014158781 ps
CPU time 8.48 seconds
Started Sep 04 02:19:02 AM UTC 24
Finished Sep 04 02:19:11 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137958220 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.1137958220
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.368913002
Short name T729
Test name
Test status
Simulation time 3451589091 ps
CPU time 7.81 seconds
Started Sep 04 02:18:59 AM UTC 24
Finished Sep 04 02:19:08 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368913002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.368913002
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.127572937
Short name T134
Test name
Test status
Simulation time 147271037947 ps
CPU time 229.47 seconds
Started Sep 04 02:19:00 AM UTC 24
Finished Sep 04 02:22:53 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127572937 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.127572937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2584155280
Short name T407
Test name
Test status
Simulation time 60904941495 ps
CPU time 180.27 seconds
Started Sep 04 02:19:01 AM UTC 24
Finished Sep 04 02:22:04 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584155280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_with_pre_cond.2584155280
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.154791334
Short name T724
Test name
Test status
Simulation time 4728756881 ps
CPU time 3.74 seconds
Started Sep 04 02:18:59 AM UTC 24
Finished Sep 04 02:19:04 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154791334 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.154791334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.2035479984
Short name T252
Test name
Test status
Simulation time 3061411394 ps
CPU time 2.46 seconds
Started Sep 04 02:19:01 AM UTC 24
Finished Sep 04 02:19:05 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035479984 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.2035479984
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.4102192090
Short name T719
Test name
Test status
Simulation time 2633751900 ps
CPU time 2.34 seconds
Started Sep 04 02:18:58 AM UTC 24
Finished Sep 04 02:19:01 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102192090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.4102192090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.2176344195
Short name T722
Test name
Test status
Simulation time 2473400440 ps
CPU time 4.64 seconds
Started Sep 04 02:18:57 AM UTC 24
Finished Sep 04 02:19:02 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176344195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.2176344195
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3495215299
Short name T717
Test name
Test status
Simulation time 2045935784 ps
CPU time 2.93 seconds
Started Sep 04 02:18:57 AM UTC 24
Finished Sep 04 02:19:01 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495215299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.3495215299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.3833211005
Short name T727
Test name
Test status
Simulation time 2510932431 ps
CPU time 7.78 seconds
Started Sep 04 02:18:58 AM UTC 24
Finished Sep 04 02:19:07 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833211005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.3833211005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.2609014286
Short name T725
Test name
Test status
Simulation time 2113736810 ps
CPU time 5.98 seconds
Started Sep 04 02:18:57 AM UTC 24
Finished Sep 04 02:19:04 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609014286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2609014286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.3966174000
Short name T744
Test name
Test status
Simulation time 6252425905 ps
CPU time 15.42 seconds
Started Sep 04 02:19:01 AM UTC 24
Finished Sep 04 02:19:18 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966174000 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.3966174000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3372664038
Short name T720
Test name
Test status
Simulation time 6274819690 ps
CPU time 18.86 seconds
Started Sep 04 02:19:01 AM UTC 24
Finished Sep 04 02:19:22 AM UTC 24
Peak memory 226992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3372664038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.3372664038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.777036214
Short name T736
Test name
Test status
Simulation time 2020341100 ps
CPU time 4.35 seconds
Started Sep 04 02:19:08 AM UTC 24
Finished Sep 04 02:19:13 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777036214 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.777036214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1967760127
Short name T131
Test name
Test status
Simulation time 3173071287 ps
CPU time 5.68 seconds
Started Sep 04 02:19:04 AM UTC 24
Finished Sep 04 02:19:11 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967760127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1967760127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.264790363
Short name T391
Test name
Test status
Simulation time 115618301854 ps
CPU time 207.04 seconds
Started Sep 04 02:19:05 AM UTC 24
Finished Sep 04 02:22:35 AM UTC 24
Peak memory 210428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264790363 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.264790363
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2685651810
Short name T277
Test name
Test status
Simulation time 42093678819 ps
CPU time 95.88 seconds
Started Sep 04 02:19:05 AM UTC 24
Finished Sep 04 02:20:43 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685651810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_with_pre_cond.2685651810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3773242003
Short name T737
Test name
Test status
Simulation time 2752371247 ps
CPU time 8.09 seconds
Started Sep 04 02:19:04 AM UTC 24
Finished Sep 04 02:19:13 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773242003 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.3773242003
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.2957356313
Short name T177
Test name
Test status
Simulation time 2849946830 ps
CPU time 3.4 seconds
Started Sep 04 02:19:05 AM UTC 24
Finished Sep 04 02:19:10 AM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957356313 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.2957356313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3244409269
Short name T730
Test name
Test status
Simulation time 2617824241 ps
CPU time 4.14 seconds
Started Sep 04 02:19:03 AM UTC 24
Finished Sep 04 02:19:08 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244409269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.3244409269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.625384799
Short name T731
Test name
Test status
Simulation time 2454601733 ps
CPU time 4.74 seconds
Started Sep 04 02:19:03 AM UTC 24
Finished Sep 04 02:19:09 AM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625384799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.625384799
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.3131368247
Short name T728
Test name
Test status
Simulation time 2234544973 ps
CPU time 4.01 seconds
Started Sep 04 02:19:03 AM UTC 24
Finished Sep 04 02:19:08 AM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131368247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3131368247
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2895469030
Short name T734
Test name
Test status
Simulation time 2510188752 ps
CPU time 8.07 seconds
Started Sep 04 02:19:03 AM UTC 24
Finished Sep 04 02:19:12 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895469030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.2895469030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.1684889782
Short name T726
Test name
Test status
Simulation time 2133863007 ps
CPU time 2.2 seconds
Started Sep 04 02:19:02 AM UTC 24
Finished Sep 04 02:19:05 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684889782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.1684889782
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1852450809
Short name T132
Test name
Test status
Simulation time 92770931122 ps
CPU time 69.22 seconds
Started Sep 04 02:19:06 AM UTC 24
Finished Sep 04 02:20:17 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852450809 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.1852450809
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.37952585
Short name T742
Test name
Test status
Simulation time 3759987745 ps
CPU time 11.25 seconds
Started Sep 04 02:19:05 AM UTC 24
Finished Sep 04 02:19:18 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=37952585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.37952585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1082256426
Short name T155
Test name
Test status
Simulation time 11761046027 ps
CPU time 4.35 seconds
Started Sep 04 02:19:04 AM UTC 24
Finished Sep 04 02:19:09 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082256426 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.1082256426
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.535144205
Short name T751
Test name
Test status
Simulation time 2010640861 ps
CPU time 7.21 seconds
Started Sep 04 02:19:14 AM UTC 24
Finished Sep 04 02:19:22 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535144205 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.535144205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1332423991
Short name T739
Test name
Test status
Simulation time 3695184048 ps
CPU time 2.74 seconds
Started Sep 04 02:19:11 AM UTC 24
Finished Sep 04 02:19:15 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332423991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1332423991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.210603231
Short name T789
Test name
Test status
Simulation time 83583879290 ps
CPU time 259.85 seconds
Started Sep 04 02:19:12 AM UTC 24
Finished Sep 04 02:23:36 AM UTC 24
Peak memory 210316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210603231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_with_pre_cond.210603231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.143961469
Short name T747
Test name
Test status
Simulation time 3582615745 ps
CPU time 8.42 seconds
Started Sep 04 02:19:10 AM UTC 24
Finished Sep 04 02:19:20 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143961469 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.143961469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.470893819
Short name T253
Test name
Test status
Simulation time 4048929863 ps
CPU time 4.75 seconds
Started Sep 04 02:19:12 AM UTC 24
Finished Sep 04 02:19:18 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470893819 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.470893819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.793724915
Short name T740
Test name
Test status
Simulation time 2622896391 ps
CPU time 4.28 seconds
Started Sep 04 02:19:10 AM UTC 24
Finished Sep 04 02:19:15 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793724915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.793724915
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3772438175
Short name T745
Test name
Test status
Simulation time 2450756672 ps
CPU time 8.43 seconds
Started Sep 04 02:19:09 AM UTC 24
Finished Sep 04 02:19:18 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772438175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3772438175
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.734081495
Short name T735
Test name
Test status
Simulation time 2055049700 ps
CPU time 2.32 seconds
Started Sep 04 02:19:09 AM UTC 24
Finished Sep 04 02:19:12 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734081495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.734081495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3472507775
Short name T749
Test name
Test status
Simulation time 2514899382 ps
CPU time 9.17 seconds
Started Sep 04 02:19:10 AM UTC 24
Finished Sep 04 02:19:20 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472507775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3472507775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3773017824
Short name T741
Test name
Test status
Simulation time 2110777279 ps
CPU time 6.57 seconds
Started Sep 04 02:19:09 AM UTC 24
Finished Sep 04 02:19:16 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773017824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3773017824
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.397210225
Short name T438
Test name
Test status
Simulation time 1763243818948 ps
CPU time 1986.67 seconds
Started Sep 04 02:19:12 AM UTC 24
Finished Sep 04 02:52:38 AM UTC 24
Peak memory 212820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397210225 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.397210225
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2826165218
Short name T755
Test name
Test status
Simulation time 9128214458 ps
CPU time 17.32 seconds
Started Sep 04 02:19:12 AM UTC 24
Finished Sep 04 02:19:31 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2826165218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.2826165218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3883523261
Short name T738
Test name
Test status
Simulation time 9003240511 ps
CPU time 2.68 seconds
Started Sep 04 02:19:11 AM UTC 24
Finished Sep 04 02:19:15 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883523261 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.3883523261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.2141365033
Short name T752
Test name
Test status
Simulation time 2032321576 ps
CPU time 2.09 seconds
Started Sep 04 02:19:21 AM UTC 24
Finished Sep 04 02:19:24 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141365033 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.2141365033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2156252597
Short name T750
Test name
Test status
Simulation time 3263623039 ps
CPU time 1.43 seconds
Started Sep 04 02:19:19 AM UTC 24
Finished Sep 04 02:19:22 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156252597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.2156252597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.513406378
Short name T795
Test name
Test status
Simulation time 104599583729 ps
CPU time 309.94 seconds
Started Sep 04 02:19:19 AM UTC 24
Finished Sep 04 02:24:33 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513406378 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.513406378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.198335469
Short name T756
Test name
Test status
Simulation time 67582010973 ps
CPU time 15.06 seconds
Started Sep 04 02:19:20 AM UTC 24
Finished Sep 04 02:19:37 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198335469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.198335469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.210123522
Short name T799
Test name
Test status
Simulation time 563173094321 ps
CPU time 1781.33 seconds
Started Sep 04 02:19:18 AM UTC 24
Finished Sep 04 02:49:18 AM UTC 24
Peak memory 212856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210123522 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.210123522
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.4253192196
Short name T266
Test name
Test status
Simulation time 3928026876 ps
CPU time 1.88 seconds
Started Sep 04 02:19:19 AM UTC 24
Finished Sep 04 02:19:22 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253192196 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.4253192196
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.314012405
Short name T754
Test name
Test status
Simulation time 2612490023 ps
CPU time 12.54 seconds
Started Sep 04 02:19:17 AM UTC 24
Finished Sep 04 02:19:31 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314012405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.314012405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.401441926
Short name T746
Test name
Test status
Simulation time 2503282473 ps
CPU time 2.21 seconds
Started Sep 04 02:19:16 AM UTC 24
Finished Sep 04 02:19:19 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401441926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.401441926
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.506333321
Short name T753
Test name
Test status
Simulation time 2037017892 ps
CPU time 7.75 seconds
Started Sep 04 02:19:16 AM UTC 24
Finished Sep 04 02:19:25 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506333321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.506333321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.1822361201
Short name T748
Test name
Test status
Simulation time 2530060879 ps
CPU time 3.33 seconds
Started Sep 04 02:19:16 AM UTC 24
Finished Sep 04 02:19:20 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822361201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1822361201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.3601904942
Short name T743
Test name
Test status
Simulation time 2132778252 ps
CPU time 3.19 seconds
Started Sep 04 02:19:14 AM UTC 24
Finished Sep 04 02:19:18 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601904942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.3601904942
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2858606599
Short name T393
Test name
Test status
Simulation time 122172817155 ps
CPU time 88.25 seconds
Started Sep 04 02:19:21 AM UTC 24
Finished Sep 04 02:20:51 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858606599 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.2858606599
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2885578498
Short name T757
Test name
Test status
Simulation time 3578012301 ps
CPU time 17.52 seconds
Started Sep 04 02:19:20 AM UTC 24
Finished Sep 04 02:19:39 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2885578498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.2885578498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.580385801
Short name T102
Test name
Test status
Simulation time 2011826981 ps
CPU time 7.24 seconds
Started Sep 04 02:13:59 AM UTC 24
Finished Sep 04 02:14:07 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580385801 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.580385801
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1321855258
Short name T126
Test name
Test status
Simulation time 53686782220 ps
CPU time 128.98 seconds
Started Sep 04 02:13:56 AM UTC 24
Finished Sep 04 02:16:07 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321855258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.1321855258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1566083148
Short name T453
Test name
Test status
Simulation time 2631300542 ps
CPU time 6.83 seconds
Started Sep 04 02:13:54 AM UTC 24
Finished Sep 04 02:14:02 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566083148 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.1566083148
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.2722203192
Short name T50
Test name
Test status
Simulation time 3216626797 ps
CPU time 3.49 seconds
Started Sep 04 02:13:56 AM UTC 24
Finished Sep 04 02:14:01 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722203192 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.2722203192
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1982832558
Short name T165
Test name
Test status
Simulation time 2623886644 ps
CPU time 3.99 seconds
Started Sep 04 02:13:53 AM UTC 24
Finished Sep 04 02:13:58 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982832558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1982832558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.4207173525
Short name T85
Test name
Test status
Simulation time 2449301439 ps
CPU time 12.2 seconds
Started Sep 04 02:13:50 AM UTC 24
Finished Sep 04 02:14:03 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207173525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.4207173525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.520798023
Short name T296
Test name
Test status
Simulation time 2203788578 ps
CPU time 8.52 seconds
Started Sep 04 02:13:50 AM UTC 24
Finished Sep 04 02:13:59 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520798023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.520798023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.779048022
Short name T295
Test name
Test status
Simulation time 2521498058 ps
CPU time 7.09 seconds
Started Sep 04 02:13:51 AM UTC 24
Finished Sep 04 02:13:59 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779048022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.779048022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.656928178
Short name T225
Test name
Test status
Simulation time 2112248559 ps
CPU time 8.56 seconds
Started Sep 04 02:13:48 AM UTC 24
Finished Sep 04 02:13:58 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656928178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.656928178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3991984102
Short name T62
Test name
Test status
Simulation time 6597567605 ps
CPU time 5.28 seconds
Started Sep 04 02:13:56 AM UTC 24
Finished Sep 04 02:14:03 AM UTC 24
Peak memory 220868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3991984102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.3991984102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2946333346
Short name T422
Test name
Test status
Simulation time 107500065373 ps
CPU time 43.1 seconds
Started Sep 04 02:19:22 AM UTC 24
Finished Sep 04 02:20:06 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946333346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_with_pre_cond.2946333346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3442838618
Short name T409
Test name
Test status
Simulation time 79920332615 ps
CPU time 290.45 seconds
Started Sep 04 02:19:22 AM UTC 24
Finished Sep 04 02:24:16 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442838618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.3442838618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2865572067
Short name T759
Test name
Test status
Simulation time 25103960101 ps
CPU time 21.62 seconds
Started Sep 04 02:19:23 AM UTC 24
Finished Sep 04 02:19:46 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865572067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.2865572067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2512966269
Short name T769
Test name
Test status
Simulation time 23329543805 ps
CPU time 77.86 seconds
Started Sep 04 02:19:23 AM UTC 24
Finished Sep 04 02:20:43 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512966269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_with_pre_cond.2512966269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.4255630827
Short name T761
Test name
Test status
Simulation time 26093735079 ps
CPU time 34.44 seconds
Started Sep 04 02:19:23 AM UTC 24
Finished Sep 04 02:19:59 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255630827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_with_pre_cond.4255630827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3964191095
Short name T765
Test name
Test status
Simulation time 28045743732 ps
CPU time 56.76 seconds
Started Sep 04 02:19:23 AM UTC 24
Finished Sep 04 02:20:21 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964191095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.3964191095
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3390875982
Short name T773
Test name
Test status
Simulation time 115902467673 ps
CPU time 100.28 seconds
Started Sep 04 02:19:25 AM UTC 24
Finished Sep 04 02:21:08 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390875982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.3390875982
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.4224638332
Short name T101
Test name
Test status
Simulation time 2034012328 ps
CPU time 3.24 seconds
Started Sep 04 02:14:03 AM UTC 24
Finished Sep 04 02:14:07 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224638332 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.4224638332
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.492591035
Short name T64
Test name
Test status
Simulation time 3502651376 ps
CPU time 9.25 seconds
Started Sep 04 02:14:00 AM UTC 24
Finished Sep 04 02:14:10 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492591035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.492591035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2948248488
Short name T444
Test name
Test status
Simulation time 74331203130 ps
CPU time 199.15 seconds
Started Sep 04 02:14:01 AM UTC 24
Finished Sep 04 02:17:23 AM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948248488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.2948248488
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.4167256561
Short name T100
Test name
Test status
Simulation time 4360248164 ps
CPU time 4.35 seconds
Started Sep 04 02:13:59 AM UTC 24
Finished Sep 04 02:14:04 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167256561 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.4167256561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.1815315920
Short name T44
Test name
Test status
Simulation time 4653634845 ps
CPU time 12.24 seconds
Started Sep 04 02:14:01 AM UTC 24
Finished Sep 04 02:14:15 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815315920 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.1815315920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.970931664
Short name T99
Test name
Test status
Simulation time 2628945981 ps
CPU time 4.27 seconds
Started Sep 04 02:13:59 AM UTC 24
Finished Sep 04 02:14:04 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970931664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.970931664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2436134928
Short name T87
Test name
Test status
Simulation time 2481767156 ps
CPU time 4.46 seconds
Started Sep 04 02:13:59 AM UTC 24
Finished Sep 04 02:14:04 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436134928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2436134928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.326208089
Short name T452
Test name
Test status
Simulation time 2266822473 ps
CPU time 3.27 seconds
Started Sep 04 02:13:59 AM UTC 24
Finished Sep 04 02:14:03 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326208089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.326208089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.2639638114
Short name T98
Test name
Test status
Simulation time 2514756984 ps
CPU time 3.69 seconds
Started Sep 04 02:13:59 AM UTC 24
Finished Sep 04 02:14:04 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639638114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.2639638114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.83347828
Short name T454
Test name
Test status
Simulation time 2115181127 ps
CPU time 7.07 seconds
Started Sep 04 02:13:59 AM UTC 24
Finished Sep 04 02:14:07 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83347828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.83347828
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3083443906
Short name T143
Test name
Test status
Simulation time 11925338178 ps
CPU time 4.77 seconds
Started Sep 04 02:14:02 AM UTC 24
Finished Sep 04 02:14:07 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083443906 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.3083443906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3892055111
Short name T75
Test name
Test status
Simulation time 12760147861 ps
CPU time 4.26 seconds
Started Sep 04 02:14:01 AM UTC 24
Finished Sep 04 02:14:07 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3892055111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.3892055111
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3004678582
Short name T81
Test name
Test status
Simulation time 7562251482 ps
CPU time 11.81 seconds
Started Sep 04 02:14:00 AM UTC 24
Finished Sep 04 02:14:13 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004678582 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.3004678582
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1140684591
Short name T776
Test name
Test status
Simulation time 29828165355 ps
CPU time 98.1 seconds
Started Sep 04 02:19:37 AM UTC 24
Finished Sep 04 02:21:17 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140684591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.1140684591
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2380220878
Short name T766
Test name
Test status
Simulation time 57492151140 ps
CPU time 40.4 seconds
Started Sep 04 02:19:42 AM UTC 24
Finished Sep 04 02:20:24 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380220878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_with_pre_cond.2380220878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.837219819
Short name T787
Test name
Test status
Simulation time 133877880604 ps
CPU time 196.42 seconds
Started Sep 04 02:19:43 AM UTC 24
Finished Sep 04 02:23:03 AM UTC 24
Peak memory 210456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837219819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.837219819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1975852495
Short name T428
Test name
Test status
Simulation time 53701480620 ps
CPU time 52.14 seconds
Started Sep 04 02:19:52 AM UTC 24
Finished Sep 04 02:20:45 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975852495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.1975852495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.211605455
Short name T207
Test name
Test status
Simulation time 2034451505 ps
CPU time 2.72 seconds
Started Sep 04 02:14:08 AM UTC 24
Finished Sep 04 02:14:11 AM UTC 24
Peak memory 209816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211605455 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.211605455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.468349555
Short name T65
Test name
Test status
Simulation time 3214780609 ps
CPU time 8.74 seconds
Started Sep 04 02:14:05 AM UTC 24
Finished Sep 04 02:14:15 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468349555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.468349555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.247392510
Short name T42
Test name
Test status
Simulation time 174733613382 ps
CPU time 38.91 seconds
Started Sep 04 02:14:05 AM UTC 24
Finished Sep 04 02:14:46 AM UTC 24
Peak memory 210228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247392510 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.247392510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1878370060
Short name T41
Test name
Test status
Simulation time 59542829264 ps
CPU time 37.3 seconds
Started Sep 04 02:14:08 AM UTC 24
Finished Sep 04 02:14:46 AM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878370060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_with_pre_cond.1878370060
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1915611887
Short name T301
Test name
Test status
Simulation time 4326401236 ps
CPU time 3.38 seconds
Started Sep 04 02:14:05 AM UTC 24
Finished Sep 04 02:14:09 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915611887 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.1915611887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.840735967
Short name T49
Test name
Test status
Simulation time 4816926832 ps
CPU time 6.36 seconds
Started Sep 04 02:14:07 AM UTC 24
Finished Sep 04 02:14:15 AM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840735967 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.840735967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3529841981
Short name T197
Test name
Test status
Simulation time 2612435681 ps
CPU time 11.03 seconds
Started Sep 04 02:14:05 AM UTC 24
Finished Sep 04 02:14:17 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529841981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.3529841981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.809962559
Short name T88
Test name
Test status
Simulation time 2559352017 ps
CPU time 1.49 seconds
Started Sep 04 02:14:04 AM UTC 24
Finished Sep 04 02:14:06 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809962559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.809962559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.3409546297
Short name T300
Test name
Test status
Simulation time 2216622858 ps
CPU time 3.59 seconds
Started Sep 04 02:14:04 AM UTC 24
Finished Sep 04 02:14:08 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409546297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.3409546297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.1457372925
Short name T206
Test name
Test status
Simulation time 2515713646 ps
CPU time 6.15 seconds
Started Sep 04 02:14:04 AM UTC 24
Finished Sep 04 02:14:11 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457372925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.1457372925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2223129110
Short name T208
Test name
Test status
Simulation time 2110610241 ps
CPU time 6.81 seconds
Started Sep 04 02:14:04 AM UTC 24
Finished Sep 04 02:14:12 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223129110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.2223129110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2633497985
Short name T274
Test name
Test status
Simulation time 9874176909 ps
CPU time 11.8 seconds
Started Sep 04 02:14:08 AM UTC 24
Finished Sep 04 02:14:21 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633497985 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.2633497985
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1000360865
Short name T196
Test name
Test status
Simulation time 9413764765 ps
CPU time 7 seconds
Started Sep 04 02:14:08 AM UTC 24
Finished Sep 04 02:14:16 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1000360865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1000360865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3597382393
Short name T76
Test name
Test status
Simulation time 2890304727 ps
CPU time 2.34 seconds
Started Sep 04 02:14:05 AM UTC 24
Finished Sep 04 02:14:09 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597382393 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.3597382393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3863677758
Short name T779
Test name
Test status
Simulation time 26330828199 ps
CPU time 95.35 seconds
Started Sep 04 02:19:59 AM UTC 24
Finished Sep 04 02:21:36 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863677758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_with_pre_cond.3863677758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3786361359
Short name T778
Test name
Test status
Simulation time 95826083723 ps
CPU time 83.26 seconds
Started Sep 04 02:20:00 AM UTC 24
Finished Sep 04 02:21:25 AM UTC 24
Peak memory 210312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786361359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_with_pre_cond.3786361359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3079124937
Short name T427
Test name
Test status
Simulation time 56279899990 ps
CPU time 164.32 seconds
Started Sep 04 02:20:04 AM UTC 24
Finished Sep 04 02:22:51 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079124937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_with_pre_cond.3079124937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1277162272
Short name T788
Test name
Test status
Simulation time 135592237866 ps
CPU time 166.91 seconds
Started Sep 04 02:20:14 AM UTC 24
Finished Sep 04 02:23:04 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277162272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_with_pre_cond.1277162272
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3644823546
Short name T781
Test name
Test status
Simulation time 58714436269 ps
CPU time 85.37 seconds
Started Sep 04 02:20:19 AM UTC 24
Finished Sep 04 02:21:47 AM UTC 24
Peak memory 210644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644823546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.3644823546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1844690303
Short name T785
Test name
Test status
Simulation time 94803322477 ps
CPU time 151.43 seconds
Started Sep 04 02:20:22 AM UTC 24
Finished Sep 04 02:22:55 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844690303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_with_pre_cond.1844690303
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2702667035
Short name T198
Test name
Test status
Simulation time 2015263898 ps
CPU time 3.9 seconds
Started Sep 04 02:14:13 AM UTC 24
Finished Sep 04 02:14:18 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702667035 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.2702667035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.806397456
Short name T571
Test name
Test status
Simulation time 241130190991 ps
CPU time 157.08 seconds
Started Sep 04 02:14:10 AM UTC 24
Finished Sep 04 02:16:50 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806397456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.806397456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.2010406417
Short name T55
Test name
Test status
Simulation time 49536261454 ps
CPU time 23.39 seconds
Started Sep 04 02:14:10 AM UTC 24
Finished Sep 04 02:14:35 AM UTC 24
Peak memory 210108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010406417 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.2010406417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2135017570
Short name T31
Test name
Test status
Simulation time 32882732148 ps
CPU time 7.98 seconds
Started Sep 04 02:14:11 AM UTC 24
Finished Sep 04 02:14:20 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135017570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.2135017570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.627896236
Short name T210
Test name
Test status
Simulation time 3595684662 ps
CPU time 3.56 seconds
Started Sep 04 02:14:09 AM UTC 24
Finished Sep 04 02:14:14 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627896236 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.627896236
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.4059131652
Short name T215
Test name
Test status
Simulation time 92057936219 ps
CPU time 45.18 seconds
Started Sep 04 02:14:11 AM UTC 24
Finished Sep 04 02:14:58 AM UTC 24
Peak memory 210068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059131652 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.4059131652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2094730555
Short name T211
Test name
Test status
Simulation time 2618505243 ps
CPU time 4.43 seconds
Started Sep 04 02:14:09 AM UTC 24
Finished Sep 04 02:14:14 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094730555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.2094730555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.1340666808
Short name T199
Test name
Test status
Simulation time 2435769420 ps
CPU time 7.77 seconds
Started Sep 04 02:14:09 AM UTC 24
Finished Sep 04 02:14:18 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340666808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1340666808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.3226073681
Short name T209
Test name
Test status
Simulation time 2041668034 ps
CPU time 3.63 seconds
Started Sep 04 02:14:09 AM UTC 24
Finished Sep 04 02:14:14 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226073681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3226073681
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.2157673422
Short name T195
Test name
Test status
Simulation time 2514402276 ps
CPU time 5.32 seconds
Started Sep 04 02:14:09 AM UTC 24
Finished Sep 04 02:14:15 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157673422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2157673422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.4199041951
Short name T205
Test name
Test status
Simulation time 2133233794 ps
CPU time 2.23 seconds
Started Sep 04 02:14:08 AM UTC 24
Finished Sep 04 02:14:11 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199041951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.4199041951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.108117720
Short name T117
Test name
Test status
Simulation time 9200134670 ps
CPU time 29.15 seconds
Started Sep 04 02:14:12 AM UTC 24
Finished Sep 04 02:14:42 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108117720 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.108117720
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3507873536
Short name T236
Test name
Test status
Simulation time 4072150380 ps
CPU time 18.82 seconds
Started Sep 04 02:14:12 AM UTC 24
Finished Sep 04 02:14:31 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3507873536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.3507873536
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3020480325
Short name T77
Test name
Test status
Simulation time 3321670541 ps
CPU time 7.98 seconds
Started Sep 04 02:14:10 AM UTC 24
Finished Sep 04 02:14:19 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020480325 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.3020480325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2833843966
Short name T768
Test name
Test status
Simulation time 35035519349 ps
CPU time 14.71 seconds
Started Sep 04 02:20:24 AM UTC 24
Finished Sep 04 02:20:40 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833843966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.2833843966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1455838381
Short name T772
Test name
Test status
Simulation time 28085489206 ps
CPU time 39.05 seconds
Started Sep 04 02:20:25 AM UTC 24
Finished Sep 04 02:21:05 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455838381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_with_pre_cond.1455838381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3684845597
Short name T771
Test name
Test status
Simulation time 38229890057 ps
CPU time 26.96 seconds
Started Sep 04 02:20:29 AM UTC 24
Finished Sep 04 02:20:58 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684845597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_with_pre_cond.3684845597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.8322564
Short name T764
Test name
Test status
Simulation time 28078033633 ps
CPU time 107.5 seconds
Started Sep 04 02:20:30 AM UTC 24
Finished Sep 04 02:22:20 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8322564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_
TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_with_pre_cond.8322564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1542986143
Short name T786
Test name
Test status
Simulation time 45033339140 ps
CPU time 140.55 seconds
Started Sep 04 02:20:35 AM UTC 24
Finished Sep 04 02:22:58 AM UTC 24
Peak memory 210312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542986143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_with_pre_cond.1542986143
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.562812518
Short name T774
Test name
Test status
Simulation time 22834146983 ps
CPU time 27.81 seconds
Started Sep 04 02:20:39 AM UTC 24
Finished Sep 04 02:21:08 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562812518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_with_pre_cond.562812518
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3489623530
Short name T419
Test name
Test status
Simulation time 84355689494 ps
CPU time 77.96 seconds
Started Sep 04 02:20:40 AM UTC 24
Finished Sep 04 02:22:00 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489623530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.3489623530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3335354632
Short name T775
Test name
Test status
Simulation time 25844074928 ps
CPU time 31.23 seconds
Started Sep 04 02:20:41 AM UTC 24
Finished Sep 04 02:21:14 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335354632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_with_pre_cond.3335354632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.4206468558
Short name T790
Test name
Test status
Simulation time 66256351754 ps
CPU time 171.94 seconds
Started Sep 04 02:20:44 AM UTC 24
Finished Sep 04 02:23:38 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206468558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.4206468558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.1244851960
Short name T247
Test name
Test status
Simulation time 2011310508 ps
CPU time 10.02 seconds
Started Sep 04 02:14:18 AM UTC 24
Finished Sep 04 02:14:29 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244851960 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.1244851960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3796158761
Short name T763
Test name
Test status
Simulation time 114298442271 ps
CPU time 354.14 seconds
Started Sep 04 02:14:15 AM UTC 24
Finished Sep 04 02:20:14 AM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796158761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3796158761
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2708756864
Short name T346
Test name
Test status
Simulation time 3056063693 ps
CPU time 4.03 seconds
Started Sep 04 02:14:15 AM UTC 24
Finished Sep 04 02:14:20 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708756864 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.2708756864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3013963198
Short name T45
Test name
Test status
Simulation time 3311809406 ps
CPU time 3.93 seconds
Started Sep 04 02:14:16 AM UTC 24
Finished Sep 04 02:14:21 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013963198 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.3013963198
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.935160089
Short name T345
Test name
Test status
Simulation time 2622706049 ps
CPU time 3.04 seconds
Started Sep 04 02:14:15 AM UTC 24
Finished Sep 04 02:14:19 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935160089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.935160089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.162189456
Short name T200
Test name
Test status
Simulation time 2493076794 ps
CPU time 2.91 seconds
Started Sep 04 02:14:14 AM UTC 24
Finished Sep 04 02:14:18 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162189456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.162189456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1225114567
Short name T201
Test name
Test status
Simulation time 2091830809 ps
CPU time 2.14 seconds
Started Sep 04 02:14:15 AM UTC 24
Finished Sep 04 02:14:18 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225114567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1225114567
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1773086131
Short name T275
Test name
Test status
Simulation time 2516198984 ps
CPU time 4.85 seconds
Started Sep 04 02:14:15 AM UTC 24
Finished Sep 04 02:14:21 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773086131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.1773086131
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.1221302164
Short name T202
Test name
Test status
Simulation time 2111289152 ps
CPU time 5.23 seconds
Started Sep 04 02:14:13 AM UTC 24
Finished Sep 04 02:14:19 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221302164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.1221302164
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.2698636469
Short name T457
Test name
Test status
Simulation time 9247548178 ps
CPU time 26.19 seconds
Started Sep 04 02:14:17 AM UTC 24
Finished Sep 04 02:14:44 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698636469 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.2698636469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.221415656
Short name T109
Test name
Test status
Simulation time 2932280884 ps
CPU time 6.32 seconds
Started Sep 04 02:14:16 AM UTC 24
Finished Sep 04 02:14:24 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221415656 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.221415656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3404372898
Short name T414
Test name
Test status
Simulation time 97199334754 ps
CPU time 63.4 seconds
Started Sep 04 02:20:49 AM UTC 24
Finished Sep 04 02:21:54 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404372898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.3404372898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3024825686
Short name T777
Test name
Test status
Simulation time 91126039848 ps
CPU time 30.03 seconds
Started Sep 04 02:20:52 AM UTC 24
Finished Sep 04 02:21:23 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024825686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.3024825686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3775158485
Short name T780
Test name
Test status
Simulation time 64098155249 ps
CPU time 42.41 seconds
Started Sep 04 02:20:54 AM UTC 24
Finished Sep 04 02:21:38 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775158485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_with_pre_cond.3775158485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2299302352
Short name T418
Test name
Test status
Simulation time 73968209359 ps
CPU time 28.95 seconds
Started Sep 04 02:20:59 AM UTC 24
Finished Sep 04 02:21:29 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299302352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.2299302352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.101366218
Short name T426
Test name
Test status
Simulation time 104007153131 ps
CPU time 89.87 seconds
Started Sep 04 02:21:00 AM UTC 24
Finished Sep 04 02:22:32 AM UTC 24
Peak memory 210316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101366218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.101366218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2140383192
Short name T784
Test name
Test status
Simulation time 53200436357 ps
CPU time 89.42 seconds
Started Sep 04 02:21:06 AM UTC 24
Finished Sep 04 02:22:38 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140383192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.2140383192
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.458382747
Short name T783
Test name
Test status
Simulation time 37088960032 ps
CPU time 80.13 seconds
Started Sep 04 02:21:08 AM UTC 24
Finished Sep 04 02:22:30 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458382747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_with_pre_cond.458382747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.13179932
Short name T412
Test name
Test status
Simulation time 41702606722 ps
CPU time 31.01 seconds
Started Sep 04 02:21:09 AM UTC 24
Finished Sep 04 02:21:42 AM UTC 24
Peak memory 210328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13179932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_with_pre_cond.13179932
Directory /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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