Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.15	89.13	90.91		66.67	85.71	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.15	89.13	90.91		66.67	85.71	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.55	93.48	95.45		83.33	90.48	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.55	93.48	95.45		83.33	90.48	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T20 T52 T48 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T20 T52 T48 
149        1/1                    cnt_en = 1'b1;
           Tests:       T20 T52 T48 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T20 T52 T48 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T20 T52 T48 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T20 T52 T48 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T52 T48 
167        1/1                    if (trigger_active) begin
           Tests:       T20 T52 T48 
168        1/1                      state_d = DetectSt;
           Tests:       T20 T52 T48 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T20 T52 T48 
182        1/1                  cnt_en = 1'b1;
           Tests:       T20 T52 T48 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T20 T52 T48 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T20 T52 T48 
191        1/1                      state_d = StableSt;
           Tests:       T20 T52 T48 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T20 T52 T48 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T20 T52 T48 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T20 T52 T48 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T20 T52 T48 
206        1/1                    state_d = IdleSt;
           Tests:       T20 T76 T189 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T20 T52 T48 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T52,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T52,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T52,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T20,T52
1	0	Covered	T4,T5,T1
1	1	Covered	T20,T52,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T52,T48
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T52,T48
0	1	Covered	T189,T217,T120
1	0	Covered	T20,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T52,T48
1	-	Covered	T189,T217,T120

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T52,T48
DetectSt	168	Covered	T20,T52,T48
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T20,T52,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T52,T48
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T20,T52,T48
IdleSt->DebounceSt	148	Covered	T20,T52,T48
StableSt->IdleSt	206	Covered	T20,T76,T189

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	18	85.71
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T52,T48
0	1	Covered	T20,T52,T48
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T52,T48
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T52,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T52,T48
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T52,T48
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T20,T52,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T76,T189
StableSt	-	-	-	-	-	-	0	Covered	T20,T52,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	42	0	0
CntIncr_A	6363167	821	0	0
CntNoWrap_A	6363167	5879356	0	0
DetectStDropOut_A	6363167	0	0	0
DetectedOut_A	6363167	1226	0	0
DetectedPulseOut_A	6363167	21	0	0
DisabledIdleSt_A	6363167	5674589	0	0
DisabledNoDetection_A	6363167	5676560	0	0
EnterDebounceSt_A	6363167	21	0	0
EnterDetectSt_A	6363167	21	0	0
EnterStableSt_A	6363167	21	0	0
PulseIsPulse_A	6363167	21	0	0
StayInStableSt	6363167	1194	0	0
gen_high_level_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	42	0	0
T20	8114	2	0	0
T32	7318	0	0	0
T48	0	2	0	0
T52	566	2	0	0
T53	0	2	0	0
T76	0	2	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	2	0	0
T122	407	0	0	0
T189	0	2	0	0
T217	0	2	0	0
T219	0	2	0	0
T220	0	2	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	821	0	0
T20	8114	20	0	0
T32	7318	0	0	0
T48	0	33	0	0
T52	566	57	0	0
T53	0	58	0	0
T76	0	19	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	49	0	0
T122	407	0	0	0
T189	0	74	0	0
T217	0	80	0	0
T219	0	16	0	0
T220	0	12	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5879356	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1226	0	0
T20	8114	23	0	0
T32	7318	0	0	0
T48	0	127	0	0
T52	566	43	0	0
T53	0	230	0	0
T76	0	26	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	3	0	0
T122	407	0	0	0
T189	0	5	0	0
T217	0	1	0	0
T219	0	42	0	0
T220	0	133	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	21	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T48	0	1	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T189	0	1	0	0
T217	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5674589	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5676560	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	21	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T48	0	1	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T189	0	1	0	0
T217	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	21	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T48	0	1	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T189	0	1	0	0
T217	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	21	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T48	0	1	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T189	0	1	0	0
T217	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	21	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T48	0	1	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T189	0	1	0	0
T217	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1194	0	0
T20	8114	22	0	0
T32	7318	0	0	0
T48	0	125	0	0
T52	566	41	0	0
T53	0	228	0	0
T76	0	25	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	2	0	0
T122	407	0	0	0
T189	0	4	0	0
T205	0	3	0	0
T219	0	40	0	0
T220	0	132	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	8	0	0
T114	30125	0	0	0
T120	0	1	0	0
T130	0	1	0	0
T153	733	0	0	0
T189	1020	1	0	0
T205	0	1	0	0
T217	885	1	0	0
T220	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0
T226	2209	0	0	0
T227	719	0	0	0
T228	2970	0	0	0
T229	439	0	0	0
T230	402	0	0	0
T231	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T47 T20 T48 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T47 T20 T48 
149        1/1                    cnt_en = 1'b1;
           Tests:       T47 T20 T48 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T47 T20 T48 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T47 T20 T48 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T47 T20 T48 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T47 T20 T48 
167        1/1                    if (trigger_active) begin
           Tests:       T47 T20 T48 
168        1/1                      state_d = DetectSt;
           Tests:       T47 T20 T48 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T51 T218 T220 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T47 T20 T48 
182        1/1                  cnt_en = 1'b1;
           Tests:       T47 T20 T48 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T47 T20 T48 
186        1/1                    state_d = IdleSt;
           Tests:       T197 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T197 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T47 T20 T48 
191        1/1                      state_d = StableSt;
           Tests:       T47 T20 T48 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T47 T20 T48 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T47 T20 T48 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T47 T20 T48 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T47 T20 T48 
206        1/1                    state_d = IdleSt;
           Tests:       T47 T20 T48 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T47 T20 T48 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T47,T20,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T47,T20,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T47,T20,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T47,T20,T48
1	0	Covered	T4,T5,T14
1	1	Covered	T47,T20,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T47,T20,T48
0	1	Covered	T197
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T20,T48
0	1	Covered	T47,T48,T54
1	0	Covered	T20,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T20,T48
1	-	Covered	T47,T48,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T47,T20,T48
DetectSt	168	Covered	T47,T20,T48
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T47,T20,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T47,T20,T48
DebounceSt->IdleSt	163	Covered	T51,T218,T220
DetectSt->IdleSt	186	Covered	T197
DetectSt->StableSt	191	Covered	T47,T20,T48
IdleSt->DebounceSt	148	Covered	T47,T20,T48
StableSt->IdleSt	206	Covered	T47,T20,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T47,T20,T48
0	1	Covered	T47,T20,T48
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T20,T48
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T47,T20,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T47,T20,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T218,T220
DebounceSt	-	0	0	-	-	-	-	Covered	T47,T20,T48
DetectSt	-	-	-	-	1	-	-	Covered	T197
DetectSt	-	-	-	-	0	1	-	Covered	T47,T20,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T20,T48
StableSt	-	-	-	-	-	-	0	Covered	T47,T20,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	85	0	0
CntIncr_A	6363167	45191	0	0
CntNoWrap_A	6363167	5879313	0	0
DetectStDropOut_A	6363167	1	0	0
DetectedOut_A	6363167	18557	0	0
DetectedPulseOut_A	6363167	38	0	0
DisabledIdleSt_A	6363167	5766548	0	0
DisabledNoDetection_A	6363167	5768520	0	0
EnterDebounceSt_A	6363167	46	0	0
EnterDetectSt_A	6363167	39	0	0
EnterStableSt_A	6363167	38	0	0
PulseIsPulse_A	6363167	38	0	0
StayInStableSt	6363167	18505	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6363167	1926	0	0
gen_low_level_sva.LowLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	85	0	0
T20	0	2	0	0
T47	798	2	0	0
T48	0	2	0	0
T51	0	5	0	0
T53	0	2	0	0
T54	0	2	0	0
T63	462	0	0	0
T76	0	2	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	2	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T232	0	4	0	0
T233	0	2	0	0
T234	523	0	0	0
T235	939	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	45191	0	0
T20	0	20	0	0
T47	798	38	0	0
T48	0	33	0	0
T51	0	111	0	0
T53	0	58	0	0
T54	0	93	0	0
T63	462	0	0	0
T76	0	19	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	47	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T232	0	194	0	0
T233	0	33	0	0
T234	523	0	0	0
T235	939	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5879313	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1	0	0
T111	1956	0	0	0
T174	204281	0	0	0
T197	970	1	0	0
T236	406	0	0	0
T237	20074	0	0	0
T238	499	0	0	0
T239	744	0	0	0
T240	3124	0	0	0
T241	422	0	0	0
T242	825	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	18557	0	0
T20	0	25	0	0
T47	798	134	0	0
T48	0	26	0	0
T51	0	140	0	0
T53	0	44	0	0
T54	0	1	0	0
T63	462	0	0	0
T76	0	27	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	87	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T232	0	85	0	0
T233	0	10	0	0
T234	523	0	0	0
T235	939	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	38	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T232	0	2	0	0
T233	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5766548	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5768520	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	46	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T51	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T232	0	2	0	0
T233	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	39	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T232	0	2	0	0
T233	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	38	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T232	0	2	0	0
T233	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	38	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T232	0	2	0	0
T233	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	18505	0	0
T20	0	24	0	0
T47	798	133	0	0
T48	0	25	0	0
T51	0	137	0	0
T53	0	43	0	0
T63	462	0	0	0
T76	0	26	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	85	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T216	0	38	0	0
T232	0	82	0	0
T233	0	9	0	0
T234	523	0	0	0
T235	939	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1926	0	0
T1	485	0	0	0
T2	486	0	0	0
T3	672	2	0	0
T4	447	5	0	0
T5	493	5	0	0
T6	0	1	0	0
T8	507	0	0	0
T13	822	0	0	0
T14	494	5	0	0
T15	421	2	0	0
T16	504	4	0	0
T26	0	6	0	0
T27	0	3	0	0
T70	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	22	0	0
T47	798	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T63	462	0	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0
T232	0	1	0	0
T233	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T13 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T47 T20 T55 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T47 T20 T55 
149        1/1                    cnt_en = 1'b1;
           Tests:       T47 T20 T55 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T47 T20 T55 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T47 T20 T55 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T47 T20 T55 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T47 T20 T55 
167        1/1                    if (trigger_active) begin
           Tests:       T47 T20 T55 
168        1/1                      state_d = DetectSt;
           Tests:       T47 T20 T55 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T47 T20 T55 
182        1/1                  cnt_en = 1'b1;
           Tests:       T47 T20 T55 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T47 T20 T55 
186        1/1                    state_d = IdleSt;
           Tests:       T119 T120 T206 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T119 T120 T206 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T47 T20 T55 
191        1/1                      state_d = StableSt;
           Tests:       T47 T20 T55 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T47 T20 T55 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T47 T20 T55 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T47 T20 T55 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T47 T20 T55 
206        1/1                    state_d = IdleSt;
           Tests:       T47 T20 T55 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T47 T20 T55 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T47,T20,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T47,T20,T55

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T47,T20,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T47,T20
1	0	Covered	T4,T5,T13
1	1	Covered	T47,T20,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T47,T20,T55
0	1	Covered	T119,T120,T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T20,T55
0	1	Covered	T47,T55,T57
1	0	Covered	T20,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T20,T55
1	-	Covered	T47,T55,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T47,T20,T55
DetectSt	168	Covered	T47,T20,T55
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T47,T20,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T47,T20,T55
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T119,T120,T206
DetectSt->StableSt	191	Covered	T47,T20,T55
IdleSt->DebounceSt	148	Covered	T47,T20,T55
StableSt->IdleSt	206	Covered	T47,T20,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T47,T20,T55
0	1	Covered	T47,T20,T55
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T20,T55
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T47,T20,T55
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T47,T20,T55
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T47,T20,T55
DetectSt	-	-	-	-	1	-	-	Covered	T119,T120,T206
DetectSt	-	-	-	-	0	1	-	Covered	T47,T20,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T20,T55
StableSt	-	-	-	-	-	-	0	Covered	T47,T20,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	92	0	0
CntIncr_A	6363167	98033	0	0
CntNoWrap_A	6363167	5879306	0	0
DetectStDropOut_A	6363167	3	0	0
DetectedOut_A	6363167	64885	0	0
DetectedPulseOut_A	6363167	43	0	0
DisabledIdleSt_A	6363167	5571851	0	0
DisabledNoDetection_A	6363167	5573822	0	0
EnterDebounceSt_A	6363167	46	0	0
EnterDetectSt_A	6363167	46	0	0
EnterStableSt_A	6363167	43	0	0
PulseIsPulse_A	6363167	43	0	0
StayInStableSt	6363167	64823	0	0
gen_high_level_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	92	0	0
T20	0	2	0	0
T47	798	6	0	0
T51	0	2	0	0
T53	0	2	0	0
T55	0	4	0	0
T57	0	2	0	0
T63	462	0	0	0
T76	0	2	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	2	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T228	0	2	0	0
T234	523	0	0	0
T235	939	0	0	0
T243	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	98033	0	0
T20	0	20	0	0
T47	798	114	0	0
T51	0	37	0	0
T53	0	58	0	0
T55	0	74	0	0
T57	0	52	0	0
T63	462	0	0	0
T76	0	19	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	47	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T228	0	75	0	0
T234	523	0	0	0
T235	939	0	0	0
T243	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5879306	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	3	0	0
T42	12969	0	0	0
T107	3287	0	0	0
T119	543	1	0	0
T120	0	1	0	0
T206	0	1	0	0
T232	1169	0	0	0
T244	422	0	0	0
T245	3397	0	0	0
T246	402	0	0	0
T247	649	0	0	0
T248	444	0	0	0
T249	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	64885	0	0
T20	0	24	0	0
T47	798	99	0	0
T51	0	144	0	0
T53	0	40	0	0
T55	0	126	0	0
T57	0	38	0	0
T63	462	0	0	0
T76	0	27	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T120	0	95	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T228	0	44	0	0
T234	523	0	0	0
T235	939	0	0	0
T243	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	43	0	0
T20	0	1	0	0
T47	798	3	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T120	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T228	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0
T243	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5571851	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	3	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5573822	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	3	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	46	0	0
T20	0	1	0	0
T47	798	3	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T228	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0
T243	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	46	0	0
T20	0	1	0	0
T47	798	3	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T119	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T228	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0
T243	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	43	0	0
T20	0	1	0	0
T47	798	3	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T120	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T228	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0
T243	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	43	0	0
T20	0	1	0	0
T47	798	3	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T120	0	1	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T228	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0
T243	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	64823	0	0
T20	0	23	0	0
T47	798	95	0	0
T51	0	142	0	0
T53	0	39	0	0
T55	0	123	0	0
T57	0	37	0	0
T63	462	0	0	0
T76	0	26	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T120	0	93	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T228	0	42	0	0
T234	523	0	0	0
T235	939	0	0	0
T243	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	22	0	0
T47	798	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T63	462	0	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T187	0	1	0	0
T190	0	1	0	0
T195	0	1	0	0
T218	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0
T250	0	2	0	0
T251	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T20 T52 T50 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T20 T52 T50 
149        1/1                    cnt_en = 1'b1;
           Tests:       T20 T52 T50 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T20 T52 T50 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T20 T52 T50 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T20 T52 T50 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T52 T50 
167        1/1                    if (trigger_active) begin
           Tests:       T20 T52 T50 
168        1/1                      state_d = DetectSt;
           Tests:       T20 T52 T50 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T225 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T20 T52 T50 
182        1/1                  cnt_en = 1'b1;
           Tests:       T20 T52 T50 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T20 T52 T50 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T20 T52 T50 
191        1/1                      state_d = StableSt;
           Tests:       T20 T52 T50 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T20 T52 T50 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T20 T52 T50 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T20 T52 T50 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T20 T52 T50 
206        1/1                    state_d = IdleSt;
           Tests:       T20 T50 T76 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T20 T52 T50 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T52,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T52,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T52,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T28,T20
1	0	Covered	T4,T5,T13
1	1	Covered	T20,T52,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T52,T50
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T52,T50
0	1	Covered	T50,T120,T181
1	0	Covered	T20,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T52,T50
1	-	Covered	T50,T120,T181

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T52,T50
DetectSt	168	Covered	T20,T52,T50
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T20,T52,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T52,T50
DebounceSt->IdleSt	163	Covered	T225
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T20,T52,T50
IdleSt->DebounceSt	148	Covered	T20,T52,T50
StableSt->IdleSt	206	Covered	T20,T50,T76

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T52,T50
0	1	Covered	T20,T52,T50
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T52,T50
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T52,T50
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T52,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T225
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T52,T50
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T20,T52,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T50,T76
StableSt	-	-	-	-	-	-	0	Covered	T20,T52,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	47	0	0
CntIncr_A	6363167	44072	0	0
CntNoWrap_A	6363167	5879351	0	0
DetectStDropOut_A	6363167	0	0	0
DetectedOut_A	6363167	2017	0	0
DetectedPulseOut_A	6363167	23	0	0
DisabledIdleSt_A	6363167	5767953	0	0
DisabledNoDetection_A	6363167	5769927	0	0
EnterDebounceSt_A	6363167	24	0	0
EnterDetectSt_A	6363167	23	0	0
EnterStableSt_A	6363167	23	0	0
PulseIsPulse_A	6363167	23	0	0
StayInStableSt	6363167	1983	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6363167	5555	0	0
gen_low_level_sva.LowLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	47	0	0
T20	8114	2	0	0
T32	7318	0	0	0
T50	0	4	0	0
T52	566	2	0	0
T53	0	2	0	0
T76	0	2	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	2	0	0
T122	407	0	0	0
T181	0	2	0	0
T218	0	2	0	0
T220	0	4	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T252	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	44072	0	0
T20	8114	20	0	0
T32	7318	0	0	0
T50	0	168	0	0
T52	566	57	0	0
T53	0	58	0	0
T76	0	19	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	49	0	0
T122	407	0	0	0
T181	0	87	0	0
T218	0	37	0	0
T220	0	24	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T252	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5879351	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	2017	0	0
T20	8114	24	0	0
T32	7318	0	0	0
T50	0	225	0	0
T52	566	43	0	0
T53	0	132	0	0
T76	0	26	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	43	0	0
T122	407	0	0	0
T181	0	1	0	0
T218	0	232	0	0
T220	0	84	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T252	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	23	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T50	0	2	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T181	0	1	0	0
T218	0	1	0	0
T220	0	2	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T252	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5767953	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	3	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5769927	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	3	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	24	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T50	0	2	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T181	0	1	0	0
T218	0	1	0	0
T220	0	2	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T252	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	23	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T50	0	2	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T181	0	1	0	0
T218	0	1	0	0
T220	0	2	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T252	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	23	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T50	0	2	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T181	0	1	0	0
T218	0	1	0	0
T220	0	2	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T252	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	23	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T50	0	2	0	0
T52	566	1	0	0
T53	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	1	0	0
T122	407	0	0	0
T181	0	1	0	0
T218	0	1	0	0
T220	0	2	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T252	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1983	0	0
T20	8114	23	0	0
T32	7318	0	0	0
T50	0	222	0	0
T52	566	41	0	0
T53	0	130	0	0
T76	0	25	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T120	0	42	0	0
T122	407	0	0	0
T218	0	230	0	0
T220	0	81	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T252	0	113	0	0
T253	0	69	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5555	0	0
T1	485	0	0	0
T2	486	0	0	0
T3	672	0	0	0
T4	447	7	0	0
T5	493	5	0	0
T6	0	2	0	0
T8	507	0	0	0
T13	822	4	0	0
T14	494	6	0	0
T15	421	3	0	0
T16	504	5	0	0
T26	0	5	0	0
T27	0	3	0	0
T70	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	10	0	0
T50	3492	1	0	0
T59	7386	0	0	0
T80	958	0	0	0
T120	0	1	0	0
T130	0	1	0	0
T151	723	0	0	0
T181	0	1	0	0
T199	402	0	0	0
T200	502	0	0	0
T201	697	0	0	0
T202	420	0	0	0
T203	893	0	0	0
T204	522	0	0	0
T220	0	1	0	0
T225	0	1	0	0
T253	0	1	0	0
T254	0	1	0	0
T255	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T28 T47 T20 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T28 T47 T20 
149        1/1                    cnt_en = 1'b1;
           Tests:       T28 T47 T20 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T28 T47 T20 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T28 T47 T20 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T28 T47 T20 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T47 T20 
167        1/1                    if (trigger_active) begin
           Tests:       T28 T47 T20 
168        1/1                      state_d = DetectSt;
           Tests:       T28 T47 T20 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T49 T216 T220 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T28 T47 T20 
182        1/1                  cnt_en = 1'b1;
           Tests:       T28 T47 T20 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T28 T47 T20 
186        1/1                    state_d = IdleSt;
           Tests:       T54 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T54 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T28 T47 T20 
191        1/1                      state_d = StableSt;
           Tests:       T28 T47 T20 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T28 T47 T20 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T28 T47 T20 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T28 T47 T20 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T28 T47 T20 
206        1/1                    state_d = IdleSt;
           Tests:       T47 T20 T48 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T28 T47 T20 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T47,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T47,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T28,T47,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T20
1	0	Covered	T4,T5,T1
1	1	Covered	T28,T47,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T47,T20
0	1	Covered	T54
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T47,T20
0	1	Covered	T47,T48,T232
1	0	Covered	T20,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T47,T20
1	-	Covered	T47,T48,T232

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T47,T20
DetectSt	168	Covered	T28,T47,T20
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T28,T47,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T47,T20
DebounceSt->IdleSt	163	Covered	T49,T188,T216
DetectSt->IdleSt	186	Covered	T54
DetectSt->StableSt	191	Covered	T28,T47,T20
IdleSt->DebounceSt	148	Covered	T28,T47,T20
StableSt->IdleSt	206	Covered	T47,T20,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T28,T47,T20
0	1	Covered	T28,T47,T20
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T47,T20
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T47,T20
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T47,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T216,T220
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T47,T20
DetectSt	-	-	-	-	1	-	-	Covered	T54
DetectSt	-	-	-	-	0	1	-	Covered	T28,T47,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T20,T48
StableSt	-	-	-	-	-	-	0	Covered	T28,T47,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	90	0	0
CntIncr_A	6363167	55138	0	0
CntNoWrap_A	6363167	5879308	0	0
DetectStDropOut_A	6363167	1	0	0
DetectedOut_A	6363167	3145	0	0
DetectedPulseOut_A	6363167	40	0	0
DisabledIdleSt_A	6363167	5673366	0	0
DisabledNoDetection_A	6363167	5675334	0	0
EnterDebounceSt_A	6363167	50	0	0
EnterDetectSt_A	6363167	41	0	0
EnterStableSt_A	6363167	40	0	0
PulseIsPulse_A	6363167	40	0	0
StayInStableSt	6363167	3083	0	0
gen_high_level_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	90	0	0
T20	0	2	0	0
T28	618	2	0	0
T30	725	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T49	0	3	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T60	500	0	0	0
T61	480	0	0	0
T99	502	0	0	0
T113	4431	0	0	0
T119	0	2	0	0
T191	406	0	0	0
T192	862	0	0	0
T193	425	0	0	0
T194	433	0	0	0
T232	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	55138	0	0
T20	0	20	0	0
T28	618	25	0	0
T30	725	0	0	0
T47	0	76	0	0
T48	0	33	0	0
T49	0	154	0	0
T53	0	58	0	0
T54	0	93	0	0
T55	0	37	0	0
T60	500	0	0	0
T61	480	0	0	0
T99	502	0	0	0
T113	4431	0	0	0
T119	0	47	0	0
T191	406	0	0	0
T192	862	0	0	0
T193	425	0	0	0
T194	433	0	0	0
T232	0	194	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5879308	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1	0	0
T50	3492	0	0	0
T54	637	1	0	0
T57	3346	0	0	0
T199	402	0	0	0
T256	502	0	0	0
T257	421	0	0	0
T258	497	0	0	0
T259	423	0	0	0
T260	489	0	0	0
T261	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	3145	0	0
T20	0	23	0	0
T28	618	184	0	0
T30	725	0	0	0
T47	0	118	0	0
T48	0	112	0	0
T49	0	44	0	0
T53	0	334	0	0
T55	0	147	0	0
T60	500	0	0	0
T61	480	0	0	0
T76	0	27	0	0
T99	502	0	0	0
T113	4431	0	0	0
T119	0	39	0	0
T191	406	0	0	0
T192	862	0	0	0
T193	425	0	0	0
T194	433	0	0	0
T232	0	442	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	40	0	0
T20	0	1	0	0
T28	618	1	0	0
T30	725	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T60	500	0	0	0
T61	480	0	0	0
T76	0	1	0	0
T99	502	0	0	0
T113	4431	0	0	0
T119	0	1	0	0
T191	406	0	0	0
T192	862	0	0	0
T193	425	0	0	0
T194	433	0	0	0
T232	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5673366	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5675334	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	50	0	0
T20	0	1	0	0
T28	618	1	0	0
T30	725	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T60	500	0	0	0
T61	480	0	0	0
T99	502	0	0	0
T113	4431	0	0	0
T119	0	1	0	0
T191	406	0	0	0
T192	862	0	0	0
T193	425	0	0	0
T194	433	0	0	0
T232	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	41	0	0
T20	0	1	0	0
T28	618	1	0	0
T30	725	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T60	500	0	0	0
T61	480	0	0	0
T99	502	0	0	0
T113	4431	0	0	0
T119	0	1	0	0
T191	406	0	0	0
T192	862	0	0	0
T193	425	0	0	0
T194	433	0	0	0
T232	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	40	0	0
T20	0	1	0	0
T28	618	1	0	0
T30	725	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T60	500	0	0	0
T61	480	0	0	0
T76	0	1	0	0
T99	502	0	0	0
T113	4431	0	0	0
T119	0	1	0	0
T191	406	0	0	0
T192	862	0	0	0
T193	425	0	0	0
T194	433	0	0	0
T232	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	40	0	0
T20	0	1	0	0
T28	618	1	0	0
T30	725	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T60	500	0	0	0
T61	480	0	0	0
T76	0	1	0	0
T99	502	0	0	0
T113	4431	0	0	0
T119	0	1	0	0
T191	406	0	0	0
T192	862	0	0	0
T193	425	0	0	0
T194	433	0	0	0
T232	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	3083	0	0
T20	0	22	0	0
T28	618	182	0	0
T30	725	0	0	0
T47	0	115	0	0
T48	0	111	0	0
T49	0	42	0	0
T53	0	332	0	0
T55	0	145	0	0
T60	500	0	0	0
T61	480	0	0	0
T76	0	26	0	0
T99	502	0	0	0
T113	4431	0	0	0
T119	0	37	0	0
T191	406	0	0	0
T192	862	0	0	0
T193	425	0	0	0
T194	433	0	0	0
T232	0	439	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	16	0	0
T47	798	1	0	0
T48	0	1	0	0
T63	462	0	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T188	0	1	0	0
T189	0	1	0	0
T195	0	1	0	0
T216	0	1	0	0
T218	0	1	0	0
T220	0	1	0	0
T232	0	1	0	0
T234	523	0	0	0
T235	939	0	0	0
T253	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T47 T20 T48 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T47 T20 T48 
149        1/1                    cnt_en = 1'b1;
           Tests:       T47 T20 T48 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T47 T20 T48 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T47 T20 T48 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T47 T20 T48 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T47 T20 T48 
167        1/1                    if (trigger_active) begin
           Tests:       T47 T20 T48 
168        1/1                      state_d = DetectSt;
           Tests:       T47 T20 T48 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T196 T262 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T47 T20 T48 
182        1/1                  cnt_en = 1'b1;
           Tests:       T47 T20 T48 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T47 T20 T48 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T47 T20 T48 
191        1/1                      state_d = StableSt;
           Tests:       T47 T20 T48 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T47 T20 T48 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T47 T20 T48 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T47 T20 T48 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T47 T20 T48 
206        1/1                    state_d = IdleSt;
           Tests:       T47 T20 T49 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T47 T20 T48 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T47,T20,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T47,T20,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T47,T20,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T28,T47
1	0	Covered	T4,T5,T1
1	1	Covered	T47,T20,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T47,T20,T48
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T20,T48
0	1	Covered	T47,T49,T51
1	0	Covered	T20,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T20,T48
1	-	Covered	T47,T49,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T47,T20,T48
DetectSt	168	Covered	T47,T20,T48
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T47,T20,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T47,T20,T48
DebounceSt->IdleSt	163	Covered	T196,T262
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T47,T20,T48
IdleSt->DebounceSt	148	Covered	T47,T20,T48
StableSt->IdleSt	206	Covered	T47,T20,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T47,T20,T48
0	1	Covered	T47,T20,T48
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T20,T48
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T47,T20,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T47,T20,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T196,T262
DebounceSt	-	0	0	-	-	-	-	Covered	T47,T20,T48
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T47,T20,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T20,T49
StableSt	-	-	-	-	-	-	0	Covered	T47,T20,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	72	0	0
CntIncr_A	6363167	71271	0	0
CntNoWrap_A	6363167	5879326	0	0
DetectStDropOut_A	6363167	0	0	0
DetectedOut_A	6363167	18548	0	0
DetectedPulseOut_A	6363167	35	0	0
DisabledIdleSt_A	6363167	5567763	0	0
DisabledNoDetection_A	6363167	5569725	0	0
EnterDebounceSt_A	6363167	37	0	0
EnterDetectSt_A	6363167	35	0	0
EnterStableSt_A	6363167	35	0	0
PulseIsPulse_A	6363167	35	0	0
StayInStableSt	6363167	18497	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6363167	5120	0	0
gen_low_level_sva.LowLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	72	0	0
T20	0	2	0	0
T47	798	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	4	0	0
T63	462	0	0	0
T76	0	2	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	2	0	0
T216	0	4	0	0
T234	523	0	0	0
T235	939	0	0	0
T263	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	71271	0	0
T20	0	20	0	0
T47	798	38	0	0
T48	0	33	0	0
T49	0	77	0	0
T50	0	84	0	0
T51	0	74	0	0
T63	462	0	0	0
T76	0	19	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	74	0	0
T216	0	116	0	0
T234	523	0	0	0
T235	939	0	0	0
T263	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5879326	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	18548	0	0
T20	0	24	0	0
T47	798	96	0	0
T48	0	41	0	0
T49	0	137	0	0
T50	0	166	0	0
T51	0	58	0	0
T63	462	0	0	0
T76	0	25	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	346	0	0
T216	0	126	0	0
T234	523	0	0	0
T235	939	0	0	0
T263	0	203	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	35	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	1	0	0
T216	0	2	0	0
T234	523	0	0	0
T235	939	0	0	0
T263	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5567763	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5569725	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	37	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	1	0	0
T216	0	2	0	0
T234	523	0	0	0
T235	939	0	0	0
T263	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	35	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	1	0	0
T216	0	2	0	0
T234	523	0	0	0
T235	939	0	0	0
T263	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	35	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	1	0	0
T216	0	2	0	0
T234	523	0	0	0
T235	939	0	0	0
T263	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	35	0	0
T20	0	1	0	0
T47	798	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T63	462	0	0	0
T76	0	1	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	1	0	0
T216	0	2	0	0
T234	523	0	0	0
T235	939	0	0	0
T263	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	18497	0	0
T20	0	23	0	0
T47	798	95	0	0
T48	0	39	0	0
T49	0	136	0	0
T50	0	164	0	0
T51	0	55	0	0
T63	462	0	0	0
T76	0	24	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T189	0	344	0	0
T216	0	124	0	0
T234	523	0	0	0
T235	939	0	0	0
T263	0	201	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5120	0	0
T1	485	1	0	0
T2	486	1	0	0
T3	672	1	0	0
T4	447	9	0	0
T5	493	9	0	0
T8	507	1	0	0
T13	822	0	0	0
T14	494	6	0	0
T15	421	2	0	0
T16	504	2	0	0
T26	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	17	0	0
T47	798	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T63	462	0	0	0
T88	1303	0	0	0
T101	2792	0	0	0
T155	506	0	0	0
T156	1251	0	0	0
T157	410	0	0	0
T158	412	0	0	0
T187	0	1	0	0
T190	0	1	0	0
T216	0	2	0	0
T217	0	1	0	0
T220	0	2	0	0
T234	523	0	0	0
T235	939	0	0	0
T250	0	1	0	0
T253	0	1	0	0