Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T4 T5 T1
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T1
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T1
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T1
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T17 T6 T7
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T13
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T13
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T1
139
140 1/1 unique case (state_q)
Tests: T4 T5 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T1
148 1/1 state_d = DebounceSt;
Tests: T17 T6 T7
149 1/1 cnt_en = 1'b1;
Tests: T17 T6 T7
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T17 T6 T7
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T17 T6 T7
163 1/1 state_d = IdleSt;
Tests: T20 T76
164 1/1 cnt_clr = 1'b1;
Tests: T20 T76
165 1/1 end else if (cnt_done) begin
Tests: T17 T6 T7
166 1/1 cnt_clr = 1'b1;
Tests: T17 T6 T7
167 1/1 if (trigger_active) begin
Tests: T17 T6 T7
168 1/1 state_d = DetectSt;
Tests: T17 T6 T29
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T7 T65 T77
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T17 T6 T29
182 1/1 cnt_en = 1'b1;
Tests: T17 T6 T29
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T17 T6 T29
186 1/1 state_d = IdleSt;
Tests: T47 T77 T108
187 1/1 cnt_clr = 1'b1;
Tests: T47 T77 T108
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T17 T6 T29
191 1/1 state_d = StableSt;
Tests: T17 T6 T29
192 1/1 cnt_clr = 1'b1;
Tests: T17 T6 T29
193 1/1 event_detected_o = 1'b1;
Tests: T17 T6 T29
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T17 T6 T29
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T17 T6 T29
206 1/1 state_d = IdleSt;
Tests: T17 T29 T28
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T17 T6 T29
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T1
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T1
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T1
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T1
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T7 T28 T18
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T13
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T13
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T1
139
140 1/1 unique case (state_q)
Tests: T4 T5 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T1
148 1/1 state_d = DebounceSt;
Tests: T7 T28 T18
149 1/1 cnt_en = 1'b1;
Tests: T7 T28 T18
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T7 T28 T18
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T7 T28 T18
163 1/1 state_d = IdleSt;
Tests: T20 T76
164 1/1 cnt_clr = 1'b1;
Tests: T20 T76
165 1/1 end else if (cnt_done) begin
Tests: T7 T28 T18
166 1/1 cnt_clr = 1'b1;
Tests: T7 T28 T18
167 1/1 if (trigger_active) begin
Tests: T7 T28 T18
168 1/1 state_d = DetectSt;
Tests: T7 T28 T18
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T28 T77 T49
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T7 T28 T18
182 1/1 cnt_en = 1'b1;
Tests: T7 T28 T18
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T7 T28 T18
186 1/1 state_d = IdleSt;
Tests: T77 T79 T54
187 1/1 cnt_clr = 1'b1;
Tests: T77 T79 T54
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T7 T28 T18
191 1/1 state_d = StableSt;
Tests: T7 T28 T18
192 1/1 cnt_clr = 1'b1;
Tests: T7 T28 T18
193 1/1 event_detected_o = 1'b1;
Tests: T7 T28 T18
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T7 T28 T18
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T7 T28 T18
206 1/1 state_d = IdleSt;
Tests: T7 T18 T20
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T7 T28 T18
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T13
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T4 T5 T13
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T7 T18 T20
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T13 T7 T18
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T13 T7 T18
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T13
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T13
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T13
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T13
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T13
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T13
139
140 1/1 unique case (state_q)
Tests: T4 T5 T13
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T13
148 1/1 state_d = DebounceSt;
Tests: T7 T18 T20
149 1/1 cnt_en = 1'b1;
Tests: T7 T18 T20
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T7 T18 T20
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T7 T18 T20
163 1/1 state_d = IdleSt;
Tests: T20 T76
164 1/1 cnt_clr = 1'b1;
Tests: T20 T76
165 1/1 end else if (cnt_done) begin
Tests: T7 T18 T20
166 1/1 cnt_clr = 1'b1;
Tests: T7 T18 T19
167 1/1 if (trigger_active) begin
Tests: T7 T18 T19
168 1/1 state_d = DetectSt;
Tests: T7 T18 T19
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T78 T57 T80
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T7 T18 T19
182 1/1 cnt_en = 1'b1;
Tests: T7 T18 T19
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T7 T18 T19
186 1/1 state_d = IdleSt;
Tests: T109 T110 T111
187 1/1 cnt_clr = 1'b1;
Tests: T109 T110 T111
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T7 T18 T19
191 1/1 state_d = StableSt;
Tests: T7 T18 T19
192 1/1 cnt_clr = 1'b1;
Tests: T7 T18 T19
193 1/1 event_detected_o = 1'b1;
Tests: T7 T18 T19
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T7 T18 T19
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T7 T18 T19
206 1/1 state_d = IdleSt;
Tests: T7 T18 T19
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T7 T18 T19
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T31 T20 T32
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T31 T20 T32
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T8 T9 T11
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T8 T9 T11
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T8 T9 T11
129 1/1 cnt_en = 1'b0;
Tests: T8 T9 T11
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T8 T9 T11
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T8 T9 T11
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T8 T9 T11
139
140 1/1 unique case (state_q)
Tests: T8 T9 T11
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T8 T9 T11
148 1/1 state_d = DebounceSt;
Tests: T8 T9 T11
149 1/1 cnt_en = 1'b1;
Tests: T8 T9 T11
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T8 T9 T11
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T8 T9 T11
163 1/1 state_d = IdleSt;
Tests: T20 T76
164 1/1 cnt_clr = 1'b1;
Tests: T20 T76
165 1/1 end else if (cnt_done) begin
Tests: T8 T9 T11
166 1/1 cnt_clr = 1'b1;
Tests: T8 T9 T11
167 1/1 if (trigger_active) begin
Tests: T8 T9 T11
168 1/1 state_d = DetectSt;
Tests: T8 T9 T11
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T31 T20 T32
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T8 T9 T11
182 1/1 cnt_en = 1'b1;
Tests: T8 T9 T11
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T8 T9 T11
186 1/1 state_d = IdleSt;
Tests: T31 T20 T32
187 1/1 cnt_clr = 1'b1;
Tests: T31 T20 T32
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T8 T9 T11
191 1/1 state_d = StableSt;
Tests: T8 T9 T11
192 1/1 cnt_clr = 1'b1;
Tests: T8 T9 T11
193 1/1 event_detected_o = 1'b1;
Tests: T8 T9 T11
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T8 T9 T11
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T8 T9 T11
206 1/1 state_d = IdleSt;
Tests: T20 T59 T42
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T8 T9 T11
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T2 T8
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T1
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T1
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T1
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T2 T8
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T1
139
140 1/1 unique case (state_q)
Tests: T4 T5 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T1
148 1/1 state_d = DebounceSt;
Tests: T1 T2 T8
149 1/1 cnt_en = 1'b1;
Tests: T1 T2 T8
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T2 T8
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T2 T8
163 1/1 state_d = IdleSt;
Tests: T20 T76
164 1/1 cnt_clr = 1'b1;
Tests: T20 T76
165 1/1 end else if (cnt_done) begin
Tests: T1 T2 T8
166 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T8
167 1/1 if (trigger_active) begin
Tests: T1 T2 T8
168 1/1 state_d = DetectSt;
Tests: T1 T2 T8
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T63 T57 T40
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T2 T8
182 1/1 cnt_en = 1'b1;
Tests: T1 T2 T8
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T2 T8
186 1/1 state_d = IdleSt;
Tests: T20 T76 T112
187 1/1 cnt_clr = 1'b1;
Tests: T20 T76 T112
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T2 T8
191 1/1 state_d = StableSt;
Tests: T1 T2 T8
192 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T8
193 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T8
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T2 T8
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T2 T8
206 1/1 state_d = IdleSt;
Tests: T1 T2 T8
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T8
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T8 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T8 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T2,T8 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T2,T8 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T2,T8 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T8 |
| 1 | 0 | Covered | T27,T113,T101 |
| 1 | 1 | Covered | T1,T2,T8 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T8 |
| 0 | 1 | Covered | T76,T112,T114 |
| 1 | 0 | Covered | T20,T76 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T8 |
| 0 | 1 | Covered | T1,T2,T8 |
| 1 | 0 | Covered | T20,T58,T76 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T2,T8 |
| 1 | - | Covered | T1,T2,T8 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T17,T6,T29 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T17,T6,T29 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T17,T6,T29 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T6,T29 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T17,T6,T29 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T17,T6,T29 |
| 0 | 1 | Covered | T47,T115,T116 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T17,T6,T29 |
| 0 | 1 | Covered | T17,T29,T28 |
| 1 | 0 | Covered | T20,T76 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T17,T6,T29 |
| 1 | - | Covered | T17,T29,T28 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T31,T20,T32 |
| 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T8,T9,T11 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T8,T9,T11 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T8,T9,T11 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T31,T20,T32 |
| 1 | 0 | Covered | T20,T59,T42 |
| 1 | 1 | Covered | T8,T9,T11 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T8,T9,T11 |
| 0 | 1 | Covered | T31,T20,T32 |
| 1 | 0 | Covered | T20,T58,T76 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T8,T9,T11 |
| 0 | 1 | Covered | T20,T59,T42 |
| 1 | 0 | Covered | T20,T117,T118 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T8,T9,T11 |
| 1 | - | Covered | T20,T59,T42 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T13 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T7,T18,T20 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T7,T18,T20 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T7,T18,T19 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T18,T20 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T7,T18,T20 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T18,T19 |
| 0 | 1 | Covered | T109,T110,T111 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T18,T19 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T7,T18,T19 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T28,T47,T20 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T28,T47,T20 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T28,T47,T20 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T6,T28 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T28,T47,T20 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T28,T47,T20 |
| 0 | 1 | Covered | T54,T119,T120 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T28,T47,T20 |
| 0 | 1 | Covered | T47,T55,T57 |
| 1 | 0 | Covered | T20,T76 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T28,T47,T20 |
| 1 | - | Covered | T47,T55,T57 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T13 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T4,T5,T13 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T7,T18,T20 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T7,T18,T20 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T7,T18,T19 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T18,T20 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T7,T18,T20 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T18,T19 |
| 0 | 1 | Covered | T77,T79,T107 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T18,T19 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T7,T18,T19 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T13 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T13 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T7,T18,T20 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T7,T18,T20 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T18,T19,T77 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T18,T20 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T7,T18,T20 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T18,T19,T78 |
| 0 | 1 | Covered | T77,T108,T121 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T18,T19,T78 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T18,T19,T78 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T17,T6,T29 |
| DetectSt |
168 |
Covered |
T17,T6,T29 |
| IdleSt |
163 |
Covered |
T4,T5,T1 |
| StableSt |
191 |
Covered |
T17,T6,T29 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T17,T6,T29 |
| DebounceSt->IdleSt |
163 |
Covered |
T20,T65,T49 |
| DetectSt->IdleSt |
186 |
Covered |
T47,T77,T79 |
| DetectSt->StableSt |
191 |
Covered |
T17,T6,T29 |
| IdleSt->DebounceSt |
148 |
Covered |
T17,T6,T29 |
| StableSt->IdleSt |
206 |
Covered |
T17,T29,T28 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T17,T6,T29 |
| 0 |
1 |
Covered |
T17,T6,T29 |
| 0 |
0 |
Covered |
T4,T5,T1 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T6,T29 |
| 0 |
Covered |
T4,T5,T1 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T17,T6,T29 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T1 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T20,T76 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T17,T6,T29 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T65,T49,T51 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T17,T6,T29 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T47,T77,T79 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T17,T6,T29 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T2,T8 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T17,T29,T28 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T17,T6,T29 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T8,T9,T7 |
| 0 |
1 |
Covered |
T8,T9,T7 |
| 0 |
0 |
Covered |
T4,T5,T1 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T9,T7 |
| 0 |
Covered |
T4,T5,T1 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T8,T9,T7 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T13 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T20,T76 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T8,T9,T7 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T31,T20,T32 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T8,T9,T7 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T31,T20,T32 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T8,T9,T7 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T8,T9,T11 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T7,T18,T20 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T8,T9,T7 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
17522 |
0 |
0 |
| T1 |
485 |
2 |
0 |
0 |
| T2 |
486 |
2 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
2151 |
0 |
0 |
0 |
| T8 |
1014 |
4 |
0 |
0 |
| T9 |
505 |
4 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1992 |
2 |
0 |
0 |
| T20 |
8114 |
17 |
0 |
0 |
| T26 |
1004 |
0 |
0 |
0 |
| T27 |
2462 |
0 |
0 |
0 |
| T29 |
0 |
2 |
0 |
0 |
| T30 |
0 |
4 |
0 |
0 |
| T31 |
0 |
11 |
0 |
0 |
| T60 |
0 |
4 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
0 |
3 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
0 |
1 |
0 |
0 |
| T66 |
0 |
6 |
0 |
0 |
| T67 |
0 |
4 |
0 |
0 |
| T68 |
0 |
2 |
0 |
0 |
| T69 |
804 |
0 |
0 |
0 |
| T70 |
1044 |
0 |
0 |
0 |
| T71 |
844 |
0 |
0 |
0 |
| T72 |
854 |
0 |
0 |
0 |
| T73 |
862 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
2377965 |
0 |
0 |
| T1 |
485 |
25 |
0 |
0 |
| T2 |
486 |
25 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
2151 |
0 |
0 |
0 |
| T8 |
1014 |
46 |
0 |
0 |
| T9 |
505 |
46 |
0 |
0 |
| T10 |
0 |
25 |
0 |
0 |
| T11 |
0 |
46 |
0 |
0 |
| T12 |
0 |
25 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1992 |
47 |
0 |
0 |
| T20 |
8114 |
603 |
0 |
0 |
| T26 |
1004 |
0 |
0 |
0 |
| T27 |
2462 |
0 |
0 |
0 |
| T29 |
0 |
89 |
0 |
0 |
| T30 |
0 |
95 |
0 |
0 |
| T31 |
0 |
469 |
0 |
0 |
| T60 |
0 |
46 |
0 |
0 |
| T61 |
0 |
25 |
0 |
0 |
| T62 |
0 |
11 |
0 |
0 |
| T63 |
0 |
41 |
0 |
0 |
| T64 |
0 |
60 |
0 |
0 |
| T65 |
0 |
59 |
0 |
0 |
| T66 |
0 |
158 |
0 |
0 |
| T67 |
0 |
177 |
0 |
0 |
| T68 |
0 |
17 |
0 |
0 |
| T69 |
804 |
0 |
0 |
0 |
| T70 |
1044 |
0 |
0 |
0 |
| T71 |
844 |
0 |
0 |
0 |
| T72 |
854 |
0 |
0 |
0 |
| T73 |
862 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
152846826 |
0 |
0 |
| T1 |
12610 |
2182 |
0 |
0 |
| T2 |
12636 |
2208 |
0 |
0 |
| T3 |
17472 |
7036 |
0 |
0 |
| T4 |
11622 |
1196 |
0 |
0 |
| T5 |
12818 |
2392 |
0 |
0 |
| T8 |
13182 |
2752 |
0 |
0 |
| T13 |
21372 |
10946 |
0 |
0 |
| T14 |
12844 |
2418 |
0 |
0 |
| T15 |
10946 |
520 |
0 |
0 |
| T16 |
13104 |
2678 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
2011 |
0 |
0 |
| T20 |
0 |
1 |
0 |
0 |
| T31 |
5971 |
4 |
0 |
0 |
| T44 |
13553 |
0 |
0 |
0 |
| T45 |
41828 |
1 |
0 |
0 |
| T58 |
0 |
9 |
0 |
0 |
| T76 |
0 |
1 |
0 |
0 |
| T115 |
594 |
1 |
0 |
0 |
| T116 |
0 |
1 |
0 |
0 |
| T120 |
2361 |
0 |
0 |
0 |
| T121 |
311116 |
0 |
0 |
0 |
| T123 |
0 |
24 |
0 |
0 |
| T124 |
7380 |
9 |
0 |
0 |
| T125 |
0 |
6 |
0 |
0 |
| T126 |
0 |
4 |
0 |
0 |
| T127 |
0 |
12 |
0 |
0 |
| T128 |
0 |
2 |
0 |
0 |
| T129 |
0 |
4 |
0 |
0 |
| T130 |
0 |
10 |
0 |
0 |
| T131 |
0 |
7 |
0 |
0 |
| T132 |
0 |
3 |
0 |
0 |
| T133 |
0 |
4 |
0 |
0 |
| T134 |
0 |
2 |
0 |
0 |
| T135 |
0 |
6 |
0 |
0 |
| T136 |
0 |
2 |
0 |
0 |
| T137 |
405 |
0 |
0 |
0 |
| T138 |
502 |
0 |
0 |
0 |
| T139 |
3492 |
0 |
0 |
0 |
| T140 |
526 |
0 |
0 |
0 |
| T141 |
522 |
0 |
0 |
0 |
| T142 |
16931 |
0 |
0 |
0 |
| T143 |
505 |
0 |
0 |
0 |
| T144 |
722 |
0 |
0 |
0 |
| T145 |
1558 |
0 |
0 |
0 |
| T146 |
1497 |
0 |
0 |
0 |
| T147 |
496 |
0 |
0 |
0 |
| T148 |
490 |
0 |
0 |
0 |
| T149 |
1245 |
0 |
0 |
0 |
| T150 |
505 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
1224297 |
0 |
0 |
| T1 |
485 |
4 |
0 |
0 |
| T2 |
486 |
3 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
2151 |
0 |
0 |
0 |
| T8 |
1014 |
85 |
0 |
0 |
| T9 |
505 |
83 |
0 |
0 |
| T10 |
0 |
4 |
0 |
0 |
| T11 |
0 |
78 |
0 |
0 |
| T12 |
0 |
3 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1992 |
4 |
0 |
0 |
| T20 |
8114 |
571 |
0 |
0 |
| T26 |
1004 |
0 |
0 |
0 |
| T27 |
2462 |
0 |
0 |
0 |
| T29 |
0 |
4 |
0 |
0 |
| T30 |
0 |
14 |
0 |
0 |
| T50 |
0 |
10 |
0 |
0 |
| T60 |
0 |
80 |
0 |
0 |
| T61 |
0 |
3 |
0 |
0 |
| T62 |
0 |
6 |
0 |
0 |
| T63 |
0 |
37 |
0 |
0 |
| T64 |
0 |
12 |
0 |
0 |
| T66 |
0 |
23 |
0 |
0 |
| T67 |
0 |
19 |
0 |
0 |
| T68 |
0 |
6 |
0 |
0 |
| T69 |
804 |
0 |
0 |
0 |
| T70 |
1044 |
0 |
0 |
0 |
| T71 |
844 |
0 |
0 |
0 |
| T72 |
854 |
0 |
0 |
0 |
| T73 |
862 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
| T151 |
0 |
14 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
5614 |
0 |
0 |
| T1 |
485 |
1 |
0 |
0 |
| T2 |
486 |
1 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
2151 |
0 |
0 |
0 |
| T8 |
1014 |
2 |
0 |
0 |
| T9 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1992 |
1 |
0 |
0 |
| T20 |
8114 |
6 |
0 |
0 |
| T26 |
1004 |
0 |
0 |
0 |
| T27 |
2462 |
0 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T50 |
0 |
2 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T66 |
0 |
3 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
804 |
0 |
0 |
0 |
| T70 |
1044 |
0 |
0 |
0 |
| T71 |
844 |
0 |
0 |
0 |
| T72 |
854 |
0 |
0 |
0 |
| T73 |
862 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
| T151 |
0 |
2 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
142634910 |
0 |
0 |
| T1 |
12610 |
2103 |
0 |
0 |
| T2 |
12636 |
2129 |
0 |
0 |
| T3 |
17472 |
5706 |
0 |
0 |
| T4 |
11622 |
1196 |
0 |
0 |
| T5 |
12818 |
2392 |
0 |
0 |
| T8 |
13182 |
2572 |
0 |
0 |
| T13 |
21372 |
10946 |
0 |
0 |
| T14 |
12844 |
2418 |
0 |
0 |
| T15 |
10946 |
520 |
0 |
0 |
| T16 |
13104 |
2678 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
142683082 |
0 |
0 |
| T1 |
12610 |
2128 |
0 |
0 |
| T2 |
12636 |
2154 |
0 |
0 |
| T3 |
17472 |
5727 |
0 |
0 |
| T4 |
11622 |
1222 |
0 |
0 |
| T5 |
12818 |
2418 |
0 |
0 |
| T8 |
13182 |
2596 |
0 |
0 |
| T13 |
21372 |
10972 |
0 |
0 |
| T14 |
12844 |
2444 |
0 |
0 |
| T15 |
10946 |
546 |
0 |
0 |
| T16 |
13104 |
2704 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
8983 |
0 |
0 |
| T1 |
485 |
1 |
0 |
0 |
| T2 |
486 |
1 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
2151 |
0 |
0 |
0 |
| T8 |
1014 |
2 |
0 |
0 |
| T9 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1992 |
1 |
0 |
0 |
| T20 |
8114 |
10 |
0 |
0 |
| T26 |
1004 |
0 |
0 |
0 |
| T27 |
2462 |
0 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T31 |
0 |
7 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T65 |
0 |
1 |
0 |
0 |
| T66 |
0 |
3 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
804 |
0 |
0 |
0 |
| T70 |
1044 |
0 |
0 |
0 |
| T71 |
844 |
0 |
0 |
0 |
| T72 |
854 |
0 |
0 |
0 |
| T73 |
862 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
8548 |
0 |
0 |
| T1 |
485 |
1 |
0 |
0 |
| T2 |
486 |
1 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
2151 |
0 |
0 |
0 |
| T8 |
1014 |
2 |
0 |
0 |
| T9 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1992 |
1 |
0 |
0 |
| T20 |
8114 |
10 |
0 |
0 |
| T26 |
1004 |
0 |
0 |
0 |
| T27 |
2462 |
0 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T50 |
0 |
2 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T66 |
0 |
3 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
804 |
0 |
0 |
0 |
| T70 |
1044 |
0 |
0 |
0 |
| T71 |
844 |
0 |
0 |
0 |
| T72 |
854 |
0 |
0 |
0 |
| T73 |
862 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
| T151 |
0 |
2 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
5614 |
0 |
0 |
| T1 |
485 |
1 |
0 |
0 |
| T2 |
486 |
1 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
2151 |
0 |
0 |
0 |
| T8 |
1014 |
2 |
0 |
0 |
| T9 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1992 |
1 |
0 |
0 |
| T20 |
8114 |
6 |
0 |
0 |
| T26 |
1004 |
0 |
0 |
0 |
| T27 |
2462 |
0 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T50 |
0 |
2 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T66 |
0 |
3 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
804 |
0 |
0 |
0 |
| T70 |
1044 |
0 |
0 |
0 |
| T71 |
844 |
0 |
0 |
0 |
| T72 |
854 |
0 |
0 |
0 |
| T73 |
862 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
| T151 |
0 |
2 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
5614 |
0 |
0 |
| T1 |
485 |
1 |
0 |
0 |
| T2 |
486 |
1 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
2151 |
0 |
0 |
0 |
| T8 |
1014 |
2 |
0 |
0 |
| T9 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1992 |
1 |
0 |
0 |
| T20 |
8114 |
6 |
0 |
0 |
| T26 |
1004 |
0 |
0 |
0 |
| T27 |
2462 |
0 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T50 |
0 |
2 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T66 |
0 |
3 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
804 |
0 |
0 |
0 |
| T70 |
1044 |
0 |
0 |
0 |
| T71 |
844 |
0 |
0 |
0 |
| T72 |
854 |
0 |
0 |
0 |
| T73 |
862 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
| T151 |
0 |
2 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
165442342 |
1217928 |
0 |
0 |
| T1 |
485 |
3 |
0 |
0 |
| T2 |
486 |
2 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
2151 |
0 |
0 |
0 |
| T8 |
1014 |
82 |
0 |
0 |
| T9 |
505 |
80 |
0 |
0 |
| T10 |
0 |
3 |
0 |
0 |
| T11 |
0 |
75 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1992 |
3 |
0 |
0 |
| T20 |
8114 |
565 |
0 |
0 |
| T26 |
1004 |
0 |
0 |
0 |
| T27 |
2462 |
0 |
0 |
0 |
| T29 |
0 |
3 |
0 |
0 |
| T30 |
0 |
12 |
0 |
0 |
| T50 |
0 |
8 |
0 |
0 |
| T60 |
0 |
77 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
5 |
0 |
0 |
| T63 |
0 |
35 |
0 |
0 |
| T64 |
0 |
11 |
0 |
0 |
| T66 |
0 |
20 |
0 |
0 |
| T67 |
0 |
17 |
0 |
0 |
| T68 |
0 |
5 |
0 |
0 |
| T69 |
804 |
0 |
0 |
0 |
| T70 |
1044 |
0 |
0 |
0 |
| T71 |
844 |
0 |
0 |
0 |
| T72 |
854 |
0 |
0 |
0 |
| T73 |
862 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
| T151 |
0 |
12 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
57268503 |
41654 |
0 |
0 |
| T1 |
4365 |
3 |
0 |
0 |
| T2 |
4374 |
3 |
0 |
0 |
| T3 |
6048 |
13 |
0 |
0 |
| T4 |
4023 |
53 |
0 |
0 |
| T5 |
4437 |
69 |
0 |
0 |
| T6 |
0 |
5 |
0 |
0 |
| T8 |
4563 |
3 |
0 |
0 |
| T13 |
7398 |
16 |
0 |
0 |
| T14 |
4446 |
51 |
0 |
0 |
| T15 |
3789 |
18 |
0 |
0 |
| T16 |
4536 |
34 |
0 |
0 |
| T17 |
0 |
9 |
0 |
0 |
| T26 |
0 |
39 |
0 |
0 |
| T27 |
0 |
23 |
0 |
0 |
| T70 |
0 |
16 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31815835 |
29407025 |
0 |
0 |
| T1 |
2425 |
425 |
0 |
0 |
| T2 |
2430 |
430 |
0 |
0 |
| T3 |
3360 |
1360 |
0 |
0 |
| T4 |
2235 |
235 |
0 |
0 |
| T5 |
2465 |
465 |
0 |
0 |
| T8 |
2535 |
535 |
0 |
0 |
| T13 |
4110 |
2110 |
0 |
0 |
| T14 |
2470 |
470 |
0 |
0 |
| T15 |
2105 |
105 |
0 |
0 |
| T16 |
2520 |
520 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
108173839 |
99983885 |
0 |
0 |
| T1 |
8245 |
1445 |
0 |
0 |
| T2 |
8262 |
1462 |
0 |
0 |
| T3 |
11424 |
4624 |
0 |
0 |
| T4 |
7599 |
799 |
0 |
0 |
| T5 |
8381 |
1581 |
0 |
0 |
| T8 |
8619 |
1819 |
0 |
0 |
| T13 |
13974 |
7174 |
0 |
0 |
| T14 |
8398 |
1598 |
0 |
0 |
| T15 |
7157 |
357 |
0 |
0 |
| T16 |
8568 |
1768 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
57268503 |
52932645 |
0 |
0 |
| T1 |
4365 |
765 |
0 |
0 |
| T2 |
4374 |
774 |
0 |
0 |
| T3 |
6048 |
2448 |
0 |
0 |
| T4 |
4023 |
423 |
0 |
0 |
| T5 |
4437 |
837 |
0 |
0 |
| T8 |
4563 |
963 |
0 |
0 |
| T13 |
7398 |
3798 |
0 |
0 |
| T14 |
4446 |
846 |
0 |
0 |
| T15 |
3789 |
189 |
0 |
0 |
| T16 |
4536 |
936 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146352841 |
4689 |
0 |
0 |
| T1 |
485 |
1 |
0 |
0 |
| T2 |
486 |
1 |
0 |
0 |
| T3 |
672 |
0 |
0 |
0 |
| T6 |
1434 |
0 |
0 |
0 |
| T8 |
507 |
1 |
0 |
0 |
| T9 |
505 |
1 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
0 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
822 |
0 |
0 |
0 |
| T14 |
494 |
0 |
0 |
0 |
| T15 |
421 |
0 |
0 |
0 |
| T16 |
504 |
0 |
0 |
0 |
| T17 |
1328 |
1 |
0 |
0 |
| T20 |
8114 |
5 |
0 |
0 |
| T26 |
502 |
0 |
0 |
0 |
| T27 |
1231 |
0 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T33 |
0 |
3 |
0 |
0 |
| T50 |
0 |
2 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T66 |
0 |
3 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
402 |
0 |
0 |
0 |
| T70 |
522 |
0 |
0 |
0 |
| T71 |
422 |
0 |
0 |
0 |
| T72 |
427 |
0 |
0 |
0 |
| T73 |
431 |
0 |
0 |
0 |
| T91 |
7504 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
| T151 |
0 |
2 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
19089501 |
1543139 |
0 |
0 |
| T7 |
1884 |
637 |
0 |
0 |
| T10 |
976 |
0 |
0 |
0 |
| T18 |
1213 |
317 |
0 |
0 |
| T19 |
0 |
1350 |
0 |
0 |
| T25 |
992 |
0 |
0 |
0 |
| T29 |
1406 |
0 |
0 |
0 |
| T47 |
798 |
0 |
0 |
0 |
| T57 |
0 |
234 |
0 |
0 |
| T62 |
664 |
0 |
0 |
0 |
| T63 |
462 |
0 |
0 |
0 |
| T77 |
0 |
35 |
0 |
0 |
| T78 |
0 |
551 |
0 |
0 |
| T79 |
0 |
250 |
0 |
0 |
| T80 |
0 |
83 |
0 |
0 |
| T81 |
1044 |
0 |
0 |
0 |
| T82 |
810 |
0 |
0 |
0 |
| T83 |
856 |
0 |
0 |
0 |
| T84 |
804 |
0 |
0 |
0 |
| T85 |
1050 |
0 |
0 |
0 |
| T86 |
1006 |
0 |
0 |
0 |
| T88 |
1303 |
0 |
0 |
0 |
| T101 |
2792 |
0 |
0 |
0 |
| T107 |
0 |
205 |
0 |
0 |
| T108 |
0 |
87 |
0 |
0 |
| T121 |
0 |
84517 |
0 |
0 |
| T139 |
0 |
322 |
0 |
0 |
| T152 |
0 |
476 |
0 |
0 |
| T153 |
0 |
340 |
0 |
0 |
| T154 |
0 |
80936 |
0 |
0 |
| T155 |
506 |
0 |
0 |
0 |
| T156 |
1251 |
0 |
0 |
0 |
| T157 |
410 |
0 |
0 |
0 |
| T158 |
412 |
0 |
0 |
0 |
