Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T31 T20 T32 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T31 T20 T32 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T9 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T8 T9 T11 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T8 T9 T11 
129        1/1              cnt_en = 1'b0;
           Tests:       T8 T9 T11 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T8 T9 T11 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T8 T9 T11 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T8 T9 T11 
139                     
140        1/1              unique case (state_q)
           Tests:       T8 T9 T11 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T8 T9 T11 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T9 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T9 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T9 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T20 T76 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T76 
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T9 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T9 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T9 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T9 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T31 T20 T32 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T9 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T9 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T31 T20 T58 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T20 T58 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T9 T11 
191        1/1                      state_d = StableSt;
           Tests:       T8 T9 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T9 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T9 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T9 T11 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T9 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T20 T59 T42 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T9 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T20,T32
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T20,T32
1	0	Covered	T20,T59,T42
1	1	Covered	T8,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T31,T20,T58
1	0	Covered	T20,T58,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T20,T59,T42
1	0	Covered	T279,T280

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T11
1	-	Covered	T20,T59,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T11
DetectSt	168	Covered	T8,T9,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T11
DebounceSt->IdleSt	163	Covered	T31,T20,T32
DetectSt->IdleSt	186	Covered	T31,T20,T58
DetectSt->StableSt	191	Covered	T8,T9,T11
IdleSt->DebounceSt	148	Covered	T8,T9,T11
StableSt->IdleSt	206	Covered	T20,T59,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T9,T11
0	1	Covered	T8,T9,T11
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T11
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T31,T20,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T20,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T31,T20,T58
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	0	0	-	Covered	T8,T9,T11
StableSt	-	-	-	-	-	-	1	Covered	T20,T59,T42
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	2860	0	0
CntIncr_A	6363167	101266	0	0
CntNoWrap_A	6363167	5876538	0	0
DetectStDropOut_A	6363167	358	0	0
DetectedOut_A	6363167	57654	0	0
DetectedPulseOut_A	6363167	733	0	0
DisabledIdleSt_A	6363167	5439188	0	0
DisabledNoDetection_A	6363167	5441026	0	0
EnterDebounceSt_A	6363167	1435	0	0
EnterDetectSt_A	6363167	1425	0	0
EnterStableSt_A	6363167	733	0	0
PulseIsPulse_A	6363167	733	0	0
StayInStableSt	6363167	56845	0	0
gen_high_event_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_high_level_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	653	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	2860	0	0
T6	717	0	0	0
T8	507	2	0	0
T9	0	2	0	0
T11	0	2	0	0
T17	664	0	0	0
T20	0	16	0	0
T26	502	0	0	0
T27	1231	0	0	0
T31	0	11	0	0
T32	0	3	0	0
T42	0	14	0	0
T59	0	12	0	0
T60	0	2	0	0
T63	0	2	0	0
T69	402	0	0	0
T70	522	0	0	0
T71	422	0	0	0
T72	427	0	0	0
T73	431	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	101266	0	0
T6	717	0	0	0
T8	507	21	0	0
T9	0	21	0	0
T11	0	21	0	0
T17	664	0	0	0
T20	0	566	0	0
T26	502	0	0	0
T27	1231	0	0	0
T31	0	469	0	0
T32	0	546	0	0
T42	0	574	0	0
T59	0	348	0	0
T60	0	21	0	0
T63	0	21	0	0
T69	402	0	0	0
T70	522	0	0	0
T71	422	0	0	0
T72	427	0	0	0
T73	431	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5876538	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	104	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	358	0	0
T20	0	1	0	0
T31	5971	4	0	0
T58	0	9	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	1	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0
T123	0	24	0	0
T124	0	9	0	0
T125	0	6	0	0
T126	0	4	0	0
T127	0	12	0	0
T281	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	57654	0	0
T6	717	0	0	0
T8	507	82	0	0
T9	0	79	0	0
T11	0	75	0	0
T17	664	0	0	0
T20	0	481	0	0
T26	502	0	0	0
T27	1231	0	0	0
T42	0	72	0	0
T43	0	837	0	0
T59	0	92	0	0
T60	0	75	0	0
T63	0	37	0	0
T69	402	0	0	0
T70	522	0	0	0
T71	422	0	0	0
T72	427	0	0	0
T73	431	0	0	0
T76	0	455	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	733	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T17	664	0	0	0
T20	0	5	0	0
T26	502	0	0	0
T27	1231	0	0	0
T42	0	7	0	0
T43	0	12	0	0
T59	0	6	0	0
T60	0	1	0	0
T63	0	1	0	0
T69	402	0	0	0
T70	522	0	0	0
T71	422	0	0	0
T72	427	0	0	0
T73	431	0	0	0
T76	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5439188	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	3	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5441026	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	3	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1435	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T17	664	0	0	0
T20	0	9	0	0
T26	502	0	0	0
T27	1231	0	0	0
T31	0	7	0	0
T32	0	3	0	0
T42	0	7	0	0
T59	0	6	0	0
T60	0	1	0	0
T63	0	1	0	0
T69	402	0	0	0
T70	522	0	0	0
T71	422	0	0	0
T72	427	0	0	0
T73	431	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1425	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T17	664	0	0	0
T20	0	7	0	0
T26	502	0	0	0
T27	1231	0	0	0
T31	0	4	0	0
T42	0	7	0	0
T58	0	21	0	0
T59	0	6	0	0
T60	0	1	0	0
T63	0	1	0	0
T69	402	0	0	0
T70	522	0	0	0
T71	422	0	0	0
T72	427	0	0	0
T73	431	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	733	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T17	664	0	0	0
T20	0	5	0	0
T26	502	0	0	0
T27	1231	0	0	0
T42	0	7	0	0
T43	0	12	0	0
T59	0	6	0	0
T60	0	1	0	0
T63	0	1	0	0
T69	402	0	0	0
T70	522	0	0	0
T71	422	0	0	0
T72	427	0	0	0
T73	431	0	0	0
T76	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	733	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T17	664	0	0	0
T20	0	5	0	0
T26	502	0	0	0
T27	1231	0	0	0
T42	0	7	0	0
T43	0	12	0	0
T59	0	6	0	0
T60	0	1	0	0
T63	0	1	0	0
T69	402	0	0	0
T70	522	0	0	0
T71	422	0	0	0
T72	427	0	0	0
T73	431	0	0	0
T76	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	56845	0	0
T6	717	0	0	0
T8	507	80	0	0
T9	0	77	0	0
T11	0	73	0	0
T17	664	0	0	0
T20	0	476	0	0
T26	502	0	0	0
T27	1231	0	0	0
T42	0	65	0	0
T43	0	824	0	0
T59	0	86	0	0
T60	0	73	0	0
T63	0	35	0	0
T69	402	0	0	0
T70	522	0	0	0
T71	422	0	0	0
T72	427	0	0	0
T73	431	0	0	0
T76	0	450	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	653	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T41	0	22	0	0
T42	0	7	0	0
T43	0	11	0	0
T44	0	20	0	0
T52	566	0	0	0
T59	0	6	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	20	0	0
T122	407	0	0	0
T142	0	12	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T282	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T2 T8 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T2 T8 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T2 T8 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T2 T8 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T8 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T2 T8 
163        1/1                    state_d = IdleSt;
           Tests:       T20 T76 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T76 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T2 T8 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T8 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T2 T8 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T2 T8 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T63 T57 T40 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T2 T8 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T8 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T2 T8 
186        1/1                    state_d = IdleSt;
           Tests:       T20 T76 T45 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T76 T45 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T2 T8 
191        1/1                      state_d = StableSt;
           Tests:       T1 T2 T8 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T2 T8 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T2 T8 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T2 T8 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T2 T8 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T8 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T2 T8 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T27,T113,T101
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T45,T128,T129
1	0	Covered	T20,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T20,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T63,T20,T57
DetectSt->IdleSt	186	Covered	T20,T76,T45
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T57,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T20,T76,T45
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	807	0	0
CntIncr_A	6363167	40994	0	0
CntNoWrap_A	6363167	5878591	0	0
DetectStDropOut_A	6363167	56	0	0
DetectedOut_A	6363167	12025	0	0
DetectedPulseOut_A	6363167	317	0	0
DisabledIdleSt_A	6363167	5560206	0	0
DisabledNoDetection_A	6363167	5561547	0	0
EnterDebounceSt_A	6363167	430	0	0
EnterDetectSt_A	6363167	377	0	0
EnterStableSt_A	6363167	317	0	0
PulseIsPulse_A	6363167	317	0	0
StayInStableSt	6363167	11693	0	0
gen_high_level_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	300	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	807	0	0
T1	485	2	0	0
T2	486	2	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T60	0	2	0	0
T61	0	2	0	0
T63	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	40994	0	0
T1	485	25	0	0
T2	486	25	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	25	0	0
T9	0	25	0	0
T10	0	25	0	0
T11	0	25	0	0
T12	0	25	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T60	0	25	0	0
T61	0	25	0	0
T63	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5878591	0	0
T1	485	82	0	0
T2	486	83	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	104	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	56	0	0
T45	41828	1	0	0
T120	2361	0	0	0
T121	311116	0	0	0
T124	7380	0	0	0
T128	0	2	0	0
T129	0	4	0	0
T130	0	10	0	0
T131	0	7	0	0
T132	0	2	0	0
T133	0	4	0	0
T134	0	2	0	0
T135	0	6	0	0
T136	0	2	0	0
T145	1558	0	0	0
T146	1497	0	0	0
T147	496	0	0	0
T148	490	0	0	0
T149	1245	0	0	0
T150	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	12025	0	0
T1	485	4	0	0
T2	486	3	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	3	0	0
T9	0	4	0	0
T10	0	4	0	0
T11	0	3	0	0
T12	0	3	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T20	0	90	0	0
T60	0	5	0	0
T61	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	317	0	0
T1	485	1	0	0
T2	486	1	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T20	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5560206	0	0
T1	485	3	0	0
T2	486	4	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	25	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5561547	0	0
T1	485	3	0	0
T2	486	4	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	25	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	430	0	0
T1	485	1	0	0
T2	486	1	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	377	0	0
T1	485	1	0	0
T2	486	1	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T20	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	317	0	0
T1	485	1	0	0
T2	486	1	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T20	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	317	0	0
T1	485	1	0	0
T2	486	1	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T20	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	11693	0	0
T1	485	3	0	0
T2	486	2	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	2	0	0
T9	0	3	0	0
T10	0	3	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T20	0	89	0	0
T60	0	4	0	0
T61	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	300	0	0
T1	485	1	0	0
T2	486	1	0	0
T3	672	0	0	0
T6	717	0	0	0
T8	507	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	822	0	0	0
T14	494	0	0	0
T15	421	0	0	0
T16	504	0	0	0
T17	664	0	0	0
T33	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T31 T20 T32 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T31 T20 T32 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T31 T20 T32 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T31 T20 T32 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T31 T20 T32 
129        1/1              cnt_en = 1'b0;
           Tests:       T31 T20 T32 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T31 T20 T32 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T31 T20 T32 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T31 T20 T32 
139                     
140        1/1              unique case (state_q)
           Tests:       T31 T20 T32 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T31 T20 T32 
148        1/1                    state_d = DebounceSt;
           Tests:       T31 T20 T32 
149        1/1                    cnt_en = 1'b1;
           Tests:       T31 T20 T32 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T31 T20 T32 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T31 T20 T32 
163        1/1                    state_d = IdleSt;
           Tests:       T20 T76 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T76 
165        1/1                  end else if (cnt_done) begin
           Tests:       T31 T20 T32 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T20 T32 
167        1/1                    if (trigger_active) begin
           Tests:       T31 T20 T32 
168        1/1                      state_d = DetectSt;
           Tests:       T31 T20 T32 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T31 T20 T32 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T31 T20 T32 
182        1/1                  cnt_en = 1'b1;
           Tests:       T31 T20 T32 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T31 T20 T32 
186        1/1                    state_d = IdleSt;
           Tests:       T31 T20 T32 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T20 T32 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T20 T32 T59 
191        1/1                      state_d = StableSt;
           Tests:       T20 T59 T42 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T20 T59 T42 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T20 T59 T42 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T20 T59 T42 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T20 T59 T42 
206        1/1                    state_d = IdleSt;
           Tests:       T20 T59 T42 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T20 T59 T42 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T20,T32
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T31,T20,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T31,T20,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T31,T20,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T20,T32
1	0	Covered	T20,T59,T42
1	1	Covered	T31,T20,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T32,T59
0	1	Covered	T31,T32,T58
1	0	Covered	T20,T58,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T59,T42
0	1	Covered	T20,T59,T42
1	0	Covered	T283

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T59,T42
1	-	Covered	T20,T59,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T20,T32
DetectSt	168	Covered	T31,T20,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T20,T59,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T20,T32
DebounceSt->IdleSt	163	Covered	T31,T20,T32
DetectSt->IdleSt	186	Covered	T31,T20,T32
DetectSt->StableSt	191	Covered	T20,T59,T42
IdleSt->DebounceSt	148	Covered	T31,T20,T32
StableSt->IdleSt	206	Covered	T20,T59,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T20,T32
0	1	Covered	T31,T20,T32
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T20,T32
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T20,T32
IdleSt	0	-	-	-	-	-	-	Covered	T31,T20,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T20,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T20,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T20,T32
DetectSt	-	-	-	-	1	-	-	Covered	T31,T20,T32
DetectSt	-	-	-	-	0	1	-	Covered	T20,T59,T42
DetectSt	-	-	-	-	0	0	-	Covered	T20,T32,T59
StableSt	-	-	-	-	-	-	1	Covered	T20,T59,T42
StableSt	-	-	-	-	-	-	0	Covered	T20,T59,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	3217	0	0
CntIncr_A	6363167	108718	0	0
CntNoWrap_A	6363167	5876181	0	0
DetectStDropOut_A	6363167	456	0	0
DetectedOut_A	6363167	77814	0	0
DetectedPulseOut_A	6363167	964	0	0
DisabledIdleSt_A	6363167	5420388	0	0
DisabledNoDetection_A	6363167	5422197	0	0
EnterDebounceSt_A	6363167	1614	0	0
EnterDetectSt_A	6363167	1603	0	0
EnterStableSt_A	6363167	964	0	0
PulseIsPulse_A	6363167	964	0	0
StayInStableSt	6363167	76746	0	0
gen_high_event_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_high_level_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	859	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	3217	0	0
T20	0	15	0	0
T31	5971	9	0	0
T32	0	27	0	0
T41	0	16	0	0
T42	0	18	0	0
T43	0	32	0	0
T44	0	56	0	0
T58	0	42	0	0
T59	0	58	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	16	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	108718	0	0
T20	0	468	0	0
T31	5971	402	0	0
T32	0	2849	0	0
T41	0	552	0	0
T42	0	702	0	0
T43	0	1168	0	0
T44	0	1945	0	0
T58	0	935	0	0
T59	0	1711	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	509	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5876181	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	456	0	0
T31	5971	3	0	0
T32	0	12	0	0
T44	0	17	0	0
T58	0	9	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	1	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0
T123	0	22	0	0
T124	0	8	0	0
T126	0	5	0	0
T282	0	26	0	0
T284	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	77814	0	0
T20	8114	481	0	0
T32	7318	0	0	0
T41	0	574	0	0
T42	0	129	0	0
T43	0	608	0	0
T52	566	0	0	0
T59	0	1533	0	0
T76	0	468	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	1742	0	0
T122	407	0	0	0
T125	0	927	0	0
T142	0	1932	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T285	0	1212	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	964	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T41	0	8	0	0
T42	0	9	0	0
T43	0	16	0	0
T52	566	0	0	0
T59	0	29	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	8	0	0
T122	407	0	0	0
T125	0	15	0	0
T142	0	27	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T285	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5420388	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5422197	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1614	0	0
T20	0	9	0	0
T31	5971	6	0	0
T32	0	15	0	0
T41	0	8	0	0
T42	0	9	0	0
T43	0	16	0	0
T44	0	28	0	0
T58	0	21	0	0
T59	0	29	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	9	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1603	0	0
T20	0	6	0	0
T31	5971	3	0	0
T32	0	12	0	0
T41	0	8	0	0
T42	0	9	0	0
T43	0	16	0	0
T44	0	28	0	0
T58	0	21	0	0
T59	0	29	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	7	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	964	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T41	0	8	0	0
T42	0	9	0	0
T43	0	16	0	0
T52	566	0	0	0
T59	0	29	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	8	0	0
T122	407	0	0	0
T125	0	15	0	0
T142	0	27	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T285	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	964	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T41	0	8	0	0
T42	0	9	0	0
T43	0	16	0	0
T52	566	0	0	0
T59	0	29	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	8	0	0
T122	407	0	0	0
T125	0	15	0	0
T142	0	27	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T285	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	76746	0	0
T20	8114	476	0	0
T32	7318	0	0	0
T41	0	562	0	0
T42	0	120	0	0
T43	0	591	0	0
T52	566	0	0	0
T59	0	1504	0	0
T76	0	463	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	1734	0	0
T122	407	0	0	0
T125	0	912	0	0
T142	0	1901	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T285	0	1203	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	859	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T41	0	4	0	0
T42	0	9	0	0
T43	0	15	0	0
T52	566	0	0	0
T59	0	29	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	8	0	0
T122	407	0	0	0
T125	0	15	0	0
T142	0	23	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T285	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T31 T20 T32 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T20 T33 T40 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T20 T33 T40 
149        1/1                    cnt_en = 1'b1;
           Tests:       T20 T33 T40 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T20 T33 T40 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T20 T33 T40 
163        1/1                    state_d = IdleSt;
           Tests:       T20 T76 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T76 
165        1/1                  end else if (cnt_done) begin
           Tests:       T20 T33 T40 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T33 T40 
167        1/1                    if (trigger_active) begin
           Tests:       T20 T33 T40 
168        1/1                      state_d = DetectSt;
           Tests:       T20 T33 T40 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T40 T112 T114 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T20 T33 T40 
182        1/1                  cnt_en = 1'b1;
           Tests:       T20 T33 T40 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T20 T33 T40 
186        1/1                    state_d = IdleSt;
           Tests:       T20 T76 T114 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T76 T114 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T20 T33 T40 
191        1/1                      state_d = StableSt;
           Tests:       T20 T33 T40 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T20 T33 T40 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T20 T33 T40 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T20 T33 T40 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T20 T33 T40 
206        1/1                    state_d = IdleSt;
           Tests:       T20 T33 T40 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T20 T33 T40 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T20,T32
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T20,T32
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T33,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T33,T40

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T33,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T33,T59
1	0	Covered	T27,T113,T101
1	1	Covered	T20,T33,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T33,T40
0	1	Covered	T76,T114,T286
1	0	Covered	T20,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T33,T40
0	1	Covered	T33,T40,T76
1	0	Covered	T20

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T33,T40
1	-	Covered	T33,T40,T76

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T33,T40
DetectSt	168	Covered	T20,T33,T40
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T20,T33,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T33,T40
DebounceSt->IdleSt	163	Covered	T20,T40,T76
DetectSt->IdleSt	186	Covered	T20,T76,T114
DetectSt->StableSt	191	Covered	T20,T33,T40
IdleSt->DebounceSt	148	Covered	T20,T33,T40
StableSt->IdleSt	206	Covered	T20,T33,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T33,T40
0	1	Covered	T20,T33,T40
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T33,T40
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T33,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T33,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T112,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T33,T40
DetectSt	-	-	-	-	1	-	-	Covered	T20,T76,T114
DetectSt	-	-	-	-	0	1	-	Covered	T20,T33,T40
DetectSt	-	-	-	-	0	0	-	Covered	T20,T33,T40
StableSt	-	-	-	-	-	-	1	Covered	T20,T33,T40
StableSt	-	-	-	-	-	-	0	Covered	T20,T33,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	823	0	0
CntIncr_A	6363167	44531	0	0
CntNoWrap_A	6363167	5878575	0	0
DetectStDropOut_A	6363167	65	0	0
DetectedOut_A	6363167	12790	0	0
DetectedPulseOut_A	6363167	319	0	0
DisabledIdleSt_A	6363167	5545304	0	0
DisabledNoDetection_A	6363167	5546649	0	0
EnterDebounceSt_A	6363167	436	0	0
EnterDetectSt_A	6363167	387	0	0
EnterStableSt_A	6363167	319	0	0
PulseIsPulse_A	6363167	319	0	0
StayInStableSt	6363167	12441	0	0
gen_high_level_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	287	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	823	0	0
T20	8114	8	0	0
T32	7318	0	0	0
T33	0	4	0	0
T40	0	12	0	0
T41	0	4	0	0
T43	0	2	0	0
T52	566	0	0	0
T76	0	8	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	7	0	0
T114	0	3	0	0
T122	407	0	0	0
T142	0	6	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	44531	0	0
T20	8114	322	0	0
T32	7318	0	0	0
T33	0	104	0	0
T40	0	588	0	0
T41	0	88	0	0
T43	0	60	0	0
T52	566	0	0	0
T76	0	307	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	415	0	0
T114	0	178	0	0
T122	407	0	0	0
T142	0	213	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	339	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5878575	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	65	0	0
T51	749	0	0	0
T76	8204	1	0	0
T114	0	1	0	0
T131	0	7	0	0
T276	0	2	0	0
T286	0	3	0	0
T288	0	3	0	0
T289	0	3	0	0
T290	0	15	0	0
T291	0	1	0	0
T292	0	2	0	0
T293	732	0	0	0
T294	732	0	0	0
T295	421	0	0	0
T296	8411	0	0	0
T297	404	0	0	0
T298	2597	0	0	0
T299	502	0	0	0
T300	439	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	12790	0	0
T20	8114	90	0	0
T32	7318	0	0	0
T33	0	89	0	0
T40	0	401	0	0
T41	0	169	0	0
T43	0	59	0	0
T45	0	153	0	0
T52	566	0	0	0
T76	0	90	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	14	0	0
T122	407	0	0	0
T142	0	154	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	60	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	319	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T33	0	2	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	1	0	0
T45	0	14	0	0
T52	566	0	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	3	0	0
T122	407	0	0	0
T142	0	3	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5545304	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5546649	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	436	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T33	0	2	0	0
T40	0	7	0	0
T41	0	2	0	0
T43	0	1	0	0
T52	566	0	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	4	0	0
T114	0	2	0	0
T122	407	0	0	0
T142	0	3	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	387	0	0
T20	8114	3	0	0
T32	7318	0	0	0
T33	0	2	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	1	0	0
T52	566	0	0	0
T76	0	3	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	3	0	0
T114	0	1	0	0
T122	407	0	0	0
T142	0	3	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	319	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T33	0	2	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	1	0	0
T45	0	14	0	0
T52	566	0	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	3	0	0
T122	407	0	0	0
T142	0	3	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	319	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T33	0	2	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	1	0	0
T45	0	14	0	0
T52	566	0	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	3	0	0
T122	407	0	0	0
T142	0	3	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	12441	0	0
T20	8114	89	0	0
T32	7318	0	0	0
T33	0	87	0	0
T40	0	396	0	0
T41	0	167	0	0
T43	0	58	0	0
T45	0	139	0	0
T52	566	0	0	0
T76	0	89	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	11	0	0
T122	407	0	0	0
T142	0	151	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	57	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	287	0	0
T19	1464	0	0	0
T33	9655	2	0	0
T40	0	5	0	0
T41	0	2	0	0
T43	0	1	0	0
T45	0	14	0	0
T48	630	0	0	0
T76	0	1	0	0
T97	3940	0	0	0
T98	1723	0	0	0
T112	0	3	0	0
T142	0	3	0	0
T182	0	1	0	0
T287	0	3	0	0
T301	633	0	0	0
T302	528	0	0	0
T303	837	0	0	0
T304	405	0	0	0
T305	531	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T31 T20 T32 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T31 T20 T32 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T31 T20 T32 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T31 T20 T32 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T31 T20 T32 
129        1/1              cnt_en = 1'b0;
           Tests:       T31 T20 T32 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T31 T20 T32 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T31 T20 T32 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T31 T20 T32 
139                     
140        1/1              unique case (state_q)
           Tests:       T31 T20 T32 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T31 T20 T32 
148        1/1                    state_d = DebounceSt;
           Tests:       T31 T20 T32 
149        1/1                    cnt_en = 1'b1;
           Tests:       T31 T20 T32 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T31 T20 T32 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T31 T20 T32 
163        1/1                    state_d = IdleSt;
           Tests:       T20 T76 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T76 
165        1/1                  end else if (cnt_done) begin
           Tests:       T31 T20 T32 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T20 T32 
167        1/1                    if (trigger_active) begin
           Tests:       T31 T20 T32 
168        1/1                      state_d = DetectSt;
           Tests:       T31 T20 T32 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T31 T20 T32 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T31 T20 T32 
182        1/1                  cnt_en = 1'b1;
           Tests:       T31 T20 T32 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T31 T20 T32 
186        1/1                    state_d = IdleSt;
           Tests:       T31 T20 T32 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T20 T32 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T20 T32 T59 
191        1/1                      state_d = StableSt;
           Tests:       T20 T59 T42 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T20 T59 T42 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T20 T59 T42 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T20 T59 T42 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T20 T59 T42 
206        1/1                    state_d = IdleSt;
           Tests:       T20 T59 T42 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T20 T59 T42 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T20,T32
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T31,T20,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T31,T20,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T31,T20,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T20,T32
1	0	Covered	T20,T59,T42
1	1	Covered	T31,T20,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T32,T59
0	1	Covered	T31,T20,T32
1	0	Covered	T20,T76,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T59,T42
0	1	Covered	T20,T59,T42
1	0	Covered	T20,T118

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T59,T42
1	-	Covered	T20,T59,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T20,T32
DetectSt	168	Covered	T31,T20,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T20,T59,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T20,T32
DebounceSt->IdleSt	163	Covered	T31,T20,T32
DetectSt->IdleSt	186	Covered	T31,T20,T32
DetectSt->StableSt	191	Covered	T20,T59,T42
IdleSt->DebounceSt	148	Covered	T31,T20,T32
StableSt->IdleSt	206	Covered	T20,T59,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T20,T32
0	1	Covered	T31,T20,T32
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T20,T32
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T20,T32
IdleSt	0	-	-	-	-	-	-	Covered	T31,T20,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T20,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T20,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T20,T32
DetectSt	-	-	-	-	1	-	-	Covered	T31,T20,T32
DetectSt	-	-	-	-	0	1	-	Covered	T20,T59,T42
DetectSt	-	-	-	-	0	0	-	Covered	T20,T32,T59
StableSt	-	-	-	-	-	-	1	Covered	T20,T59,T42
StableSt	-	-	-	-	-	-	0	Covered	T20,T59,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	3289	0	0
CntIncr_A	6363167	114719	0	0
CntNoWrap_A	6363167	5876109	0	0
DetectStDropOut_A	6363167	403	0	0
DetectedOut_A	6363167	84063	0	0
DetectedPulseOut_A	6363167	1007	0	0
DisabledIdleSt_A	6363167	5418951	0	0
DisabledNoDetection_A	6363167	5420738	0	0
EnterDebounceSt_A	6363167	1654	0	0
EnterDetectSt_A	6363167	1637	0	0
EnterStableSt_A	6363167	1007	0	0
PulseIsPulse_A	6363167	1007	0	0
StayInStableSt	6363167	82930	0	0
gen_high_event_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_high_level_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	876	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	3289	0	0
T20	0	16	0	0
T31	5971	6	0	0
T32	0	25	0	0
T41	0	16	0	0
T42	0	58	0	0
T43	0	36	0	0
T44	0	52	0	0
T58	0	16	0	0
T59	0	12	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	16	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	114719	0	0
T20	0	544	0	0
T31	5971	268	0	0
T32	0	3343	0	0
T41	0	368	0	0
T42	0	2088	0	0
T43	0	1044	0	0
T44	0	1810	0	0
T58	0	352	0	0
T59	0	330	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	600	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5876109	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	403	0	0
T20	0	1	0	0
T31	5971	2	0	0
T32	0	7	0	0
T44	0	16	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	1	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0
T123	0	22	0	0
T125	0	13	0	0
T127	0	24	0	0
T282	0	3	0	0
T306	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	84063	0	0
T20	8114	423	0	0
T32	7318	0	0	0
T41	0	358	0	0
T42	0	1192	0	0
T43	0	2018	0	0
T52	566	0	0	0
T58	0	489	0	0
T59	0	109	0	0
T76	0	510	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	4236	0	0
T122	407	0	0	0
T124	0	1488	0	0
T142	0	1464	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1007	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T41	0	8	0	0
T42	0	29	0	0
T43	0	18	0	0
T52	566	0	0	0
T58	0	8	0	0
T59	0	6	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	20	0	0
T122	407	0	0	0
T124	0	29	0	0
T142	0	12	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5418951	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5420738	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1654	0	0
T20	0	9	0	0
T31	5971	4	0	0
T32	0	18	0	0
T41	0	8	0	0
T42	0	29	0	0
T43	0	18	0	0
T44	0	26	0	0
T58	0	8	0	0
T59	0	6	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	9	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1637	0	0
T20	0	7	0	0
T31	5971	2	0	0
T32	0	7	0	0
T41	0	8	0	0
T42	0	29	0	0
T43	0	18	0	0
T44	0	26	0	0
T58	0	8	0	0
T59	0	6	0	0
T74	553	0	0	0
T75	428	0	0	0
T76	0	7	0	0
T89	538	0	0	0
T90	1288	0	0	0
T102	408	0	0	0
T103	421	0	0	0
T104	543	0	0	0
T105	422	0	0	0
T106	1308	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1007	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T41	0	8	0	0
T42	0	29	0	0
T43	0	18	0	0
T52	566	0	0	0
T58	0	8	0	0
T59	0	6	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	20	0	0
T122	407	0	0	0
T124	0	29	0	0
T142	0	12	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	1007	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T41	0	8	0	0
T42	0	29	0	0
T43	0	18	0	0
T52	566	0	0	0
T58	0	8	0	0
T59	0	6	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	20	0	0
T122	407	0	0	0
T124	0	29	0	0
T142	0	12	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	82930	0	0
T20	8114	418	0	0
T32	7318	0	0	0
T41	0	349	0	0
T42	0	1163	0	0
T43	0	1998	0	0
T52	566	0	0	0
T58	0	480	0	0
T59	0	103	0	0
T76	0	505	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	4216	0	0
T122	407	0	0	0
T124	0	1459	0	0
T142	0	1451	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	876	0	0
T20	8114	4	0	0
T32	7318	0	0	0
T41	0	7	0	0
T42	0	29	0	0
T43	0	16	0	0
T52	566	0	0	0
T58	0	7	0	0
T59	0	6	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T117	0	20	0	0
T122	407	0	0	0
T124	0	29	0	0
T142	0	11	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T31 T20 T32 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T20 T33 T42 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T20 T42 T58 
149        1/1                    cnt_en = 1'b1;
           Tests:       T20 T42 T58 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T20 T42 T58 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T20 T42 T58 
163        1/1                    state_d = IdleSt;
           Tests:       T20 T76 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T76 
165        1/1                  end else if (cnt_done) begin
           Tests:       T20 T42 T58 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T42 T58 
167        1/1                    if (trigger_active) begin
           Tests:       T20 T42 T58 
168        1/1                      state_d = DetectSt;
           Tests:       T20 T42 T58 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T112 T307 T114 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T20 T42 T58 
182        1/1                  cnt_en = 1'b1;
           Tests:       T20 T42 T58 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T20 T42 T58 
186        1/1                    state_d = IdleSt;
           Tests:       T20 T76 T112 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T20 T76 T112 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T20 T42 T58 
191        1/1                      state_d = StableSt;
           Tests:       T20 T42 T58 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T20 T42 T58 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T20 T42 T58 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T20 T42 T58 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T20 T42 T58 
206        1/1                    state_d = IdleSt;
           Tests:       T20 T42 T40 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T20 T42 T58 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T20,T32
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T20,T32
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T42,T58

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T42,T58

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T20,T42,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T33,T59
1	0	Covered	T27,T113,T101
1	1	Covered	T20,T42,T58

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T42,T58
0	1	Covered	T112,T308,T290
1	0	Covered	T20,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T42,T58
0	1	Covered	T20,T42,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T42,T58
1	-	Covered	T20,T42,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T42,T58
DetectSt	168	Covered	T20,T42,T58
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T20,T42,T58

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T42,T58
DebounceSt->IdleSt	163	Covered	T20,T76,T112
DetectSt->IdleSt	186	Covered	T20,T76,T112
DetectSt->StableSt	191	Covered	T20,T42,T58
IdleSt->DebounceSt	148	Covered	T20,T42,T58
StableSt->IdleSt	206	Covered	T20,T42,T58

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T42,T58
0	1	Covered	T20,T42,T58
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T42,T58
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T42,T58
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T42,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T112,T307,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T42,T58
DetectSt	-	-	-	-	1	-	-	Covered	T20,T76,T112
DetectSt	-	-	-	-	0	1	-	Covered	T20,T42,T58
DetectSt	-	-	-	-	0	0	-	Covered	T20,T42,T58
StableSt	-	-	-	-	-	-	1	Covered	T20,T42,T40
StableSt	-	-	-	-	-	-	0	Covered	T20,T42,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6363167	905	0	0
CntIncr_A	6363167	48648	0	0
CntNoWrap_A	6363167	5878493	0	0
DetectStDropOut_A	6363167	63	0	0
DetectedOut_A	6363167	14774	0	0
DetectedPulseOut_A	6363167	362	0	0
DisabledIdleSt_A	6363167	5533418	0	0
DisabledNoDetection_A	6363167	5534734	0	0
EnterDebounceSt_A	6363167	476	0	0
EnterDetectSt_A	6363167	429	0	0
EnterStableSt_A	6363167	362	0	0
PulseIsPulse_A	6363167	362	0	0
StayInStableSt	6363167	14378	0	0
gen_high_level_sva.HighLevelEvent_A	6363167	5881405	0	0
gen_not_sticky_sva.StableStDropOut_A	6363167	327	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	905	0	0
T20	8114	8	0	0
T32	7318	0	0	0
T40	0	6	0	0
T42	0	4	0	0
T43	0	4	0	0
T52	566	0	0	0
T58	0	2	0	0
T76	0	8	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	20	0	0
T114	0	27	0	0
T122	407	0	0	0
T142	0	2	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T307	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	48648	0	0
T20	8114	264	0	0
T32	7318	0	0	0
T40	0	303	0	0
T42	0	136	0	0
T43	0	90	0	0
T52	566	0	0	0
T58	0	67	0	0
T76	0	349	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	1226	0	0
T114	0	1449	0	0
T122	407	0	0	0
T142	0	77	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T307	0	2046	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5878493	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	63	0	0
T112	11824	8	0	0
T123	4967	0	0	0
T129	0	7	0	0
T131	0	4	0	0
T263	671	0	0	0
T290	0	1	0	0
T291	0	7	0	0
T308	0	14	0	0
T309	0	7	0	0
T310	0	4	0	0
T311	0	2	0	0
T312	0	2	0	0
T313	496	0	0	0
T314	522	0	0	0
T315	415	0	0	0
T316	435	0	0	0
T317	422	0	0	0
T318	495	0	0	0
T319	516	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	14774	0	0
T20	8114	91	0	0
T32	7318	0	0	0
T40	0	237	0	0
T42	0	139	0	0
T43	0	147	0	0
T52	566	0	0	0
T58	0	45	0	0
T76	0	92	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T114	0	171	0	0
T122	407	0	0	0
T142	0	46	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	11	0	0
T307	0	141	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	362	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T52	566	0	0	0
T58	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T114	0	12	0	0
T122	407	0	0	0
T142	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	2	0	0
T307	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5533418	0	0
T1	485	84	0	0
T2	486	85	0	0
T3	672	271	0	0
T4	447	46	0	0
T5	493	92	0	0
T8	507	106	0	0
T13	822	421	0	0
T14	494	93	0	0
T15	421	20	0	0
T16	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5534734	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	476	0	0
T20	8114	5	0	0
T32	7318	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T52	566	0	0	0
T58	0	1	0	0
T76	0	5	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	12	0	0
T114	0	15	0	0
T122	407	0	0	0
T142	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T307	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	429	0	0
T20	8114	3	0	0
T32	7318	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T52	566	0	0	0
T58	0	1	0	0
T76	0	3	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T112	0	8	0	0
T114	0	12	0	0
T122	407	0	0	0
T142	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T307	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	362	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T52	566	0	0	0
T58	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T114	0	12	0	0
T122	407	0	0	0
T142	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	2	0	0
T307	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	362	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T52	566	0	0	0
T58	0	1	0	0
T76	0	1	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T114	0	12	0	0
T122	407	0	0	0
T142	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	2	0	0
T307	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	14378	0	0
T20	8114	90	0	0
T32	7318	0	0	0
T40	0	234	0	0
T42	0	137	0	0
T43	0	145	0	0
T52	566	0	0	0
T58	0	43	0	0
T76	0	91	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T114	0	159	0	0
T122	407	0	0	0
T142	0	45	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	9	0	0
T307	0	130	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	5881405	0	0
T1	485	85	0	0
T2	486	86	0	0
T3	672	272	0	0
T4	447	47	0	0
T5	493	93	0	0
T8	507	107	0	0
T13	822	422	0	0
T14	494	94	0	0
T15	421	21	0	0
T16	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6363167	327	0	0
T20	8114	1	0	0
T32	7318	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	0	14	0	0
T52	566	0	0	0
T91	7504	0	0	0
T95	502	0	0	0
T96	490	0	0	0
T114	0	12	0	0
T122	407	0	0	0
T124	0	3	0	0
T142	0	1	0	0
T221	8418	0	0	0
T222	541	0	0	0
T223	427	0	0	0
T287	0	2	0	0
T307	0	11	0	0