Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
89.02	89.02	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	89.02	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.02	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	9	53	85.48

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	1	30	96.77	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1626

1

T31

12

T37

22

T52

20

auto[1]

524

1

T37

6

T40

5

T91

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1628

1

T31

12

T37

28

T52

17

auto[1]

522

1

T40

5

T52

3

T86

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1620

1

T31

12

T37

28

T40

1

auto[1]

530

1

T40

4

T91

2

T86

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1679

1

T31

12

T37

28

T40

2

auto[1]

471

1

T40

3

T52

4

T91

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1961

1

T31

12

T37

28

T40

5

auto[1]

189

1

T52

7

T111

2

T113

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2022

1

T31

12

T37

22

T40

5

auto[1]

128

1

T37

6

T111

2

T228

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1990

1

T31

9

T37

28

T40

5

auto[1]

160

1

T31

3

T229

10

T230

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1912

1

T31

9

T37

24

T40

5

auto[1]

238

1

T31

3

T37

4

T52

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1981

1

T31

12

T37

28

T40

5

auto[1]

169

1

T52

4

T86

2

T111

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1744

1

T31

9

T37

24

T40

4

auto[1]

406

1

T31

3

T37

4

T40

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	710	1			T40	5		T91	7		T41	11
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	58	1			T233	3		T258	1		T340	13
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	64	1			T86	2		T43	2		T232	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	18	1			T52	4		T113	2		T204	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	87	1			T37	4		T86	1		T101	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	44	1			T52	3		T230	1		T231	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	16	1			T233	1		T258	1		T341	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T231	4		T100	2		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	50	1			T229	10		T342	1		T343	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T233	3		T344	1		T345	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	18	1			T230	4		T257	2		T346	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	19	1			T31	3		T231	1		T232	2
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	4	1			T340	4		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	32	1			T37	6		T230	3		T347	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	17	1			T348	11		T349	4		T259	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	11	1			T229	9		T350	1		T351	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	16	1			T229	5		T352	8		T353	3
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T354	3		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T348	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	12	1			T342	1		T348	7		T328	3
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	8	1			T257	5		T328	3		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T352	2		T259	1		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T355	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	1	30	96.77	1
Automatically Generated Cross Bins	31	1	30	96.77	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Uncovered bins

cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

95

1

T37

6

T86

2

T121

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

74

1

T31

3

T37

4

T232

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T229

10

T230

3

T117

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

155

1

T52

4

T235

8

T257

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

25

1

T43

2

T327

9

T324

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T91

3

T336

5

T233

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T91

2

T114

2

T118

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

95

1

T41

9

T114

15

T340

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

52

1

T39

7

T229

5

T232

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T258

1

T327

3

T334

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T91

2

T116

2

T260

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T38

4

T117

8

T236

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T356

3

T208

3

T357

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T358

2

T359

2

T330

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T41

2

T118

1

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

103

1

T115

8

T231

4

T356

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

66

1

T42

2

T231

1

T336

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

18

1

T52

3

T121

4

T230

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T358

1

T210

6

T251

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

29

1

T250

5

T237

4

T342

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T256

2

T261

3

T323

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

12

1

T154

2

T120

3

T237

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T40

1

T208

1

T252

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T113

2

T114

7

T101

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

61

1

T40

2

T39

2

T116

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T86

1

T119

3

T340

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T236

6

T358

1

T237

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T112

1

T102

4

T360

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T40

2

T350

1

T332

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T38

1

T233

3

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded