Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

646

1

T4

8

T78

11

T79

6

auto[1]

677

1

T4

12

T78

9

T79

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

299

1

T4

4

T78

4

T79

5

from_0to1

308

1

T4

5

T78

4

T79

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678

1

T4

13

T78

9

T79

7

auto[1]

645

1

T4

7

T78

11

T79

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T4

9

T78

10

T79

12

auto[1]

681

1

T4

11

T78

10

T79

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

33

1

T78

2

T80

1

T75

1

auto[0]

from_1to0

auto[0]

auto[1]

32

1

T4

1

T80

1

T75

1

auto[0]

from_1to0

auto[1]

auto[0]

37

1

T78

1

T79

1

T80

1

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T4

1

T78

1

T79

1

auto[0]

from_0to1

auto[0]

auto[0]

30

1

T4

2

T78

1

T79

1

auto[0]

from_0to1

auto[0]

auto[1]

42

1

T80

1

T83

1

T375

1

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T286

1

T375

1

T295

1

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T4

1

T83

2

T75

2

auto[1]

from_1to0

auto[0]

auto[0]

29

1

T4

1

T75

1

T376

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T79

1

T286

1

T375

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T79

1

T80

1

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T4

1

T79

1

T83

3

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T78

2

T79

1

T75

1

auto[1]

from_0to1

auto[0]

auto[1]

33

1

T4

1

T78

1

T80

1

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T79

4

T80

2

T376

1

auto[1]

from_0to1

auto[1]

auto[1]

38

1

T4

1

T83

1

T375

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

671

1

T4

10

T78

6

T79

11

auto[1]

652

1

T4

10

T78

14

T79

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

310

1

T4

4

T78

6

T79

4

from_0to1

310

1

T4

4

T78

7

T79

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

663

1

T4

14

T78

8

T79

9

auto[1]

660

1

T4

6

T78

12

T79

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657

1

T4

8

T78

12

T79

11

auto[1]

666

1

T4

12

T78

8

T79

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

34

1

T4

1

T80

1

T143

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T4

1

T78

1

T83

1

auto[0]

from_1to0

auto[1]

auto[0]

31

1

T286

1

T375

1

T295

1

auto[0]

from_1to0

auto[1]

auto[1]

37

1

T78

1

T80

1

T286

1

auto[0]

from_0to1

auto[0]

auto[0]

36

1

T80

1

T83

1

T375

1

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T4

1

T80

3

T286

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T78

1

T83

1

T241

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T79

2

T80

1

T83

1

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T4

1

T79

1

T375

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T4

1

T79

1

T80

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T78

1

T79

1

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T78

3

T79

1

T80

1

auto[1]

from_0to1

auto[0]

auto[0]

33

1

T78

3

T75

1

T376

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T4

1

T78

1

T80

1

auto[1]

from_0to1

auto[1]

auto[0]

35

1

T78

2

T79

1

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T4

2

T79

2

T75

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

646

1

T4

9

T78

7

T79

9

auto[1]

677

1

T4

11

T78

13

T79

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

300

1

T4

4

T78

5

T79

4

from_0to1

300

1

T4

3

T78

6

T79

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

697

1

T4

11

T78

9

T79

9

auto[1]

626

1

T4

9

T78

11

T79

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T4

9

T78

10

T79

10

auto[1]

636

1

T4

11

T78

10

T79

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T79

2

T83

1

T75

2

auto[0]

from_1to0

auto[0]

auto[1]

31

1

T4

1

T80

1

T83

1

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T78

1

T80

1

T83

2

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T286

1

T375

1

T295

1

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T79

1

T80

1

T143

1

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T79

2

T75

1

T286

1

auto[0]

from_0to1

auto[1]

auto[0]

32

1

T4

1

T78

1

T83

1

auto[0]

from_0to1

auto[1]

auto[1]

32

1

T78

1

T79

1

T83

1

auto[1]

from_1to0

auto[0]

auto[0]

44

1

T4

1

T78

1

T79

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T4

1

T78

2

T79

1

auto[1]

from_1to0

auto[1]

auto[0]

25

1

T4

1

T78

1

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

23

1

T80

1

T295

1

T376

1

auto[1]

from_0to1

auto[0]

auto[0]

46

1

T375

2

T295

2

T376

1

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T78

2

T80

1

T83

3

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T78

2

T79

1

T75

1

auto[1]

from_0to1

auto[1]

auto[1]

29

1

T4

2

T80

2

T75

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

652

1

T4

14

T78

12

T79

9

auto[1]

671

1

T4

6

T78

8

T79

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

330

1

T4

7

T78

4

T79

7

from_0to1

323

1

T4

7

T78

4

T79

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

663

1

T4

8

T78

8

T79

7

auto[1]

660

1

T4

12

T78

12

T79

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657

1

T4

10

T78

10

T79

10

auto[1]

666

1

T4

10

T78

10

T79

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T4

1

T79

1

T80

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T4

1

T75

1

T286

1

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T4

1

T79

1

T75

1

auto[0]

from_1to0

auto[1]

auto[1]

33

1

T4

2

T78

1

T80

1

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T4

2

T83

2

T286

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T4

1

T75

1

T375

2

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T4

1

T78

3

T79

1

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T4

1

T79

2

T83

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T79

2

T83

1

T295

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T78

1

T79

1

T75

1

auto[1]

from_1to0

auto[1]

auto[0]

35

1

T78

1

T79

1

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T4

2

T78

1

T79

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T75

1

T286

2

T376

2

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T78

1

T80

1

T75

1

auto[1]

from_0to1

auto[1]

auto[0]

45

1

T4

2

T79

1

T80

2

auto[1]

from_0to1

auto[1]

auto[1]

45

1

T79

2

T75

1

T375

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T4

8

T78

9

T79

12

auto[1]

681

1

T4

12

T78

11

T79

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

321

1

T4

5

T78

6

T79

5

from_0to1

302

1

T4

6

T78

5

T79

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676

1

T4

10

T78

9

T79

6

auto[1]

647

1

T4

10

T78

11

T79

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656

1

T4

13

T78

6

T79

7

auto[1]

667

1

T4

7

T78

14

T79

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T4

2

T78

1

T80

1

auto[0]

from_1to0

auto[0]

auto[1]

37

1

T79

1

T80

1

T75

2

auto[0]

from_1to0

auto[1]

auto[0]

25

1

T78

1

T79

1

T75

1

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T78

1

T83

1

T286

2

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T4

1

T78

1

T75

1

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T79

1

T80

1

T286

1

auto[0]

from_0to1

auto[1]

auto[0]

32

1

T79

1

T80

1

T286

1

auto[0]

from_0to1

auto[1]

auto[1]

34

1

T4

1

T78

1

T79

2

auto[1]

from_1to0

auto[0]

auto[0]

46

1

T4

1

T80

1

T75

2

auto[1]

from_1to0

auto[0]

auto[1]

35

1

T80

1

T83

1

T286

1

auto[1]

from_1to0

auto[1]

auto[0]

49

1

T4

1

T79

2

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T4

1

T78

3

T79

1

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T75

1

T286

1

T375

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T4

2

T78

1

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

38

1

T4

1

T83

2

T75

1

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T4

1

T78

2

T80

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

665

1

T4

9

T78

12

T79

7

auto[1]

658

1

T4

11

T78

8

T79

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

305

1

T4

6

T78

6

T79

6

from_0to1

305

1

T4

5

T78

5

T79

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

613

1

T4

11

T78

10

T79

12

auto[1]

710

1

T4

9

T78

10

T79

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

684

1

T4

10

T78

11

T79

11

auto[1]

639

1

T4

10

T78

9

T79

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T4

2

T78

1

T79

2

auto[0]

from_1to0

auto[0]

auto[1]

26

1

T78

2

T75

1

T145

1

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T78

1

T83

1

T375

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T80

1

T83

2

T376

1

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T4

1

T78

1

T79

1

auto[0]

from_0to1

auto[0]

auto[1]

41

1

T4

1

T80

1

T83

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T78

2

T80

1

T83

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T4

1

T83

1

T286

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T79

1

T80

2

T376

1

auto[1]

from_1to0

auto[0]

auto[1]

34

1

T4

2

T78

1

T79

1

auto[1]

from_1to0

auto[1]

auto[0]

41

1

T4

1

T78

1

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T4

1

T79

1

T169

1

auto[1]

from_0to1

auto[0]

auto[0]

33

1

T79

1

T80

1

T83

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T4

1

T79

2

T286

1

auto[1]

from_0to1

auto[1]

auto[0]

31

1

T78

1

T80

1

T286

1

auto[1]

from_0to1

auto[1]

auto[1]

44

1

T4

1

T78

1

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

673

1

T4

13

T78

8

T79

8

auto[1]

650

1

T4

7

T78

12

T79

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

317

1

T4

3

T78

6

T79

6

from_0to1

320

1

T4

3

T78

5

T79

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

643

1

T4

8

T78

7

T79

7

auto[1]

680

1

T4

12

T78

13

T79

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T4

10

T78

12

T79

11

auto[1]

674

1

T4

10

T78

8

T79

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

29

1

T80

1

T83

1

T286

1

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T4

1

T78

1

T79

1

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T4

1

T78

1

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

45

1

T78

1

T286

1

T295

1

auto[0]

from_0to1

auto[0]

auto[0]

43

1

T4

1

T79

1

T286

1

auto[0]

from_0to1

auto[0]

auto[1]

43

1

T4

1

T83

2

T75

2

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T4

1

T79

1

T75

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T78

1

T79

1

T80

2

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T79

2

T75

1

T376

1

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T78

2

T80

1

T75

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T78

1

T79

2

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T4

1

T79

1

T83

2

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T78

2

T83

1

T286

1

auto[1]

from_0to1

auto[0]

auto[1]

27

1

T80

1

T75

1

T375

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T78

1

T79

1

T80

1

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T78

1

T79

2

T75

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

650

1

T4

11

T78

12

T79

10

auto[1]

673

1

T4

9

T78

8

T79

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

312

1

T4

6

T78

6

T79

4

from_0to1

308

1

T4

6

T78

6

T79

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

654

1

T4

9

T78

8

T79

9

auto[1]

669

1

T4

11

T78

12

T79

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675

1

T4

11

T78

9

T79

8

auto[1]

648

1

T4

9

T78

11

T79

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

24

1

T4

1

T78

1

T80

2

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T4

1

T78

2

T79

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T4

1

T83

2

T295

1

auto[0]

from_1to0

auto[1]

auto[1]

31

1

T80

2

T75

2

T375

1

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T4

2

T78

2

T75

1

auto[0]

from_0to1

auto[0]

auto[1]

42

1

T4

1

T79

1

T83

2

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T4

1

T80

2

T286

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T4

1

T78

2

T75

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T4

1

T75

2

T286

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T4

1

T79

1

T83

1

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T4

1

T78

2

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

30

1

T78

1

T79

1

T83

1

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T79

1

T80

2

T83

2

auto[1]

from_0to1

auto[0]

auto[1]

35

1

T4

1

T78

1

T295

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T79

1

T80

1

T295

1

auto[1]

from_0to1

auto[1]

auto[1]

30

1

T78

1

T80

1

T83

1