Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142938	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

110510

1

T1

10

T4

60

T2

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	134824	1			T1	4		T4	62		T2	4
values[0x0]	58658	1			T1	7		T4	30		T2	5
values[0x1]	59966	1			T1	3		T4	31		T2	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	115464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

137984

1

T1

11

T4

69

T2

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1089	1			T16	14		T26	1		T25	4
valid_sources[0x01]	765	1			T14	1		T25	12		T7	1
valid_sources[0x02]	883	1			T26	4		T25	10		T72	1
valid_sources[0x03]	1074	1			T71	1		T72	3		T10	1
valid_sources[0x04]	805	1			T3	1		T62	1		T9	1
valid_sources[0x05]	738	1			T3	1		T7	1		T71	1
valid_sources[0x06]	696	1			T3	1		T81	1		T194	3
valid_sources[0x07]	2018	1			T7	1		T9	2		T58	13
valid_sources[0x08]	852	1			T79	1		T58	13		T299	9
valid_sources[0x09]	1049	1			T25	3		T9	4		T58	1
valid_sources[0x0a]	1096	1			T7	1		T77	4		T72	2
valid_sources[0x0b]	1418	1			T7	1		T77	1		T9	1
valid_sources[0x0c]	763	1			T25	6		T62	1		T9	1
valid_sources[0x0d]	1694	1			T1	1		T7	1		T9	2
valid_sources[0x0e]	942	1			T14	1		T23	1		T58	5
valid_sources[0x0f]	1702	1			T25	3		T7	1		T72	2
valid_sources[0x10]	871	1			T25	4		T7	1		T77	1
valid_sources[0x11]	762	1			T295	2		T376	2		T264	4
valid_sources[0x12]	1079	1			T7	1		T9	1		T79	1
valid_sources[0x13]	832	1			T2	3		T26	1		T82	2
valid_sources[0x14]	779	1			T72	2		T79	1		T82	1
valid_sources[0x15]	725	1			T194	4		T58	3		T214	1
valid_sources[0x16]	985	1			T25	4		T57	4		T75	9
valid_sources[0x17]	991	1			T3	2		T25	1		T7	1
valid_sources[0x18]	739	1			T77	2		T9	1		T82	2
valid_sources[0x19]	756	1			T25	4		T194	1		T377	1
valid_sources[0x1a]	1426	1			T7	1		T72	1		T9	1
valid_sources[0x1b]	799	1			T55	1		T58	4		T75	2
valid_sources[0x1c]	790	1			T9	1		T194	9		T58	1
valid_sources[0x1d]	853	1			T4	8		T71	2		T10	1
valid_sources[0x1e]	836	1			T3	2		T25	19		T194	1
valid_sources[0x1f]	904	1			T7	1		T71	1		T72	1
valid_sources[0x20]	958	1			T7	1		T79	1		T82	1
valid_sources[0x21]	1259	1			T25	2		T9	2		T82	1
valid_sources[0x22]	773	1			T7	2		T71	1		T79	2
valid_sources[0x23]	748	1			T25	3		T71	2		T23	2
valid_sources[0x24]	816	1			T1	1		T7	1		T71	3
valid_sources[0x25]	748	1			T3	1		T9	4		T90	2
valid_sources[0x26]	910	1			T3	1		T26	2		T9	2
valid_sources[0x27]	974	1			T25	3		T194	3		T58	1
valid_sources[0x28]	851	1			T25	2		T81	1		T75	12
valid_sources[0x29]	793	1			T14	1		T7	1		T58	4
valid_sources[0x2a]	730	1			T3	1		T9	2		T76	1
valid_sources[0x2b]	770	1			T1	1		T25	2		T7	1
valid_sources[0x2c]	925	1			T25	3		T23	1		T64	1
valid_sources[0x2d]	1071	1			T7	1		T9	2		T194	3
valid_sources[0x2e]	1166	1			T79	5		T30	281		T194	1
valid_sources[0x2f]	939	1			T7	1		T81	1		T10	1
valid_sources[0x30]	1053	1			T15	7		T26	2		T9	1
valid_sources[0x31]	964	1			T71	1		T10	1		T194	1
valid_sources[0x32]	704	1			T9	2		T58	3		T264	1
valid_sources[0x33]	1068	1			T7	2		T77	1		T9	2
valid_sources[0x34]	822	1			T26	1		T77	1		T71	1
valid_sources[0x35]	920	1			T9	1		T64	1		T58	6
valid_sources[0x36]	879	1			T3	1		T25	7		T9	1
valid_sources[0x37]	1850	1			T3	1		T7	1		T9	1
valid_sources[0x38]	784	1			T7	1		T72	1		T194	15
valid_sources[0x39]	826	1			T26	4		T9	1		T10	1
valid_sources[0x3a]	903	1			T25	6		T77	1		T9	2
valid_sources[0x3b]	948	1			T25	5		T7	1		T77	3
valid_sources[0x3c]	1032	1			T71	1		T29	1		T81	3
valid_sources[0x3d]	726	1			T7	1		T9	1		T79	5
valid_sources[0x3e]	1096	1			T26	2		T69	5		T9	1
valid_sources[0x3f]	776	1			T29	1		T58	1		T75	2
valid_sources[0x40]	983	1			T26	1		T7	1		T77	3
valid_sources[0x41]	1034	1			T26	1		T72	4		T79	1
valid_sources[0x42]	780	1			T1	2		T194	4		T75	4
valid_sources[0x43]	1002	1			T1	1		T25	4		T7	1
valid_sources[0x44]	941	1			T25	2		T72	2		T9	1
valid_sources[0x45]	1154	1			T26	1		T25	2		T7	1
valid_sources[0x46]	900	1			T7	1		T58	3		T75	6
valid_sources[0x47]	792	1			T77	1		T110	4		T189	7
valid_sources[0x48]	813	1			T3	1		T25	1		T72	2
valid_sources[0x49]	972	1			T7	1		T29	1		T172	1
valid_sources[0x4a]	748	1			T54	1		T9	2		T11	1
valid_sources[0x4b]	1614	1			T9	2		T82	2		T194	5
valid_sources[0x4c]	788	1			T26	1		T77	2		T72	1
valid_sources[0x4d]	888	1			T79	1		T194	8		T58	4
valid_sources[0x4e]	980	1			T26	1		T25	8		T79	4
valid_sources[0x4f]	858	1			T26	1		T25	6		T7	1
valid_sources[0x50]	1705	1			T3	2		T25	3		T77	1
valid_sources[0x51]	1592	1			T63	3		T31	881		T75	3
valid_sources[0x52]	817	1			T7	1		T62	1		T58	1
valid_sources[0x53]	799	1			T26	1		T25	8		T214	1
valid_sources[0x54]	869	1			T25	2		T9	2		T81	1
valid_sources[0x55]	1972	1			T7	2		T72	1		T29	1
valid_sources[0x56]	817	1			T25	1		T77	1		T9	2
valid_sources[0x57]	960	1			T26	2		T77	1		T9	1
valid_sources[0x58]	993	1			T3	1		T81	1		T195	5
valid_sources[0x59]	837	1			T77	1		T27	1		T75	1
valid_sources[0x5a]	868	1			T25	2		T79	2		T23	3
valid_sources[0x5b]	988	1			T81	2		T58	3		T286	2
valid_sources[0x5c]	1087	1			T25	3		T79	1		T82	3
valid_sources[0x5d]	1379	1			T26	1		T25	8		T62	2
valid_sources[0x5e]	810	1			T26	2		T194	4		T58	1
valid_sources[0x5f]	820	1			T26	3		T25	3		T9	4
valid_sources[0x60]	1226	1			T14	1		T72	1		T9	1
valid_sources[0x61]	800	1			T58	2		T286	1		T45	1
valid_sources[0x62]	711	1			T194	5		T58	3		T175	1
valid_sources[0x63]	789	1			T76	2		T264	1		T37	12
valid_sources[0x64]	774	1			T25	4		T194	2		T286	1
valid_sources[0x65]	912	1			T25	7		T9	2		T58	6
valid_sources[0x66]	1050	1			T25	1		T7	1		T72	1
valid_sources[0x67]	816	1			T12	47		T3	2		T5	7
valid_sources[0x68]	1482	1			T7	3		T9	2		T81	1
valid_sources[0x69]	754	1			T4	23		T25	1		T7	1
valid_sources[0x6a]	2386	1			T25	1		T78	123		T9	2
valid_sources[0x6b]	995	1			T7	1		T77	1		T9	4
valid_sources[0x6c]	827	1			T7	1		T62	2		T194	10
valid_sources[0x6d]	860	1			T9	1		T81	1		T82	3
valid_sources[0x6e]	701	1			T194	1		T216	3		T76	1
valid_sources[0x6f]	980	1			T62	1		T77	2		T72	1
valid_sources[0x70]	828	1			T7	1		T62	1		T194	1
valid_sources[0x71]	933	1			T7	1		T72	1		T75	3
valid_sources[0x72]	924	1			T25	1		T77	1		T54	2
valid_sources[0x73]	776	1			T23	1		T76	1		T378	1
valid_sources[0x74]	668	1			T25	6		T7	1		T194	1
valid_sources[0x75]	1230	1			T1	1		T72	1		T9	1
valid_sources[0x76]	811	1			T81	2		T11	3		T58	4
valid_sources[0x77]	602	1			T7	3		T9	2		T194	12
valid_sources[0x78]	924	1			T81	2		T82	1		T216	3
valid_sources[0x79]	811	1			T4	13		T7	1		T79	4
valid_sources[0x7a]	1183	1			T77	1		T81	1		T194	9
valid_sources[0x7b]	895	1			T25	4		T58	7		T377	1
valid_sources[0x7c]	859	1			T3	1		T25	10		T64	2
valid_sources[0x7d]	1330	1			T9	4		T58	1		T76	1
valid_sources[0x7e]	753	1			T26	4		T7	2		T77	1
valid_sources[0x7f]	860	1			T26	3		T77	3		T71	1
valid_sources[0x80]	742	1			T15	5		T26	1		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60662

1

T1

2

T4

37

T2

3

values[0x0]

all_enables

biggest_size

29065

1

T1

7

T4

17

T2

1

values[0x1]

all_enables

biggest_size

20783

1

T1

1

T4

6

T2

1