Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1237025007 10758 0 0
auto_block_debounce_ctl_rd_A 1237025007 1779 0 0
auto_block_out_ctl_rd_A 1237025007 2493 0 0
com_det_ctl_0_rd_A 1237025007 3919 0 0
com_det_ctl_1_rd_A 1237025007 3755 0 0
com_det_ctl_2_rd_A 1237025007 4116 0 0
com_det_ctl_3_rd_A 1237025007 3966 0 0
com_out_ctl_0_rd_A 1237025007 4290 0 0
com_out_ctl_1_rd_A 1237025007 4208 0 0
com_out_ctl_2_rd_A 1237025007 4171 0 0
com_out_ctl_3_rd_A 1237025007 4222 0 0
com_pre_det_ctl_0_rd_A 1237025007 1639 0 0
com_pre_det_ctl_1_rd_A 1237025007 1625 0 0
com_pre_det_ctl_2_rd_A 1237025007 1433 0 0
com_pre_det_ctl_3_rd_A 1237025007 1535 0 0
com_pre_sel_ctl_0_rd_A 1237025007 4486 0 0
com_pre_sel_ctl_1_rd_A 1237025007 4453 0 0
com_pre_sel_ctl_2_rd_A 1237025007 4409 0 0
com_pre_sel_ctl_3_rd_A 1237025007 4562 0 0
com_sel_ctl_0_rd_A 1237025007 4505 0 0
com_sel_ctl_1_rd_A 1237025007 4644 0 0
com_sel_ctl_2_rd_A 1237025007 4274 0 0
com_sel_ctl_3_rd_A 1237025007 4571 0 0
ec_rst_ctl_rd_A 1237025007 2454 0 0
intr_enable_rd_A 1237025007 1998 0 0
key_intr_ctl_rd_A 1237025007 3789 0 0
key_intr_debounce_ctl_rd_A 1237025007 1488 0 0
key_invert_ctl_rd_A 1237025007 4883 0 0
pin_allowed_ctl_rd_A 1237025007 4879 0 0
pin_out_ctl_rd_A 1237025007 3652 0 0
pin_out_value_rd_A 1237025007 3721 0 0
regwen_rd_A 1237025007 1471 0 0
ulp_ac_debounce_ctl_rd_A 1237025007 1774 0 0
ulp_ctl_rd_A 1237025007 1716 0 0
ulp_lid_debounce_ctl_rd_A 1237025007 1697 0 0
ulp_pwrb_debounce_ctl_rd_A 1237025007 1667 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 10758 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 1 0 0
T25 104974 7 0 0
T27 88822 0 0 0
T58 0 8 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 8 0 0
T194 0 5 0 0
T216 0 12 0 0
T239 0 4 0 0
T271 0 14 0 0
T287 0 6 0 0
T288 0 6 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1779 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 16 0 0
T25 104974 4 0 0
T27 88822 11 0 0
T60 0 10 0 0
T61 0 4 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T132 0 7 0 0
T144 0 12 0 0
T152 0 6 0 0
T239 0 23 0 0
T287 0 55 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 2493 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 24 0 0
T25 104974 8 0 0
T27 88822 16 0 0
T28 0 10 0 0
T60 0 1 0 0
T61 0 3 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T132 0 3 0 0
T144 0 20 0 0
T239 0 7 0 0
T287 0 30 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 3919 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 25 0 0
T25 104974 11 0 0
T27 88822 0 0 0
T37 0 44 0 0
T41 0 70 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 64 0 0
T144 0 17 0 0
T152 0 11 0 0
T239 0 18 0 0
T287 0 39 0 0
T289 0 7 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 3755 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 17 0 0
T25 104974 16 0 0
T27 88822 0 0 0
T37 0 25 0 0
T41 0 74 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 78 0 0
T144 0 13 0 0
T152 0 9 0 0
T239 0 15 0 0
T287 0 46 0 0
T289 0 30 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4116 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 14 0 0
T25 104974 2 0 0
T27 88822 0 0 0
T37 0 92 0 0
T41 0 83 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 62 0 0
T144 0 7 0 0
T152 0 8 0 0
T239 0 18 0 0
T287 0 53 0 0
T289 0 11 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 3966 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 16 0 0
T25 104974 15 0 0
T27 88822 0 0 0
T37 0 40 0 0
T41 0 70 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 70 0 0
T144 0 7 0 0
T152 0 8 0 0
T239 0 10 0 0
T287 0 42 0 0
T289 0 16 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4290 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 28 0 0
T25 104974 3 0 0
T27 88822 0 0 0
T37 0 40 0 0
T41 0 72 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 54 0 0
T144 0 14 0 0
T152 0 6 0 0
T239 0 15 0 0
T287 0 27 0 0
T289 0 4 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4208 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 27 0 0
T25 104974 9 0 0
T27 88822 0 0 0
T37 0 16 0 0
T41 0 67 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 73 0 0
T144 0 15 0 0
T152 0 8 0 0
T239 0 17 0 0
T287 0 40 0 0
T289 0 17 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4171 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 3 0 0
T25 104974 7 0 0
T27 88822 0 0 0
T37 0 33 0 0
T41 0 66 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 59 0 0
T144 0 13 0 0
T152 0 10 0 0
T239 0 22 0 0
T287 0 30 0 0
T289 0 20 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4222 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 21 0 0
T25 104974 13 0 0
T27 88822 0 0 0
T37 0 46 0 0
T41 0 59 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 64 0 0
T144 0 19 0 0
T152 0 4 0 0
T239 0 7 0 0
T287 0 41 0 0
T289 0 9 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1639 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 30 0 0
T25 104974 12 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 20 0 0
T152 0 14 0 0
T239 0 7 0 0
T272 0 42 0 0
T287 0 38 0 0
T289 0 11 0 0
T290 0 43 0 0
T291 0 31 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1625 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 25 0 0
T25 104974 4 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 24 0 0
T152 0 13 0 0
T239 0 13 0 0
T272 0 28 0 0
T287 0 34 0 0
T289 0 8 0 0
T290 0 38 0 0
T291 0 25 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1433 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 26 0 0
T25 104974 17 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 13 0 0
T152 0 18 0 0
T239 0 24 0 0
T272 0 50 0 0
T287 0 40 0 0
T289 0 18 0 0
T290 0 24 0 0
T291 0 30 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1535 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 19 0 0
T25 104974 8 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 8 0 0
T152 0 10 0 0
T239 0 18 0 0
T272 0 39 0 0
T287 0 30 0 0
T289 0 14 0 0
T290 0 57 0 0
T291 0 18 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4486 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 12 0 0
T25 104974 9 0 0
T27 88822 0 0 0
T37 0 37 0 0
T41 0 86 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 65 0 0
T144 0 18 0 0
T152 0 7 0 0
T239 0 17 0 0
T287 0 54 0 0
T289 0 7 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4453 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 22 0 0
T25 104974 7 0 0
T27 88822 0 0 0
T37 0 43 0 0
T41 0 58 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 79 0 0
T144 0 23 0 0
T152 0 8 0 0
T239 0 21 0 0
T287 0 47 0 0
T289 0 13 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4409 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 12 0 0
T25 104974 3 0 0
T27 88822 0 0 0
T37 0 64 0 0
T41 0 48 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 84 0 0
T144 0 13 0 0
T152 0 9 0 0
T239 0 9 0 0
T287 0 28 0 0
T289 0 20 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4562 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 20 0 0
T25 104974 16 0 0
T27 88822 0 0 0
T37 0 29 0 0
T41 0 72 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 55 0 0
T144 0 19 0 0
T152 0 19 0 0
T239 0 13 0 0
T287 0 42 0 0
T289 0 16 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4505 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 13 0 0
T25 104974 11 0 0
T27 88822 0 0 0
T37 0 40 0 0
T41 0 70 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 56 0 0
T144 0 14 0 0
T152 0 13 0 0
T239 0 7 0 0
T287 0 27 0 0
T289 0 13 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4644 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 12 0 0
T25 104974 2 0 0
T27 88822 0 0 0
T37 0 56 0 0
T41 0 58 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 55 0 0
T144 0 28 0 0
T152 0 19 0 0
T239 0 10 0 0
T287 0 43 0 0
T289 0 9 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4274 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 26 0 0
T25 104974 13 0 0
T27 88822 0 0 0
T37 0 52 0 0
T41 0 53 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 36 0 0
T144 0 8 0 0
T152 0 12 0 0
T239 0 13 0 0
T287 0 40 0 0
T289 0 16 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4571 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 14 0 0
T25 104974 1 0 0
T27 88822 0 0 0
T37 0 46 0 0
T41 0 62 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T91 0 70 0 0
T144 0 15 0 0
T152 0 28 0 0
T239 0 22 0 0
T287 0 36 0 0
T289 0 19 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 2454 0 0
T3 117509 0 0 0
T5 211269 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 19 0 0
T14 91412 6 0 0
T15 243722 0 0 0
T16 160902 0 0 0
T17 32710 0 0 0
T25 104974 9 0 0
T26 250798 0 0 0
T30 0 6 0 0
T37 0 18 0 0
T69 0 3 0 0
T91 0 11 0 0
T144 0 14 0 0
T239 0 7 0 0
T287 0 38 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1998 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 30 0 0
T25 104974 33 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 14 0 0
T152 0 17 0 0
T239 0 27 0 0
T272 0 35 0 0
T287 0 35 0 0
T289 0 16 0 0
T290 0 45 0 0
T292 0 17 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 3789 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 17 0 0
T25 104974 9 0 0
T27 88822 0 0 0
T30 0 83 0 0
T45 0 4 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 31 0 0
T152 0 12 0 0
T163 0 6 0 0
T239 0 14 0 0
T287 0 38 0 0
T289 0 22 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1488 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 17 0 0
T25 104974 6 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 21 0 0
T152 0 2 0 0
T239 0 9 0 0
T272 0 40 0 0
T287 0 36 0 0
T289 0 14 0 0
T290 0 32 0 0
T291 0 27 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4883 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 18 0 0
T25 104974 56 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 65 0 0
T72 0 95 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 15 0 0
T146 0 68 0 0
T239 0 4 0 0
T287 0 35 0 0
T293 0 58 0 0
T294 0 62 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 4879 0 0
T2 118961 0 0 0
T3 117509 0 0 0
T4 30650 54 0 0
T5 211269 0 0 0
T9 0 23 0 0
T12 51830 0 0 0
T13 211429 0 0 0
T14 91412 0 0 0
T15 243722 0 0 0
T16 160902 0 0 0
T17 32710 0 0 0
T25 0 5 0 0
T144 0 14 0 0
T165 0 61 0 0
T169 0 55 0 0
T239 0 13 0 0
T286 0 75 0 0
T287 0 38 0 0
T295 0 67 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 3652 0 0
T2 118961 0 0 0
T3 117509 0 0 0
T4 30650 51 0 0
T5 211269 0 0 0
T9 0 23 0 0
T12 51830 0 0 0
T13 211429 0 0 0
T14 91412 0 0 0
T15 243722 0 0 0
T16 160902 0 0 0
T17 32710 0 0 0
T25 0 1 0 0
T144 0 15 0 0
T165 0 79 0 0
T169 0 66 0 0
T239 0 11 0 0
T286 0 71 0 0
T287 0 48 0 0
T295 0 74 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 3721 0 0
T2 118961 0 0 0
T3 117509 0 0 0
T4 30650 33 0 0
T5 211269 0 0 0
T9 0 16 0 0
T12 51830 0 0 0
T13 211429 0 0 0
T14 91412 0 0 0
T15 243722 0 0 0
T16 160902 0 0 0
T17 32710 0 0 0
T25 0 5 0 0
T144 0 13 0 0
T165 0 81 0 0
T169 0 72 0 0
T239 0 15 0 0
T286 0 78 0 0
T287 0 35 0 0
T295 0 76 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1471 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 8 0 0
T25 104974 13 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T144 0 16 0 0
T152 0 17 0 0
T239 0 13 0 0
T272 0 43 0 0
T287 0 43 0 0
T289 0 17 0 0
T290 0 20 0 0
T291 0 39 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1774 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 23 0 0
T25 104974 8 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T95 0 7 0 0
T144 0 23 0 0
T146 0 4 0 0
T152 0 10 0 0
T239 0 15 0 0
T287 0 42 0 0
T289 0 12 0 0
T296 0 9 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1716 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 14 0 0
T25 104974 3 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T66 0 1 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T95 0 16 0 0
T136 0 4 0 0
T144 0 25 0 0
T146 0 2 0 0
T152 0 15 0 0
T239 0 9 0 0
T287 0 36 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1697 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 19 0 0
T25 104974 9 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T95 0 11 0 0
T136 0 14 0 0
T144 0 17 0 0
T146 0 1 0 0
T152 0 13 0 0
T239 0 13 0 0
T287 0 42 0 0
T296 0 5 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237025007 1667 0 0
T6 91716 0 0 0
T7 120934 0 0 0
T8 23335 0 0 0
T9 0 7 0 0
T25 104974 23 0 0
T27 88822 0 0 0
T62 60938 0 0 0
T63 205116 0 0 0
T71 246069 0 0 0
T77 260847 0 0 0
T78 120737 0 0 0
T95 0 13 0 0
T136 0 8 0 0
T144 0 3 0 0
T146 0 1 0 0
T152 0 13 0 0
T239 0 14 0 0
T287 0 40 0 0
T296 0 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%