| T477 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2338348987 |
|
|
Sep 18 06:24:13 AM UTC 24 |
Sep 18 06:24:25 AM UTC 24 |
2511283332 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1149878634 |
|
|
Sep 18 06:24:19 AM UTC 24 |
Sep 18 06:24:26 AM UTC 24 |
2118273435 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1860349864 |
|
|
Sep 18 06:24:04 AM UTC 24 |
Sep 18 06:24:26 AM UTC 24 |
11204105055 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2164787034 |
|
|
Sep 18 06:24:24 AM UTC 24 |
Sep 18 06:24:26 AM UTC 24 |
4083289007 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.708686806 |
|
|
Sep 18 06:24:23 AM UTC 24 |
Sep 18 06:24:27 AM UTC 24 |
3079707495 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1982404941 |
|
|
Sep 18 06:23:23 AM UTC 24 |
Sep 18 06:24:27 AM UTC 24 |
41418518109 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.163920398 |
|
|
Sep 18 06:24:19 AM UTC 24 |
Sep 18 06:24:28 AM UTC 24 |
2012584277 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.4204007978 |
|
|
Sep 18 06:24:22 AM UTC 24 |
Sep 18 06:24:28 AM UTC 24 |
2615581316 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3169841609 |
|
|
Sep 18 06:24:22 AM UTC 24 |
Sep 18 06:24:29 AM UTC 24 |
3457944412 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.789021184 |
|
|
Sep 18 06:24:11 AM UTC 24 |
Sep 18 06:24:30 AM UTC 24 |
16283303814 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2584196107 |
|
|
Sep 18 06:24:18 AM UTC 24 |
Sep 18 06:24:31 AM UTC 24 |
3150494744 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.1595710073 |
|
|
Sep 18 06:24:27 AM UTC 24 |
Sep 18 06:24:31 AM UTC 24 |
2133880187 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.170845509 |
|
|
Sep 18 06:24:20 AM UTC 24 |
Sep 18 06:24:32 AM UTC 24 |
2477240656 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3899924154 |
|
|
Sep 18 06:24:21 AM UTC 24 |
Sep 18 06:24:32 AM UTC 24 |
2130505121 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1812833138 |
|
|
Sep 18 06:24:28 AM UTC 24 |
Sep 18 06:24:32 AM UTC 24 |
2127828013 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.314834946 |
|
|
Sep 18 06:24:28 AM UTC 24 |
Sep 18 06:24:33 AM UTC 24 |
3799538111 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.2558601539 |
|
|
Sep 18 06:24:25 AM UTC 24 |
Sep 18 06:24:33 AM UTC 24 |
2833410706 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.2727735249 |
|
|
Sep 18 06:24:22 AM UTC 24 |
Sep 18 06:24:34 AM UTC 24 |
2512594960 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2779981949 |
|
|
Sep 18 06:24:33 AM UTC 24 |
Sep 18 06:24:37 AM UTC 24 |
2132327206 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.1937186350 |
|
|
Sep 18 06:24:28 AM UTC 24 |
Sep 18 06:24:37 AM UTC 24 |
2510524543 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2873014764 |
|
|
Sep 18 06:24:27 AM UTC 24 |
Sep 18 06:24:37 AM UTC 24 |
2012257602 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1576779031 |
|
|
Sep 18 06:24:26 AM UTC 24 |
Sep 18 06:24:37 AM UTC 24 |
7432196552 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.1026227457 |
|
|
Sep 18 06:24:34 AM UTC 24 |
Sep 18 06:24:37 AM UTC 24 |
2196677164 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.753575725 |
|
|
Sep 18 06:24:27 AM UTC 24 |
Sep 18 06:24:38 AM UTC 24 |
2462634236 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3148582467 |
|
|
Sep 18 06:24:34 AM UTC 24 |
Sep 18 06:24:38 AM UTC 24 |
2488196962 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.3344597906 |
|
|
Sep 18 06:24:35 AM UTC 24 |
Sep 18 06:24:39 AM UTC 24 |
2531155160 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1530682284 |
|
|
Sep 18 06:24:31 AM UTC 24 |
Sep 18 06:24:39 AM UTC 24 |
7199499881 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3146555925 |
|
|
Sep 18 06:24:28 AM UTC 24 |
Sep 18 06:24:39 AM UTC 24 |
2613091510 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3608896797 |
|
|
Sep 18 06:24:18 AM UTC 24 |
Sep 18 06:24:40 AM UTC 24 |
38542342119 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.908114454 |
|
|
Sep 18 06:24:32 AM UTC 24 |
Sep 18 06:24:42 AM UTC 24 |
4262327206 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1085310823 |
|
|
Sep 18 06:24:37 AM UTC 24 |
Sep 18 06:24:42 AM UTC 24 |
3300372072 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1997016268 |
|
|
Sep 18 06:24:39 AM UTC 24 |
Sep 18 06:24:42 AM UTC 24 |
2114258876 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.512910302 |
|
|
Sep 18 06:24:33 AM UTC 24 |
Sep 18 06:24:43 AM UTC 24 |
2011742433 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.446751825 |
|
|
Sep 18 06:24:18 AM UTC 24 |
Sep 18 06:24:43 AM UTC 24 |
7674060756 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2708624946 |
|
|
Sep 18 06:23:13 AM UTC 24 |
Sep 18 06:24:43 AM UTC 24 |
76514796057 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3964804356 |
|
|
Sep 18 06:24:35 AM UTC 24 |
Sep 18 06:24:45 AM UTC 24 |
2608646810 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2226531446 |
|
|
Sep 18 06:24:39 AM UTC 24 |
Sep 18 06:24:46 AM UTC 24 |
2119399269 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.3319746470 |
|
|
Sep 18 06:24:44 AM UTC 24 |
Sep 18 06:24:47 AM UTC 24 |
3434808410 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1003599154 |
|
|
Sep 18 06:24:32 AM UTC 24 |
Sep 18 06:24:48 AM UTC 24 |
3978503306 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1094356654 |
|
|
Sep 18 06:24:43 AM UTC 24 |
Sep 18 06:24:49 AM UTC 24 |
3529354730 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2976759774 |
|
|
Sep 18 06:24:39 AM UTC 24 |
Sep 18 06:24:50 AM UTC 24 |
9706998683 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3532418797 |
|
|
Sep 18 06:24:38 AM UTC 24 |
Sep 18 06:24:50 AM UTC 24 |
3583133455 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.819928152 |
|
|
Sep 18 06:24:42 AM UTC 24 |
Sep 18 06:24:50 AM UTC 24 |
2508376408 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.805993245 |
|
|
Sep 18 06:24:44 AM UTC 24 |
Sep 18 06:24:50 AM UTC 24 |
13186552273 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.981191344 |
|
|
Sep 18 06:24:39 AM UTC 24 |
Sep 18 06:24:51 AM UTC 24 |
5951496447 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2406898520 |
|
|
Sep 18 06:24:40 AM UTC 24 |
Sep 18 06:24:52 AM UTC 24 |
2153178609 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.3394668589 |
|
|
Sep 18 06:24:39 AM UTC 24 |
Sep 18 06:24:52 AM UTC 24 |
2463302773 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2860696688 |
|
|
Sep 18 06:24:38 AM UTC 24 |
Sep 18 06:24:53 AM UTC 24 |
8090792658 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.196880481 |
|
|
Sep 18 06:24:43 AM UTC 24 |
Sep 18 06:24:53 AM UTC 24 |
2611725882 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.866650185 |
|
|
Sep 18 06:24:49 AM UTC 24 |
Sep 18 06:24:54 AM UTC 24 |
2124432528 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.4213045614 |
|
|
Sep 18 06:24:50 AM UTC 24 |
Sep 18 06:24:54 AM UTC 24 |
2146937878 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3676404903 |
|
|
Sep 18 06:24:33 AM UTC 24 |
Sep 18 06:24:54 AM UTC 24 |
6541421436 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.138958269 |
|
|
Sep 18 06:24:51 AM UTC 24 |
Sep 18 06:24:55 AM UTC 24 |
2640107963 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.214878596 |
|
|
Sep 18 06:24:27 AM UTC 24 |
Sep 18 06:24:55 AM UTC 24 |
10667722483 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1090765827 |
|
|
Sep 18 06:23:50 AM UTC 24 |
Sep 18 06:24:56 AM UTC 24 |
94592131488 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2508600113 |
|
|
Sep 18 06:22:11 AM UTC 24 |
Sep 18 06:24:56 AM UTC 24 |
1623148066593 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2618677740 |
|
|
Sep 18 06:25:30 AM UTC 24 |
Sep 18 06:25:33 AM UTC 24 |
2054214884 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.489108948 |
|
|
Sep 18 06:23:43 AM UTC 24 |
Sep 18 06:24:57 AM UTC 24 |
79522546836 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.257861052 |
|
|
Sep 18 06:24:54 AM UTC 24 |
Sep 18 06:24:57 AM UTC 24 |
2453158288 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.72538573 |
|
|
Sep 18 06:24:48 AM UTC 24 |
Sep 18 06:24:58 AM UTC 24 |
2011546515 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2329879349 |
|
|
Sep 18 06:24:43 AM UTC 24 |
Sep 18 06:24:58 AM UTC 24 |
3509794511 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2269603514 |
|
|
Sep 18 06:24:53 AM UTC 24 |
Sep 18 06:24:59 AM UTC 24 |
3071854729 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1705006623 |
|
|
Sep 18 06:24:10 AM UTC 24 |
Sep 18 06:24:59 AM UTC 24 |
99130751811 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.777410533 |
|
|
Sep 18 06:24:47 AM UTC 24 |
Sep 18 06:25:00 AM UTC 24 |
5723289378 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.2030794144 |
|
|
Sep 18 06:24:56 AM UTC 24 |
Sep 18 06:25:01 AM UTC 24 |
2034806779 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2204290292 |
|
|
Sep 18 06:24:56 AM UTC 24 |
Sep 18 06:25:01 AM UTC 24 |
2126362301 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1032466837 |
|
|
Sep 18 06:24:59 AM UTC 24 |
Sep 18 06:25:01 AM UTC 24 |
3019194405 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.4070655102 |
|
|
Sep 18 06:24:50 AM UTC 24 |
Sep 18 06:25:02 AM UTC 24 |
2428867125 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3488939892 |
|
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Sep 18 06:24:53 AM UTC 24 |
Sep 18 06:25:02 AM UTC 24 |
11253601828 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3505518358 |
|
|
Sep 18 06:24:58 AM UTC 24 |
Sep 18 06:25:02 AM UTC 24 |
2252629687 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.785380427 |
|
|
Sep 18 06:24:51 AM UTC 24 |
Sep 18 06:25:03 AM UTC 24 |
2514733810 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.760699320 |
|
|
Sep 18 06:24:58 AM UTC 24 |
Sep 18 06:25:03 AM UTC 24 |
2530599368 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.571030670 |
|
|
Sep 18 06:25:00 AM UTC 24 |
Sep 18 06:25:03 AM UTC 24 |
4113129292 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3672831524 |
|
|
Sep 18 06:23:43 AM UTC 24 |
Sep 18 06:25:03 AM UTC 24 |
139459488078 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3621000347 |
|
|
Sep 18 06:24:58 AM UTC 24 |
Sep 18 06:25:05 AM UTC 24 |
2615471831 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.3252137443 |
|
|
Sep 18 06:25:02 AM UTC 24 |
Sep 18 06:25:05 AM UTC 24 |
2185636636 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.4007745071 |
|
|
Sep 18 06:24:55 AM UTC 24 |
Sep 18 06:25:07 AM UTC 24 |
8139924892 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2421488506 |
|
|
Sep 18 06:24:56 AM UTC 24 |
Sep 18 06:25:08 AM UTC 24 |
2462641919 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1108758643 |
|
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Sep 18 06:25:04 AM UTC 24 |
Sep 18 06:25:09 AM UTC 24 |
2622820324 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4065668410 |
|
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Sep 18 06:25:01 AM UTC 24 |
Sep 18 06:25:09 AM UTC 24 |
4720573084 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1187029568 |
|
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Sep 18 06:25:04 AM UTC 24 |
Sep 18 06:25:10 AM UTC 24 |
3407378007 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2566857862 |
|
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Sep 18 06:23:35 AM UTC 24 |
Sep 18 06:25:10 AM UTC 24 |
130760462786 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3696125704 |
|
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Sep 18 06:25:04 AM UTC 24 |
Sep 18 06:25:10 AM UTC 24 |
2953005941 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.3456611669 |
|
|
Sep 18 06:23:33 AM UTC 24 |
Sep 18 06:25:11 AM UTC 24 |
128147276152 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.36029263 |
|
|
Sep 18 06:25:02 AM UTC 24 |
Sep 18 06:25:12 AM UTC 24 |
2016211587 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.1763861615 |
|
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Sep 18 06:25:10 AM UTC 24 |
Sep 18 06:25:13 AM UTC 24 |
2048380991 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1786651855 |
|
|
Sep 18 06:25:02 AM UTC 24 |
Sep 18 06:25:14 AM UTC 24 |
2141612261 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.4096169786 |
|
|
Sep 18 06:25:10 AM UTC 24 |
Sep 18 06:25:14 AM UTC 24 |
2137481960 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2664471355 |
|
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Sep 18 06:24:55 AM UTC 24 |
Sep 18 06:25:14 AM UTC 24 |
15125094800 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.3600382290 |
|
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Sep 18 06:25:02 AM UTC 24 |
Sep 18 06:25:15 AM UTC 24 |
2472604521 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.3007894366 |
|
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Sep 18 06:25:11 AM UTC 24 |
Sep 18 06:25:15 AM UTC 24 |
2464654986 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.4070168515 |
|
|
Sep 18 06:25:04 AM UTC 24 |
Sep 18 06:25:16 AM UTC 24 |
2511863327 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3994506187 |
|
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Sep 18 06:24:59 AM UTC 24 |
Sep 18 06:25:16 AM UTC 24 |
3554767862 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2258615347 |
|
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Sep 18 06:23:28 AM UTC 24 |
Sep 18 06:25:17 AM UTC 24 |
81350993449 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.177910378 |
|
|
Sep 18 06:25:06 AM UTC 24 |
Sep 18 06:25:18 AM UTC 24 |
12614643453 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3838056391 |
|
|
Sep 18 06:25:15 AM UTC 24 |
Sep 18 06:25:18 AM UTC 24 |
3155366304 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.2185757803 |
|
|
Sep 18 06:25:12 AM UTC 24 |
Sep 18 06:25:18 AM UTC 24 |
2511815693 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.3246717232 |
|
|
Sep 18 06:25:08 AM UTC 24 |
Sep 18 06:25:20 AM UTC 24 |
2398802978 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.734365378 |
|
|
Sep 18 06:25:18 AM UTC 24 |
Sep 18 06:25:23 AM UTC 24 |
2481661772 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.1912769576 |
|
|
Sep 18 06:25:01 AM UTC 24 |
Sep 18 06:25:24 AM UTC 24 |
7118105597 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.310635672 |
|
|
Sep 18 06:25:12 AM UTC 24 |
Sep 18 06:25:24 AM UTC 24 |
2117017895 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2827133302 |
|
|
Sep 18 06:25:14 AM UTC 24 |
Sep 18 06:25:25 AM UTC 24 |
2611049826 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.356223595 |
|
|
Sep 18 06:25:10 AM UTC 24 |
Sep 18 06:25:25 AM UTC 24 |
4070001764 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2590429682 |
|
|
Sep 18 06:25:20 AM UTC 24 |
Sep 18 06:25:26 AM UTC 24 |
2149294016 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.2311908401 |
|
|
Sep 18 06:25:18 AM UTC 24 |
Sep 18 06:25:27 AM UTC 24 |
2010642370 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.2747996215 |
|
|
Sep 18 06:25:17 AM UTC 24 |
Sep 18 06:25:28 AM UTC 24 |
12443319678 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1630472758 |
|
|
Sep 18 06:25:16 AM UTC 24 |
Sep 18 06:25:28 AM UTC 24 |
3494324540 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.1196611039 |
|
|
Sep 18 06:25:18 AM UTC 24 |
Sep 18 06:25:29 AM UTC 24 |
2111558893 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.327175847 |
|
|
Sep 18 06:25:26 AM UTC 24 |
Sep 18 06:25:29 AM UTC 24 |
5668634962 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.40643892 |
|
|
Sep 18 06:25:09 AM UTC 24 |
Sep 18 06:25:30 AM UTC 24 |
30096424334 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3916338840 |
|
|
Sep 18 06:25:24 AM UTC 24 |
Sep 18 06:25:31 AM UTC 24 |
2616063167 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.2577331659 |
|
|
Sep 18 06:25:21 AM UTC 24 |
Sep 18 06:25:32 AM UTC 24 |
2511944233 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3032872548 |
|
|
Sep 18 06:25:27 AM UTC 24 |
Sep 18 06:25:32 AM UTC 24 |
2943404570 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3685485046 |
|
|
Sep 18 06:25:17 AM UTC 24 |
Sep 18 06:25:33 AM UTC 24 |
5100062911 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.3834834379 |
|
|
Sep 18 06:24:54 AM UTC 24 |
Sep 18 06:25:34 AM UTC 24 |
55079097437 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2355385292 |
|
|
Sep 18 06:25:30 AM UTC 24 |
Sep 18 06:25:36 AM UTC 24 |
2119541359 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1011868676 |
|
|
Sep 18 06:25:33 AM UTC 24 |
Sep 18 06:25:36 AM UTC 24 |
2644491300 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1710321780 |
|
|
Sep 18 06:25:35 AM UTC 24 |
Sep 18 06:25:38 AM UTC 24 |
3804458217 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.4202071101 |
|
|
Sep 18 06:25:30 AM UTC 24 |
Sep 18 06:25:38 AM UTC 24 |
2444032774 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3724334128 |
|
|
Sep 18 06:25:34 AM UTC 24 |
Sep 18 06:25:39 AM UTC 24 |
3177451838 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.3504948263 |
|
|
Sep 18 06:23:53 AM UTC 24 |
Sep 18 06:25:40 AM UTC 24 |
71059950671 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2919553762 |
|
|
Sep 18 06:25:33 AM UTC 24 |
Sep 18 06:25:40 AM UTC 24 |
2521147610 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4228732074 |
|
|
Sep 18 06:25:15 AM UTC 24 |
Sep 18 06:25:41 AM UTC 24 |
5087600017 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.2477934816 |
|
|
Sep 18 06:25:37 AM UTC 24 |
Sep 18 06:25:41 AM UTC 24 |
4297252209 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.2651047325 |
|
|
Sep 18 06:25:33 AM UTC 24 |
Sep 18 06:25:41 AM UTC 24 |
2189435310 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.2841075993 |
|
|
Sep 18 06:24:17 AM UTC 24 |
Sep 18 06:25:41 AM UTC 24 |
113478350345 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.2026462867 |
|
|
Sep 18 06:24:38 AM UTC 24 |
Sep 18 06:25:42 AM UTC 24 |
84098059560 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.4192800991 |
|
|
Sep 18 06:25:25 AM UTC 24 |
Sep 18 06:25:43 AM UTC 24 |
3406214058 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1561490088 |
|
|
Sep 18 06:25:34 AM UTC 24 |
Sep 18 06:25:44 AM UTC 24 |
4120806280 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2920765036 |
|
|
Sep 18 06:25:00 AM UTC 24 |
Sep 18 06:25:44 AM UTC 24 |
67843561095 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.130086102 |
|
|
Sep 18 06:25:39 AM UTC 24 |
Sep 18 06:25:45 AM UTC 24 |
11026835837 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.1365351759 |
|
|
Sep 18 06:25:42 AM UTC 24 |
Sep 18 06:25:45 AM UTC 24 |
2492874662 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1298588825 |
|
|
Sep 18 06:25:41 AM UTC 24 |
Sep 18 06:25:46 AM UTC 24 |
2136248403 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3446704820 |
|
|
Sep 18 06:25:43 AM UTC 24 |
Sep 18 06:25:46 AM UTC 24 |
2543895382 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.1746798845 |
|
|
Sep 18 06:25:42 AM UTC 24 |
Sep 18 06:25:46 AM UTC 24 |
2159017273 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2825423850 |
|
|
Sep 18 06:25:29 AM UTC 24 |
Sep 18 06:25:46 AM UTC 24 |
7043615570 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3406537404 |
|
|
Sep 18 06:22:35 AM UTC 24 |
Sep 18 06:25:48 AM UTC 24 |
73113976248 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3942931701 |
|
|
Sep 18 06:25:43 AM UTC 24 |
Sep 18 06:25:48 AM UTC 24 |
2620618617 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.3042131654 |
|
|
Sep 18 06:22:51 AM UTC 24 |
Sep 18 06:25:48 AM UTC 24 |
68562138025 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2555134047 |
|
|
Sep 18 06:25:45 AM UTC 24 |
Sep 18 06:25:50 AM UTC 24 |
9367139845 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.141762021 |
|
|
Sep 18 06:25:40 AM UTC 24 |
Sep 18 06:25:50 AM UTC 24 |
2011466907 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.1273744843 |
|
|
Sep 18 06:25:47 AM UTC 24 |
Sep 18 06:25:50 AM UTC 24 |
2043354122 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.206031839 |
|
|
Sep 18 06:25:47 AM UTC 24 |
Sep 18 06:25:50 AM UTC 24 |
2124807127 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1108680514 |
|
|
Sep 18 06:25:43 AM UTC 24 |
Sep 18 06:25:52 AM UTC 24 |
3913486243 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3490236652 |
|
|
Sep 18 06:25:44 AM UTC 24 |
Sep 18 06:25:57 AM UTC 24 |
3438921365 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2640058826 |
|
|
Sep 18 06:25:46 AM UTC 24 |
Sep 18 06:25:58 AM UTC 24 |
12718459828 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.604368080 |
|
|
Sep 18 06:25:46 AM UTC 24 |
Sep 18 06:25:59 AM UTC 24 |
2755129150 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3991221067 |
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Sep 18 06:24:32 AM UTC 24 |
Sep 18 06:26:00 AM UTC 24 |
27080194580 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2223690868 |
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Sep 18 06:25:52 AM UTC 24 |
Sep 18 06:26:00 AM UTC 24 |
3456074593 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.2123479802 |
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Sep 18 06:25:50 AM UTC 24 |
Sep 18 06:26:00 AM UTC 24 |
2179271535 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.1545501908 |
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Sep 18 06:25:50 AM UTC 24 |
Sep 18 06:26:01 AM UTC 24 |
2509155713 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.3363612750 |
|
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Sep 18 06:25:49 AM UTC 24 |
Sep 18 06:26:01 AM UTC 24 |
2451513540 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.551513831 |
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Sep 18 06:24:04 AM UTC 24 |
Sep 18 06:26:04 AM UTC 24 |
161450503307 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2438481002 |
|
|
Sep 18 06:25:51 AM UTC 24 |
Sep 18 06:26:04 AM UTC 24 |
2610545097 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.4246658646 |
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|
Sep 18 06:26:01 AM UTC 24 |
Sep 18 06:26:05 AM UTC 24 |
2039171573 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2809944677 |
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Sep 18 06:26:03 AM UTC 24 |
Sep 18 06:26:05 AM UTC 24 |
2580947372 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.3109598526 |
|
|
Sep 18 06:26:02 AM UTC 24 |
Sep 18 06:26:06 AM UTC 24 |
2498327755 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3903183554 |
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|
Sep 18 06:25:58 AM UTC 24 |
Sep 18 06:26:06 AM UTC 24 |
3544062688 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.2469156760 |
|
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Sep 18 06:26:03 AM UTC 24 |
Sep 18 06:26:07 AM UTC 24 |
2197204991 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.937634000 |
|
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Sep 18 06:25:46 AM UTC 24 |
Sep 18 06:26:07 AM UTC 24 |
9339680708 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.4137086822 |
|
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Sep 18 06:23:58 AM UTC 24 |
Sep 18 06:26:08 AM UTC 24 |
174476009730 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3106455650 |
|
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Sep 18 06:23:18 AM UTC 24 |
Sep 18 06:26:08 AM UTC 24 |
58429875999 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.3793379452 |
|
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Sep 18 06:26:14 AM UTC 24 |
Sep 18 06:26:23 AM UTC 24 |
3042395605 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2539186351 |
|
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Sep 18 06:25:51 AM UTC 24 |
Sep 18 06:26:09 AM UTC 24 |
4063748482 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3718710238 |
|
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Sep 18 06:26:01 AM UTC 24 |
Sep 18 06:26:09 AM UTC 24 |
2109289067 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.3879703745 |
|
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Sep 18 06:25:15 AM UTC 24 |
Sep 18 06:26:09 AM UTC 24 |
67514528138 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.989507870 |
|
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Sep 18 06:26:06 AM UTC 24 |
Sep 18 06:26:09 AM UTC 24 |
2881619809 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2473480655 |
|
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Sep 18 06:25:39 AM UTC 24 |
Sep 18 06:26:11 AM UTC 24 |
530850418497 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2338997391 |
|
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Sep 18 06:26:07 AM UTC 24 |
Sep 18 06:26:11 AM UTC 24 |
3549453922 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.1546849253 |
|
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Sep 18 06:26:07 AM UTC 24 |
Sep 18 06:26:12 AM UTC 24 |
3910608602 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1201627436 |
|
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Sep 18 06:26:10 AM UTC 24 |
Sep 18 06:26:12 AM UTC 24 |
2160085279 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1237305242 |
|
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Sep 18 06:24:55 AM UTC 24 |
Sep 18 06:26:12 AM UTC 24 |
110705487126 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3237425763 |
|
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Sep 18 06:24:31 AM UTC 24 |
Sep 18 06:26:13 AM UTC 24 |
62199584832 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.3750280641 |
|
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Sep 18 06:26:10 AM UTC 24 |
Sep 18 06:26:13 AM UTC 24 |
2102316751 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.3125468027 |
|
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Sep 18 06:26:10 AM UTC 24 |
Sep 18 06:26:14 AM UTC 24 |
2019885403 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.4195605443 |
|
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Sep 18 06:26:06 AM UTC 24 |
Sep 18 06:26:14 AM UTC 24 |
2609868178 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2535556582 |
|
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Sep 18 06:26:10 AM UTC 24 |
Sep 18 06:26:15 AM UTC 24 |
2629476898 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.894954221 |
|
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Sep 18 06:22:43 AM UTC 24 |
Sep 18 06:26:16 AM UTC 24 |
89610138946 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.4189921085 |
|
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Sep 18 06:26:10 AM UTC 24 |
Sep 18 06:26:17 AM UTC 24 |
2511331382 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.115734531 |
|
|
Sep 18 06:26:10 AM UTC 24 |
Sep 18 06:26:17 AM UTC 24 |
2463507906 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.787986082 |
|
|
Sep 18 06:26:17 AM UTC 24 |
Sep 18 06:26:20 AM UTC 24 |
2236985016 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.1553698702 |
|
|
Sep 18 06:26:17 AM UTC 24 |
Sep 18 06:26:20 AM UTC 24 |
2486737154 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.330801037 |
|
|
Sep 18 06:26:15 AM UTC 24 |
Sep 18 06:26:22 AM UTC 24 |
2025968402 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3182596809 |
|
|
Sep 18 06:24:46 AM UTC 24 |
Sep 18 06:26:23 AM UTC 24 |
121093883730 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.658370939 |
|
|
Sep 18 06:26:12 AM UTC 24 |
Sep 18 06:26:24 AM UTC 24 |
2987295135 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.598674266 |
|
|
Sep 18 06:26:12 AM UTC 24 |
Sep 18 06:26:24 AM UTC 24 |
3871873734 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.300960243 |
|
|
Sep 18 06:26:16 AM UTC 24 |
Sep 18 06:26:24 AM UTC 24 |
2107764506 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.354644459 |
|
|
Sep 18 06:26:21 AM UTC 24 |
Sep 18 06:26:25 AM UTC 24 |
3728672759 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.1844471338 |
|
|
Sep 18 06:26:18 AM UTC 24 |
Sep 18 06:26:26 AM UTC 24 |
2520758868 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1061133172 |
|
|
Sep 18 06:26:07 AM UTC 24 |
Sep 18 06:26:28 AM UTC 24 |
9117380820 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2898225455 |
|
|
Sep 18 06:26:01 AM UTC 24 |
Sep 18 06:26:28 AM UTC 24 |
11969577716 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2532568238 |
|
|
Sep 18 06:25:37 AM UTC 24 |
Sep 18 06:26:30 AM UTC 24 |
105102825097 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2000851393 |
|
|
Sep 18 06:24:26 AM UTC 24 |
Sep 18 06:26:30 AM UTC 24 |
248325215263 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2888439307 |
|
|
Sep 18 06:25:46 AM UTC 24 |
Sep 18 06:26:30 AM UTC 24 |
63315795245 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.3663553374 |
|
|
Sep 18 06:26:27 AM UTC 24 |
Sep 18 06:26:32 AM UTC 24 |
2479831141 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3815235621 |
|
|
Sep 18 06:26:15 AM UTC 24 |
Sep 18 06:26:32 AM UTC 24 |
8567279879 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.4167701499 |
|
|
Sep 18 06:26:18 AM UTC 24 |
Sep 18 06:26:32 AM UTC 24 |
2610773136 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.3736562837 |
|
|
Sep 18 06:26:23 AM UTC 24 |
Sep 18 06:26:32 AM UTC 24 |
3524785793 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1816880349 |
|
|
Sep 18 06:26:21 AM UTC 24 |
Sep 18 06:26:33 AM UTC 24 |
3369883950 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2296772627 |
|
|
Sep 18 06:26:29 AM UTC 24 |
Sep 18 06:26:34 AM UTC 24 |
2150806378 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.1845723422 |
|
|
Sep 18 06:26:30 AM UTC 24 |
Sep 18 06:26:35 AM UTC 24 |
2519253631 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.481667757 |
|
|
Sep 18 06:26:25 AM UTC 24 |
Sep 18 06:26:35 AM UTC 24 |
13327114120 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.730170324 |
|
|
Sep 18 06:26:27 AM UTC 24 |
Sep 18 06:26:35 AM UTC 24 |
2109884930 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.914605998 |
|
|
Sep 18 06:26:25 AM UTC 24 |
Sep 18 06:26:36 AM UTC 24 |
2017212150 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3175020822 |
|
|
Sep 18 06:24:31 AM UTC 24 |
Sep 18 06:26:36 AM UTC 24 |
80864258623 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1790208479 |
|
|
Sep 18 06:24:48 AM UTC 24 |
Sep 18 06:26:37 AM UTC 24 |
157015797870 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2234662599 |
|
|
Sep 18 06:26:24 AM UTC 24 |
Sep 18 06:26:38 AM UTC 24 |
14066604925 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.784079025 |
|
|
Sep 18 06:26:31 AM UTC 24 |
Sep 18 06:26:38 AM UTC 24 |
2617562587 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3225138466 |
|
|
Sep 18 06:26:37 AM UTC 24 |
Sep 18 06:26:41 AM UTC 24 |
2474981523 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1876867931 |
|
|
Sep 18 06:26:24 AM UTC 24 |
Sep 18 06:26:41 AM UTC 24 |
26460698704 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.579397641 |
|
|
Sep 18 06:26:37 AM UTC 24 |
Sep 18 06:26:41 AM UTC 24 |
2185915656 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.3723235665 |
|
|
Sep 18 06:26:35 AM UTC 24 |
Sep 18 06:26:42 AM UTC 24 |
2012104895 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1174329030 |
|
|
Sep 18 06:26:15 AM UTC 24 |
Sep 18 06:26:42 AM UTC 24 |
17421646203 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.3451734566 |
|
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Sep 18 06:25:10 AM UTC 24 |
Sep 18 06:26:43 AM UTC 24 |
61111931758 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3482224235 |
|
|
Sep 18 06:26:39 AM UTC 24 |
Sep 18 06:26:43 AM UTC 24 |
3036091096 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.546824105 |
|
|
Sep 18 06:26:32 AM UTC 24 |
Sep 18 06:26:44 AM UTC 24 |
6285650561 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.318039436 |
|
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Sep 18 06:26:38 AM UTC 24 |
Sep 18 06:26:44 AM UTC 24 |
2618952080 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.3974915192 |
|
|
Sep 18 06:26:38 AM UTC 24 |
Sep 18 06:26:44 AM UTC 24 |
2515805850 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3764918276 |
|
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Sep 18 06:26:41 AM UTC 24 |
Sep 18 06:26:45 AM UTC 24 |
8637880479 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3087133418 |
|
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Sep 18 06:26:32 AM UTC 24 |
Sep 18 06:26:45 AM UTC 24 |
2994014445 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3726712233 |
|
|
Sep 18 06:26:23 AM UTC 24 |
Sep 18 06:26:46 AM UTC 24 |
150497237013 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3080431224 |
|
|
Sep 18 06:26:33 AM UTC 24 |
Sep 18 06:26:47 AM UTC 24 |
31277064688 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.980907945 |
|
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Sep 18 06:26:37 AM UTC 24 |
Sep 18 06:26:47 AM UTC 24 |
2110941769 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3952981190 |
|
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Sep 18 06:26:32 AM UTC 24 |
Sep 18 06:26:48 AM UTC 24 |
9993517493 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.2920526931 |
|
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Sep 18 06:23:37 AM UTC 24 |
Sep 18 06:26:49 AM UTC 24 |
55744481889 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3362027443 |
|
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Sep 18 06:26:46 AM UTC 24 |
Sep 18 06:26:50 AM UTC 24 |
2184538998 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.3638728712 |
|
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Sep 18 06:26:46 AM UTC 24 |
Sep 18 06:26:51 AM UTC 24 |
2525705830 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.4243369357 |
|
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Sep 18 06:26:43 AM UTC 24 |
Sep 18 06:26:51 AM UTC 24 |
2016269718 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3410790867 |
|
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Sep 18 06:26:46 AM UTC 24 |
Sep 18 06:26:51 AM UTC 24 |
2623757730 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1616087269 |
|
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Sep 18 06:25:39 AM UTC 24 |
Sep 18 06:26:52 AM UTC 24 |
28584948469 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3862177865 |
|
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Sep 18 06:26:42 AM UTC 24 |
Sep 18 06:26:53 AM UTC 24 |
4632701790 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.298735168 |
|
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Sep 18 06:26:48 AM UTC 24 |
Sep 18 06:26:53 AM UTC 24 |
3209736939 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2977756552 |
|
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Sep 18 06:26:48 AM UTC 24 |
Sep 18 06:26:53 AM UTC 24 |
6355116937 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2830118786 |
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Sep 18 06:23:07 AM UTC 24 |
Sep 18 06:26:53 AM UTC 24 |
78294153274 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.4083563796 |
|
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Sep 18 06:26:47 AM UTC 24 |
Sep 18 06:26:54 AM UTC 24 |
4775086664 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.3955897587 |
|
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Sep 18 06:26:46 AM UTC 24 |
Sep 18 06:26:55 AM UTC 24 |
2110302683 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2463886383 |
|
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Sep 18 06:26:39 AM UTC 24 |
Sep 18 06:26:55 AM UTC 24 |
5332667840 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.3360925049 |
|
|
Sep 18 06:27:01 AM UTC 24 |
Sep 18 06:27:05 AM UTC 24 |
2131567007 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.3216472119 |
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|
Sep 18 06:25:29 AM UTC 24 |
Sep 18 06:26:55 AM UTC 24 |
224713399464 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.1859536019 |
|
|
Sep 18 06:26:50 AM UTC 24 |
Sep 18 06:26:56 AM UTC 24 |
6251049532 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1431517712 |
|
|
Sep 18 06:23:19 AM UTC 24 |
Sep 18 06:26:56 AM UTC 24 |
67477392041 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.504412237 |
|
|
Sep 18 06:26:46 AM UTC 24 |
Sep 18 06:26:56 AM UTC 24 |
2460283271 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.1738889319 |
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|
Sep 18 06:26:43 AM UTC 24 |
Sep 18 06:26:58 AM UTC 24 |
14262419043 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2709093289 |
|
|
Sep 18 06:26:54 AM UTC 24 |
Sep 18 06:26:59 AM UTC 24 |
2260943801 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.17813163 |
|
|
Sep 18 06:26:43 AM UTC 24 |
Sep 18 06:26:59 AM UTC 24 |
8445413448 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2766657885 |
|
|
Sep 18 06:26:52 AM UTC 24 |
Sep 18 06:27:00 AM UTC 24 |
2014431671 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1211961899 |
|
|
Sep 18 06:26:55 AM UTC 24 |
Sep 18 06:27:00 AM UTC 24 |
3019254859 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.590736917 |
|
|
Sep 18 06:26:56 AM UTC 24 |
Sep 18 06:27:01 AM UTC 24 |
9581417850 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.548220158 |
|
|
Sep 18 06:26:43 AM UTC 24 |
Sep 18 06:27:01 AM UTC 24 |
21354079384 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.568218180 |
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Sep 18 06:26:54 AM UTC 24 |
Sep 18 06:27:01 AM UTC 24 |
2520009844 ps |