| T644 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3600547142 |
|
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Sep 18 06:26:54 AM UTC 24 |
Sep 18 06:27:03 AM UTC 24 |
2469375913 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2182960167 |
|
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Sep 18 06:26:53 AM UTC 24 |
Sep 18 06:27:04 AM UTC 24 |
2109378924 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.812777174 |
|
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Sep 18 06:26:59 AM UTC 24 |
Sep 18 06:27:04 AM UTC 24 |
2038646428 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.1785985725 |
|
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Sep 18 06:26:57 AM UTC 24 |
Sep 18 06:27:04 AM UTC 24 |
3321287075 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3910197915 |
|
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Sep 18 06:26:54 AM UTC 24 |
Sep 18 06:27:05 AM UTC 24 |
2612414350 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.4169417228 |
|
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Sep 18 06:27:01 AM UTC 24 |
Sep 18 06:27:05 AM UTC 24 |
2142604314 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3927871458 |
|
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Sep 18 06:27:37 AM UTC 24 |
Sep 18 06:27:49 AM UTC 24 |
9302177793 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2295761474 |
|
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Sep 18 06:26:56 AM UTC 24 |
Sep 18 06:27:05 AM UTC 24 |
3007170272 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.2615079223 |
|
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Sep 18 06:22:35 AM UTC 24 |
Sep 18 06:27:07 AM UTC 24 |
82632578711 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1810285328 |
|
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Sep 18 06:27:02 AM UTC 24 |
Sep 18 06:27:08 AM UTC 24 |
2615789988 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2282595619 |
|
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Sep 18 06:27:06 AM UTC 24 |
Sep 18 06:27:09 AM UTC 24 |
2060479984 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.199670155 |
|
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Sep 18 06:26:14 AM UTC 24 |
Sep 18 06:27:10 AM UTC 24 |
83385780022 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.310264213 |
|
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Sep 18 06:27:04 AM UTC 24 |
Sep 18 06:27:10 AM UTC 24 |
3205529715 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.285929659 |
|
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Sep 18 06:27:06 AM UTC 24 |
Sep 18 06:27:11 AM UTC 24 |
2133269968 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1222033883 |
|
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Sep 18 06:27:02 AM UTC 24 |
Sep 18 06:27:11 AM UTC 24 |
2509661153 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.528473811 |
|
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Sep 18 06:26:07 AM UTC 24 |
Sep 18 06:27:11 AM UTC 24 |
104523338445 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.4143110631 |
|
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Sep 18 06:27:02 AM UTC 24 |
Sep 18 06:27:11 AM UTC 24 |
4114955601 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.1424976322 |
|
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Sep 18 06:27:05 AM UTC 24 |
Sep 18 06:27:12 AM UTC 24 |
2791065803 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.987467586 |
|
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Sep 18 06:27:07 AM UTC 24 |
Sep 18 06:27:13 AM UTC 24 |
2482134762 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3681110691 |
|
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Sep 18 06:26:51 AM UTC 24 |
Sep 18 06:27:13 AM UTC 24 |
6479355182 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.1519644600 |
|
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Sep 18 06:27:01 AM UTC 24 |
Sep 18 06:27:14 AM UTC 24 |
2445244224 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2452346613 |
|
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Sep 18 06:25:59 AM UTC 24 |
Sep 18 06:27:14 AM UTC 24 |
113893253312 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2348829082 |
|
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Sep 18 06:23:01 AM UTC 24 |
Sep 18 06:27:14 AM UTC 24 |
79868089275 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1787225548 |
|
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Sep 18 06:25:16 AM UTC 24 |
Sep 18 06:27:15 AM UTC 24 |
83711121221 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3004878339 |
|
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Sep 18 06:27:05 AM UTC 24 |
Sep 18 06:27:15 AM UTC 24 |
3195164681 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.841240592 |
|
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Sep 18 06:27:09 AM UTC 24 |
Sep 18 06:27:16 AM UTC 24 |
2055928334 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.3045528366 |
|
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Sep 18 06:26:58 AM UTC 24 |
Sep 18 06:27:18 AM UTC 24 |
10090814832 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.379870979 |
|
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Sep 18 06:27:10 AM UTC 24 |
Sep 18 06:27:18 AM UTC 24 |
2511385863 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.221538201 |
|
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Sep 18 06:27:16 AM UTC 24 |
Sep 18 06:27:18 AM UTC 24 |
2344915334 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.120772042 |
|
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Sep 18 06:27:14 AM UTC 24 |
Sep 18 06:27:19 AM UTC 24 |
2039559598 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2550705094 |
|
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Sep 18 06:27:16 AM UTC 24 |
Sep 18 06:27:20 AM UTC 24 |
2460044842 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1526208179 |
|
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Sep 18 06:27:12 AM UTC 24 |
Sep 18 06:27:21 AM UTC 24 |
2817909800 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.34677420 |
|
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Sep 18 06:27:14 AM UTC 24 |
Sep 18 06:27:21 AM UTC 24 |
2119590964 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1021351668 |
|
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Sep 18 06:27:19 AM UTC 24 |
Sep 18 06:27:21 AM UTC 24 |
3545696908 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.4162328011 |
|
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Sep 18 06:27:14 AM UTC 24 |
Sep 18 06:27:22 AM UTC 24 |
6789680130 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.4041450547 |
|
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Sep 18 06:27:17 AM UTC 24 |
Sep 18 06:27:22 AM UTC 24 |
2628319894 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1643968324 |
|
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Sep 18 06:27:12 AM UTC 24 |
Sep 18 06:27:22 AM UTC 24 |
6423311392 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1897153700 |
|
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Sep 18 06:24:03 AM UTC 24 |
Sep 18 06:27:23 AM UTC 24 |
2381724073074 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.3358218289 |
|
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Sep 18 06:27:45 AM UTC 24 |
Sep 18 06:27:51 AM UTC 24 |
3285507090 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.997325876 |
|
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Sep 18 06:27:11 AM UTC 24 |
Sep 18 06:27:23 AM UTC 24 |
2897051937 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3280144425 |
|
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Sep 18 06:27:05 AM UTC 24 |
Sep 18 06:27:23 AM UTC 24 |
4157888946 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1624913860 |
|
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Sep 18 06:27:19 AM UTC 24 |
Sep 18 06:27:23 AM UTC 24 |
15035037911 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2038037427 |
|
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Sep 18 06:27:11 AM UTC 24 |
Sep 18 06:27:24 AM UTC 24 |
2612776047 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3565782345 |
|
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Sep 18 06:27:19 AM UTC 24 |
Sep 18 06:27:24 AM UTC 24 |
3176484706 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.1171712908 |
|
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Sep 18 06:27:21 AM UTC 24 |
Sep 18 06:27:24 AM UTC 24 |
3165262174 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.36914944 |
|
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Sep 18 06:26:56 AM UTC 24 |
Sep 18 06:27:24 AM UTC 24 |
48620778238 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.866025557 |
|
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Sep 18 06:26:49 AM UTC 24 |
Sep 18 06:27:26 AM UTC 24 |
47151791484 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.3329031636 |
|
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Sep 18 06:27:24 AM UTC 24 |
Sep 18 06:27:26 AM UTC 24 |
2065919899 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.734506943 |
|
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Sep 18 06:27:12 AM UTC 24 |
Sep 18 06:27:27 AM UTC 24 |
3738069701 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.249159313 |
|
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Sep 18 06:27:22 AM UTC 24 |
Sep 18 06:27:28 AM UTC 24 |
2013160719 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.137727426 |
|
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Sep 18 06:27:24 AM UTC 24 |
Sep 18 06:27:28 AM UTC 24 |
2622408432 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.848817301 |
|
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Sep 18 06:27:17 AM UTC 24 |
Sep 18 06:27:28 AM UTC 24 |
2513733640 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.414365485 |
|
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Sep 18 06:27:24 AM UTC 24 |
Sep 18 06:27:28 AM UTC 24 |
2538421907 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.1071907258 |
|
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Sep 18 06:27:22 AM UTC 24 |
Sep 18 06:27:30 AM UTC 24 |
2111345724 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.391905459 |
|
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Sep 18 06:27:25 AM UTC 24 |
Sep 18 06:27:30 AM UTC 24 |
3315723388 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.1548931203 |
|
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Sep 18 06:25:53 AM UTC 24 |
Sep 18 06:27:31 AM UTC 24 |
137416400006 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3006346701 |
|
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Sep 18 06:27:29 AM UTC 24 |
Sep 18 06:27:32 AM UTC 24 |
2538146711 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1836699790 |
|
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Sep 18 06:27:24 AM UTC 24 |
Sep 18 06:27:35 AM UTC 24 |
2466426769 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.4221717371 |
|
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Sep 18 06:27:28 AM UTC 24 |
Sep 18 06:27:35 AM UTC 24 |
2013589411 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2239171798 |
|
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Sep 18 06:27:24 AM UTC 24 |
Sep 18 06:27:36 AM UTC 24 |
4217156577 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.2017338042 |
|
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Sep 18 06:23:13 AM UTC 24 |
Sep 18 06:27:36 AM UTC 24 |
167783787445 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2216084086 |
|
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Sep 18 06:27:29 AM UTC 24 |
Sep 18 06:27:36 AM UTC 24 |
2114192101 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.208438614 |
|
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Sep 18 06:27:13 AM UTC 24 |
Sep 18 06:27:36 AM UTC 24 |
4960861371 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1096065835 |
|
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Sep 18 06:27:32 AM UTC 24 |
Sep 18 06:27:37 AM UTC 24 |
2635564905 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1368591130 |
|
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Sep 18 06:27:22 AM UTC 24 |
Sep 18 06:27:38 AM UTC 24 |
21775650074 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2293923283 |
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Sep 18 06:26:32 AM UTC 24 |
Sep 18 06:27:39 AM UTC 24 |
42163795670 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2843165672 |
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Sep 18 06:22:44 AM UTC 24 |
Sep 18 06:27:39 AM UTC 24 |
97109710988 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.360554306 |
|
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Sep 18 06:27:30 AM UTC 24 |
Sep 18 06:27:39 AM UTC 24 |
2198861364 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.3255335910 |
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Sep 18 06:27:37 AM UTC 24 |
Sep 18 06:27:41 AM UTC 24 |
2038383934 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.3197199309 |
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Sep 18 06:27:25 AM UTC 24 |
Sep 18 06:27:42 AM UTC 24 |
5467522385 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.1434717383 |
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Sep 18 06:27:31 AM UTC 24 |
Sep 18 06:27:43 AM UTC 24 |
2509407161 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3403939040 |
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Sep 18 06:27:37 AM UTC 24 |
Sep 18 06:27:43 AM UTC 24 |
4466683709 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.907020689 |
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Sep 18 06:27:41 AM UTC 24 |
Sep 18 06:27:44 AM UTC 24 |
2536615857 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.2691987842 |
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Sep 18 06:27:39 AM UTC 24 |
Sep 18 06:27:44 AM UTC 24 |
2122828309 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.2731125092 |
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Sep 18 06:27:28 AM UTC 24 |
Sep 18 06:27:46 AM UTC 24 |
13968020405 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.1310714690 |
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Sep 18 06:27:39 AM UTC 24 |
Sep 18 06:27:49 AM UTC 24 |
2449979044 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2922157250 |
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Sep 18 06:27:44 AM UTC 24 |
Sep 18 06:27:49 AM UTC 24 |
5204805778 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2874396212 |
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Sep 18 06:27:42 AM UTC 24 |
Sep 18 06:27:49 AM UTC 24 |
2618365813 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3904110701 |
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Sep 18 06:27:39 AM UTC 24 |
Sep 18 06:27:51 AM UTC 24 |
2099270385 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1294572988 |
|
|
Sep 18 06:27:32 AM UTC 24 |
Sep 18 06:27:52 AM UTC 24 |
4389070065 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2367285608 |
|
|
Sep 18 06:27:37 AM UTC 24 |
Sep 18 06:27:54 AM UTC 24 |
21459081464 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.3529856949 |
|
|
Sep 18 06:27:50 AM UTC 24 |
Sep 18 06:27:54 AM UTC 24 |
2137288030 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.801591780 |
|
|
Sep 18 06:27:51 AM UTC 24 |
Sep 18 06:27:55 AM UTC 24 |
2485620054 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2516518585 |
|
|
Sep 18 06:27:27 AM UTC 24 |
Sep 18 06:27:55 AM UTC 24 |
5426736667 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.556297298 |
|
|
Sep 18 06:27:53 AM UTC 24 |
Sep 18 06:27:57 AM UTC 24 |
2527769262 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2089362687 |
|
|
Sep 18 06:26:57 AM UTC 24 |
Sep 18 06:27:58 AM UTC 24 |
57992165687 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.579032482 |
|
|
Sep 18 06:24:14 AM UTC 24 |
Sep 18 06:27:58 AM UTC 24 |
252163011389 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2830909826 |
|
|
Sep 18 06:27:55 AM UTC 24 |
Sep 18 06:27:59 AM UTC 24 |
2626551951 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.2136960591 |
|
|
Sep 18 06:25:26 AM UTC 24 |
Sep 18 06:27:59 AM UTC 24 |
156549824061 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.3045907462 |
|
|
Sep 18 06:22:36 AM UTC 24 |
Sep 18 06:31:33 AM UTC 24 |
1559244810066 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.937864679 |
|
|
Sep 18 06:27:56 AM UTC 24 |
Sep 18 06:27:59 AM UTC 24 |
3924399774 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.58410347 |
|
|
Sep 18 06:27:05 AM UTC 24 |
Sep 18 06:27:59 AM UTC 24 |
110221084075 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1143192064 |
|
|
Sep 18 06:27:44 AM UTC 24 |
Sep 18 06:28:00 AM UTC 24 |
3328975852 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.4105101117 |
|
|
Sep 18 06:27:37 AM UTC 24 |
Sep 18 06:28:00 AM UTC 24 |
46259060652 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.3236084701 |
|
|
Sep 18 06:27:53 AM UTC 24 |
Sep 18 06:28:01 AM UTC 24 |
2133699503 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1714457838 |
|
|
Sep 18 06:27:50 AM UTC 24 |
Sep 18 06:28:02 AM UTC 24 |
2011476793 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.1607967427 |
|
|
Sep 18 06:28:01 AM UTC 24 |
Sep 18 06:28:03 AM UTC 24 |
2177501905 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.413058231 |
|
|
Sep 18 06:28:00 AM UTC 24 |
Sep 18 06:28:03 AM UTC 24 |
2077641355 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.1707823699 |
|
|
Sep 18 06:28:01 AM UTC 24 |
Sep 18 06:28:05 AM UTC 24 |
2149148975 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.3288707856 |
|
|
Sep 18 06:28:01 AM UTC 24 |
Sep 18 06:28:05 AM UTC 24 |
2498644406 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.1920534978 |
|
|
Sep 18 06:28:01 AM UTC 24 |
Sep 18 06:28:07 AM UTC 24 |
2515702030 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3965696399 |
|
|
Sep 18 06:27:55 AM UTC 24 |
Sep 18 06:28:08 AM UTC 24 |
3453719963 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.72639708 |
|
|
Sep 18 06:27:43 AM UTC 24 |
Sep 18 06:28:09 AM UTC 24 |
4410440194 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2456934918 |
|
|
Sep 18 06:27:59 AM UTC 24 |
Sep 18 06:28:11 AM UTC 24 |
6336345863 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3719447770 |
|
|
Sep 18 06:27:49 AM UTC 24 |
Sep 18 06:28:11 AM UTC 24 |
4419705299 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.4281801801 |
|
|
Sep 18 06:26:32 AM UTC 24 |
Sep 18 06:28:11 AM UTC 24 |
108196591396 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2360275068 |
|
|
Sep 18 06:27:59 AM UTC 24 |
Sep 18 06:28:12 AM UTC 24 |
2550182650 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.616901313 |
|
|
Sep 18 06:26:14 AM UTC 24 |
Sep 18 06:28:13 AM UTC 24 |
35970655050 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1979706126 |
|
|
Sep 18 06:28:02 AM UTC 24 |
Sep 18 06:28:14 AM UTC 24 |
2610225998 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3853299928 |
|
|
Sep 18 06:28:04 AM UTC 24 |
Sep 18 06:28:14 AM UTC 24 |
4069228004 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3435066608 |
|
|
Sep 18 06:28:04 AM UTC 24 |
Sep 18 06:28:15 AM UTC 24 |
3636784302 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3292144487 |
|
|
Sep 18 06:28:11 AM UTC 24 |
Sep 18 06:28:16 AM UTC 24 |
2040762460 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.987350385 |
|
|
Sep 18 06:28:12 AM UTC 24 |
Sep 18 06:28:16 AM UTC 24 |
2482301267 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.92968510 |
|
|
Sep 18 06:28:12 AM UTC 24 |
Sep 18 06:28:16 AM UTC 24 |
2133040356 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.3226614056 |
|
|
Sep 18 06:25:00 AM UTC 24 |
Sep 18 06:28:18 AM UTC 24 |
130296772577 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.800411224 |
|
|
Sep 18 06:28:14 AM UTC 24 |
Sep 18 06:28:18 AM UTC 24 |
2266426081 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.3395506069 |
|
|
Sep 18 06:28:15 AM UTC 24 |
Sep 18 06:28:19 AM UTC 24 |
2527415031 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.375804339 |
|
|
Sep 18 06:28:06 AM UTC 24 |
Sep 18 06:28:20 AM UTC 24 |
3359735583 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.117292065 |
|
|
Sep 18 06:27:36 AM UTC 24 |
Sep 18 06:28:21 AM UTC 24 |
29883821794 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1191993740 |
|
|
Sep 18 06:27:59 AM UTC 24 |
Sep 18 06:28:21 AM UTC 24 |
11032795382 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2625925195 |
|
|
Sep 18 06:28:03 AM UTC 24 |
Sep 18 06:28:22 AM UTC 24 |
4266752475 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.635132147 |
|
|
Sep 18 06:25:27 AM UTC 24 |
Sep 18 06:28:22 AM UTC 24 |
111503461360 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.4007759689 |
|
|
Sep 18 06:28:16 AM UTC 24 |
Sep 18 06:28:22 AM UTC 24 |
3576506503 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3947799064 |
|
|
Sep 18 06:28:15 AM UTC 24 |
Sep 18 06:28:23 AM UTC 24 |
2616645563 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.4026548306 |
|
|
Sep 18 06:28:20 AM UTC 24 |
Sep 18 06:28:25 AM UTC 24 |
2043438357 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2699631457 |
|
|
Sep 18 06:28:23 AM UTC 24 |
Sep 18 06:28:26 AM UTC 24 |
2716820981 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3891525660 |
|
|
Sep 18 06:28:23 AM UTC 24 |
Sep 18 06:28:27 AM UTC 24 |
2524613679 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.1403536393 |
|
|
Sep 18 06:28:23 AM UTC 24 |
Sep 18 06:28:27 AM UTC 24 |
2262794778 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.2531029893 |
|
|
Sep 18 06:28:23 AM UTC 24 |
Sep 18 06:28:28 AM UTC 24 |
2472779160 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2689683301 |
|
|
Sep 18 06:28:19 AM UTC 24 |
Sep 18 06:28:29 AM UTC 24 |
6419349050 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3397959986 |
|
|
Sep 18 06:28:16 AM UTC 24 |
Sep 18 06:28:29 AM UTC 24 |
4989887324 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2506658908 |
|
|
Sep 18 06:28:09 AM UTC 24 |
Sep 18 06:28:29 AM UTC 24 |
6943416962 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.4199726172 |
|
|
Sep 18 06:28:17 AM UTC 24 |
Sep 18 06:28:29 AM UTC 24 |
3510375966 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.713629267 |
|
|
Sep 18 06:26:10 AM UTC 24 |
Sep 18 06:28:29 AM UTC 24 |
102443469560 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3855391198 |
|
|
Sep 18 06:27:33 AM UTC 24 |
Sep 18 06:28:29 AM UTC 24 |
67243352497 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.480352612 |
|
|
Sep 18 06:28:21 AM UTC 24 |
Sep 18 06:28:30 AM UTC 24 |
2114127348 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1931316870 |
|
|
Sep 18 06:28:24 AM UTC 24 |
Sep 18 06:28:30 AM UTC 24 |
3353253396 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2985832936 |
|
|
Sep 18 06:28:26 AM UTC 24 |
Sep 18 06:28:32 AM UTC 24 |
3529739095 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.2183703797 |
|
|
Sep 18 06:28:28 AM UTC 24 |
Sep 18 06:28:33 AM UTC 24 |
3295241721 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.3981948563 |
|
|
Sep 18 06:28:31 AM UTC 24 |
Sep 18 06:28:33 AM UTC 24 |
2207171297 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2341960830 |
|
|
Sep 18 06:28:31 AM UTC 24 |
Sep 18 06:28:34 AM UTC 24 |
2641844422 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3974676364 |
|
|
Sep 18 06:25:06 AM UTC 24 |
Sep 18 06:31:28 AM UTC 24 |
150253549330 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.195227700 |
|
|
Sep 18 06:28:31 AM UTC 24 |
Sep 18 06:28:34 AM UTC 24 |
2468539274 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3075436797 |
|
|
Sep 18 06:28:29 AM UTC 24 |
Sep 18 06:28:35 AM UTC 24 |
2022820323 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.1698741932 |
|
|
Sep 18 06:28:31 AM UTC 24 |
Sep 18 06:28:35 AM UTC 24 |
2127203122 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2067057448 |
|
|
Sep 18 06:26:07 AM UTC 24 |
Sep 18 06:28:37 AM UTC 24 |
153255918143 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.1952361625 |
|
|
Sep 18 06:28:35 AM UTC 24 |
Sep 18 06:28:38 AM UTC 24 |
4222301943 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1680203931 |
|
|
Sep 18 06:28:34 AM UTC 24 |
Sep 18 06:28:38 AM UTC 24 |
3217738652 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4063597911 |
|
|
Sep 18 06:26:51 AM UTC 24 |
Sep 18 06:28:39 AM UTC 24 |
129587257365 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3725020983 |
|
|
Sep 18 06:28:19 AM UTC 24 |
Sep 18 06:28:39 AM UTC 24 |
27849315791 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.2004892890 |
|
|
Sep 18 06:27:06 AM UTC 24 |
Sep 18 06:31:24 AM UTC 24 |
147531579878 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3969667193 |
|
|
Sep 18 06:28:27 AM UTC 24 |
Sep 18 06:28:40 AM UTC 24 |
6405523736 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3460829207 |
|
|
Sep 18 06:28:33 AM UTC 24 |
Sep 18 06:28:41 AM UTC 24 |
2553017601 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.4244005398 |
|
|
Sep 18 06:28:10 AM UTC 24 |
Sep 18 06:28:41 AM UTC 24 |
94574968435 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.1640490259 |
|
|
Sep 18 06:27:58 AM UTC 24 |
Sep 18 06:28:42 AM UTC 24 |
43552480675 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3330362626 |
|
|
Sep 18 06:26:42 AM UTC 24 |
Sep 18 06:28:42 AM UTC 24 |
46263320143 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.89524474 |
|
|
Sep 18 06:26:07 AM UTC 24 |
Sep 18 06:28:43 AM UTC 24 |
778196878105 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1023648259 |
|
|
Sep 18 06:25:15 AM UTC 24 |
Sep 18 06:28:43 AM UTC 24 |
2832297487274 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3731332399 |
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Sep 18 06:28:34 AM UTC 24 |
Sep 18 06:28:44 AM UTC 24 |
13595029528 ps |
| T363 |
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Sep 18 06:26:35 AM UTC 24 |
Sep 18 06:31:26 AM UTC 24 |
214339658253 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1695141910 |
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Sep 18 06:27:59 AM UTC 24 |
Sep 18 06:28:45 AM UTC 24 |
60180135731 ps |
| T759 |
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Sep 18 06:28:35 AM UTC 24 |
Sep 18 06:28:45 AM UTC 24 |
11075893267 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.656717492 |
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Sep 18 06:28:36 AM UTC 24 |
Sep 18 06:28:48 AM UTC 24 |
12871205950 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.3862252747 |
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Sep 18 06:28:31 AM UTC 24 |
Sep 18 06:28:48 AM UTC 24 |
2512511145 ps |
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Sep 18 06:28:37 AM UTC 24 |
Sep 18 06:28:48 AM UTC 24 |
2010933619 ps |
| T385 |
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Sep 18 06:27:22 AM UTC 24 |
Sep 18 06:28:51 AM UTC 24 |
41125561730 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.1583526849 |
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Sep 18 06:28:29 AM UTC 24 |
Sep 18 06:28:51 AM UTC 24 |
15389719478 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.33788771 |
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Sep 18 06:28:20 AM UTC 24 |
Sep 18 06:28:51 AM UTC 24 |
16004449322 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.3106845925 |
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Sep 18 06:28:05 AM UTC 24 |
Sep 18 06:28:56 AM UTC 24 |
109722758126 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3716330262 |
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Sep 18 06:24:10 AM UTC 24 |
Sep 18 06:28:57 AM UTC 24 |
193688951591 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.4122452426 |
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Sep 18 06:28:40 AM UTC 24 |
Sep 18 06:28:59 AM UTC 24 |
56933764804 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.599550094 |
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Sep 18 06:28:49 AM UTC 24 |
Sep 18 06:29:03 AM UTC 24 |
28607076802 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1584169693 |
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Sep 18 06:27:13 AM UTC 24 |
Sep 18 06:29:03 AM UTC 24 |
41823385647 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.171275080 |
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Sep 18 06:23:01 AM UTC 24 |
Sep 18 06:29:11 AM UTC 24 |
177970100183 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.563826887 |
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Sep 18 06:27:49 AM UTC 24 |
Sep 18 06:29:12 AM UTC 24 |
77116320602 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.1131304448 |
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Sep 18 06:27:05 AM UTC 24 |
Sep 18 06:29:13 AM UTC 24 |
144496303438 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.93759139 |
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Sep 18 06:27:12 AM UTC 24 |
Sep 18 06:29:13 AM UTC 24 |
33231388133 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3713428451 |
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Sep 18 06:23:58 AM UTC 24 |
Sep 18 06:29:20 AM UTC 24 |
113292513543 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3077697439 |
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Sep 18 06:28:43 AM UTC 24 |
Sep 18 06:29:25 AM UTC 24 |
32928456451 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4288645384 |
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Sep 18 06:29:05 AM UTC 24 |
Sep 18 06:29:26 AM UTC 24 |
25449134427 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2189953212 |
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Sep 18 06:28:29 AM UTC 24 |
Sep 18 06:29:30 AM UTC 24 |
31489693393 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1754202643 |
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Sep 18 06:22:02 AM UTC 24 |
Sep 18 06:29:31 AM UTC 24 |
153217273688 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.1271524480 |
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Sep 18 06:24:24 AM UTC 24 |
Sep 18 06:29:33 AM UTC 24 |
96696082477 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.279956279 |
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Sep 18 06:29:14 AM UTC 24 |
Sep 18 06:29:34 AM UTC 24 |
24609046976 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.1633135069 |
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Sep 18 06:27:45 AM UTC 24 |
Sep 18 06:29:34 AM UTC 24 |
38239054228 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3603951513 |
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Sep 18 06:27:27 AM UTC 24 |
Sep 18 06:29:39 AM UTC 24 |
49554040446 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.155786680 |
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Sep 18 06:23:28 AM UTC 24 |
Sep 18 06:29:45 AM UTC 24 |
133305029186 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.956594254 |
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Sep 18 06:28:42 AM UTC 24 |
Sep 18 06:29:54 AM UTC 24 |
24081677944 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2625170009 |
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Sep 18 06:29:45 AM UTC 24 |
Sep 18 06:29:58 AM UTC 24 |
53808648497 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.425154535 |
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|
Sep 18 06:27:46 AM UTC 24 |
Sep 18 06:30:02 AM UTC 24 |
61010445412 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3088729332 |
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Sep 18 06:28:43 AM UTC 24 |
Sep 18 06:30:04 AM UTC 24 |
70216314277 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3602381416 |
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Sep 18 06:29:12 AM UTC 24 |
Sep 18 06:30:05 AM UTC 24 |
73817566833 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3644033640 |
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Sep 18 06:28:43 AM UTC 24 |
Sep 18 06:30:09 AM UTC 24 |
111771569783 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2975391127 |
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Sep 18 06:29:55 AM UTC 24 |
Sep 18 06:30:13 AM UTC 24 |
35047059420 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1228088234 |
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Sep 18 06:28:39 AM UTC 24 |
Sep 18 06:30:18 AM UTC 24 |
23584086630 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.973030340 |
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Sep 18 06:28:42 AM UTC 24 |
Sep 18 06:30:19 AM UTC 24 |
49988394411 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1702976168 |
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|
Sep 18 06:28:53 AM UTC 24 |
Sep 18 06:30:25 AM UTC 24 |
79320482714 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.509551117 |
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Sep 18 06:29:14 AM UTC 24 |
Sep 18 06:30:27 AM UTC 24 |
21080780232 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3773966723 |
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Sep 18 06:28:35 AM UTC 24 |
Sep 18 06:30:34 AM UTC 24 |
44397172593 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.865301610 |
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Sep 18 06:29:27 AM UTC 24 |
Sep 18 06:30:39 AM UTC 24 |
46048397727 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.209816889 |
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Sep 18 06:28:56 AM UTC 24 |
Sep 18 06:30:42 AM UTC 24 |
26335312232 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2906673958 |
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Sep 18 06:29:15 AM UTC 24 |
Sep 18 06:30:42 AM UTC 24 |
85248361576 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.201345558 |
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Sep 18 06:28:53 AM UTC 24 |
Sep 18 06:30:45 AM UTC 24 |
105774453319 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.4286909426 |
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Sep 18 06:29:03 AM UTC 24 |
Sep 18 06:30:46 AM UTC 24 |
111227891955 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1071320074 |
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Sep 18 06:29:04 AM UTC 24 |
Sep 18 06:30:48 AM UTC 24 |
50090752948 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3145106519 |
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|
Sep 18 06:30:14 AM UTC 24 |
Sep 18 06:30:48 AM UTC 24 |
27336458434 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.2654902252 |
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Sep 18 06:26:23 AM UTC 24 |
Sep 18 06:30:49 AM UTC 24 |
89259947577 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2369324341 |
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|
Sep 18 06:29:37 AM UTC 24 |
Sep 18 06:30:56 AM UTC 24 |
103551789424 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3129625472 |
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Sep 18 06:29:40 AM UTC 24 |
Sep 18 06:30:56 AM UTC 24 |
54088071304 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1312351967 |
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Sep 18 06:23:58 AM UTC 24 |
Sep 18 06:31:02 AM UTC 24 |
224621461446 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3482658280 |
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Sep 18 06:27:22 AM UTC 24 |
Sep 18 06:31:03 AM UTC 24 |
74111104720 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4123769047 |
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Sep 18 06:29:35 AM UTC 24 |
Sep 18 06:31:09 AM UTC 24 |
88129637128 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.3868438382 |
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Sep 18 06:24:44 AM UTC 24 |
Sep 18 06:31:10 AM UTC 24 |
142851433958 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2890738075 |
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Sep 18 06:30:02 AM UTC 24 |
Sep 18 06:31:13 AM UTC 24 |
86287575234 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.247298814 |
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Sep 18 06:30:06 AM UTC 24 |
Sep 18 06:31:14 AM UTC 24 |
41580008945 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2687268937 |
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Sep 18 06:28:47 AM UTC 24 |
Sep 18 06:31:18 AM UTC 24 |
49549475825 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2889318558 |
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Sep 18 06:29:26 AM UTC 24 |
Sep 18 06:31:42 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3117421244 |
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Sep 18 06:28:58 AM UTC 24 |
Sep 18 06:31:46 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3770103836 |
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Sep 18 06:29:21 AM UTC 24 |
Sep 18 06:32:00 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.3370386288 |
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Sep 18 06:23:06 AM UTC 24 |
Sep 18 06:32:02 AM UTC 24 |
188316649449 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.327192292 |
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Sep 18 06:25:45 AM UTC 24 |
Sep 18 06:32:04 AM UTC 24 |
149877549236 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3598139583 |
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Sep 18 06:28:41 AM UTC 24 |
Sep 18 06:32:07 AM UTC 24 |
51579481607 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.203473978 |
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Sep 18 06:29:31 AM UTC 24 |
Sep 18 06:32:16 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.844891605 |
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Sep 18 06:27:25 AM UTC 24 |
Sep 18 06:32:18 AM UTC 24 |
109759383293 ps |
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Sep 18 06:28:28 AM UTC 24 |
Sep 18 06:32:19 AM UTC 24 |
146279109910 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1492079805 |
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Sep 18 06:30:10 AM UTC 24 |
Sep 18 06:32:29 AM UTC 24 |
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Sep 18 06:30:05 AM UTC 24 |
Sep 18 06:32:32 AM UTC 24 |
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Sep 18 06:28:45 AM UTC 24 |
Sep 18 06:32:36 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2343916862 |
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Sep 18 06:25:52 AM UTC 24 |
Sep 18 06:32:36 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3111079149 |
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Sep 18 06:28:40 AM UTC 24 |
Sep 18 06:32:53 AM UTC 24 |
90747308428 ps |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.369755744 |
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Sep 18 06:28:43 AM UTC 24 |
Sep 18 06:33:02 AM UTC 24 |
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Sep 18 06:29:35 AM UTC 24 |
Sep 18 06:33:05 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.202497795 |
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Sep 18 06:28:53 AM UTC 24 |
Sep 18 06:33:18 AM UTC 24 |
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Sep 18 06:29:58 AM UTC 24 |
Sep 18 06:33:27 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.709759546 |
|
|
Sep 18 06:28:49 AM UTC 24 |
Sep 18 06:34:18 AM UTC 24 |
78641183490 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.713797904 |
|
|
Sep 18 06:24:58 AM UTC 24 |
Sep 18 06:34:26 AM UTC 24 |
734684730792 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.2596416384 |
|
|
Sep 18 06:28:35 AM UTC 24 |
Sep 18 06:34:51 AM UTC 24 |
147700395821 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1839185692 |
|
|
Sep 18 06:29:13 AM UTC 24 |
Sep 18 06:35:18 AM UTC 24 |
117843800154 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3796136855 |
|
|
Sep 18 06:29:34 AM UTC 24 |
Sep 18 06:35:53 AM UTC 24 |
136164439560 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.2574306714 |
|
|
Sep 18 06:28:17 AM UTC 24 |
Sep 18 06:35:54 AM UTC 24 |
154895261069 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3688247367 |
|
|
Sep 18 06:28:49 AM UTC 24 |
Sep 18 06:36:15 AM UTC 24 |
152729758990 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.737114539 |
|
|
Sep 18 06:29:01 AM UTC 24 |
Sep 18 06:36:33 AM UTC 24 |
118884974281 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1579361470 |
|
|
Sep 18 06:27:35 AM UTC 24 |
Sep 18 06:37:01 AM UTC 24 |
1670538758783 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.316242607 |
|
|
Sep 18 06:29:32 AM UTC 24 |
Sep 18 06:39:34 AM UTC 24 |
209932768778 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.371760712 |
|
|
Sep 18 06:27:20 AM UTC 24 |
Sep 18 06:39:43 AM UTC 24 |
198822662029 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.755500939 |
|
|
Sep 18 06:28:15 AM UTC 24 |
Sep 18 06:40:25 AM UTC 24 |
1282347594252 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.3855502504 |
|
|
Sep 18 06:24:38 AM UTC 24 |
Sep 18 06:46:13 AM UTC 24 |
1767714038428 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.521940463 |
|
|
Sep 18 06:26:31 AM UTC 24 |
Sep 18 07:13:45 AM UTC 24 |
783246012274 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3006617265 |
|
|
Sep 18 06:24:11 AM UTC 24 |
Sep 18 07:20:33 AM UTC 24 |
1826056789917 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.902789210 |
|
|
Sep 18 06:30:19 AM UTC 24 |
Sep 18 06:30:27 AM UTC 24 |
2251778744 ps |