| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.91 | 99.08 | 98.00 | 100.00 | 96.15 | 99.30 | 99.23 | 93.62 |
| T811 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2292611705 | Sep 18 06:30:26 AM UTC 24 | Sep 18 06:30:35 AM UTC 24 | 2012754406 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1363491125 | Sep 18 06:30:28 AM UTC 24 | Sep 18 06:30:35 AM UTC 24 | 2072929956 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1185740609 | Sep 18 06:30:28 AM UTC 24 | Sep 18 06:30:38 AM UTC 24 | 4047069664 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4214447070 | Sep 18 06:30:43 AM UTC 24 | Sep 18 06:30:46 AM UTC 24 | 2048984125 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3079991014 | Sep 18 06:30:37 AM UTC 24 | Sep 18 06:30:49 AM UTC 24 | 2987065190 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1860448290 | Sep 18 06:30:40 AM UTC 24 | Sep 18 06:30:49 AM UTC 24 | 2025977959 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1949375744 | Sep 18 06:30:39 AM UTC 24 | Sep 18 06:30:50 AM UTC 24 | 2040789008 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2329446105 | Sep 18 06:30:51 AM UTC 24 | Sep 18 06:30:54 AM UTC 24 | 2052979077 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2893865090 | Sep 18 06:30:46 AM UTC 24 | Sep 18 06:30:54 AM UTC 24 | 2033956243 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3902435054 | Sep 18 06:30:37 AM UTC 24 | Sep 18 06:30:54 AM UTC 24 | 5168191323 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.4156713628 | Sep 18 06:30:49 AM UTC 24 | Sep 18 06:30:55 AM UTC 24 | 2399972640 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2278743599 | Sep 18 06:30:49 AM UTC 24 | Sep 18 06:30:56 AM UTC 24 | 2075136288 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3854943263 | Sep 18 06:30:43 AM UTC 24 | Sep 18 06:31:01 AM UTC 24 | 22479366898 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2810069521 | Sep 18 06:30:47 AM UTC 24 | Sep 18 06:31:02 AM UTC 24 | 2771292559 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3953177582 | Sep 18 06:30:57 AM UTC 24 | Sep 18 06:31:03 AM UTC 24 | 2096049080 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.135021903 | Sep 18 06:30:49 AM UTC 24 | Sep 18 06:31:05 AM UTC 24 | 4892862990 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1560788350 | Sep 18 06:30:55 AM UTC 24 | Sep 18 06:31:06 AM UTC 24 | 2030404926 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.78143490 | Sep 18 06:30:51 AM UTC 24 | Sep 18 06:31:07 AM UTC 24 | 4034217972 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.629448183 | Sep 18 06:31:03 AM UTC 24 | Sep 18 06:31:07 AM UTC 24 | 2062615920 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.836213052 | Sep 18 06:30:55 AM UTC 24 | Sep 18 06:31:08 AM UTC 24 | 2141499053 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1825550732 | Sep 18 06:31:03 AM UTC 24 | Sep 18 06:31:08 AM UTC 24 | 6106444080 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2356950799 | Sep 18 06:30:45 AM UTC 24 | Sep 18 06:31:08 AM UTC 24 | 6029900582 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3946931646 | Sep 18 06:31:01 AM UTC 24 | Sep 18 06:31:08 AM UTC 24 | 2010592075 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3997681572 | Sep 18 06:30:57 AM UTC 24 | Sep 18 06:31:11 AM UTC 24 | 2040627288 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.451028046 | Sep 18 06:30:56 AM UTC 24 | Sep 18 06:31:11 AM UTC 24 | 7889592097 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1903460433 | Sep 18 06:31:08 AM UTC 24 | Sep 18 06:31:12 AM UTC 24 | 2045686786 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3301028353 | Sep 18 06:31:04 AM UTC 24 | Sep 18 06:31:13 AM UTC 24 | 12989019995 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.975799705 | Sep 18 06:31:07 AM UTC 24 | Sep 18 06:31:14 AM UTC 24 | 2048163654 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1169922794 | Sep 18 06:31:04 AM UTC 24 | Sep 18 06:31:14 AM UTC 24 | 2717929956 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2540298574 | Sep 18 06:31:08 AM UTC 24 | Sep 18 06:31:16 AM UTC 24 | 2157416997 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2229889982 | Sep 18 06:31:09 AM UTC 24 | Sep 18 06:31:16 AM UTC 24 | 2042807621 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.935263399 | Sep 18 06:31:12 AM UTC 24 | Sep 18 06:31:16 AM UTC 24 | 2098984818 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1453382290 | Sep 18 06:31:12 AM UTC 24 | Sep 18 06:31:19 AM UTC 24 | 2524881976 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2143040702 | Sep 18 06:31:14 AM UTC 24 | Sep 18 06:31:20 AM UTC 24 | 2025378815 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2002221048 | Sep 18 06:31:16 AM UTC 24 | Sep 18 06:31:20 AM UTC 24 | 2027625452 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2338185157 | Sep 18 06:31:10 AM UTC 24 | Sep 18 06:31:21 AM UTC 24 | 2542210432 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.957428839 | Sep 18 06:31:14 AM UTC 24 | Sep 18 06:31:21 AM UTC 24 | 2036747841 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3709451402 | Sep 18 06:31:17 AM UTC 24 | Sep 18 06:31:22 AM UTC 24 | 2074223252 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1756818209 | Sep 18 06:31:09 AM UTC 24 | Sep 18 06:31:23 AM UTC 24 | 4028558608 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2975743957 | Sep 18 06:31:15 AM UTC 24 | Sep 18 06:31:23 AM UTC 24 | 2117881555 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.176588505 | Sep 18 06:31:20 AM UTC 24 | Sep 18 06:31:24 AM UTC 24 | 2100139735 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.169986452 | Sep 18 06:31:18 AM UTC 24 | Sep 18 06:31:26 AM UTC 24 | 4618410810 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3578953549 | Sep 18 06:31:22 AM UTC 24 | Sep 18 06:31:27 AM UTC 24 | 2080495873 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3598646751 | Sep 18 06:31:15 AM UTC 24 | Sep 18 06:31:28 AM UTC 24 | 2021993692 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1244621703 | Sep 18 06:31:21 AM UTC 24 | Sep 18 06:31:28 AM UTC 24 | 2370794031 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3252959994 | Sep 18 06:31:24 AM UTC 24 | Sep 18 06:31:28 AM UTC 24 | 2288885189 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1289408001 | Sep 18 06:31:24 AM UTC 24 | Sep 18 06:31:30 AM UTC 24 | 2042407759 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2984211879 | Sep 18 06:31:22 AM UTC 24 | Sep 18 06:31:31 AM UTC 24 | 2010423563 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3778159180 | Sep 18 06:31:30 AM UTC 24 | Sep 18 06:31:33 AM UTC 24 | 2080893515 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2568199091 | Sep 18 06:31:24 AM UTC 24 | Sep 18 06:31:33 AM UTC 24 | 2011674153 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1883385965 | Sep 18 06:31:28 AM UTC 24 | Sep 18 06:31:33 AM UTC 24 | 2127624403 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1167843023 | Sep 18 06:31:11 AM UTC 24 | Sep 18 06:31:34 AM UTC 24 | 4814405658 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3028813834 | Sep 18 06:31:27 AM UTC 24 | Sep 18 06:31:35 AM UTC 24 | 2034847494 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.296909080 | Sep 18 06:31:23 AM UTC 24 | Sep 18 06:31:38 AM UTC 24 | 10272165057 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2178562197 | Sep 18 06:31:28 AM UTC 24 | Sep 18 06:31:38 AM UTC 24 | 2073180108 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1866423913 | Sep 18 06:31:33 AM UTC 24 | Sep 18 06:31:38 AM UTC 24 | 2163827345 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2266009080 | Sep 18 06:31:34 AM UTC 24 | Sep 18 06:31:38 AM UTC 24 | 2037018940 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3398692840 | Sep 18 06:31:30 AM UTC 24 | Sep 18 06:31:40 AM UTC 24 | 2037813506 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1902578302 | Sep 18 06:30:46 AM UTC 24 | Sep 18 06:31:40 AM UTC 24 | 64824464998 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2355316729 | Sep 18 06:31:35 AM UTC 24 | Sep 18 06:31:40 AM UTC 24 | 2075584224 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.801036594 | Sep 18 06:31:08 AM UTC 24 | Sep 18 06:31:40 AM UTC 24 | 22299931679 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3988346513 | Sep 18 06:31:39 AM UTC 24 | Sep 18 06:31:42 AM UTC 24 | 2038310624 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.660581272 | Sep 18 06:31:31 AM UTC 24 | Sep 18 06:31:42 AM UTC 24 | 8201472617 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3150034590 | Sep 18 06:31:38 AM UTC 24 | Sep 18 06:31:43 AM UTC 24 | 2321020440 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2902529400 | Sep 18 06:31:24 AM UTC 24 | Sep 18 06:31:43 AM UTC 24 | 22278447955 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1121363231 | Sep 18 06:31:32 AM UTC 24 | Sep 18 06:31:43 AM UTC 24 | 2043016953 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1135462425 | Sep 18 06:31:40 AM UTC 24 | Sep 18 06:31:44 AM UTC 24 | 2088079811 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2816587688 | Sep 18 06:31:42 AM UTC 24 | Sep 18 06:31:45 AM UTC 24 | 2053717530 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2452160065 | Sep 18 06:31:34 AM UTC 24 | Sep 18 06:31:45 AM UTC 24 | 2069031384 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3183950895 | Sep 18 06:31:27 AM UTC 24 | Sep 18 06:31:46 AM UTC 24 | 4359405540 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.833792596 | Sep 18 06:31:09 AM UTC 24 | Sep 18 06:31:47 AM UTC 24 | 40671076064 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1646032133 | Sep 18 06:31:41 AM UTC 24 | Sep 18 06:31:47 AM UTC 24 | 2439174243 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2795320358 | Sep 18 06:31:45 AM UTC 24 | Sep 18 06:31:47 AM UTC 24 | 2143804354 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1871965748 | Sep 18 06:31:42 AM UTC 24 | Sep 18 06:31:48 AM UTC 24 | 4654039805 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.64519346 | Sep 18 06:31:41 AM UTC 24 | Sep 18 06:31:49 AM UTC 24 | 2083019909 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2445005499 | Sep 18 06:31:43 AM UTC 24 | Sep 18 06:31:50 AM UTC 24 | 2155706486 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1783875283 | Sep 18 06:31:34 AM UTC 24 | Sep 18 06:31:51 AM UTC 24 | 10210055056 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4181528882 | Sep 18 06:31:48 AM UTC 24 | Sep 18 06:31:52 AM UTC 24 | 2054499386 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1133674040 | Sep 18 06:31:49 AM UTC 24 | Sep 18 06:31:53 AM UTC 24 | 2197150098 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1115010403 | Sep 18 06:31:44 AM UTC 24 | Sep 18 06:31:53 AM UTC 24 | 2010657620 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3561507854 | Sep 18 06:31:06 AM UTC 24 | Sep 18 06:31:53 AM UTC 24 | 9995909096 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1174066050 | Sep 18 06:31:46 AM UTC 24 | Sep 18 06:31:53 AM UTC 24 | 2060547074 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1304086646 | Sep 18 06:31:46 AM UTC 24 | Sep 18 06:31:54 AM UTC 24 | 4942078038 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.308537388 | Sep 18 06:31:41 AM UTC 24 | Sep 18 06:31:54 AM UTC 24 | 4883941157 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2283622424 | Sep 18 06:31:49 AM UTC 24 | Sep 18 06:31:54 AM UTC 24 | 3455901930 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3763936141 | Sep 18 06:31:42 AM UTC 24 | Sep 18 06:31:55 AM UTC 24 | 2047260217 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4125126870 | Sep 18 06:31:42 AM UTC 24 | Sep 18 06:31:56 AM UTC 24 | 2068023706 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.517148037 | Sep 18 06:31:47 AM UTC 24 | Sep 18 06:31:57 AM UTC 24 | 2037791089 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1798947302 | Sep 18 06:31:54 AM UTC 24 | Sep 18 06:31:57 AM UTC 24 | 2308354687 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.528953068 | Sep 18 06:31:54 AM UTC 24 | Sep 18 06:31:57 AM UTC 24 | 2180231599 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1234746984 | Sep 18 06:31:16 AM UTC 24 | Sep 18 06:31:59 AM UTC 24 | 22211078259 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.586505362 | Sep 18 06:31:48 AM UTC 24 | Sep 18 06:32:00 AM UTC 24 | 2010766263 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1575894322 | Sep 18 06:31:55 AM UTC 24 | Sep 18 06:32:00 AM UTC 24 | 4976753040 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.4161774601 | Sep 18 06:31:14 AM UTC 24 | Sep 18 06:32:00 AM UTC 24 | 9677800338 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4000355800 | Sep 18 06:31:55 AM UTC 24 | Sep 18 06:32:01 AM UTC 24 | 2464702425 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2080525647 | Sep 18 06:31:57 AM UTC 24 | Sep 18 06:32:02 AM UTC 24 | 2031882622 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2142973210 | Sep 18 06:31:51 AM UTC 24 | Sep 18 06:32:02 AM UTC 24 | 2010071248 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3705487709 | Sep 18 06:31:56 AM UTC 24 | Sep 18 06:32:02 AM UTC 24 | 2053461002 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.767050257 | Sep 18 06:31:57 AM UTC 24 | Sep 18 06:32:02 AM UTC 24 | 2295268274 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1460001228 | Sep 18 06:31:55 AM UTC 24 | Sep 18 06:32:03 AM UTC 24 | 2073259809 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2347234231 | Sep 18 06:31:58 AM UTC 24 | Sep 18 06:32:03 AM UTC 24 | 2061504606 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3831076314 | Sep 18 06:31:55 AM UTC 24 | Sep 18 06:32:03 AM UTC 24 | 2011701166 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1515804602 | Sep 18 06:30:57 AM UTC 24 | Sep 18 06:32:04 AM UTC 24 | 42414716521 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1358724061 | Sep 18 06:32:02 AM UTC 24 | Sep 18 06:32:06 AM UTC 24 | 2058038393 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1148571187 | Sep 18 06:32:02 AM UTC 24 | Sep 18 06:32:06 AM UTC 24 | 2032677177 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.611262324 | Sep 18 06:32:01 AM UTC 24 | Sep 18 06:32:06 AM UTC 24 | 2298846893 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3715354610 | Sep 18 06:32:03 AM UTC 24 | Sep 18 06:32:08 AM UTC 24 | 2102686990 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.215093034 | Sep 18 06:32:04 AM UTC 24 | Sep 18 06:32:08 AM UTC 24 | 2047841319 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3296820739 | Sep 18 06:32:04 AM UTC 24 | Sep 18 06:32:08 AM UTC 24 | 2037921973 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2137562458 | Sep 18 06:32:01 AM UTC 24 | Sep 18 06:32:10 AM UTC 24 | 2078024086 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1273434820 | Sep 18 06:32:04 AM UTC 24 | Sep 18 06:32:10 AM UTC 24 | 2077086163 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1622378112 | Sep 18 06:32:07 AM UTC 24 | Sep 18 06:32:11 AM UTC 24 | 2042284164 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1004206994 | Sep 18 06:32:07 AM UTC 24 | Sep 18 06:32:11 AM UTC 24 | 2033165410 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1213764921 | Sep 18 06:32:03 AM UTC 24 | Sep 18 06:32:12 AM UTC 24 | 2011787763 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3737020895 | Sep 18 06:32:08 AM UTC 24 | Sep 18 06:32:12 AM UTC 24 | 2031528124 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1784581123 | Sep 18 06:32:00 AM UTC 24 | Sep 18 06:32:12 AM UTC 24 | 4713244708 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.4059844994 | Sep 18 06:32:09 AM UTC 24 | Sep 18 06:32:13 AM UTC 24 | 2033495226 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2542685812 | Sep 18 06:32:08 AM UTC 24 | Sep 18 06:32:14 AM UTC 24 | 2015164670 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.883043439 | Sep 18 06:32:18 AM UTC 24 | Sep 18 06:32:26 AM UTC 24 | 2013720619 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1630222579 | Sep 18 06:31:13 AM UTC 24 | Sep 18 06:32:28 AM UTC 24 | 22193897030 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4218166133 | Sep 18 06:32:05 AM UTC 24 | Sep 18 06:32:14 AM UTC 24 | 2009255999 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2996119651 | Sep 18 06:32:09 AM UTC 24 | Sep 18 06:32:14 AM UTC 24 | 2020458187 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1740086524 | Sep 18 06:31:48 AM UTC 24 | Sep 18 06:32:15 AM UTC 24 | 10270392791 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1708847237 | Sep 18 06:32:11 AM UTC 24 | Sep 18 06:32:16 AM UTC 24 | 2015153784 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2396135284 | Sep 18 06:32:12 AM UTC 24 | Sep 18 06:32:16 AM UTC 24 | 2057067641 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2748905884 | Sep 18 06:31:55 AM UTC 24 | Sep 18 06:32:17 AM UTC 24 | 22278479690 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3303717867 | Sep 18 06:32:04 AM UTC 24 | Sep 18 06:32:17 AM UTC 24 | 5532770552 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2363331148 | Sep 18 06:32:03 AM UTC 24 | Sep 18 06:32:17 AM UTC 24 | 2129391476 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2608882991 | Sep 18 06:32:03 AM UTC 24 | Sep 18 06:32:17 AM UTC 24 | 4828574308 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2394750265 | Sep 18 06:32:12 AM UTC 24 | Sep 18 06:32:18 AM UTC 24 | 2019074738 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3122526663 | Sep 18 06:32:11 AM UTC 24 | Sep 18 06:32:18 AM UTC 24 | 2018045032 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1253229904 | Sep 18 06:32:14 AM UTC 24 | Sep 18 06:32:19 AM UTC 24 | 2015074663 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3774751566 | Sep 18 06:32:11 AM UTC 24 | Sep 18 06:32:19 AM UTC 24 | 2011211064 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1404016811 | Sep 18 06:32:15 AM UTC 24 | Sep 18 06:32:19 AM UTC 24 | 2031455032 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.512415000 | Sep 18 06:32:09 AM UTC 24 | Sep 18 06:32:19 AM UTC 24 | 2013363809 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3692565049 | Sep 18 06:32:17 AM UTC 24 | Sep 18 06:32:19 AM UTC 24 | 2071489593 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1184270237 | Sep 18 06:32:15 AM UTC 24 | Sep 18 06:32:20 AM UTC 24 | 2022877983 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1856847796 | Sep 18 06:31:54 AM UTC 24 | Sep 18 06:32:20 AM UTC 24 | 4727268259 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1511358815 | Sep 18 06:32:16 AM UTC 24 | Sep 18 06:32:21 AM UTC 24 | 2016935165 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3604942312 | Sep 18 06:32:14 AM UTC 24 | Sep 18 06:32:21 AM UTC 24 | 2012264374 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.4125139757 | Sep 18 06:32:17 AM UTC 24 | Sep 18 06:32:21 AM UTC 24 | 2031748331 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1600646952 | Sep 18 06:30:20 AM UTC 24 | Sep 18 06:32:22 AM UTC 24 | 42378394197 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2029228443 | Sep 18 06:32:14 AM UTC 24 | Sep 18 06:32:23 AM UTC 24 | 2012709067 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2980626253 | Sep 18 06:32:03 AM UTC 24 | Sep 18 06:32:23 AM UTC 24 | 22524245160 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.761983060 | Sep 18 06:32:14 AM UTC 24 | Sep 18 06:32:23 AM UTC 24 | 2011167645 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.307063560 | Sep 18 06:32:17 AM UTC 24 | Sep 18 06:32:24 AM UTC 24 | 2014291706 ps | ||
| T901 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3601385633 | Sep 18 06:32:17 AM UTC 24 | Sep 18 06:32:24 AM UTC 24 | 2014393752 ps | ||
| T902 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3173283117 | Sep 18 06:32:15 AM UTC 24 | Sep 18 06:32:24 AM UTC 24 | 2015086998 ps | ||
| T903 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2882707841 | Sep 18 06:32:18 AM UTC 24 | Sep 18 06:32:25 AM UTC 24 | 2018351332 ps | ||
| T904 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2806244980 | Sep 18 06:32:18 AM UTC 24 | Sep 18 06:32:28 AM UTC 24 | 2015677038 ps | ||
| T905 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.838691302 | Sep 18 06:32:18 AM UTC 24 | Sep 18 06:32:29 AM UTC 24 | 2015694558 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3643638873 | Sep 18 06:31:57 AM UTC 24 | Sep 18 06:32:29 AM UTC 24 | 43141495961 ps | ||
| T906 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2938817895 | Sep 18 06:31:22 AM UTC 24 | Sep 18 06:32:29 AM UTC 24 | 42466786829 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.659779605 | Sep 18 06:31:47 AM UTC 24 | Sep 18 06:32:43 AM UTC 24 | 42407062843 ps | ||
| T907 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.4093471739 | Sep 18 06:30:55 AM UTC 24 | Sep 18 06:32:45 AM UTC 24 | 24361024805 ps | ||
| T908 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3245327785 | Sep 18 06:31:38 AM UTC 24 | Sep 18 06:32:45 AM UTC 24 | 42530877053 ps | ||
| T909 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.491246342 | Sep 18 06:31:41 AM UTC 24 | Sep 18 06:32:53 AM UTC 24 | 22228461170 ps | ||
| T910 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3472400883 | Sep 18 06:31:43 AM UTC 24 | Sep 18 06:32:54 AM UTC 24 | 42473061573 ps | ||
| T911 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2120649853 | Sep 18 06:32:01 AM UTC 24 | Sep 18 06:32:54 AM UTC 24 | 22195358546 ps | ||
| T912 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1424082549 | Sep 18 06:31:29 AM UTC 24 | Sep 18 06:33:35 AM UTC 24 | 42475428430 ps | ||
| T913 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3662450625 | Sep 18 06:30:49 AM UTC 24 | Sep 18 06:33:40 AM UTC 24 | 42369393217 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2724324080 | Sep 18 06:31:34 AM UTC 24 | Sep 18 06:33:43 AM UTC 24 | 42389327288 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.300405469 | Sep 18 06:31:50 AM UTC 24 | Sep 18 06:35:00 AM UTC 24 | 42363439637 ps | ||
| T914 | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3516211400 | Sep 18 06:30:34 AM UTC 24 | Sep 18 06:36:32 AM UTC 24 | 71081106822 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3633452658 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2508577408 ps |
| CPU time | 7.1 seconds |
| Started | Sep 18 06:21:58 AM UTC 24 |
| Finished | Sep 18 06:22:06 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633452658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3633452658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.899783572 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 29384917137 ps |
| CPU time | 38.3 seconds |
| Started | Sep 18 06:22:03 AM UTC 24 |
| Finished | Sep 18 06:22:43 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899783572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.899783572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3824365608 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 43460828727 ps |
| CPU time | 13.19 seconds |
| Started | Sep 18 06:22:21 AM UTC 24 |
| Finished | Sep 18 06:22:35 AM UTC 24 |
| Peak memory | 222308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3824365608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.3824365608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4223232916 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 13122043028 ps |
| CPU time | 13.62 seconds |
| Started | Sep 18 06:22:45 AM UTC 24 |
| Finished | Sep 18 06:23:00 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223232916 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.4223232916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1420097022 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 21267147396 ps |
| CPU time | 7.1 seconds |
| Started | Sep 18 06:23:25 AM UTC 24 |
| Finished | Sep 18 06:23:33 AM UTC 24 |
| Peak memory | 222320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1420097022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1420097022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3340790864 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 60117960036 ps |
| CPU time | 54.94 seconds |
| Started | Sep 18 06:22:11 AM UTC 24 |
| Finished | Sep 18 06:23:08 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340790864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.3340790864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3080431224 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 31277064688 ps |
| CPU time | 12.18 seconds |
| Started | Sep 18 06:26:33 AM UTC 24 |
| Finished | Sep 18 06:26:47 AM UTC 24 |
| Peak memory | 222048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3080431224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.3080431224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2508600113 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1623148066593 ps |
| CPU time | 162.25 seconds |
| Started | Sep 18 06:22:11 AM UTC 24 |
| Finished | Sep 18 06:24:56 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508600113 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.2508600113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3854943263 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 22479366898 ps |
| CPU time | 16.77 seconds |
| Started | Sep 18 06:30:43 AM UTC 24 |
| Finished | Sep 18 06:31:01 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854943263 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.3854943263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.656433252 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2201205403 ps |
| CPU time | 8.73 seconds |
| Started | Sep 18 06:22:37 AM UTC 24 |
| Finished | Sep 18 06:22:47 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656433252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.656433252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.2569622997 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 125489972509 ps |
| CPU time | 72.08 seconds |
| Started | Sep 18 06:22:11 AM UTC 24 |
| Finished | Sep 18 06:23:25 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569622997 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.2569622997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1090765827 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 94592131488 ps |
| CPU time | 64.63 seconds |
| Started | Sep 18 06:23:50 AM UTC 24 |
| Finished | Sep 18 06:24:56 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090765827 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.1090765827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1790208479 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 157015797870 ps |
| CPU time | 106.36 seconds |
| Started | Sep 18 06:24:48 AM UTC 24 |
| Finished | Sep 18 06:26:37 AM UTC 24 |
| Peak memory | 211728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790208479 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.1790208479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3406537404 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 73113976248 ps |
| CPU time | 190.69 seconds |
| Started | Sep 18 06:22:35 AM UTC 24 |
| Finished | Sep 18 06:25:48 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406537404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with_pre_cond.3406537404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1488074513 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 42093019728 ps |
| CPU time | 36.43 seconds |
| Started | Sep 18 06:22:14 AM UTC 24 |
| Finished | Sep 18 06:22:51 AM UTC 24 |
| Peak memory | 241556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488074513 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.1488074513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3175020822 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 80864258623 ps |
| CPU time | 123.5 seconds |
| Started | Sep 18 06:24:31 AM UTC 24 |
| Finished | Sep 18 06:26:36 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175020822 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.3175020822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2589782021 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 14879378517 ps |
| CPU time | 21.54 seconds |
| Started | Sep 18 06:22:12 AM UTC 24 |
| Finished | Sep 18 06:22:35 AM UTC 24 |
| Peak memory | 222308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2589782021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.2589782021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2959802995 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 5824533552 ps |
| CPU time | 3.67 seconds |
| Started | Sep 18 06:23:13 AM UTC 24 |
| Finished | Sep 18 06:23:18 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959802995 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.2959802995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2640058826 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 12718459828 ps |
| CPU time | 11.27 seconds |
| Started | Sep 18 06:25:46 AM UTC 24 |
| Finished | Sep 18 06:25:58 AM UTC 24 |
| Peak memory | 222108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2640058826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.2640058826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3079991014 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2987065190 ps |
| CPU time | 11.03 seconds |
| Started | Sep 18 06:30:37 AM UTC 24 |
| Finished | Sep 18 06:30:49 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079991014 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.3079991014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.3216472119 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 224713399464 ps |
| CPU time | 84.31 seconds |
| Started | Sep 18 06:25:29 AM UTC 24 |
| Finished | Sep 18 06:26:55 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216472119 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.3216472119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.902789210 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2251778744 ps |
| CPU time | 7.33 seconds |
| Started | Sep 18 06:30:19 AM UTC 24 |
| Finished | Sep 18 06:30:27 AM UTC 24 |
| Peak memory | 221532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902789210 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.902789210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2000851393 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 248325215263 ps |
| CPU time | 122.41 seconds |
| Started | Sep 18 06:24:26 AM UTC 24 |
| Finished | Sep 18 06:26:30 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000851393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.2000851393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1630472758 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3494324540 ps |
| CPU time | 11.24 seconds |
| Started | Sep 18 06:25:16 AM UTC 24 |
| Finished | Sep 18 06:25:28 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630472758 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.1630472758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.3451734566 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 61111931758 ps |
| CPU time | 90.68 seconds |
| Started | Sep 18 06:25:10 AM UTC 24 |
| Finished | Sep 18 06:26:43 AM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451734566 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.3451734566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2470581458 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3898257698 ps |
| CPU time | 11.89 seconds |
| Started | Sep 18 06:22:02 AM UTC 24 |
| Finished | Sep 18 06:22:15 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470581458 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.2470581458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2671567838 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 527178694177 ps |
| CPU time | 79.65 seconds |
| Started | Sep 18 06:22:10 AM UTC 24 |
| Finished | Sep 18 06:23:31 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671567838 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.2671567838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4105320412 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 43085412506 ps |
| CPU time | 29.35 seconds |
| Started | Sep 18 06:23:00 AM UTC 24 |
| Finished | Sep 18 06:23:30 AM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105320412 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.4105320412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.1546849253 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3910608602 ps |
| CPU time | 3.91 seconds |
| Started | Sep 18 06:26:07 AM UTC 24 |
| Finished | Sep 18 06:26:12 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546849253 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.1546849253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3944909225 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2704878951 ps |
| CPU time | 1.75 seconds |
| Started | Sep 18 06:22:52 AM UTC 24 |
| Finished | Sep 18 06:22:55 AM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944909225 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.3944909225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.3090983520 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3345341487 ps |
| CPU time | 4.18 seconds |
| Started | Sep 18 06:23:13 AM UTC 24 |
| Finished | Sep 18 06:23:18 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090983520 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.3090983520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.713629267 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 102443469560 ps |
| CPU time | 137.37 seconds |
| Started | Sep 18 06:26:10 AM UTC 24 |
| Finished | Sep 18 06:28:29 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713629267 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.713629267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1705006623 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 99130751811 ps |
| CPU time | 47.58 seconds |
| Started | Sep 18 06:24:10 AM UTC 24 |
| Finished | Sep 18 06:24:59 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705006623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.1705006623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3378867664 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2038411470 ps |
| CPU time | 3.6 seconds |
| Started | Sep 18 06:22:05 AM UTC 24 |
| Finished | Sep 18 06:22:10 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378867664 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.3378867664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.231606336 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 41153191936 ps |
| CPU time | 112.15 seconds |
| Started | Sep 18 06:22:12 AM UTC 24 |
| Finished | Sep 18 06:24:07 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231606336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.231606336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2229889982 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2042807621 ps |
| CPU time | 5.36 seconds |
| Started | Sep 18 06:31:09 AM UTC 24 |
| Finished | Sep 18 06:31:16 AM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229889982 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.2229889982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.155786680 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 133305029186 ps |
| CPU time | 372.11 seconds |
| Started | Sep 18 06:23:28 AM UTC 24 |
| Finished | Sep 18 06:29:45 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155786680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_with_pre_cond.155786680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.2841075993 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 113478350345 ps |
| CPU time | 82.88 seconds |
| Started | Sep 18 06:24:17 AM UTC 24 |
| Finished | Sep 18 06:25:41 AM UTC 24 |
| Peak memory | 211788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841075993 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.2841075993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2067057448 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 153255918143 ps |
| CPU time | 147.72 seconds |
| Started | Sep 18 06:26:07 AM UTC 24 |
| Finished | Sep 18 06:28:37 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067057448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.2067057448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1860448290 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2025977959 ps |
| CPU time | 8.53 seconds |
| Started | Sep 18 06:30:40 AM UTC 24 |
| Finished | Sep 18 06:30:49 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860448290 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.1860448290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1619509924 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11416791880 ps |
| CPU time | 7.18 seconds |
| Started | Sep 18 06:22:04 AM UTC 24 |
| Finished | Sep 18 06:22:13 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619509924 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.1619509924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1902578302 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 64824464998 ps |
| CPU time | 52.09 seconds |
| Started | Sep 18 06:30:46 AM UTC 24 |
| Finished | Sep 18 06:31:40 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902578302 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.1902578302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1586178258 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3891934004 ps |
| CPU time | 6.3 seconds |
| Started | Sep 18 06:22:00 AM UTC 24 |
| Finished | Sep 18 06:22:07 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586178258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1586178258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.551513831 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 161450503307 ps |
| CPU time | 118.06 seconds |
| Started | Sep 18 06:24:04 AM UTC 24 |
| Finished | Sep 18 06:26:04 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551513831 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.551513831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1492079805 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 156611367798 ps |
| CPU time | 136.54 seconds |
| Started | Sep 18 06:30:10 AM UTC 24 |
| Finished | Sep 18 06:32:29 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492079805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_with_pre_cond.1492079805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2888439307 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 63315795245 ps |
| CPU time | 43.06 seconds |
| Started | Sep 18 06:25:46 AM UTC 24 |
| Finished | Sep 18 06:26:30 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888439307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_with_pre_cond.2888439307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3754875067 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 75779183412 ps |
| CPU time | 55.77 seconds |
| Started | Sep 18 06:23:14 AM UTC 24 |
| Finished | Sep 18 06:24:11 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754875067 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.3754875067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3643638873 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 43141495961 ps |
| CPU time | 29.99 seconds |
| Started | Sep 18 06:31:57 AM UTC 24 |
| Finished | Sep 18 06:32:29 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643638873 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.3643638873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1754202643 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 153217273688 ps |
| CPU time | 443.45 seconds |
| Started | Sep 18 06:22:02 AM UTC 24 |
| Finished | Sep 18 06:29:31 AM UTC 24 |
| Peak memory | 213212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754202643 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.1754202643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2920765036 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 67843561095 ps |
| CPU time | 42.34 seconds |
| Started | Sep 18 06:25:00 AM UTC 24 |
| Finished | Sep 18 06:25:44 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920765036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_with_pre_cond.2920765036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1023623778 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 9736476837 ps |
| CPU time | 9.41 seconds |
| Started | Sep 18 06:22:36 AM UTC 24 |
| Finished | Sep 18 06:22:46 AM UTC 24 |
| Peak memory | 211920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1023623778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.1023623778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4141962986 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 141136238913 ps |
| CPU time | 227.34 seconds |
| Started | Sep 18 06:28:45 AM UTC 24 |
| Finished | Sep 18 06:32:36 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141962986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.4141962986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.4286909426 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 111227891955 ps |
| CPU time | 101.06 seconds |
| Started | Sep 18 06:29:03 AM UTC 24 |
| Finished | Sep 18 06:30:46 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286909426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.4286909426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2724324080 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 42389327288 ps |
| CPU time | 127.15 seconds |
| Started | Sep 18 06:31:34 AM UTC 24 |
| Finished | Sep 18 06:33:43 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724324080 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.2724324080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1825550732 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 6106444080 ps |
| CPU time | 4.3 seconds |
| Started | Sep 18 06:31:03 AM UTC 24 |
| Finished | Sep 18 06:31:08 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825550732 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.1825550732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3485102053 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3513834651 ps |
| CPU time | 9.26 seconds |
| Started | Sep 18 06:23:23 AM UTC 24 |
| Finished | Sep 18 06:23:33 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485102053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.3485102053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2258615347 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 81350993449 ps |
| CPU time | 107.44 seconds |
| Started | Sep 18 06:23:28 AM UTC 24 |
| Finished | Sep 18 06:25:17 AM UTC 24 |
| Peak memory | 212044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258615347 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.2258615347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2364278987 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 30106677418 ps |
| CPU time | 22.97 seconds |
| Started | Sep 18 06:23:33 AM UTC 24 |
| Finished | Sep 18 06:23:57 AM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364278987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_with_pre_cond.2364278987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.10264569 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 26829729536 ps |
| CPU time | 18.55 seconds |
| Started | Sep 18 06:23:37 AM UTC 24 |
| Finished | Sep 18 06:23:56 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10264569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_with_pre_cond.10264569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.489108948 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 79522546836 ps |
| CPU time | 72.75 seconds |
| Started | Sep 18 06:23:43 AM UTC 24 |
| Finished | Sep 18 06:24:57 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489108948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.489108948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.3504948263 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 71059950671 ps |
| CPU time | 104.95 seconds |
| Started | Sep 18 06:23:53 AM UTC 24 |
| Finished | Sep 18 06:25:40 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504948263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_with_pre_cond.3504948263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1897153700 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2381724073074 ps |
| CPU time | 197.23 seconds |
| Started | Sep 18 06:24:03 AM UTC 24 |
| Finished | Sep 18 06:27:23 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897153700 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.1897153700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1237305242 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 110705487126 ps |
| CPU time | 75.68 seconds |
| Started | Sep 18 06:24:55 AM UTC 24 |
| Finished | Sep 18 06:26:12 AM UTC 24 |
| Peak memory | 211736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237305242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_with_pre_cond.1237305242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.3879703745 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 67514528138 ps |
| CPU time | 52.28 seconds |
| Started | Sep 18 06:25:15 AM UTC 24 |
| Finished | Sep 18 06:26:09 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879703745 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.3879703745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.528473811 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 104523338445 ps |
| CPU time | 62.45 seconds |
| Started | Sep 18 06:26:07 AM UTC 24 |
| Finished | Sep 18 06:27:11 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528473811 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.528473811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.89524474 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 778196878105 ps |
| CPU time | 153.15 seconds |
| Started | Sep 18 06:26:07 AM UTC 24 |
| Finished | Sep 18 06:28:43 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89524474 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.89524474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1702976168 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 79320482714 ps |
| CPU time | 90.11 seconds |
| Started | Sep 18 06:28:53 AM UTC 24 |
| Finished | Sep 18 06:30:25 AM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702976168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.1702976168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.737114539 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 118884974281 ps |
| CPU time | 447.32 seconds |
| Started | Sep 18 06:29:01 AM UTC 24 |
| Finished | Sep 18 06:36:33 AM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737114539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_with_pre_cond.737114539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.316242607 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 209932768778 ps |
| CPU time | 596.25 seconds |
| Started | Sep 18 06:29:32 AM UTC 24 |
| Finished | Sep 18 06:39:34 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316242607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.316242607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2890738075 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 86287575234 ps |
| CPU time | 68.86 seconds |
| Started | Sep 18 06:30:02 AM UTC 24 |
| Finished | Sep 18 06:31:13 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890738075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.2890738075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3765486086 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3226933591 ps |
| CPU time | 5.03 seconds |
| Started | Sep 18 06:23:23 AM UTC 24 |
| Finished | Sep 18 06:23:29 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765486086 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.3765486086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.752182343 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3342096196 ps |
| CPU time | 14.91 seconds |
| Started | Sep 18 06:23:57 AM UTC 24 |
| Finished | Sep 18 06:24:13 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752182343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.752182343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3032872548 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2943404570 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 06:25:27 AM UTC 24 |
| Finished | Sep 18 06:25:32 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032872548 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.3032872548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.3793379452 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3042395605 ps |
| CPU time | 7.92 seconds |
| Started | Sep 18 06:26:14 AM UTC 24 |
| Finished | Sep 18 06:26:23 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793379452 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.3793379452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.135021903 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4892862990 ps |
| CPU time | 14.39 seconds |
| Started | Sep 18 06:30:49 AM UTC 24 |
| Finished | Sep 18 06:31:05 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135021903 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.135021903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1866423913 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2163827345 ps |
| CPU time | 3.95 seconds |
| Started | Sep 18 06:31:33 AM UTC 24 |
| Finished | Sep 18 06:31:38 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866423913 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.1866423913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4063597911 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 129587257365 ps |
| CPU time | 105.49 seconds |
| Started | Sep 18 06:26:51 AM UTC 24 |
| Finished | Sep 18 06:28:39 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063597911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_with_pre_cond.4063597911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3516211400 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 71081106822 ps |
| CPU time | 352.97 seconds |
| Started | Sep 18 06:30:34 AM UTC 24 |
| Finished | Sep 18 06:36:32 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516211400 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.3516211400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1185740609 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4047069664 ps |
| CPU time | 8.82 seconds |
| Started | Sep 18 06:30:28 AM UTC 24 |
| Finished | Sep 18 06:30:38 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185740609 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.1185740609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1949375744 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2040789008 ps |
| CPU time | 10.49 seconds |
| Started | Sep 18 06:30:39 AM UTC 24 |
| Finished | Sep 18 06:30:50 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1949375744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .sysrst_ctrl_csr_mem_rw_with_rand_reset.1949375744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1363491125 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2072929956 ps |
| CPU time | 6.23 seconds |
| Started | Sep 18 06:30:28 AM UTC 24 |
| Finished | Sep 18 06:30:35 AM UTC 24 |
| Peak memory | 211000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363491125 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.1363491125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2292611705 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2012754406 ps |
| CPU time | 7.91 seconds |
| Started | Sep 18 06:30:26 AM UTC 24 |
| Finished | Sep 18 06:30:35 AM UTC 24 |
| Peak memory | 210600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292611705 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.2292611705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3902435054 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 5168191323 ps |
| CPU time | 16.36 seconds |
| Started | Sep 18 06:30:37 AM UTC 24 |
| Finished | Sep 18 06:30:54 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902435054 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.3902435054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1600646952 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 42378394197 ps |
| CPU time | 119.47 seconds |
| Started | Sep 18 06:30:20 AM UTC 24 |
| Finished | Sep 18 06:32:22 AM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600646952 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.1600646952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2810069521 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 2771292559 ps |
| CPU time | 13.55 seconds |
| Started | Sep 18 06:30:47 AM UTC 24 |
| Finished | Sep 18 06:31:02 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810069521 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.2810069521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2356950799 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 6029900582 ps |
| CPU time | 22 seconds |
| Started | Sep 18 06:30:45 AM UTC 24 |
| Finished | Sep 18 06:31:08 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356950799 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.2356950799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2278743599 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2075136288 ps |
| CPU time | 5.45 seconds |
| Started | Sep 18 06:30:49 AM UTC 24 |
| Finished | Sep 18 06:30:56 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2278743599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .sysrst_ctrl_csr_mem_rw_with_rand_reset.2278743599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2893865090 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2033956243 ps |
| CPU time | 6.57 seconds |
| Started | Sep 18 06:30:46 AM UTC 24 |
| Finished | Sep 18 06:30:54 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893865090 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.2893865090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4214447070 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2048984125 ps |
| CPU time | 2.45 seconds |
| Started | Sep 18 06:30:43 AM UTC 24 |
| Finished | Sep 18 06:30:46 AM UTC 24 |
| Peak memory | 210532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214447070 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.4214447070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2355316729 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2075584224 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 06:31:35 AM UTC 24 |
| Finished | Sep 18 06:31:40 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2355316729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2355316729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2452160065 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2069031384 ps |
| CPU time | 9.96 seconds |
| Started | Sep 18 06:31:34 AM UTC 24 |
| Finished | Sep 18 06:31:45 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452160065 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.2452160065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2266009080 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2037018940 ps |
| CPU time | 3.31 seconds |
| Started | Sep 18 06:31:34 AM UTC 24 |
| Finished | Sep 18 06:31:38 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266009080 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.2266009080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1783875283 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 10210055056 ps |
| CPU time | 15.5 seconds |
| Started | Sep 18 06:31:34 AM UTC 24 |
| Finished | Sep 18 06:31:51 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783875283 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.1783875283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.64519346 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2083019909 ps |
| CPU time | 6.78 seconds |
| Started | Sep 18 06:31:41 AM UTC 24 |
| Finished | Sep 18 06:31:49 AM UTC 24 |
| Peak memory | 211000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=64519346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. sysrst_ctrl_csr_mem_rw_with_rand_reset.64519346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1135462425 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2088079811 ps |
| CPU time | 3.56 seconds |
| Started | Sep 18 06:31:40 AM UTC 24 |
| Finished | Sep 18 06:31:44 AM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135462425 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.1135462425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3988346513 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2038310624 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 06:31:39 AM UTC 24 |
| Finished | Sep 18 06:31:42 AM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988346513 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.3988346513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.308537388 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 4883941157 ps |
| CPU time | 12.49 seconds |
| Started | Sep 18 06:31:41 AM UTC 24 |
| Finished | Sep 18 06:31:54 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308537388 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.308537388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3150034590 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 2321020440 ps |
| CPU time | 3.2 seconds |
| Started | Sep 18 06:31:38 AM UTC 24 |
| Finished | Sep 18 06:31:43 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150034590 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.3150034590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3245327785 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 42530877053 ps |
| CPU time | 65.44 seconds |
| Started | Sep 18 06:31:38 AM UTC 24 |
| Finished | Sep 18 06:32:45 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245327785 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.3245327785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4125126870 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2068023706 ps |
| CPU time | 12.59 seconds |
| Started | Sep 18 06:31:42 AM UTC 24 |
| Finished | Sep 18 06:31:56 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4125126870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.4125126870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3763936141 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2047260217 ps |
| CPU time | 11.9 seconds |
| Started | Sep 18 06:31:42 AM UTC 24 |
| Finished | Sep 18 06:31:55 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763936141 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.3763936141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2816587688 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 2053717530 ps |
| CPU time | 1.89 seconds |
| Started | Sep 18 06:31:42 AM UTC 24 |
| Finished | Sep 18 06:31:45 AM UTC 24 |
| Peak memory | 209936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816587688 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.2816587688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1871965748 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4654039805 ps |
| CPU time | 5.11 seconds |
| Started | Sep 18 06:31:42 AM UTC 24 |
| Finished | Sep 18 06:31:48 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871965748 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.1871965748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1646032133 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2439174243 ps |
| CPU time | 5.02 seconds |
| Started | Sep 18 06:31:41 AM UTC 24 |
| Finished | Sep 18 06:31:47 AM UTC 24 |
| Peak memory | 221476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646032133 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.1646032133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.491246342 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 22228461170 ps |
| CPU time | 70.89 seconds |
| Started | Sep 18 06:31:41 AM UTC 24 |
| Finished | Sep 18 06:32:53 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491246342 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.491246342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1174066050 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2060547074 ps |
| CPU time | 6.83 seconds |
| Started | Sep 18 06:31:46 AM UTC 24 |
| Finished | Sep 18 06:31:53 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1174066050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1174066050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2795320358 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2143804354 ps |
| CPU time | 1.95 seconds |
| Started | Sep 18 06:31:45 AM UTC 24 |
| Finished | Sep 18 06:31:47 AM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795320358 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.2795320358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1115010403 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2010657620 ps |
| CPU time | 7.39 seconds |
| Started | Sep 18 06:31:44 AM UTC 24 |
| Finished | Sep 18 06:31:53 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115010403 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.1115010403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1304086646 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 4942078038 ps |
| CPU time | 7.28 seconds |
| Started | Sep 18 06:31:46 AM UTC 24 |
| Finished | Sep 18 06:31:54 AM UTC 24 |
| Peak memory | 210948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304086646 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.1304086646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2445005499 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2155706486 ps |
| CPU time | 5.56 seconds |
| Started | Sep 18 06:31:43 AM UTC 24 |
| Finished | Sep 18 06:31:50 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445005499 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.2445005499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3472400883 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 42473061573 ps |
| CPU time | 68.62 seconds |
| Started | Sep 18 06:31:43 AM UTC 24 |
| Finished | Sep 18 06:32:54 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472400883 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.3472400883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1133674040 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2197150098 ps |
| CPU time | 2.38 seconds |
| Started | Sep 18 06:31:49 AM UTC 24 |
| Finished | Sep 18 06:31:53 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1133674040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1133674040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4181528882 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2054499386 ps |
| CPU time | 2.76 seconds |
| Started | Sep 18 06:31:48 AM UTC 24 |
| Finished | Sep 18 06:31:52 AM UTC 24 |
| Peak memory | 211000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181528882 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.4181528882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.586505362 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2010766263 ps |
| CPU time | 10.13 seconds |
| Started | Sep 18 06:31:48 AM UTC 24 |
| Finished | Sep 18 06:32:00 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586505362 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.586505362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1740086524 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 10270392791 ps |
| CPU time | 25.66 seconds |
| Started | Sep 18 06:31:48 AM UTC 24 |
| Finished | Sep 18 06:32:15 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740086524 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.1740086524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.517148037 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2037791089 ps |
| CPU time | 8.64 seconds |
| Started | Sep 18 06:31:47 AM UTC 24 |
| Finished | Sep 18 06:31:57 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517148037 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.517148037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.659779605 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 42407062843 ps |
| CPU time | 55.1 seconds |
| Started | Sep 18 06:31:47 AM UTC 24 |
| Finished | Sep 18 06:32:43 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659779605 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.659779605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.528953068 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 2180231599 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 06:31:54 AM UTC 24 |
| Finished | Sep 18 06:31:57 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=528953068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .sysrst_ctrl_csr_mem_rw_with_rand_reset.528953068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1798947302 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2308354687 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 06:31:54 AM UTC 24 |
| Finished | Sep 18 06:31:57 AM UTC 24 |
| Peak memory | 209664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798947302 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.1798947302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2142973210 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2010071248 ps |
| CPU time | 9.37 seconds |
| Started | Sep 18 06:31:51 AM UTC 24 |
| Finished | Sep 18 06:32:02 AM UTC 24 |
| Peak memory | 210684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142973210 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.2142973210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1856847796 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 4727268259 ps |
| CPU time | 25.09 seconds |
| Started | Sep 18 06:31:54 AM UTC 24 |
| Finished | Sep 18 06:32:20 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856847796 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.1856847796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2283622424 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 3455901930 ps |
| CPU time | 4.15 seconds |
| Started | Sep 18 06:31:49 AM UTC 24 |
| Finished | Sep 18 06:31:54 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283622424 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.2283622424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.300405469 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 42363439637 ps |
| CPU time | 186.59 seconds |
| Started | Sep 18 06:31:50 AM UTC 24 |
| Finished | Sep 18 06:35:00 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300405469 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.300405469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3705487709 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2053461002 ps |
| CPU time | 4.93 seconds |
| Started | Sep 18 06:31:56 AM UTC 24 |
| Finished | Sep 18 06:32:02 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3705487709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3705487709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1460001228 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2073259809 ps |
| CPU time | 6.29 seconds |
| Started | Sep 18 06:31:55 AM UTC 24 |
| Finished | Sep 18 06:32:03 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460001228 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.1460001228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3831076314 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2011701166 ps |
| CPU time | 7.07 seconds |
| Started | Sep 18 06:31:55 AM UTC 24 |
| Finished | Sep 18 06:32:03 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831076314 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.3831076314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1575894322 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 4976753040 ps |
| CPU time | 3.51 seconds |
| Started | Sep 18 06:31:55 AM UTC 24 |
| Finished | Sep 18 06:32:00 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575894322 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.1575894322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4000355800 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2464702425 ps |
| CPU time | 5.01 seconds |
| Started | Sep 18 06:31:55 AM UTC 24 |
| Finished | Sep 18 06:32:01 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000355800 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.4000355800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2748905884 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 22278479690 ps |
| CPU time | 20.43 seconds |
| Started | Sep 18 06:31:55 AM UTC 24 |
| Finished | Sep 18 06:32:17 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748905884 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.2748905884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2137562458 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2078024086 ps |
| CPU time | 8.13 seconds |
| Started | Sep 18 06:32:01 AM UTC 24 |
| Finished | Sep 18 06:32:10 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2137562458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2137562458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2347234231 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2061504606 ps |
| CPU time | 3.26 seconds |
| Started | Sep 18 06:31:58 AM UTC 24 |
| Finished | Sep 18 06:32:03 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347234231 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.2347234231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2080525647 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2031882622 ps |
| CPU time | 3.03 seconds |
| Started | Sep 18 06:31:57 AM UTC 24 |
| Finished | Sep 18 06:32:02 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080525647 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.2080525647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1784581123 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 4713244708 ps |
| CPU time | 11.68 seconds |
| Started | Sep 18 06:32:00 AM UTC 24 |
| Finished | Sep 18 06:32:12 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784581123 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.1784581123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.767050257 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2295268274 ps |
| CPU time | 4.17 seconds |
| Started | Sep 18 06:31:57 AM UTC 24 |
| Finished | Sep 18 06:32:02 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767050257 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.767050257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3715354610 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2102686990 ps |
| CPU time | 3.83 seconds |
| Started | Sep 18 06:32:03 AM UTC 24 |
| Finished | Sep 18 06:32:08 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3715354610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3715354610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1358724061 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2058038393 ps |
| CPU time | 2.96 seconds |
| Started | Sep 18 06:32:02 AM UTC 24 |
| Finished | Sep 18 06:32:06 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358724061 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.1358724061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1148571187 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2032677177 ps |
| CPU time | 3.18 seconds |
| Started | Sep 18 06:32:02 AM UTC 24 |
| Finished | Sep 18 06:32:06 AM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148571187 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.1148571187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2608882991 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4828574308 ps |
| CPU time | 13.18 seconds |
| Started | Sep 18 06:32:03 AM UTC 24 |
| Finished | Sep 18 06:32:17 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608882991 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.2608882991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.611262324 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2298846893 ps |
| CPU time | 4.6 seconds |
| Started | Sep 18 06:32:01 AM UTC 24 |
| Finished | Sep 18 06:32:06 AM UTC 24 |
| Peak memory | 221216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611262324 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.611262324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2120649853 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 22195358546 ps |
| CPU time | 51.93 seconds |
| Started | Sep 18 06:32:01 AM UTC 24 |
| Finished | Sep 18 06:32:54 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120649853 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.2120649853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1273434820 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2077086163 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 06:32:04 AM UTC 24 |
| Finished | Sep 18 06:32:10 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1273434820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1273434820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.215093034 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 2047841319 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 06:32:04 AM UTC 24 |
| Finished | Sep 18 06:32:08 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215093034 -assert nopostproc +UVM_TESTNAME=s ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.215093034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1213764921 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2011787763 ps |
| CPU time | 8.08 seconds |
| Started | Sep 18 06:32:03 AM UTC 24 |
| Finished | Sep 18 06:32:12 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213764921 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.1213764921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3303717867 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 5532770552 ps |
| CPU time | 11.41 seconds |
| Started | Sep 18 06:32:04 AM UTC 24 |
| Finished | Sep 18 06:32:17 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303717867 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.3303717867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2363331148 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2129391476 ps |
| CPU time | 13.05 seconds |
| Started | Sep 18 06:32:03 AM UTC 24 |
| Finished | Sep 18 06:32:17 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363331148 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.2363331148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2980626253 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 22524245160 ps |
| CPU time | 18.69 seconds |
| Started | Sep 18 06:32:03 AM UTC 24 |
| Finished | Sep 18 06:32:23 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980626253 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.2980626253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.836213052 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2141499053 ps |
| CPU time | 11.74 seconds |
| Started | Sep 18 06:30:55 AM UTC 24 |
| Finished | Sep 18 06:31:08 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836213052 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.836213052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.4093471739 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 24361024805 ps |
| CPU time | 107.96 seconds |
| Started | Sep 18 06:30:55 AM UTC 24 |
| Finished | Sep 18 06:32:45 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093471739 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.4093471739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.78143490 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4034217972 ps |
| CPU time | 14.96 seconds |
| Started | Sep 18 06:30:51 AM UTC 24 |
| Finished | Sep 18 06:31:07 AM UTC 24 |
| Peak memory | 210944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78143490 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.78143490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3953177582 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2096049080 ps |
| CPU time | 4.47 seconds |
| Started | Sep 18 06:30:57 AM UTC 24 |
| Finished | Sep 18 06:31:03 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3953177582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3953177582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1560788350 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2030404926 ps |
| CPU time | 9.99 seconds |
| Started | Sep 18 06:30:55 AM UTC 24 |
| Finished | Sep 18 06:31:06 AM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560788350 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.1560788350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2329446105 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2052979077 ps |
| CPU time | 1.84 seconds |
| Started | Sep 18 06:30:51 AM UTC 24 |
| Finished | Sep 18 06:30:54 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329446105 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.2329446105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.451028046 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7889592097 ps |
| CPU time | 13.44 seconds |
| Started | Sep 18 06:30:56 AM UTC 24 |
| Finished | Sep 18 06:31:11 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451028046 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.451028046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.4156713628 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2399972640 ps |
| CPU time | 5.07 seconds |
| Started | Sep 18 06:30:49 AM UTC 24 |
| Finished | Sep 18 06:30:55 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156713628 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.4156713628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3662450625 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 42369393217 ps |
| CPU time | 168.16 seconds |
| Started | Sep 18 06:30:49 AM UTC 24 |
| Finished | Sep 18 06:33:40 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662450625 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.3662450625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3296820739 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2037921973 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 06:32:04 AM UTC 24 |
| Finished | Sep 18 06:32:08 AM UTC 24 |
| Peak memory | 210600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296820739 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.3296820739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4218166133 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2009255999 ps |
| CPU time | 7.5 seconds |
| Started | Sep 18 06:32:05 AM UTC 24 |
| Finished | Sep 18 06:32:14 AM UTC 24 |
| Peak memory | 210684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218166133 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.4218166133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1622378112 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2042284164 ps |
| CPU time | 3.24 seconds |
| Started | Sep 18 06:32:07 AM UTC 24 |
| Finished | Sep 18 06:32:11 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622378112 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.1622378112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1004206994 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2033165410 ps |
| CPU time | 3.64 seconds |
| Started | Sep 18 06:32:07 AM UTC 24 |
| Finished | Sep 18 06:32:11 AM UTC 24 |
| Peak memory | 210168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004206994 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.1004206994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3737020895 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2031528124 ps |
| CPU time | 3.31 seconds |
| Started | Sep 18 06:32:08 AM UTC 24 |
| Finished | Sep 18 06:32:12 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737020895 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.3737020895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2542685812 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2015164670 ps |
| CPU time | 4.74 seconds |
| Started | Sep 18 06:32:08 AM UTC 24 |
| Finished | Sep 18 06:32:14 AM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542685812 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.2542685812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.4059844994 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2033495226 ps |
| CPU time | 2.83 seconds |
| Started | Sep 18 06:32:09 AM UTC 24 |
| Finished | Sep 18 06:32:13 AM UTC 24 |
| Peak memory | 210840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059844994 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.4059844994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2996119651 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2020458187 ps |
| CPU time | 4.11 seconds |
| Started | Sep 18 06:32:09 AM UTC 24 |
| Finished | Sep 18 06:32:14 AM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996119651 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.2996119651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.512415000 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2013363809 ps |
| CPU time | 9.26 seconds |
| Started | Sep 18 06:32:09 AM UTC 24 |
| Finished | Sep 18 06:32:19 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512415000 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.512415000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1708847237 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2015153784 ps |
| CPU time | 3.51 seconds |
| Started | Sep 18 06:32:11 AM UTC 24 |
| Finished | Sep 18 06:32:16 AM UTC 24 |
| Peak memory | 210848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708847237 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.1708847237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1169922794 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2717929956 ps |
| CPU time | 9.53 seconds |
| Started | Sep 18 06:31:04 AM UTC 24 |
| Finished | Sep 18 06:31:14 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169922794 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.1169922794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3301028353 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 12989019995 ps |
| CPU time | 8.09 seconds |
| Started | Sep 18 06:31:04 AM UTC 24 |
| Finished | Sep 18 06:31:13 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301028353 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.3301028353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.975799705 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2048163654 ps |
| CPU time | 5.6 seconds |
| Started | Sep 18 06:31:07 AM UTC 24 |
| Finished | Sep 18 06:31:14 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=975799705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. sysrst_ctrl_csr_mem_rw_with_rand_reset.975799705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.629448183 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2062615920 ps |
| CPU time | 3.35 seconds |
| Started | Sep 18 06:31:03 AM UTC 24 |
| Finished | Sep 18 06:31:07 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629448183 -assert nopostproc +UVM_TESTNAME=s ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.629448183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3946931646 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2010592075 ps |
| CPU time | 5.78 seconds |
| Started | Sep 18 06:31:01 AM UTC 24 |
| Finished | Sep 18 06:31:08 AM UTC 24 |
| Peak memory | 210840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946931646 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.3946931646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3561507854 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 9995909096 ps |
| CPU time | 46.27 seconds |
| Started | Sep 18 06:31:06 AM UTC 24 |
| Finished | Sep 18 06:31:53 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561507854 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.3561507854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3997681572 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2040627288 ps |
| CPU time | 12.29 seconds |
| Started | Sep 18 06:30:57 AM UTC 24 |
| Finished | Sep 18 06:31:11 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997681572 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.3997681572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1515804602 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 42414716521 ps |
| CPU time | 65.63 seconds |
| Started | Sep 18 06:30:57 AM UTC 24 |
| Finished | Sep 18 06:32:04 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515804602 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.1515804602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3122526663 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2018045032 ps |
| CPU time | 5.72 seconds |
| Started | Sep 18 06:32:11 AM UTC 24 |
| Finished | Sep 18 06:32:18 AM UTC 24 |
| Peak memory | 210684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122526663 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.3122526663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3774751566 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2011211064 ps |
| CPU time | 6.33 seconds |
| Started | Sep 18 06:32:11 AM UTC 24 |
| Finished | Sep 18 06:32:19 AM UTC 24 |
| Peak memory | 210548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774751566 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.3774751566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2396135284 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2057067641 ps |
| CPU time | 2.62 seconds |
| Started | Sep 18 06:32:12 AM UTC 24 |
| Finished | Sep 18 06:32:16 AM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396135284 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.2396135284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2394750265 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2019074738 ps |
| CPU time | 4.22 seconds |
| Started | Sep 18 06:32:12 AM UTC 24 |
| Finished | Sep 18 06:32:18 AM UTC 24 |
| Peak memory | 210676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394750265 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.2394750265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3604942312 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2012264374 ps |
| CPU time | 5.91 seconds |
| Started | Sep 18 06:32:14 AM UTC 24 |
| Finished | Sep 18 06:32:21 AM UTC 24 |
| Peak memory | 210840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604942312 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.3604942312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.761983060 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2011167645 ps |
| CPU time | 8.55 seconds |
| Started | Sep 18 06:32:14 AM UTC 24 |
| Finished | Sep 18 06:32:23 AM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761983060 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.761983060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2029228443 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2012709067 ps |
| CPU time | 7.79 seconds |
| Started | Sep 18 06:32:14 AM UTC 24 |
| Finished | Sep 18 06:32:23 AM UTC 24 |
| Peak memory | 210868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029228443 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.2029228443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1253229904 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2015074663 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 06:32:14 AM UTC 24 |
| Finished | Sep 18 06:32:19 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253229904 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.1253229904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1184270237 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2022877983 ps |
| CPU time | 4.19 seconds |
| Started | Sep 18 06:32:15 AM UTC 24 |
| Finished | Sep 18 06:32:20 AM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184270237 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.1184270237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1404016811 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2031455032 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 06:32:15 AM UTC 24 |
| Finished | Sep 18 06:32:19 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404016811 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.1404016811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2338185157 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2542210432 ps |
| CPU time | 9.17 seconds |
| Started | Sep 18 06:31:10 AM UTC 24 |
| Finished | Sep 18 06:31:21 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338185157 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.2338185157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.833792596 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 40671076064 ps |
| CPU time | 35.91 seconds |
| Started | Sep 18 06:31:09 AM UTC 24 |
| Finished | Sep 18 06:31:47 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833792596 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.833792596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1756818209 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 4028558608 ps |
| CPU time | 12.54 seconds |
| Started | Sep 18 06:31:09 AM UTC 24 |
| Finished | Sep 18 06:31:23 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756818209 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.1756818209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.935263399 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2098984818 ps |
| CPU time | 3.81 seconds |
| Started | Sep 18 06:31:12 AM UTC 24 |
| Finished | Sep 18 06:31:16 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=935263399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. sysrst_ctrl_csr_mem_rw_with_rand_reset.935263399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1903460433 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 2045686786 ps |
| CPU time | 3.08 seconds |
| Started | Sep 18 06:31:08 AM UTC 24 |
| Finished | Sep 18 06:31:12 AM UTC 24 |
| Peak memory | 210532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903460433 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.1903460433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1167843023 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 4814405658 ps |
| CPU time | 22.07 seconds |
| Started | Sep 18 06:31:11 AM UTC 24 |
| Finished | Sep 18 06:31:34 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167843023 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.1167843023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2540298574 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2157416997 ps |
| CPU time | 6.52 seconds |
| Started | Sep 18 06:31:08 AM UTC 24 |
| Finished | Sep 18 06:31:16 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540298574 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.2540298574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.801036594 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 22299931679 ps |
| CPU time | 31.07 seconds |
| Started | Sep 18 06:31:08 AM UTC 24 |
| Finished | Sep 18 06:31:40 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801036594 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.801036594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3173283117 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2015086998 ps |
| CPU time | 8.59 seconds |
| Started | Sep 18 06:32:15 AM UTC 24 |
| Finished | Sep 18 06:32:24 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173283117 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.3173283117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1511358815 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2016935165 ps |
| CPU time | 3.81 seconds |
| Started | Sep 18 06:32:16 AM UTC 24 |
| Finished | Sep 18 06:32:21 AM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511358815 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.1511358815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.4125139757 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2031748331 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 06:32:17 AM UTC 24 |
| Finished | Sep 18 06:32:21 AM UTC 24 |
| Peak memory | 210944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125139757 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.4125139757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3692565049 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2071489593 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 06:32:17 AM UTC 24 |
| Finished | Sep 18 06:32:19 AM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692565049 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.3692565049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.307063560 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2014291706 ps |
| CPU time | 5.77 seconds |
| Started | Sep 18 06:32:17 AM UTC 24 |
| Finished | Sep 18 06:32:24 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307063560 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.307063560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3601385633 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2014393752 ps |
| CPU time | 6 seconds |
| Started | Sep 18 06:32:17 AM UTC 24 |
| Finished | Sep 18 06:32:24 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601385633 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.3601385633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.883043439 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2013720619 ps |
| CPU time | 6.85 seconds |
| Started | Sep 18 06:32:18 AM UTC 24 |
| Finished | Sep 18 06:32:26 AM UTC 24 |
| Peak memory | 210868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883043439 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.883043439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.838691302 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2015694558 ps |
| CPU time | 9.33 seconds |
| Started | Sep 18 06:32:18 AM UTC 24 |
| Finished | Sep 18 06:32:29 AM UTC 24 |
| Peak memory | 210680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838691302 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.838691302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2882707841 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2018351332 ps |
| CPU time | 5.68 seconds |
| Started | Sep 18 06:32:18 AM UTC 24 |
| Finished | Sep 18 06:32:25 AM UTC 24 |
| Peak memory | 210848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882707841 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.2882707841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2806244980 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 2015677038 ps |
| CPU time | 8.28 seconds |
| Started | Sep 18 06:32:18 AM UTC 24 |
| Finished | Sep 18 06:32:28 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806244980 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.2806244980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2975743957 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 2117881555 ps |
| CPU time | 6.82 seconds |
| Started | Sep 18 06:31:15 AM UTC 24 |
| Finished | Sep 18 06:31:23 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2975743957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5 .sysrst_ctrl_csr_mem_rw_with_rand_reset.2975743957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.957428839 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2036747841 ps |
| CPU time | 6.13 seconds |
| Started | Sep 18 06:31:14 AM UTC 24 |
| Finished | Sep 18 06:31:21 AM UTC 24 |
| Peak memory | 211064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957428839 -assert nopostproc +UVM_TESTNAME=s ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.957428839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2143040702 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2025378815 ps |
| CPU time | 5.19 seconds |
| Started | Sep 18 06:31:14 AM UTC 24 |
| Finished | Sep 18 06:31:20 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143040702 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.2143040702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.4161774601 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 9677800338 ps |
| CPU time | 45.16 seconds |
| Started | Sep 18 06:31:14 AM UTC 24 |
| Finished | Sep 18 06:32:00 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161774601 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.4161774601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1453382290 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2524881976 ps |
| CPU time | 5.96 seconds |
| Started | Sep 18 06:31:12 AM UTC 24 |
| Finished | Sep 18 06:31:19 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453382290 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.1453382290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1630222579 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 22193897030 ps |
| CPU time | 73.84 seconds |
| Started | Sep 18 06:31:13 AM UTC 24 |
| Finished | Sep 18 06:32:28 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630222579 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.1630222579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.176588505 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2100139735 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 06:31:20 AM UTC 24 |
| Finished | Sep 18 06:31:24 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=176588505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. sysrst_ctrl_csr_mem_rw_with_rand_reset.176588505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3709451402 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2074223252 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 06:31:17 AM UTC 24 |
| Finished | Sep 18 06:31:22 AM UTC 24 |
| Peak memory | 211000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709451402 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.3709451402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2002221048 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2027625452 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 06:31:16 AM UTC 24 |
| Finished | Sep 18 06:31:20 AM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002221048 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.2002221048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.169986452 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4618410810 ps |
| CPU time | 6.42 seconds |
| Started | Sep 18 06:31:18 AM UTC 24 |
| Finished | Sep 18 06:31:26 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169986452 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.169986452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3598646751 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2021993692 ps |
| CPU time | 11.45 seconds |
| Started | Sep 18 06:31:15 AM UTC 24 |
| Finished | Sep 18 06:31:28 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598646751 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.3598646751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1234746984 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 22211078259 ps |
| CPU time | 41.53 seconds |
| Started | Sep 18 06:31:16 AM UTC 24 |
| Finished | Sep 18 06:31:59 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234746984 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.1234746984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1289408001 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2042407759 ps |
| CPU time | 4.63 seconds |
| Started | Sep 18 06:31:24 AM UTC 24 |
| Finished | Sep 18 06:31:30 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1289408001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7 .sysrst_ctrl_csr_mem_rw_with_rand_reset.1289408001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3578953549 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2080495873 ps |
| CPU time | 4.39 seconds |
| Started | Sep 18 06:31:22 AM UTC 24 |
| Finished | Sep 18 06:31:27 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578953549 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.3578953549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2984211879 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2010423563 ps |
| CPU time | 7.82 seconds |
| Started | Sep 18 06:31:22 AM UTC 24 |
| Finished | Sep 18 06:31:31 AM UTC 24 |
| Peak memory | 210604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984211879 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.2984211879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.296909080 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10272165057 ps |
| CPU time | 13.51 seconds |
| Started | Sep 18 06:31:23 AM UTC 24 |
| Finished | Sep 18 06:31:38 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296909080 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.296909080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1244621703 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2370794031 ps |
| CPU time | 5.88 seconds |
| Started | Sep 18 06:31:21 AM UTC 24 |
| Finished | Sep 18 06:31:28 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244621703 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.1244621703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2938817895 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 42466786829 ps |
| CPU time | 65.34 seconds |
| Started | Sep 18 06:31:22 AM UTC 24 |
| Finished | Sep 18 06:32:29 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938817895 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.2938817895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2178562197 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2073180108 ps |
| CPU time | 8.39 seconds |
| Started | Sep 18 06:31:28 AM UTC 24 |
| Finished | Sep 18 06:31:38 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2178562197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8 .sysrst_ctrl_csr_mem_rw_with_rand_reset.2178562197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3028813834 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2034847494 ps |
| CPU time | 6.31 seconds |
| Started | Sep 18 06:31:27 AM UTC 24 |
| Finished | Sep 18 06:31:35 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028813834 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.3028813834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2568199091 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 2011674153 ps |
| CPU time | 7.75 seconds |
| Started | Sep 18 06:31:24 AM UTC 24 |
| Finished | Sep 18 06:31:33 AM UTC 24 |
| Peak memory | 210664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568199091 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.2568199091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3183950895 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 4359405540 ps |
| CPU time | 17.59 seconds |
| Started | Sep 18 06:31:27 AM UTC 24 |
| Finished | Sep 18 06:31:46 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183950895 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.3183950895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3252959994 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2288885189 ps |
| CPU time | 3.03 seconds |
| Started | Sep 18 06:31:24 AM UTC 24 |
| Finished | Sep 18 06:31:28 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252959994 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.3252959994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2902529400 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 22278447955 ps |
| CPU time | 17.61 seconds |
| Started | Sep 18 06:31:24 AM UTC 24 |
| Finished | Sep 18 06:31:43 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902529400 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.2902529400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1121363231 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2043016953 ps |
| CPU time | 10.18 seconds |
| Started | Sep 18 06:31:32 AM UTC 24 |
| Finished | Sep 18 06:31:43 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1121363231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9 .sysrst_ctrl_csr_mem_rw_with_rand_reset.1121363231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3398692840 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 2037813506 ps |
| CPU time | 8.84 seconds |
| Started | Sep 18 06:31:30 AM UTC 24 |
| Finished | Sep 18 06:31:40 AM UTC 24 |
| Peak memory | 210928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398692840 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.3398692840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3778159180 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2080893515 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 06:31:30 AM UTC 24 |
| Finished | Sep 18 06:31:33 AM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778159180 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.3778159180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.660581272 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 8201472617 ps |
| CPU time | 9.88 seconds |
| Started | Sep 18 06:31:31 AM UTC 24 |
| Finished | Sep 18 06:31:42 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660581272 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.660581272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1883385965 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2127624403 ps |
| CPU time | 3.88 seconds |
| Started | Sep 18 06:31:28 AM UTC 24 |
| Finished | Sep 18 06:31:33 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883385965 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.1883385965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1424082549 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 42475428430 ps |
| CPU time | 124.69 seconds |
| Started | Sep 18 06:31:29 AM UTC 24 |
| Finished | Sep 18 06:33:35 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424082549 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.1424082549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.459295616 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2443791107 ps |
| CPU time | 5.9 seconds |
| Started | Sep 18 06:21:56 AM UTC 24 |
| Finished | Sep 18 06:22:02 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459295616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.459295616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1141874227 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2277201202 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 06:21:57 AM UTC 24 |
| Finished | Sep 18 06:22:01 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141874227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1141874227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1972985220 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 33410485664 ps |
| CPU time | 20.93 seconds |
| Started | Sep 18 06:22:03 AM UTC 24 |
| Finished | Sep 18 06:22:25 AM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972985220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.1972985220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.297324468 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3960477434 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 06:21:59 AM UTC 24 |
| Finished | Sep 18 06:22:03 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297324468 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.297324468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3460147734 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2610591086 ps |
| CPU time | 11.7 seconds |
| Started | Sep 18 06:21:58 AM UTC 24 |
| Finished | Sep 18 06:22:11 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460147734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.3460147734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2304452180 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2484260411 ps |
| CPU time | 2.07 seconds |
| Started | Sep 18 06:21:54 AM UTC 24 |
| Finished | Sep 18 06:21:57 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304452180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.2304452180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.571356239 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2274107349 ps |
| CPU time | 3.44 seconds |
| Started | Sep 18 06:21:57 AM UTC 24 |
| Finished | Sep 18 06:22:01 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571356239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.571356239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.1139758564 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 22012943321 ps |
| CPU time | 53.89 seconds |
| Started | Sep 18 06:22:05 AM UTC 24 |
| Finished | Sep 18 06:23:01 AM UTC 24 |
| Peak memory | 243616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139758564 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.1139758564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.3094175392 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2126040417 ps |
| CPU time | 3.29 seconds |
| Started | Sep 18 06:21:54 AM UTC 24 |
| Finished | Sep 18 06:21:59 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094175392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.3094175392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1827338789 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 7026696130 ps |
| CPU time | 12.57 seconds |
| Started | Sep 18 06:22:03 AM UTC 24 |
| Finished | Sep 18 06:22:17 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1827338789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.1827338789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.1988870126 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2019449271 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 06:22:14 AM UTC 24 |
| Finished | Sep 18 06:22:20 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988870126 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.1988870126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1163761782 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3674364845 ps |
| CPU time | 3.63 seconds |
| Started | Sep 18 06:22:09 AM UTC 24 |
| Finished | Sep 18 06:22:14 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163761782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1163761782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3434622669 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2222917090 ps |
| CPU time | 3.68 seconds |
| Started | Sep 18 06:22:07 AM UTC 24 |
| Finished | Sep 18 06:22:11 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434622669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.3434622669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3546553625 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2540296265 ps |
| CPU time | 4.29 seconds |
| Started | Sep 18 06:22:08 AM UTC 24 |
| Finished | Sep 18 06:22:13 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546553625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3546553625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1655002585 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2955367791 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 06:22:09 AM UTC 24 |
| Finished | Sep 18 06:22:12 AM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655002585 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.1655002585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1598332037 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2627126156 ps |
| CPU time | 2.74 seconds |
| Started | Sep 18 06:22:08 AM UTC 24 |
| Finished | Sep 18 06:22:12 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598332037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.1598332037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.2824324908 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2461987175 ps |
| CPU time | 4.57 seconds |
| Started | Sep 18 06:22:07 AM UTC 24 |
| Finished | Sep 18 06:22:12 AM UTC 24 |
| Peak memory | 210928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824324908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2824324908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.1869057123 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2049999228 ps |
| CPU time | 6.94 seconds |
| Started | Sep 18 06:22:08 AM UTC 24 |
| Finished | Sep 18 06:22:16 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869057123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1869057123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2488388852 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2514604307 ps |
| CPU time | 7.21 seconds |
| Started | Sep 18 06:22:08 AM UTC 24 |
| Finished | Sep 18 06:22:16 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488388852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.2488388852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.1717961008 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2146812673 ps |
| CPU time | 2.31 seconds |
| Started | Sep 18 06:22:07 AM UTC 24 |
| Finished | Sep 18 06:22:10 AM UTC 24 |
| Peak memory | 210592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717961008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.1717961008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.537443496 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 7223181428 ps |
| CPU time | 22.88 seconds |
| Started | Sep 18 06:22:12 AM UTC 24 |
| Finished | Sep 18 06:22:36 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537443496 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.537443496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2397487553 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2009535920 ps |
| CPU time | 5.82 seconds |
| Started | Sep 18 06:23:25 AM UTC 24 |
| Finished | Sep 18 06:23:32 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397487553 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.2397487553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1982404941 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 41418518109 ps |
| CPU time | 62.86 seconds |
| Started | Sep 18 06:23:23 AM UTC 24 |
| Finished | Sep 18 06:24:27 AM UTC 24 |
| Peak memory | 211924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982404941 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.1982404941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.4166918883 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 69388532376 ps |
| CPU time | 44.13 seconds |
| Started | Sep 18 06:23:24 AM UTC 24 |
| Finished | Sep 18 06:24:09 AM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166918883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_with_pre_cond.4166918883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2231594045 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3208658623 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 06:23:22 AM UTC 24 |
| Finished | Sep 18 06:23:24 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231594045 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.2231594045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1325503374 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2627369517 ps |
| CPU time | 2.63 seconds |
| Started | Sep 18 06:23:22 AM UTC 24 |
| Finished | Sep 18 06:23:25 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325503374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.1325503374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.2869979329 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2459200526 ps |
| CPU time | 3.55 seconds |
| Started | Sep 18 06:23:20 AM UTC 24 |
| Finished | Sep 18 06:23:25 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869979329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.2869979329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.2794422198 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2164358080 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 06:23:20 AM UTC 24 |
| Finished | Sep 18 06:23:24 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794422198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.2794422198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3894091271 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2535616088 ps |
| CPU time | 2.59 seconds |
| Started | Sep 18 06:23:20 AM UTC 24 |
| Finished | Sep 18 06:23:24 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894091271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3894091271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.261671842 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2128111977 ps |
| CPU time | 3.5 seconds |
| Started | Sep 18 06:23:20 AM UTC 24 |
| Finished | Sep 18 06:23:25 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261671842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.261671842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.268726705 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 13931047110 ps |
| CPU time | 36.79 seconds |
| Started | Sep 18 06:23:25 AM UTC 24 |
| Finished | Sep 18 06:24:03 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268726705 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.268726705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2895063330 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 7159533931 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 06:23:23 AM UTC 24 |
| Finished | Sep 18 06:23:27 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895063330 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.2895063330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.2394699660 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2050528084 ps |
| CPU time | 2.42 seconds |
| Started | Sep 18 06:23:29 AM UTC 24 |
| Finished | Sep 18 06:23:32 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394699660 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.2394699660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1653192502 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3561095367 ps |
| CPU time | 10.01 seconds |
| Started | Sep 18 06:23:28 AM UTC 24 |
| Finished | Sep 18 06:23:39 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653192502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.1653192502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1274535098 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2887249357 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 06:23:28 AM UTC 24 |
| Finished | Sep 18 06:23:30 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274535098 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.1274535098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.4162559457 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 5394139961 ps |
| CPU time | 7.53 seconds |
| Started | Sep 18 06:23:28 AM UTC 24 |
| Finished | Sep 18 06:23:36 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162559457 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.4162559457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1839901421 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2612314448 ps |
| CPU time | 7.11 seconds |
| Started | Sep 18 06:23:27 AM UTC 24 |
| Finished | Sep 18 06:23:35 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839901421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1839901421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.713641705 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2463269976 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 06:23:26 AM UTC 24 |
| Finished | Sep 18 06:23:31 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713641705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.713641705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1584937368 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2107279860 ps |
| CPU time | 2.25 seconds |
| Started | Sep 18 06:23:26 AM UTC 24 |
| Finished | Sep 18 06:23:30 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584937368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1584937368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3228852734 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2535055447 ps |
| CPU time | 2.66 seconds |
| Started | Sep 18 06:23:26 AM UTC 24 |
| Finished | Sep 18 06:23:30 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228852734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3228852734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2663063203 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2113609086 ps |
| CPU time | 5.31 seconds |
| Started | Sep 18 06:23:26 AM UTC 24 |
| Finished | Sep 18 06:23:33 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663063203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2663063203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.3114562330 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 15058127513 ps |
| CPU time | 11.55 seconds |
| Started | Sep 18 06:23:29 AM UTC 24 |
| Finished | Sep 18 06:23:42 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114562330 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.3114562330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.4103212769 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 13382497824 ps |
| CPU time | 8.69 seconds |
| Started | Sep 18 06:23:29 AM UTC 24 |
| Finished | Sep 18 06:23:39 AM UTC 24 |
| Peak memory | 222224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4103212769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.4103212769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1638689284 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 9238236978 ps |
| CPU time | 3.4 seconds |
| Started | Sep 18 06:23:28 AM UTC 24 |
| Finished | Sep 18 06:23:32 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638689284 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.1638689284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.2763469746 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2016528034 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 06:23:34 AM UTC 24 |
| Finished | Sep 18 06:23:41 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763469746 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.2763469746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3451787488 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3535055735 ps |
| CPU time | 3.61 seconds |
| Started | Sep 18 06:23:32 AM UTC 24 |
| Finished | Sep 18 06:23:36 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451787488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3451787488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.3456611669 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 128147276152 ps |
| CPU time | 96.52 seconds |
| Started | Sep 18 06:23:33 AM UTC 24 |
| Finished | Sep 18 06:25:11 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456611669 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.3456611669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2885007623 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3580845937 ps |
| CPU time | 2.45 seconds |
| Started | Sep 18 06:23:31 AM UTC 24 |
| Finished | Sep 18 06:23:35 AM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885007623 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.2885007623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.2898812163 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2806608958 ps |
| CPU time | 2.96 seconds |
| Started | Sep 18 06:23:33 AM UTC 24 |
| Finished | Sep 18 06:23:37 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898812163 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.2898812163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.448188839 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2611210514 ps |
| CPU time | 7.58 seconds |
| Started | Sep 18 06:23:31 AM UTC 24 |
| Finished | Sep 18 06:23:40 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448188839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.448188839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.4070856541 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2481966090 ps |
| CPU time | 3.98 seconds |
| Started | Sep 18 06:23:30 AM UTC 24 |
| Finished | Sep 18 06:23:35 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070856541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.4070856541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.2429441671 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2183264408 ps |
| CPU time | 6.45 seconds |
| Started | Sep 18 06:23:30 AM UTC 24 |
| Finished | Sep 18 06:23:38 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429441671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.2429441671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.111599529 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2517354305 ps |
| CPU time | 7.04 seconds |
| Started | Sep 18 06:23:30 AM UTC 24 |
| Finished | Sep 18 06:23:38 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111599529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.111599529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.243406805 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2112555404 ps |
| CPU time | 7.21 seconds |
| Started | Sep 18 06:23:30 AM UTC 24 |
| Finished | Sep 18 06:23:38 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243406805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.243406805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3667726081 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 10856227552 ps |
| CPU time | 19.58 seconds |
| Started | Sep 18 06:23:34 AM UTC 24 |
| Finished | Sep 18 06:23:55 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667726081 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.3667726081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1499353041 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 5432500057 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 06:23:32 AM UTC 24 |
| Finished | Sep 18 06:23:35 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499353041 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.1499353041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.697626466 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2037655910 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 06:23:39 AM UTC 24 |
| Finished | Sep 18 06:23:43 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697626466 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.697626466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2566857862 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 130760462786 ps |
| CPU time | 92.15 seconds |
| Started | Sep 18 06:23:35 AM UTC 24 |
| Finished | Sep 18 06:25:10 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566857862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2566857862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.2920526931 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 55744481889 ps |
| CPU time | 189.65 seconds |
| Started | Sep 18 06:23:37 AM UTC 24 |
| Finished | Sep 18 06:26:49 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920526931 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.2920526931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.455940486 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 3578240310 ps |
| CPU time | 13.46 seconds |
| Started | Sep 18 06:23:35 AM UTC 24 |
| Finished | Sep 18 06:23:50 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455940486 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.455940486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.4246012251 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2843721448 ps |
| CPU time | 9.14 seconds |
| Started | Sep 18 06:23:37 AM UTC 24 |
| Finished | Sep 18 06:23:47 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246012251 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.4246012251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2082103998 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2718438448 ps |
| CPU time | 1.78 seconds |
| Started | Sep 18 06:23:35 AM UTC 24 |
| Finished | Sep 18 06:23:38 AM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082103998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.2082103998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.4182488110 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2480654183 ps |
| CPU time | 11.99 seconds |
| Started | Sep 18 06:23:34 AM UTC 24 |
| Finished | Sep 18 06:23:47 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182488110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.4182488110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.1541906651 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2139644731 ps |
| CPU time | 10.87 seconds |
| Started | Sep 18 06:23:34 AM UTC 24 |
| Finished | Sep 18 06:23:46 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541906651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1541906651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.4199193847 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2512026881 ps |
| CPU time | 9.37 seconds |
| Started | Sep 18 06:23:35 AM UTC 24 |
| Finished | Sep 18 06:23:46 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199193847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.4199193847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.3699343447 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2113334035 ps |
| CPU time | 6.63 seconds |
| Started | Sep 18 06:23:34 AM UTC 24 |
| Finished | Sep 18 06:23:42 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699343447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.3699343447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2166945340 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 9455491011 ps |
| CPU time | 23.34 seconds |
| Started | Sep 18 06:23:39 AM UTC 24 |
| Finished | Sep 18 06:24:03 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166945340 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.2166945340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2349790291 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3617406430 ps |
| CPU time | 9.92 seconds |
| Started | Sep 18 06:23:38 AM UTC 24 |
| Finished | Sep 18 06:23:49 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2349790291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.2349790291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.989069100 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4018939877 ps |
| CPU time | 7.45 seconds |
| Started | Sep 18 06:23:36 AM UTC 24 |
| Finished | Sep 18 06:23:44 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989069100 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.989069100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.1724910332 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2012274450 ps |
| CPU time | 9.84 seconds |
| Started | Sep 18 06:23:45 AM UTC 24 |
| Finished | Sep 18 06:23:56 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724910332 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.1724910332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.608778498 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3470194465 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 06:23:42 AM UTC 24 |
| Finished | Sep 18 06:23:45 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608778498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.608778498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3672831524 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 139459488078 ps |
| CPU time | 78.78 seconds |
| Started | Sep 18 06:23:43 AM UTC 24 |
| Finished | Sep 18 06:25:03 AM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672831524 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.3672831524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1945800234 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2787621140 ps |
| CPU time | 12.24 seconds |
| Started | Sep 18 06:23:41 AM UTC 24 |
| Finished | Sep 18 06:23:55 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945800234 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.1945800234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.1982250211 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 3561989081 ps |
| CPU time | 9.41 seconds |
| Started | Sep 18 06:23:43 AM UTC 24 |
| Finished | Sep 18 06:23:53 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982250211 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.1982250211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1172127220 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2611713839 ps |
| CPU time | 11.5 seconds |
| Started | Sep 18 06:23:41 AM UTC 24 |
| Finished | Sep 18 06:23:54 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172127220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1172127220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.162053604 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2496422882 ps |
| CPU time | 2.25 seconds |
| Started | Sep 18 06:23:39 AM UTC 24 |
| Finished | Sep 18 06:23:42 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162053604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.162053604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.3642467093 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2184794616 ps |
| CPU time | 6.01 seconds |
| Started | Sep 18 06:23:40 AM UTC 24 |
| Finished | Sep 18 06:23:47 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642467093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3642467093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.1408001917 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2512422517 ps |
| CPU time | 7.45 seconds |
| Started | Sep 18 06:23:40 AM UTC 24 |
| Finished | Sep 18 06:23:49 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408001917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1408001917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.4186209295 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2177207528 ps |
| CPU time | 1.61 seconds |
| Started | Sep 18 06:23:39 AM UTC 24 |
| Finished | Sep 18 06:23:42 AM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186209295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.4186209295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3726235931 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 13933055950 ps |
| CPU time | 15.72 seconds |
| Started | Sep 18 06:23:44 AM UTC 24 |
| Finished | Sep 18 06:24:01 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726235931 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.3726235931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.4096514727 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2922618049 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 06:23:43 AM UTC 24 |
| Finished | Sep 18 06:23:47 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096514727 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.4096514727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.3269609376 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2031370917 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 06:23:53 AM UTC 24 |
| Finished | Sep 18 06:23:56 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269609376 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.3269609376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1819672102 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3485451052 ps |
| CPU time | 15.66 seconds |
| Started | Sep 18 06:23:49 AM UTC 24 |
| Finished | Sep 18 06:24:05 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819672102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.1819672102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2615636894 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3303093447 ps |
| CPU time | 12.74 seconds |
| Started | Sep 18 06:23:48 AM UTC 24 |
| Finished | Sep 18 06:24:02 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615636894 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.2615636894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1567256175 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4363598540 ps |
| CPU time | 7.03 seconds |
| Started | Sep 18 06:23:51 AM UTC 24 |
| Finished | Sep 18 06:23:59 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567256175 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.1567256175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3912766875 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2639837917 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 06:23:48 AM UTC 24 |
| Finished | Sep 18 06:23:52 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912766875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.3912766875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1199762859 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2453035921 ps |
| CPU time | 4.5 seconds |
| Started | Sep 18 06:23:46 AM UTC 24 |
| Finished | Sep 18 06:23:52 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199762859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1199762859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1255381503 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2069018339 ps |
| CPU time | 8.47 seconds |
| Started | Sep 18 06:23:47 AM UTC 24 |
| Finished | Sep 18 06:23:57 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255381503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.1255381503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2610794497 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2530956006 ps |
| CPU time | 3.9 seconds |
| Started | Sep 18 06:23:47 AM UTC 24 |
| Finished | Sep 18 06:23:52 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610794497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2610794497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.799041451 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2109126295 ps |
| CPU time | 6.12 seconds |
| Started | Sep 18 06:23:46 AM UTC 24 |
| Finished | Sep 18 06:23:53 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799041451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.799041451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3525789746 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 7745159736 ps |
| CPU time | 14.05 seconds |
| Started | Sep 18 06:23:53 AM UTC 24 |
| Finished | Sep 18 06:24:08 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3525789746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.3525789746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1499573153 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 5111857167 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 06:23:50 AM UTC 24 |
| Finished | Sep 18 06:23:54 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499573153 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.1499573153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.3957269059 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2032169758 ps |
| CPU time | 3.12 seconds |
| Started | Sep 18 06:23:58 AM UTC 24 |
| Finished | Sep 18 06:24:02 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957269059 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.3957269059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.4137086822 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 174476009730 ps |
| CPU time | 127.72 seconds |
| Started | Sep 18 06:23:58 AM UTC 24 |
| Finished | Sep 18 06:26:08 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137086822 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.4137086822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3713428451 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 113292513543 ps |
| CPU time | 318.44 seconds |
| Started | Sep 18 06:23:58 AM UTC 24 |
| Finished | Sep 18 06:29:20 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713428451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.3713428451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2813319313 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3228431719 ps |
| CPU time | 6.43 seconds |
| Started | Sep 18 06:23:55 AM UTC 24 |
| Finished | Sep 18 06:24:03 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813319313 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.2813319313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.995203704 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5566805847 ps |
| CPU time | 4.34 seconds |
| Started | Sep 18 06:23:58 AM UTC 24 |
| Finished | Sep 18 06:24:03 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995203704 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.995203704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1019270367 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2615024601 ps |
| CPU time | 4.3 seconds |
| Started | Sep 18 06:23:55 AM UTC 24 |
| Finished | Sep 18 06:24:01 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019270367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.1019270367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.3796885747 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2527364690 ps |
| CPU time | 1.92 seconds |
| Started | Sep 18 06:23:54 AM UTC 24 |
| Finished | Sep 18 06:23:57 AM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796885747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3796885747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.2916881355 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2038482702 ps |
| CPU time | 2.45 seconds |
| Started | Sep 18 06:23:55 AM UTC 24 |
| Finished | Sep 18 06:23:59 AM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916881355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.2916881355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.1642339782 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2515561690 ps |
| CPU time | 4.11 seconds |
| Started | Sep 18 06:23:55 AM UTC 24 |
| Finished | Sep 18 06:24:00 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642339782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.1642339782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1723179110 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2169191567 ps |
| CPU time | 1.79 seconds |
| Started | Sep 18 06:23:54 AM UTC 24 |
| Finished | Sep 18 06:23:57 AM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723179110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1723179110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1312351967 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 224621461446 ps |
| CPU time | 418.59 seconds |
| Started | Sep 18 06:23:58 AM UTC 24 |
| Finished | Sep 18 06:31:02 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312351967 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.1312351967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1529817803 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 7743439134 ps |
| CPU time | 22.14 seconds |
| Started | Sep 18 06:23:58 AM UTC 24 |
| Finished | Sep 18 06:24:21 AM UTC 24 |
| Peak memory | 222068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1529817803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.1529817803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.689657728 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 6115127151 ps |
| CPU time | 6.48 seconds |
| Started | Sep 18 06:23:57 AM UTC 24 |
| Finished | Sep 18 06:24:04 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689657728 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.689657728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.195665367 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2039604062 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 06:24:05 AM UTC 24 |
| Finished | Sep 18 06:24:08 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195665367 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.195665367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4154195359 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3102073487 ps |
| CPU time | 4.96 seconds |
| Started | Sep 18 06:24:02 AM UTC 24 |
| Finished | Sep 18 06:24:08 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154195359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.4154195359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2420102409 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 26355182056 ps |
| CPU time | 17.74 seconds |
| Started | Sep 18 06:24:04 AM UTC 24 |
| Finished | Sep 18 06:24:23 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420102409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_with_pre_cond.2420102409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1151312287 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 3511254103 ps |
| CPU time | 13.23 seconds |
| Started | Sep 18 06:24:01 AM UTC 24 |
| Finished | Sep 18 06:24:16 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151312287 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.1151312287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.3011772899 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 5531570280 ps |
| CPU time | 2.56 seconds |
| Started | Sep 18 06:24:04 AM UTC 24 |
| Finished | Sep 18 06:24:07 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011772899 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.3011772899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2632144218 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2614646016 ps |
| CPU time | 5.99 seconds |
| Started | Sep 18 06:24:01 AM UTC 24 |
| Finished | Sep 18 06:24:08 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632144218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.2632144218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.2355848449 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2486541192 ps |
| CPU time | 10.39 seconds |
| Started | Sep 18 06:24:00 AM UTC 24 |
| Finished | Sep 18 06:24:12 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355848449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.2355848449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.4047428413 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2099553047 ps |
| CPU time | 3.24 seconds |
| Started | Sep 18 06:24:00 AM UTC 24 |
| Finished | Sep 18 06:24:04 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047428413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.4047428413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.60381432 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2510335425 ps |
| CPU time | 8.12 seconds |
| Started | Sep 18 06:24:01 AM UTC 24 |
| Finished | Sep 18 06:24:10 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60381432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.60381432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.3427405490 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2119888558 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 06:23:59 AM UTC 24 |
| Finished | Sep 18 06:24:03 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427405490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.3427405490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1860349864 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 11204105055 ps |
| CPU time | 20.94 seconds |
| Started | Sep 18 06:24:04 AM UTC 24 |
| Finished | Sep 18 06:24:26 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860349864 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.1860349864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1180558789 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2282836459 ps |
| CPU time | 9.22 seconds |
| Started | Sep 18 06:24:04 AM UTC 24 |
| Finished | Sep 18 06:24:14 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1180558789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.1180558789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.239739652 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2020122117 ps |
| CPU time | 4.78 seconds |
| Started | Sep 18 06:24:11 AM UTC 24 |
| Finished | Sep 18 06:24:17 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239739652 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.239739652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1288044498 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3268006711 ps |
| CPU time | 3.25 seconds |
| Started | Sep 18 06:24:10 AM UTC 24 |
| Finished | Sep 18 06:24:14 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288044498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1288044498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3716330262 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 193688951591 ps |
| CPU time | 284.09 seconds |
| Started | Sep 18 06:24:10 AM UTC 24 |
| Finished | Sep 18 06:28:57 AM UTC 24 |
| Peak memory | 211788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716330262 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.3716330262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.646737605 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 4840663728 ps |
| CPU time | 12.13 seconds |
| Started | Sep 18 06:24:08 AM UTC 24 |
| Finished | Sep 18 06:24:22 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646737605 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.646737605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2377508128 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3280802161 ps |
| CPU time | 11.28 seconds |
| Started | Sep 18 06:24:10 AM UTC 24 |
| Finished | Sep 18 06:24:22 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377508128 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.2377508128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1588536339 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2679813651 ps |
| CPU time | 2.67 seconds |
| Started | Sep 18 06:24:08 AM UTC 24 |
| Finished | Sep 18 06:24:12 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588536339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1588536339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.556073399 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2479293271 ps |
| CPU time | 2.32 seconds |
| Started | Sep 18 06:24:05 AM UTC 24 |
| Finished | Sep 18 06:24:08 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556073399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.556073399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.4221671716 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2240926392 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 06:24:06 AM UTC 24 |
| Finished | Sep 18 06:24:09 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221671716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.4221671716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.1758190688 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2526601641 ps |
| CPU time | 5.37 seconds |
| Started | Sep 18 06:24:07 AM UTC 24 |
| Finished | Sep 18 06:24:14 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758190688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1758190688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.3660862760 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2223439207 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 06:24:05 AM UTC 24 |
| Finished | Sep 18 06:24:07 AM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660862760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3660862760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3006617265 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1826056789917 ps |
| CPU time | 3351.86 seconds |
| Started | Sep 18 06:24:11 AM UTC 24 |
| Finished | Sep 18 07:20:33 AM UTC 24 |
| Peak memory | 213336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006617265 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.3006617265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.789021184 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 16283303814 ps |
| CPU time | 18.56 seconds |
| Started | Sep 18 06:24:11 AM UTC 24 |
| Finished | Sep 18 06:24:30 AM UTC 24 |
| Peak memory | 222108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=789021184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.789021184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2168348281 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5144704148 ps |
| CPU time | 1.91 seconds |
| Started | Sep 18 06:24:10 AM UTC 24 |
| Finished | Sep 18 06:24:12 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168348281 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.2168348281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.163920398 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2012584277 ps |
| CPU time | 7.72 seconds |
| Started | Sep 18 06:24:19 AM UTC 24 |
| Finished | Sep 18 06:24:28 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163920398 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.163920398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.579032482 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 252163011389 ps |
| CPU time | 220.8 seconds |
| Started | Sep 18 06:24:14 AM UTC 24 |
| Finished | Sep 18 06:27:58 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579032482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.579032482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3608896797 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 38542342119 ps |
| CPU time | 21.32 seconds |
| Started | Sep 18 06:24:18 AM UTC 24 |
| Finished | Sep 18 06:24:40 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608896797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_with_pre_cond.3608896797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1902963239 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 3052311896 ps |
| CPU time | 3.05 seconds |
| Started | Sep 18 06:24:14 AM UTC 24 |
| Finished | Sep 18 06:24:18 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902963239 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.1902963239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2083641312 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3961808293 ps |
| CPU time | 5.76 seconds |
| Started | Sep 18 06:24:17 AM UTC 24 |
| Finished | Sep 18 06:24:23 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083641312 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.2083641312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1749933534 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2610893076 ps |
| CPU time | 6.52 seconds |
| Started | Sep 18 06:24:13 AM UTC 24 |
| Finished | Sep 18 06:24:21 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749933534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.1749933534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.2099908938 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2456212334 ps |
| CPU time | 11.52 seconds |
| Started | Sep 18 06:24:12 AM UTC 24 |
| Finished | Sep 18 06:24:25 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099908938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.2099908938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3245442971 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2081829887 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 06:24:13 AM UTC 24 |
| Finished | Sep 18 06:24:17 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245442971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3245442971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2338348987 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2511283332 ps |
| CPU time | 10.61 seconds |
| Started | Sep 18 06:24:13 AM UTC 24 |
| Finished | Sep 18 06:24:25 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338348987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.2338348987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.346702632 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2109291130 ps |
| CPU time | 9.33 seconds |
| Started | Sep 18 06:24:12 AM UTC 24 |
| Finished | Sep 18 06:24:22 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346702632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.346702632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.446751825 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 7674060756 ps |
| CPU time | 23.83 seconds |
| Started | Sep 18 06:24:18 AM UTC 24 |
| Finished | Sep 18 06:24:43 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446751825 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.446751825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2584196107 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3150494744 ps |
| CPU time | 12.31 seconds |
| Started | Sep 18 06:24:18 AM UTC 24 |
| Finished | Sep 18 06:24:31 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2584196107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.2584196107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2850554977 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 12513958162 ps |
| CPU time | 1.67 seconds |
| Started | Sep 18 06:24:15 AM UTC 24 |
| Finished | Sep 18 06:24:18 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850554977 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.2850554977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2487254802 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2016791121 ps |
| CPU time | 10.83 seconds |
| Started | Sep 18 06:22:23 AM UTC 24 |
| Finished | Sep 18 06:22:35 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487254802 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.2487254802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1481421591 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3852290567 ps |
| CPU time | 15.41 seconds |
| Started | Sep 18 06:22:18 AM UTC 24 |
| Finished | Sep 18 06:22:35 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481421591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1481421591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3944678499 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 99358600319 ps |
| CPU time | 67.9 seconds |
| Started | Sep 18 06:22:19 AM UTC 24 |
| Finished | Sep 18 06:23:29 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944678499 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.3944678499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3486542238 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2533271385 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 06:22:15 AM UTC 24 |
| Finished | Sep 18 06:22:17 AM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486542238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3486542238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.266168790 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2354399381 ps |
| CPU time | 2.8 seconds |
| Started | Sep 18 06:22:16 AM UTC 24 |
| Finished | Sep 18 06:22:20 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266168790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.266168790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2524063924 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 38255443911 ps |
| CPU time | 89.91 seconds |
| Started | Sep 18 06:22:21 AM UTC 24 |
| Finished | Sep 18 06:23:52 AM UTC 24 |
| Peak memory | 211736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524063924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.2524063924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.230426126 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3952690362 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 06:22:18 AM UTC 24 |
| Finished | Sep 18 06:22:21 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230426126 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.230426126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.192150451 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2959970275 ps |
| CPU time | 2.11 seconds |
| Started | Sep 18 06:22:20 AM UTC 24 |
| Finished | Sep 18 06:22:24 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192150451 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.192150451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.467906420 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2619916788 ps |
| CPU time | 4.22 seconds |
| Started | Sep 18 06:22:17 AM UTC 24 |
| Finished | Sep 18 06:22:22 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467906420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.467906420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.1051969780 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2485335100 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 06:22:14 AM UTC 24 |
| Finished | Sep 18 06:22:17 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051969780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.1051969780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.2262110690 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2199301749 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 06:22:16 AM UTC 24 |
| Finished | Sep 18 06:22:19 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262110690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2262110690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.4249312904 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2550707101 ps |
| CPU time | 1.75 seconds |
| Started | Sep 18 06:22:17 AM UTC 24 |
| Finished | Sep 18 06:22:20 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249312904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.4249312904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.1339848344 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 22049246672 ps |
| CPU time | 32.76 seconds |
| Started | Sep 18 06:22:22 AM UTC 24 |
| Finished | Sep 18 06:22:56 AM UTC 24 |
| Peak memory | 243468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339848344 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1339848344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.4066293005 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2112323118 ps |
| CPU time | 8.42 seconds |
| Started | Sep 18 06:22:14 AM UTC 24 |
| Finished | Sep 18 06:22:23 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066293005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.4066293005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.2083727136 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8578639255 ps |
| CPU time | 4.11 seconds |
| Started | Sep 18 06:22:22 AM UTC 24 |
| Finished | Sep 18 06:22:27 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083727136 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.2083727136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1805733361 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5442741320 ps |
| CPU time | 14.23 seconds |
| Started | Sep 18 06:22:18 AM UTC 24 |
| Finished | Sep 18 06:22:34 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805733361 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.1805733361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2873014764 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2012257602 ps |
| CPU time | 8.79 seconds |
| Started | Sep 18 06:24:27 AM UTC 24 |
| Finished | Sep 18 06:24:37 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873014764 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.2873014764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.708686806 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3079707495 ps |
| CPU time | 3.62 seconds |
| Started | Sep 18 06:24:23 AM UTC 24 |
| Finished | Sep 18 06:24:27 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708686806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.708686806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.1271524480 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 96696082477 ps |
| CPU time | 305.15 seconds |
| Started | Sep 18 06:24:24 AM UTC 24 |
| Finished | Sep 18 06:29:33 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271524480 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.1271524480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3169841609 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 3457944412 ps |
| CPU time | 5.77 seconds |
| Started | Sep 18 06:24:22 AM UTC 24 |
| Finished | Sep 18 06:24:29 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169841609 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.3169841609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.2558601539 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 2833410706 ps |
| CPU time | 7.54 seconds |
| Started | Sep 18 06:24:25 AM UTC 24 |
| Finished | Sep 18 06:24:33 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558601539 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.2558601539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.4204007978 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2615581316 ps |
| CPU time | 4.58 seconds |
| Started | Sep 18 06:24:22 AM UTC 24 |
| Finished | Sep 18 06:24:28 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204007978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.4204007978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.170845509 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2477240656 ps |
| CPU time | 10.54 seconds |
| Started | Sep 18 06:24:20 AM UTC 24 |
| Finished | Sep 18 06:24:32 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170845509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.170845509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3899924154 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2130505121 ps |
| CPU time | 9.53 seconds |
| Started | Sep 18 06:24:21 AM UTC 24 |
| Finished | Sep 18 06:24:32 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899924154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3899924154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.2727735249 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2512594960 ps |
| CPU time | 11.08 seconds |
| Started | Sep 18 06:24:22 AM UTC 24 |
| Finished | Sep 18 06:24:34 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727735249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.2727735249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1149878634 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2118273435 ps |
| CPU time | 5.78 seconds |
| Started | Sep 18 06:24:19 AM UTC 24 |
| Finished | Sep 18 06:24:26 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149878634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1149878634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.214878596 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 10667722483 ps |
| CPU time | 26.73 seconds |
| Started | Sep 18 06:24:27 AM UTC 24 |
| Finished | Sep 18 06:24:55 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214878596 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.214878596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1576779031 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 7432196552 ps |
| CPU time | 10.36 seconds |
| Started | Sep 18 06:24:26 AM UTC 24 |
| Finished | Sep 18 06:24:37 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1576779031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1576779031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2164787034 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 4083289007 ps |
| CPU time | 1.84 seconds |
| Started | Sep 18 06:24:24 AM UTC 24 |
| Finished | Sep 18 06:24:26 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164787034 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.2164787034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.512910302 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2011742433 ps |
| CPU time | 8.73 seconds |
| Started | Sep 18 06:24:33 AM UTC 24 |
| Finished | Sep 18 06:24:43 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512910302 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.512910302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3237425763 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 62199584832 ps |
| CPU time | 100.14 seconds |
| Started | Sep 18 06:24:31 AM UTC 24 |
| Finished | Sep 18 06:26:13 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237425763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.3237425763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3991221067 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 27080194580 ps |
| CPU time | 86.34 seconds |
| Started | Sep 18 06:24:32 AM UTC 24 |
| Finished | Sep 18 06:26:00 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991221067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.3991221067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.314834946 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 3799538111 ps |
| CPU time | 3.59 seconds |
| Started | Sep 18 06:24:28 AM UTC 24 |
| Finished | Sep 18 06:24:33 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314834946 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.314834946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.908114454 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4262327206 ps |
| CPU time | 8.77 seconds |
| Started | Sep 18 06:24:32 AM UTC 24 |
| Finished | Sep 18 06:24:42 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908114454 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.908114454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3146555925 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2613091510 ps |
| CPU time | 9.45 seconds |
| Started | Sep 18 06:24:28 AM UTC 24 |
| Finished | Sep 18 06:24:39 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146555925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.3146555925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.753575725 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2462634236 ps |
| CPU time | 9.31 seconds |
| Started | Sep 18 06:24:27 AM UTC 24 |
| Finished | Sep 18 06:24:38 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753575725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.753575725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1812833138 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2127828013 ps |
| CPU time | 2.91 seconds |
| Started | Sep 18 06:24:28 AM UTC 24 |
| Finished | Sep 18 06:24:32 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812833138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1812833138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.1937186350 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2510524543 ps |
| CPU time | 7.35 seconds |
| Started | Sep 18 06:24:28 AM UTC 24 |
| Finished | Sep 18 06:24:37 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937186350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.1937186350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.1595710073 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2133880187 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 06:24:27 AM UTC 24 |
| Finished | Sep 18 06:24:31 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595710073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1595710073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3676404903 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 6541421436 ps |
| CPU time | 19.9 seconds |
| Started | Sep 18 06:24:33 AM UTC 24 |
| Finished | Sep 18 06:24:54 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676404903 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.3676404903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1003599154 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 3978503306 ps |
| CPU time | 14.68 seconds |
| Started | Sep 18 06:24:32 AM UTC 24 |
| Finished | Sep 18 06:24:48 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1003599154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.1003599154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1530682284 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 7199499881 ps |
| CPU time | 7.05 seconds |
| Started | Sep 18 06:24:31 AM UTC 24 |
| Finished | Sep 18 06:24:39 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530682284 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.1530682284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1997016268 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2114258876 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 06:24:39 AM UTC 24 |
| Finished | Sep 18 06:24:42 AM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997016268 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.1997016268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3532418797 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3583133455 ps |
| CPU time | 10.92 seconds |
| Started | Sep 18 06:24:38 AM UTC 24 |
| Finished | Sep 18 06:24:50 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532418797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.3532418797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.2026462867 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 84098059560 ps |
| CPU time | 62.52 seconds |
| Started | Sep 18 06:24:38 AM UTC 24 |
| Finished | Sep 18 06:25:42 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026462867 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.2026462867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1085310823 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3300372072 ps |
| CPU time | 4.23 seconds |
| Started | Sep 18 06:24:37 AM UTC 24 |
| Finished | Sep 18 06:24:42 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085310823 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.1085310823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.3855502504 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1767714038428 ps |
| CPU time | 1282.43 seconds |
| Started | Sep 18 06:24:38 AM UTC 24 |
| Finished | Sep 18 06:46:13 AM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855502504 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.3855502504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3964804356 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2608646810 ps |
| CPU time | 8.96 seconds |
| Started | Sep 18 06:24:35 AM UTC 24 |
| Finished | Sep 18 06:24:45 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964804356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3964804356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3148582467 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2488196962 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 06:24:34 AM UTC 24 |
| Finished | Sep 18 06:24:38 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148582467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3148582467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.1026227457 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2196677164 ps |
| CPU time | 2.14 seconds |
| Started | Sep 18 06:24:34 AM UTC 24 |
| Finished | Sep 18 06:24:37 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026227457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1026227457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.3344597906 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2531155160 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 06:24:35 AM UTC 24 |
| Finished | Sep 18 06:24:39 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344597906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.3344597906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2779981949 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2132327206 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 06:24:33 AM UTC 24 |
| Finished | Sep 18 06:24:37 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779981949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2779981949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2976759774 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 9706998683 ps |
| CPU time | 9.32 seconds |
| Started | Sep 18 06:24:39 AM UTC 24 |
| Finished | Sep 18 06:24:50 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976759774 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.2976759774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.981191344 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5951496447 ps |
| CPU time | 10.92 seconds |
| Started | Sep 18 06:24:39 AM UTC 24 |
| Finished | Sep 18 06:24:51 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=981191344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.981191344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2860696688 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 8090792658 ps |
| CPU time | 13.98 seconds |
| Started | Sep 18 06:24:38 AM UTC 24 |
| Finished | Sep 18 06:24:53 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860696688 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.2860696688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.72538573 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2011546515 ps |
| CPU time | 8.6 seconds |
| Started | Sep 18 06:24:48 AM UTC 24 |
| Finished | Sep 18 06:24:58 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72538573 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.72538573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2329879349 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 3509794511 ps |
| CPU time | 14.48 seconds |
| Started | Sep 18 06:24:43 AM UTC 24 |
| Finished | Sep 18 06:24:58 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329879349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2329879349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.3868438382 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 142851433958 ps |
| CPU time | 381.62 seconds |
| Started | Sep 18 06:24:44 AM UTC 24 |
| Finished | Sep 18 06:31:10 AM UTC 24 |
| Peak memory | 211788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868438382 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.3868438382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3182596809 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 121093883730 ps |
| CPU time | 94.31 seconds |
| Started | Sep 18 06:24:46 AM UTC 24 |
| Finished | Sep 18 06:26:23 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182596809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_with_pre_cond.3182596809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1094356654 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3529354730 ps |
| CPU time | 4.92 seconds |
| Started | Sep 18 06:24:43 AM UTC 24 |
| Finished | Sep 18 06:24:49 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094356654 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.1094356654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.3319746470 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3434808410 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 06:24:44 AM UTC 24 |
| Finished | Sep 18 06:24:47 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319746470 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.3319746470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.196880481 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2611725882 ps |
| CPU time | 9.44 seconds |
| Started | Sep 18 06:24:43 AM UTC 24 |
| Finished | Sep 18 06:24:53 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196880481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.196880481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.3394668589 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2463302773 ps |
| CPU time | 11.8 seconds |
| Started | Sep 18 06:24:39 AM UTC 24 |
| Finished | Sep 18 06:24:52 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394668589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.3394668589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2406898520 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2153178609 ps |
| CPU time | 10.18 seconds |
| Started | Sep 18 06:24:40 AM UTC 24 |
| Finished | Sep 18 06:24:52 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406898520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.2406898520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.819928152 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2508376408 ps |
| CPU time | 6.97 seconds |
| Started | Sep 18 06:24:42 AM UTC 24 |
| Finished | Sep 18 06:24:50 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819928152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.819928152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2226531446 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2119399269 ps |
| CPU time | 5.74 seconds |
| Started | Sep 18 06:24:39 AM UTC 24 |
| Finished | Sep 18 06:24:46 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226531446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.2226531446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.777410533 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 5723289378 ps |
| CPU time | 10.93 seconds |
| Started | Sep 18 06:24:47 AM UTC 24 |
| Finished | Sep 18 06:25:00 AM UTC 24 |
| Peak memory | 222312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=777410533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.777410533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.805993245 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 13186552273 ps |
| CPU time | 5.18 seconds |
| Started | Sep 18 06:24:44 AM UTC 24 |
| Finished | Sep 18 06:24:50 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805993245 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.805993245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.2030794144 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2034806779 ps |
| CPU time | 3.24 seconds |
| Started | Sep 18 06:24:56 AM UTC 24 |
| Finished | Sep 18 06:25:01 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030794144 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.2030794144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2269603514 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 3071854729 ps |
| CPU time | 4.79 seconds |
| Started | Sep 18 06:24:53 AM UTC 24 |
| Finished | Sep 18 06:24:59 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269603514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2269603514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.3834834379 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 55079097437 ps |
| CPU time | 38.5 seconds |
| Started | Sep 18 06:24:54 AM UTC 24 |
| Finished | Sep 18 06:25:34 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834834379 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.3834834379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.257861052 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2453158288 ps |
| CPU time | 2.32 seconds |
| Started | Sep 18 06:24:54 AM UTC 24 |
| Finished | Sep 18 06:24:57 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257861052 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.257861052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.138958269 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2640107963 ps |
| CPU time | 3.03 seconds |
| Started | Sep 18 06:24:51 AM UTC 24 |
| Finished | Sep 18 06:24:55 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138958269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.138958269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.4070655102 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2428867125 ps |
| CPU time | 9.82 seconds |
| Started | Sep 18 06:24:50 AM UTC 24 |
| Finished | Sep 18 06:25:02 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070655102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.4070655102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.4213045614 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2146937878 ps |
| CPU time | 2.06 seconds |
| Started | Sep 18 06:24:50 AM UTC 24 |
| Finished | Sep 18 06:24:54 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213045614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.4213045614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.785380427 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2514733810 ps |
| CPU time | 10.67 seconds |
| Started | Sep 18 06:24:51 AM UTC 24 |
| Finished | Sep 18 06:25:03 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785380427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.785380427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.866650185 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2124432528 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 06:24:49 AM UTC 24 |
| Finished | Sep 18 06:24:54 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866650185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.866650185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2664471355 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 15125094800 ps |
| CPU time | 17.91 seconds |
| Started | Sep 18 06:24:55 AM UTC 24 |
| Finished | Sep 18 06:25:14 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664471355 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.2664471355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.4007745071 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 8139924892 ps |
| CPU time | 10.43 seconds |
| Started | Sep 18 06:24:55 AM UTC 24 |
| Finished | Sep 18 06:25:07 AM UTC 24 |
| Peak memory | 221992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4007745071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.4007745071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3488939892 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 11253601828 ps |
| CPU time | 7.79 seconds |
| Started | Sep 18 06:24:53 AM UTC 24 |
| Finished | Sep 18 06:25:02 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488939892 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.3488939892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.36029263 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2016211587 ps |
| CPU time | 8.14 seconds |
| Started | Sep 18 06:25:02 AM UTC 24 |
| Finished | Sep 18 06:25:12 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36029263 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.36029263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3994506187 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3554767862 ps |
| CPU time | 16.52 seconds |
| Started | Sep 18 06:24:59 AM UTC 24 |
| Finished | Sep 18 06:25:16 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994506187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.3994506187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.3226614056 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 130296772577 ps |
| CPU time | 194.6 seconds |
| Started | Sep 18 06:25:00 AM UTC 24 |
| Finished | Sep 18 06:28:18 AM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226614056 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.3226614056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.713797904 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 734684730792 ps |
| CPU time | 561.55 seconds |
| Started | Sep 18 06:24:58 AM UTC 24 |
| Finished | Sep 18 06:34:26 AM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713797904 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.713797904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.571030670 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4113129292 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 06:25:00 AM UTC 24 |
| Finished | Sep 18 06:25:03 AM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571030670 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.571030670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3621000347 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2615471831 ps |
| CPU time | 5.92 seconds |
| Started | Sep 18 06:24:58 AM UTC 24 |
| Finished | Sep 18 06:25:05 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621000347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3621000347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2421488506 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2462641919 ps |
| CPU time | 10.96 seconds |
| Started | Sep 18 06:24:56 AM UTC 24 |
| Finished | Sep 18 06:25:08 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421488506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.2421488506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3505518358 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2252629687 ps |
| CPU time | 3.26 seconds |
| Started | Sep 18 06:24:58 AM UTC 24 |
| Finished | Sep 18 06:25:02 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505518358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.3505518358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.760699320 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2530599368 ps |
| CPU time | 3.96 seconds |
| Started | Sep 18 06:24:58 AM UTC 24 |
| Finished | Sep 18 06:25:03 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760699320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.760699320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2204290292 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2126362301 ps |
| CPU time | 3.39 seconds |
| Started | Sep 18 06:24:56 AM UTC 24 |
| Finished | Sep 18 06:25:01 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204290292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2204290292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.1912769576 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 7118105597 ps |
| CPU time | 21.23 seconds |
| Started | Sep 18 06:25:01 AM UTC 24 |
| Finished | Sep 18 06:25:24 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912769576 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.1912769576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4065668410 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4720573084 ps |
| CPU time | 6.77 seconds |
| Started | Sep 18 06:25:01 AM UTC 24 |
| Finished | Sep 18 06:25:09 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4065668410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.4065668410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1032466837 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 3019194405 ps |
| CPU time | 1.48 seconds |
| Started | Sep 18 06:24:59 AM UTC 24 |
| Finished | Sep 18 06:25:01 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032466837 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.1032466837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.1763861615 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2048380991 ps |
| CPU time | 2.06 seconds |
| Started | Sep 18 06:25:10 AM UTC 24 |
| Finished | Sep 18 06:25:13 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763861615 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.1763861615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1187029568 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 3407378007 ps |
| CPU time | 4.63 seconds |
| Started | Sep 18 06:25:04 AM UTC 24 |
| Finished | Sep 18 06:25:10 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187029568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.1187029568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3974676364 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 150253549330 ps |
| CPU time | 377.77 seconds |
| Started | Sep 18 06:25:06 AM UTC 24 |
| Finished | Sep 18 06:31:28 AM UTC 24 |
| Peak memory | 211880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974676364 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.3974676364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.40643892 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 30096424334 ps |
| CPU time | 19.74 seconds |
| Started | Sep 18 06:25:09 AM UTC 24 |
| Finished | Sep 18 06:25:30 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40643892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_with_pre_cond.40643892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3696125704 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2953005941 ps |
| CPU time | 5.19 seconds |
| Started | Sep 18 06:25:04 AM UTC 24 |
| Finished | Sep 18 06:25:10 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696125704 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.3696125704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.3246717232 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2398802978 ps |
| CPU time | 10.88 seconds |
| Started | Sep 18 06:25:08 AM UTC 24 |
| Finished | Sep 18 06:25:20 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246717232 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.3246717232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1108758643 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2622820324 ps |
| CPU time | 3.93 seconds |
| Started | Sep 18 06:25:04 AM UTC 24 |
| Finished | Sep 18 06:25:09 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108758643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1108758643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.3600382290 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2472604521 ps |
| CPU time | 10.93 seconds |
| Started | Sep 18 06:25:02 AM UTC 24 |
| Finished | Sep 18 06:25:15 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600382290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.3600382290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1786651855 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2141612261 ps |
| CPU time | 9.85 seconds |
| Started | Sep 18 06:25:02 AM UTC 24 |
| Finished | Sep 18 06:25:14 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786651855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.1786651855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.4070168515 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2511863327 ps |
| CPU time | 10.95 seconds |
| Started | Sep 18 06:25:04 AM UTC 24 |
| Finished | Sep 18 06:25:16 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070168515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.4070168515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.3252137443 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2185636636 ps |
| CPU time | 1.61 seconds |
| Started | Sep 18 06:25:02 AM UTC 24 |
| Finished | Sep 18 06:25:05 AM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252137443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.3252137443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.356223595 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 4070001764 ps |
| CPU time | 13.57 seconds |
| Started | Sep 18 06:25:10 AM UTC 24 |
| Finished | Sep 18 06:25:25 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=356223595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.356223595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.177910378 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 12614643453 ps |
| CPU time | 10.55 seconds |
| Started | Sep 18 06:25:06 AM UTC 24 |
| Finished | Sep 18 06:25:18 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177910378 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.177910378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.2311908401 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2010642370 ps |
| CPU time | 7.39 seconds |
| Started | Sep 18 06:25:18 AM UTC 24 |
| Finished | Sep 18 06:25:27 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311908401 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.2311908401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3838056391 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3155366304 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 06:25:15 AM UTC 24 |
| Finished | Sep 18 06:25:18 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838056391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.3838056391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1787225548 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 83711121221 ps |
| CPU time | 116.8 seconds |
| Started | Sep 18 06:25:16 AM UTC 24 |
| Finished | Sep 18 06:27:15 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787225548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.1787225548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4228732074 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 5087600017 ps |
| CPU time | 24.74 seconds |
| Started | Sep 18 06:25:15 AM UTC 24 |
| Finished | Sep 18 06:25:41 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228732074 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.4228732074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2827133302 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2611049826 ps |
| CPU time | 9.95 seconds |
| Started | Sep 18 06:25:14 AM UTC 24 |
| Finished | Sep 18 06:25:25 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827133302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.2827133302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.3007894366 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 2464654986 ps |
| CPU time | 2.85 seconds |
| Started | Sep 18 06:25:11 AM UTC 24 |
| Finished | Sep 18 06:25:15 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007894366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3007894366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.310635672 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2117017895 ps |
| CPU time | 10.63 seconds |
| Started | Sep 18 06:25:12 AM UTC 24 |
| Finished | Sep 18 06:25:24 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310635672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.310635672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.2185757803 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 2511815693 ps |
| CPU time | 5.02 seconds |
| Started | Sep 18 06:25:12 AM UTC 24 |
| Finished | Sep 18 06:25:18 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185757803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.2185757803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.4096169786 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2137481960 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 06:25:10 AM UTC 24 |
| Finished | Sep 18 06:25:14 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096169786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.4096169786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.2747996215 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 12443319678 ps |
| CPU time | 9.83 seconds |
| Started | Sep 18 06:25:17 AM UTC 24 |
| Finished | Sep 18 06:25:28 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747996215 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.2747996215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3685485046 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 5100062911 ps |
| CPU time | 15.14 seconds |
| Started | Sep 18 06:25:17 AM UTC 24 |
| Finished | Sep 18 06:25:33 AM UTC 24 |
| Peak memory | 222164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3685485046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.3685485046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1023648259 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2832297487274 ps |
| CPU time | 205.07 seconds |
| Started | Sep 18 06:25:15 AM UTC 24 |
| Finished | Sep 18 06:28:43 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023648259 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.1023648259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2618677740 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2054214884 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 06:25:30 AM UTC 24 |
| Finished | Sep 18 06:25:33 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618677740 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.2618677740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.4192800991 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 3406214058 ps |
| CPU time | 16.46 seconds |
| Started | Sep 18 06:25:25 AM UTC 24 |
| Finished | Sep 18 06:25:43 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192800991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.4192800991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.2136960591 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 156549824061 ps |
| CPU time | 150.22 seconds |
| Started | Sep 18 06:25:26 AM UTC 24 |
| Finished | Sep 18 06:27:59 AM UTC 24 |
| Peak memory | 211664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136960591 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.2136960591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.635132147 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 111503461360 ps |
| CPU time | 171.95 seconds |
| Started | Sep 18 06:25:27 AM UTC 24 |
| Finished | Sep 18 06:28:22 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635132147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.635132147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3916338840 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2616063167 ps |
| CPU time | 6.63 seconds |
| Started | Sep 18 06:25:24 AM UTC 24 |
| Finished | Sep 18 06:25:31 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916338840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.3916338840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.734365378 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2481661772 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 06:25:18 AM UTC 24 |
| Finished | Sep 18 06:25:23 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734365378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.734365378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2590429682 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2149294016 ps |
| CPU time | 5.27 seconds |
| Started | Sep 18 06:25:20 AM UTC 24 |
| Finished | Sep 18 06:25:26 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590429682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2590429682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.2577331659 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2511944233 ps |
| CPU time | 9.96 seconds |
| Started | Sep 18 06:25:21 AM UTC 24 |
| Finished | Sep 18 06:25:32 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577331659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2577331659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.1196611039 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 2111558893 ps |
| CPU time | 9.56 seconds |
| Started | Sep 18 06:25:18 AM UTC 24 |
| Finished | Sep 18 06:25:29 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196611039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.1196611039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2825423850 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 7043615570 ps |
| CPU time | 15.55 seconds |
| Started | Sep 18 06:25:29 AM UTC 24 |
| Finished | Sep 18 06:25:46 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2825423850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2825423850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.327175847 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 5668634962 ps |
| CPU time | 2.45 seconds |
| Started | Sep 18 06:25:26 AM UTC 24 |
| Finished | Sep 18 06:25:29 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327175847 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.327175847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.141762021 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2011466907 ps |
| CPU time | 8.92 seconds |
| Started | Sep 18 06:25:40 AM UTC 24 |
| Finished | Sep 18 06:25:50 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141762021 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.141762021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3724334128 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 3177451838 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 06:25:34 AM UTC 24 |
| Finished | Sep 18 06:25:39 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724334128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3724334128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2532568238 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 105102825097 ps |
| CPU time | 51.08 seconds |
| Started | Sep 18 06:25:37 AM UTC 24 |
| Finished | Sep 18 06:26:30 AM UTC 24 |
| Peak memory | 211788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532568238 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.2532568238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1616087269 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 28584948469 ps |
| CPU time | 71.21 seconds |
| Started | Sep 18 06:25:39 AM UTC 24 |
| Finished | Sep 18 06:26:52 AM UTC 24 |
| Peak memory | 211992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616087269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.1616087269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1561490088 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 4120806280 ps |
| CPU time | 9.19 seconds |
| Started | Sep 18 06:25:34 AM UTC 24 |
| Finished | Sep 18 06:25:44 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561490088 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.1561490088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.2477934816 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4297252209 ps |
| CPU time | 2.99 seconds |
| Started | Sep 18 06:25:37 AM UTC 24 |
| Finished | Sep 18 06:25:41 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477934816 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.2477934816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1011868676 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2644491300 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 06:25:33 AM UTC 24 |
| Finished | Sep 18 06:25:36 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011868676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1011868676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.4202071101 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2444032774 ps |
| CPU time | 6.95 seconds |
| Started | Sep 18 06:25:30 AM UTC 24 |
| Finished | Sep 18 06:25:38 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202071101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.4202071101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.2651047325 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2189435310 ps |
| CPU time | 7.52 seconds |
| Started | Sep 18 06:25:33 AM UTC 24 |
| Finished | Sep 18 06:25:41 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651047325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.2651047325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2919553762 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2521147610 ps |
| CPU time | 6.57 seconds |
| Started | Sep 18 06:25:33 AM UTC 24 |
| Finished | Sep 18 06:25:40 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919553762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.2919553762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2355385292 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2119541359 ps |
| CPU time | 4.91 seconds |
| Started | Sep 18 06:25:30 AM UTC 24 |
| Finished | Sep 18 06:25:36 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355385292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.2355385292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.130086102 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 11026835837 ps |
| CPU time | 5.1 seconds |
| Started | Sep 18 06:25:39 AM UTC 24 |
| Finished | Sep 18 06:25:45 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130086102 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.130086102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2473480655 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 530850418497 ps |
| CPU time | 30.23 seconds |
| Started | Sep 18 06:25:39 AM UTC 24 |
| Finished | Sep 18 06:26:11 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2473480655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2473480655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1710321780 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3804458217 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 06:25:35 AM UTC 24 |
| Finished | Sep 18 06:25:38 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710321780 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.1710321780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1418831804 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2062248294 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 06:22:36 AM UTC 24 |
| Finished | Sep 18 06:22:38 AM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418831804 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.1418831804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3071538631 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4162343945 ps |
| CPU time | 3.71 seconds |
| Started | Sep 18 06:22:33 AM UTC 24 |
| Finished | Sep 18 06:22:38 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071538631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3071538631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.2615079223 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 82632578711 ps |
| CPU time | 268.61 seconds |
| Started | Sep 18 06:22:35 AM UTC 24 |
| Finished | Sep 18 06:27:07 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615079223 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.2615079223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1222418 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2419667665 ps |
| CPU time | 2.2 seconds |
| Started | Sep 18 06:22:25 AM UTC 24 |
| Finished | Sep 18 06:22:28 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_ TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.1222418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2752793933 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2309690412 ps |
| CPU time | 9.37 seconds |
| Started | Sep 18 06:22:26 AM UTC 24 |
| Finished | Sep 18 06:22:37 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752793933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2752793933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1327916583 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3245652061 ps |
| CPU time | 4.58 seconds |
| Started | Sep 18 06:22:31 AM UTC 24 |
| Finished | Sep 18 06:22:37 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327916583 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.1327916583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3750071227 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3509595114 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 06:22:35 AM UTC 24 |
| Finished | Sep 18 06:22:38 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750071227 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.3750071227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.957118072 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2632256368 ps |
| CPU time | 3.86 seconds |
| Started | Sep 18 06:22:29 AM UTC 24 |
| Finished | Sep 18 06:22:34 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957118072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.957118072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.3742607747 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2462148746 ps |
| CPU time | 5.96 seconds |
| Started | Sep 18 06:22:24 AM UTC 24 |
| Finished | Sep 18 06:22:31 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742607747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.3742607747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2470523685 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2197545105 ps |
| CPU time | 4.39 seconds |
| Started | Sep 18 06:22:28 AM UTC 24 |
| Finished | Sep 18 06:22:34 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470523685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2470523685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.3339095013 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2524221239 ps |
| CPU time | 3.05 seconds |
| Started | Sep 18 06:22:28 AM UTC 24 |
| Finished | Sep 18 06:22:32 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339095013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.3339095013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.796641117 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 22066149514 ps |
| CPU time | 19.1 seconds |
| Started | Sep 18 06:22:36 AM UTC 24 |
| Finished | Sep 18 06:22:56 AM UTC 24 |
| Peak memory | 243548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796641117 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.796641117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.119623678 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2115106735 ps |
| CPU time | 3.38 seconds |
| Started | Sep 18 06:22:23 AM UTC 24 |
| Finished | Sep 18 06:22:27 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119623678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.119623678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.3045907462 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1559244810066 ps |
| CPU time | 531.66 seconds |
| Started | Sep 18 06:22:36 AM UTC 24 |
| Finished | Sep 18 06:31:33 AM UTC 24 |
| Peak memory | 213256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045907462 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.3045907462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.686496902 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3860872594 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 06:22:34 AM UTC 24 |
| Finished | Sep 18 06:22:37 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686496902 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.686496902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.1273744843 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2043354122 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 06:25:47 AM UTC 24 |
| Finished | Sep 18 06:25:50 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273744843 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.1273744843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3490236652 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3438921365 ps |
| CPU time | 11.98 seconds |
| Started | Sep 18 06:25:44 AM UTC 24 |
| Finished | Sep 18 06:25:57 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490236652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.3490236652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.327192292 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 149877549236 ps |
| CPU time | 374.24 seconds |
| Started | Sep 18 06:25:45 AM UTC 24 |
| Finished | Sep 18 06:32:04 AM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327192292 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.327192292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1108680514 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 3913486243 ps |
| CPU time | 7.95 seconds |
| Started | Sep 18 06:25:43 AM UTC 24 |
| Finished | Sep 18 06:25:52 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108680514 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.1108680514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.604368080 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2755129150 ps |
| CPU time | 11.56 seconds |
| Started | Sep 18 06:25:46 AM UTC 24 |
| Finished | Sep 18 06:25:59 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604368080 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.604368080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3942931701 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2620618617 ps |
| CPU time | 4.71 seconds |
| Started | Sep 18 06:25:43 AM UTC 24 |
| Finished | Sep 18 06:25:48 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942931701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.3942931701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.1365351759 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2492874662 ps |
| CPU time | 3.06 seconds |
| Started | Sep 18 06:25:42 AM UTC 24 |
| Finished | Sep 18 06:25:45 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365351759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1365351759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.1746798845 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2159017273 ps |
| CPU time | 3.33 seconds |
| Started | Sep 18 06:25:42 AM UTC 24 |
| Finished | Sep 18 06:25:46 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746798845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.1746798845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3446704820 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2543895382 ps |
| CPU time | 2.07 seconds |
| Started | Sep 18 06:25:43 AM UTC 24 |
| Finished | Sep 18 06:25:46 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446704820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3446704820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1298588825 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2136248403 ps |
| CPU time | 3.15 seconds |
| Started | Sep 18 06:25:41 AM UTC 24 |
| Finished | Sep 18 06:25:46 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298588825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1298588825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.937634000 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 9339680708 ps |
| CPU time | 19.48 seconds |
| Started | Sep 18 06:25:46 AM UTC 24 |
| Finished | Sep 18 06:26:07 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937634000 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.937634000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2555134047 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 9367139845 ps |
| CPU time | 3.68 seconds |
| Started | Sep 18 06:25:45 AM UTC 24 |
| Finished | Sep 18 06:25:50 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555134047 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.2555134047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.4246658646 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2039171573 ps |
| CPU time | 2.33 seconds |
| Started | Sep 18 06:26:01 AM UTC 24 |
| Finished | Sep 18 06:26:05 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246658646 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.4246658646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2223690868 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3456074593 ps |
| CPU time | 7.29 seconds |
| Started | Sep 18 06:25:52 AM UTC 24 |
| Finished | Sep 18 06:26:00 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223690868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.2223690868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.1548931203 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 137416400006 ps |
| CPU time | 96.08 seconds |
| Started | Sep 18 06:25:53 AM UTC 24 |
| Finished | Sep 18 06:27:31 AM UTC 24 |
| Peak memory | 211788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548931203 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.1548931203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2452346613 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 113893253312 ps |
| CPU time | 73.13 seconds |
| Started | Sep 18 06:25:59 AM UTC 24 |
| Finished | Sep 18 06:27:14 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452346613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.2452346613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2539186351 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 4063748482 ps |
| CPU time | 16.72 seconds |
| Started | Sep 18 06:25:51 AM UTC 24 |
| Finished | Sep 18 06:26:09 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539186351 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.2539186351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3903183554 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3544062688 ps |
| CPU time | 7.32 seconds |
| Started | Sep 18 06:25:58 AM UTC 24 |
| Finished | Sep 18 06:26:06 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903183554 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.3903183554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2438481002 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2610545097 ps |
| CPU time | 12.36 seconds |
| Started | Sep 18 06:25:51 AM UTC 24 |
| Finished | Sep 18 06:26:04 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438481002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2438481002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.3363612750 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2451513540 ps |
| CPU time | 10.93 seconds |
| Started | Sep 18 06:25:49 AM UTC 24 |
| Finished | Sep 18 06:26:01 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363612750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.3363612750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.2123479802 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2179271535 ps |
| CPU time | 9.88 seconds |
| Started | Sep 18 06:25:50 AM UTC 24 |
| Finished | Sep 18 06:26:00 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123479802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2123479802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.1545501908 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2509155713 ps |
| CPU time | 10.7 seconds |
| Started | Sep 18 06:25:50 AM UTC 24 |
| Finished | Sep 18 06:26:01 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545501908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.1545501908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.206031839 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2124807127 ps |
| CPU time | 2.27 seconds |
| Started | Sep 18 06:25:47 AM UTC 24 |
| Finished | Sep 18 06:25:50 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206031839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.206031839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2898225455 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 11969577716 ps |
| CPU time | 25.93 seconds |
| Started | Sep 18 06:26:01 AM UTC 24 |
| Finished | Sep 18 06:26:28 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898225455 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.2898225455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2343916862 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 3382406444348 ps |
| CPU time | 399.39 seconds |
| Started | Sep 18 06:25:52 AM UTC 24 |
| Finished | Sep 18 06:32:36 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343916862 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.2343916862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.3125468027 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2019885403 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 06:26:10 AM UTC 24 |
| Finished | Sep 18 06:26:14 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125468027 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.3125468027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2338997391 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3549453922 ps |
| CPU time | 2.98 seconds |
| Started | Sep 18 06:26:07 AM UTC 24 |
| Finished | Sep 18 06:26:11 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338997391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2338997391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.989507870 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 2881619809 ps |
| CPU time | 1.98 seconds |
| Started | Sep 18 06:26:06 AM UTC 24 |
| Finished | Sep 18 06:26:09 AM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989507870 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.989507870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.4195605443 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2609868178 ps |
| CPU time | 7.44 seconds |
| Started | Sep 18 06:26:06 AM UTC 24 |
| Finished | Sep 18 06:26:14 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195605443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.4195605443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.3109598526 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 2498327755 ps |
| CPU time | 3.65 seconds |
| Started | Sep 18 06:26:02 AM UTC 24 |
| Finished | Sep 18 06:26:06 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109598526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3109598526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.2469156760 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2197204991 ps |
| CPU time | 3.25 seconds |
| Started | Sep 18 06:26:03 AM UTC 24 |
| Finished | Sep 18 06:26:07 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469156760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.2469156760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2809944677 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2580947372 ps |
| CPU time | 1.59 seconds |
| Started | Sep 18 06:26:03 AM UTC 24 |
| Finished | Sep 18 06:26:05 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809944677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2809944677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3718710238 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2109289067 ps |
| CPU time | 6.29 seconds |
| Started | Sep 18 06:26:01 AM UTC 24 |
| Finished | Sep 18 06:26:09 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718710238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3718710238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1061133172 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 9117380820 ps |
| CPU time | 19.82 seconds |
| Started | Sep 18 06:26:07 AM UTC 24 |
| Finished | Sep 18 06:26:28 AM UTC 24 |
| Peak memory | 222056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1061133172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1061133172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.330801037 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2025968402 ps |
| CPU time | 5.45 seconds |
| Started | Sep 18 06:26:15 AM UTC 24 |
| Finished | Sep 18 06:26:22 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330801037 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.330801037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.598674266 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3871873734 ps |
| CPU time | 11.24 seconds |
| Started | Sep 18 06:26:12 AM UTC 24 |
| Finished | Sep 18 06:26:24 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598674266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.598674266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.199670155 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 83385780022 ps |
| CPU time | 54.35 seconds |
| Started | Sep 18 06:26:14 AM UTC 24 |
| Finished | Sep 18 06:27:10 AM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199670155 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.199670155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.616901313 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 35970655050 ps |
| CPU time | 116.99 seconds |
| Started | Sep 18 06:26:14 AM UTC 24 |
| Finished | Sep 18 06:28:13 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616901313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.616901313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.658370939 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2987295135 ps |
| CPU time | 10.86 seconds |
| Started | Sep 18 06:26:12 AM UTC 24 |
| Finished | Sep 18 06:26:24 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658370939 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.658370939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2535556582 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2629476898 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 06:26:10 AM UTC 24 |
| Finished | Sep 18 06:26:15 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535556582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.2535556582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.115734531 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2463507906 ps |
| CPU time | 6.11 seconds |
| Started | Sep 18 06:26:10 AM UTC 24 |
| Finished | Sep 18 06:26:17 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115734531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.115734531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.3750280641 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2102316751 ps |
| CPU time | 2.5 seconds |
| Started | Sep 18 06:26:10 AM UTC 24 |
| Finished | Sep 18 06:26:13 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750280641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3750280641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.4189921085 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2511331382 ps |
| CPU time | 5.79 seconds |
| Started | Sep 18 06:26:10 AM UTC 24 |
| Finished | Sep 18 06:26:17 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189921085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.4189921085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1201627436 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2160085279 ps |
| CPU time | 1.76 seconds |
| Started | Sep 18 06:26:10 AM UTC 24 |
| Finished | Sep 18 06:26:12 AM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201627436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1201627436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1174329030 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 17421646203 ps |
| CPU time | 25.77 seconds |
| Started | Sep 18 06:26:15 AM UTC 24 |
| Finished | Sep 18 06:26:42 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174329030 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.1174329030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3815235621 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 8567279879 ps |
| CPU time | 15.06 seconds |
| Started | Sep 18 06:26:15 AM UTC 24 |
| Finished | Sep 18 06:26:32 AM UTC 24 |
| Peak memory | 222036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3815235621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3815235621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.914605998 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2017212150 ps |
| CPU time | 9.44 seconds |
| Started | Sep 18 06:26:25 AM UTC 24 |
| Finished | Sep 18 06:26:36 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914605998 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.914605998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.354644459 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 3728672759 ps |
| CPU time | 3.25 seconds |
| Started | Sep 18 06:26:21 AM UTC 24 |
| Finished | Sep 18 06:26:25 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354644459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.354644459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.2654902252 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 89259947577 ps |
| CPU time | 262.07 seconds |
| Started | Sep 18 06:26:23 AM UTC 24 |
| Finished | Sep 18 06:30:49 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654902252 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.2654902252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1876867931 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 26460698704 ps |
| CPU time | 15.03 seconds |
| Started | Sep 18 06:26:24 AM UTC 24 |
| Finished | Sep 18 06:26:41 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876867931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_with_pre_cond.1876867931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1816880349 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3369883950 ps |
| CPU time | 10.89 seconds |
| Started | Sep 18 06:26:21 AM UTC 24 |
| Finished | Sep 18 06:26:33 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816880349 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.1816880349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.3736562837 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3524785793 ps |
| CPU time | 7.46 seconds |
| Started | Sep 18 06:26:23 AM UTC 24 |
| Finished | Sep 18 06:26:32 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736562837 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.3736562837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.4167701499 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2610773136 ps |
| CPU time | 12.75 seconds |
| Started | Sep 18 06:26:18 AM UTC 24 |
| Finished | Sep 18 06:26:32 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167701499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.4167701499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.1553698702 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2486737154 ps |
| CPU time | 2.82 seconds |
| Started | Sep 18 06:26:17 AM UTC 24 |
| Finished | Sep 18 06:26:20 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553698702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.1553698702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.787986082 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2236985016 ps |
| CPU time | 2.43 seconds |
| Started | Sep 18 06:26:17 AM UTC 24 |
| Finished | Sep 18 06:26:20 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787986082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.787986082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.1844471338 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 2520758868 ps |
| CPU time | 6.84 seconds |
| Started | Sep 18 06:26:18 AM UTC 24 |
| Finished | Sep 18 06:26:26 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844471338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.1844471338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.300960243 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2107764506 ps |
| CPU time | 7.92 seconds |
| Started | Sep 18 06:26:16 AM UTC 24 |
| Finished | Sep 18 06:26:24 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300960243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.300960243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.481667757 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 13327114120 ps |
| CPU time | 8.77 seconds |
| Started | Sep 18 06:26:25 AM UTC 24 |
| Finished | Sep 18 06:26:35 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481667757 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.481667757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2234662599 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 14066604925 ps |
| CPU time | 11.66 seconds |
| Started | Sep 18 06:26:24 AM UTC 24 |
| Finished | Sep 18 06:26:38 AM UTC 24 |
| Peak memory | 222048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2234662599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2234662599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3726712233 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 150497237013 ps |
| CPU time | 21.61 seconds |
| Started | Sep 18 06:26:23 AM UTC 24 |
| Finished | Sep 18 06:26:46 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726712233 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.3726712233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.3723235665 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2012104895 ps |
| CPU time | 5.73 seconds |
| Started | Sep 18 06:26:35 AM UTC 24 |
| Finished | Sep 18 06:26:42 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723235665 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.3723235665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3087133418 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2994014445 ps |
| CPU time | 11.36 seconds |
| Started | Sep 18 06:26:32 AM UTC 24 |
| Finished | Sep 18 06:26:45 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087133418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.3087133418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.4281801801 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 108196591396 ps |
| CPU time | 96.57 seconds |
| Started | Sep 18 06:26:32 AM UTC 24 |
| Finished | Sep 18 06:28:11 AM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281801801 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.4281801801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2293923283 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 42163795670 ps |
| CPU time | 64.63 seconds |
| Started | Sep 18 06:26:32 AM UTC 24 |
| Finished | Sep 18 06:27:39 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293923283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.2293923283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.521940463 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 783246012274 ps |
| CPU time | 2807 seconds |
| Started | Sep 18 06:26:31 AM UTC 24 |
| Finished | Sep 18 07:13:45 AM UTC 24 |
| Peak memory | 213252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521940463 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.521940463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.546824105 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 6285650561 ps |
| CPU time | 10.65 seconds |
| Started | Sep 18 06:26:32 AM UTC 24 |
| Finished | Sep 18 06:26:44 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546824105 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.546824105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.784079025 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2617562587 ps |
| CPU time | 6.1 seconds |
| Started | Sep 18 06:26:31 AM UTC 24 |
| Finished | Sep 18 06:26:38 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784079025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.784079025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.3663553374 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2479831141 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 06:26:27 AM UTC 24 |
| Finished | Sep 18 06:26:32 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663553374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.3663553374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2296772627 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2150806378 ps |
| CPU time | 4.3 seconds |
| Started | Sep 18 06:26:29 AM UTC 24 |
| Finished | Sep 18 06:26:34 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296772627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.2296772627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.1845723422 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2519253631 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 06:26:30 AM UTC 24 |
| Finished | Sep 18 06:26:35 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845723422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1845723422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.730170324 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2109884930 ps |
| CPU time | 7.87 seconds |
| Started | Sep 18 06:26:27 AM UTC 24 |
| Finished | Sep 18 06:26:35 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730170324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.730170324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.644117829 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 214339658253 ps |
| CPU time | 287.03 seconds |
| Started | Sep 18 06:26:35 AM UTC 24 |
| Finished | Sep 18 06:31:26 AM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644117829 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.644117829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3952981190 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 9993517493 ps |
| CPU time | 14.9 seconds |
| Started | Sep 18 06:26:32 AM UTC 24 |
| Finished | Sep 18 06:26:48 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952981190 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.3952981190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.4243369357 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 2016269718 ps |
| CPU time | 5.91 seconds |
| Started | Sep 18 06:26:43 AM UTC 24 |
| Finished | Sep 18 06:26:51 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243369357 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.4243369357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3482224235 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 3036091096 ps |
| CPU time | 3.07 seconds |
| Started | Sep 18 06:26:39 AM UTC 24 |
| Finished | Sep 18 06:26:43 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482224235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3482224235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3330362626 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 46263320143 ps |
| CPU time | 117.7 seconds |
| Started | Sep 18 06:26:42 AM UTC 24 |
| Finished | Sep 18 06:28:42 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330362626 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.3330362626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.548220158 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 21354079384 ps |
| CPU time | 16.78 seconds |
| Started | Sep 18 06:26:43 AM UTC 24 |
| Finished | Sep 18 06:27:01 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548220158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_with_pre_cond.548220158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2463886383 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 5332667840 ps |
| CPU time | 14.76 seconds |
| Started | Sep 18 06:26:39 AM UTC 24 |
| Finished | Sep 18 06:26:55 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463886383 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.2463886383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3862177865 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 4632701790 ps |
| CPU time | 9.35 seconds |
| Started | Sep 18 06:26:42 AM UTC 24 |
| Finished | Sep 18 06:26:53 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862177865 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.3862177865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.318039436 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2618952080 ps |
| CPU time | 5.32 seconds |
| Started | Sep 18 06:26:38 AM UTC 24 |
| Finished | Sep 18 06:26:44 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318039436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.318039436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3225138466 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 2474981523 ps |
| CPU time | 3.05 seconds |
| Started | Sep 18 06:26:37 AM UTC 24 |
| Finished | Sep 18 06:26:41 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225138466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3225138466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.579397641 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2185915656 ps |
| CPU time | 3.33 seconds |
| Started | Sep 18 06:26:37 AM UTC 24 |
| Finished | Sep 18 06:26:41 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579397641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.579397641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.3974915192 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2515805850 ps |
| CPU time | 5.44 seconds |
| Started | Sep 18 06:26:38 AM UTC 24 |
| Finished | Sep 18 06:26:44 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974915192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.3974915192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.980907945 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2110941769 ps |
| CPU time | 9.74 seconds |
| Started | Sep 18 06:26:37 AM UTC 24 |
| Finished | Sep 18 06:26:47 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980907945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.980907945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.1738889319 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 14262419043 ps |
| CPU time | 13.1 seconds |
| Started | Sep 18 06:26:43 AM UTC 24 |
| Finished | Sep 18 06:26:58 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738889319 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.1738889319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.17813163 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 8445413448 ps |
| CPU time | 14.81 seconds |
| Started | Sep 18 06:26:43 AM UTC 24 |
| Finished | Sep 18 06:26:59 AM UTC 24 |
| Peak memory | 222116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=17813163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.17813163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3764918276 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 8637880479 ps |
| CPU time | 2.54 seconds |
| Started | Sep 18 06:26:41 AM UTC 24 |
| Finished | Sep 18 06:26:45 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764918276 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.3764918276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2766657885 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2014431671 ps |
| CPU time | 6.24 seconds |
| Started | Sep 18 06:26:52 AM UTC 24 |
| Finished | Sep 18 06:27:00 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766657885 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.2766657885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.298735168 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3209736939 ps |
| CPU time | 3.86 seconds |
| Started | Sep 18 06:26:48 AM UTC 24 |
| Finished | Sep 18 06:26:53 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298735168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.298735168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.866025557 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 47151791484 ps |
| CPU time | 35.77 seconds |
| Started | Sep 18 06:26:49 AM UTC 24 |
| Finished | Sep 18 06:27:26 AM UTC 24 |
| Peak memory | 211928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866025557 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.866025557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.4083563796 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 4775086664 ps |
| CPU time | 5.58 seconds |
| Started | Sep 18 06:26:47 AM UTC 24 |
| Finished | Sep 18 06:26:54 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083563796 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.4083563796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.1859536019 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 6251049532 ps |
| CPU time | 4.83 seconds |
| Started | Sep 18 06:26:50 AM UTC 24 |
| Finished | Sep 18 06:26:56 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859536019 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.1859536019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3410790867 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2623757730 ps |
| CPU time | 4.35 seconds |
| Started | Sep 18 06:26:46 AM UTC 24 |
| Finished | Sep 18 06:26:51 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410790867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3410790867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.504412237 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 2460283271 ps |
| CPU time | 9.45 seconds |
| Started | Sep 18 06:26:46 AM UTC 24 |
| Finished | Sep 18 06:26:56 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504412237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.504412237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3362027443 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2184538998 ps |
| CPU time | 3.36 seconds |
| Started | Sep 18 06:26:46 AM UTC 24 |
| Finished | Sep 18 06:26:50 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362027443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3362027443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.3638728712 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2525705830 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 06:26:46 AM UTC 24 |
| Finished | Sep 18 06:26:51 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638728712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3638728712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.3955897587 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2110302683 ps |
| CPU time | 7.6 seconds |
| Started | Sep 18 06:26:46 AM UTC 24 |
| Finished | Sep 18 06:26:55 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955897587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.3955897587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3681110691 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 6479355182 ps |
| CPU time | 20.78 seconds |
| Started | Sep 18 06:26:51 AM UTC 24 |
| Finished | Sep 18 06:27:13 AM UTC 24 |
| Peak memory | 222048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3681110691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.3681110691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2977756552 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 6355116937 ps |
| CPU time | 4.08 seconds |
| Started | Sep 18 06:26:48 AM UTC 24 |
| Finished | Sep 18 06:26:53 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977756552 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.2977756552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.812777174 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2038646428 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 06:26:59 AM UTC 24 |
| Finished | Sep 18 06:27:04 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812777174 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.812777174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2295761474 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 3007170272 ps |
| CPU time | 8.45 seconds |
| Started | Sep 18 06:26:56 AM UTC 24 |
| Finished | Sep 18 06:27:05 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295761474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2295761474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.36914944 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 48620778238 ps |
| CPU time | 27.21 seconds |
| Started | Sep 18 06:26:56 AM UTC 24 |
| Finished | Sep 18 06:27:24 AM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36914944 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.36914944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2089362687 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 57992165687 ps |
| CPU time | 59.23 seconds |
| Started | Sep 18 06:26:57 AM UTC 24 |
| Finished | Sep 18 06:27:58 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089362687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_with_pre_cond.2089362687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1211961899 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3019254859 ps |
| CPU time | 4.14 seconds |
| Started | Sep 18 06:26:55 AM UTC 24 |
| Finished | Sep 18 06:27:00 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211961899 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.1211961899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.1785985725 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3321287075 ps |
| CPU time | 6.27 seconds |
| Started | Sep 18 06:26:57 AM UTC 24 |
| Finished | Sep 18 06:27:04 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785985725 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.1785985725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3910197915 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2612414350 ps |
| CPU time | 9.74 seconds |
| Started | Sep 18 06:26:54 AM UTC 24 |
| Finished | Sep 18 06:27:05 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910197915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3910197915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3600547142 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2469375913 ps |
| CPU time | 8.52 seconds |
| Started | Sep 18 06:26:54 AM UTC 24 |
| Finished | Sep 18 06:27:03 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600547142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3600547142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2709093289 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2260943801 ps |
| CPU time | 4.1 seconds |
| Started | Sep 18 06:26:54 AM UTC 24 |
| Finished | Sep 18 06:26:59 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709093289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.2709093289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.568218180 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2520009844 ps |
| CPU time | 6.71 seconds |
| Started | Sep 18 06:26:54 AM UTC 24 |
| Finished | Sep 18 06:27:01 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568218180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.568218180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2182960167 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2109378924 ps |
| CPU time | 10.14 seconds |
| Started | Sep 18 06:26:53 AM UTC 24 |
| Finished | Sep 18 06:27:04 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182960167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2182960167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.3045528366 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 10090814832 ps |
| CPU time | 18.11 seconds |
| Started | Sep 18 06:26:58 AM UTC 24 |
| Finished | Sep 18 06:27:18 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045528366 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.3045528366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.590736917 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 9581417850 ps |
| CPU time | 4.2 seconds |
| Started | Sep 18 06:26:56 AM UTC 24 |
| Finished | Sep 18 06:27:01 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590736917 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.590736917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2282595619 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2060479984 ps |
| CPU time | 1.88 seconds |
| Started | Sep 18 06:27:06 AM UTC 24 |
| Finished | Sep 18 06:27:09 AM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282595619 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.2282595619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.310264213 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3205529715 ps |
| CPU time | 5.34 seconds |
| Started | Sep 18 06:27:04 AM UTC 24 |
| Finished | Sep 18 06:27:10 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310264213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.310264213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.1131304448 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 144496303438 ps |
| CPU time | 125.59 seconds |
| Started | Sep 18 06:27:05 AM UTC 24 |
| Finished | Sep 18 06:29:13 AM UTC 24 |
| Peak memory | 211788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131304448 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.1131304448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.58410347 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 110221084075 ps |
| CPU time | 52.91 seconds |
| Started | Sep 18 06:27:05 AM UTC 24 |
| Finished | Sep 18 06:27:59 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58410347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.58410347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.4143110631 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4114955601 ps |
| CPU time | 8.53 seconds |
| Started | Sep 18 06:27:02 AM UTC 24 |
| Finished | Sep 18 06:27:11 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143110631 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.4143110631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.1424976322 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2791065803 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 06:27:05 AM UTC 24 |
| Finished | Sep 18 06:27:12 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424976322 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.1424976322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1810285328 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2615789988 ps |
| CPU time | 5.06 seconds |
| Started | Sep 18 06:27:02 AM UTC 24 |
| Finished | Sep 18 06:27:08 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810285328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1810285328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.1519644600 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2445244224 ps |
| CPU time | 11.95 seconds |
| Started | Sep 18 06:27:01 AM UTC 24 |
| Finished | Sep 18 06:27:14 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519644600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.1519644600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.4169417228 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2142604314 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 06:27:01 AM UTC 24 |
| Finished | Sep 18 06:27:05 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169417228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.4169417228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1222033883 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2509661153 ps |
| CPU time | 8.3 seconds |
| Started | Sep 18 06:27:02 AM UTC 24 |
| Finished | Sep 18 06:27:11 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222033883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1222033883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.3360925049 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2131567007 ps |
| CPU time | 3.29 seconds |
| Started | Sep 18 06:27:01 AM UTC 24 |
| Finished | Sep 18 06:27:05 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360925049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3360925049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.2004892890 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 147531579878 ps |
| CPU time | 253.97 seconds |
| Started | Sep 18 06:27:06 AM UTC 24 |
| Finished | Sep 18 06:31:24 AM UTC 24 |
| Peak memory | 211668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004892890 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.2004892890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3280144425 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4157888946 ps |
| CPU time | 16.99 seconds |
| Started | Sep 18 06:27:05 AM UTC 24 |
| Finished | Sep 18 06:27:23 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3280144425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.3280144425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3004878339 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3195164681 ps |
| CPU time | 9.52 seconds |
| Started | Sep 18 06:27:05 AM UTC 24 |
| Finished | Sep 18 06:27:15 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004878339 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.3004878339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.4221512027 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2012433064 ps |
| CPU time | 11.3 seconds |
| Started | Sep 18 06:22:47 AM UTC 24 |
| Finished | Sep 18 06:23:00 AM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221512027 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.4221512027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1110033602 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3275839521 ps |
| CPU time | 5.32 seconds |
| Started | Sep 18 06:22:41 AM UTC 24 |
| Finished | Sep 18 06:22:47 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110033602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.1110033602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.894954221 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 89610138946 ps |
| CPU time | 210.37 seconds |
| Started | Sep 18 06:22:43 AM UTC 24 |
| Finished | Sep 18 06:26:16 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894954221 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.894954221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4157995730 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2360037050 ps |
| CPU time | 6.71 seconds |
| Started | Sep 18 06:22:38 AM UTC 24 |
| Finished | Sep 18 06:22:46 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157995730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4157995730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2843165672 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 97109710988 ps |
| CPU time | 291.15 seconds |
| Started | Sep 18 06:22:44 AM UTC 24 |
| Finished | Sep 18 06:27:39 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843165672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.2843165672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1800748407 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2860337406 ps |
| CPU time | 4.27 seconds |
| Started | Sep 18 06:22:39 AM UTC 24 |
| Finished | Sep 18 06:22:45 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800748407 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.1800748407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.715069262 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3293888481 ps |
| CPU time | 8.75 seconds |
| Started | Sep 18 06:22:43 AM UTC 24 |
| Finished | Sep 18 06:22:52 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715069262 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.715069262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3574901558 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2609569259 ps |
| CPU time | 9.11 seconds |
| Started | Sep 18 06:22:39 AM UTC 24 |
| Finished | Sep 18 06:22:50 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574901558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.3574901558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.1149910002 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2517780022 ps |
| CPU time | 2.22 seconds |
| Started | Sep 18 06:22:37 AM UTC 24 |
| Finished | Sep 18 06:22:40 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149910002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1149910002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.1473877391 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2134750520 ps |
| CPU time | 3.11 seconds |
| Started | Sep 18 06:22:38 AM UTC 24 |
| Finished | Sep 18 06:22:42 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473877391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1473877391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.3307933559 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2512127699 ps |
| CPU time | 8.28 seconds |
| Started | Sep 18 06:22:38 AM UTC 24 |
| Finished | Sep 18 06:22:48 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307933559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.3307933559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.698031699 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 22100528508 ps |
| CPU time | 22.89 seconds |
| Started | Sep 18 06:22:46 AM UTC 24 |
| Finished | Sep 18 06:23:10 AM UTC 24 |
| Peak memory | 243548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698031699 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.698031699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.3998546878 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2172148672 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 06:22:37 AM UTC 24 |
| Finished | Sep 18 06:22:40 AM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998546878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.3998546878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4028970483 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 10439526170 ps |
| CPU time | 8.38 seconds |
| Started | Sep 18 06:22:44 AM UTC 24 |
| Finished | Sep 18 06:22:53 AM UTC 24 |
| Peak memory | 222328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4028970483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.4028970483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2900655385 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4732872833 ps |
| CPU time | 3.97 seconds |
| Started | Sep 18 06:22:42 AM UTC 24 |
| Finished | Sep 18 06:22:47 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900655385 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.2900655385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.120772042 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2039559598 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 06:27:14 AM UTC 24 |
| Finished | Sep 18 06:27:19 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120772042 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.120772042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.734506943 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3738069701 ps |
| CPU time | 14.4 seconds |
| Started | Sep 18 06:27:12 AM UTC 24 |
| Finished | Sep 18 06:27:27 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734506943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.734506943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.93759139 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 33231388133 ps |
| CPU time | 118.8 seconds |
| Started | Sep 18 06:27:12 AM UTC 24 |
| Finished | Sep 18 06:29:13 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93759139 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.93759139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1584169693 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 41823385647 ps |
| CPU time | 108.43 seconds |
| Started | Sep 18 06:27:13 AM UTC 24 |
| Finished | Sep 18 06:29:03 AM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584169693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_with_pre_cond.1584169693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.997325876 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2897051937 ps |
| CPU time | 10.99 seconds |
| Started | Sep 18 06:27:11 AM UTC 24 |
| Finished | Sep 18 06:27:23 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997325876 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.997325876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1526208179 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2817909800 ps |
| CPU time | 7.98 seconds |
| Started | Sep 18 06:27:12 AM UTC 24 |
| Finished | Sep 18 06:27:21 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526208179 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.1526208179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2038037427 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2612776047 ps |
| CPU time | 11.83 seconds |
| Started | Sep 18 06:27:11 AM UTC 24 |
| Finished | Sep 18 06:27:24 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038037427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.2038037427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.987467586 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2482134762 ps |
| CPU time | 4.14 seconds |
| Started | Sep 18 06:27:07 AM UTC 24 |
| Finished | Sep 18 06:27:13 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987467586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.987467586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.841240592 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2055928334 ps |
| CPU time | 6.37 seconds |
| Started | Sep 18 06:27:09 AM UTC 24 |
| Finished | Sep 18 06:27:16 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841240592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.841240592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.379870979 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2511385863 ps |
| CPU time | 7.61 seconds |
| Started | Sep 18 06:27:10 AM UTC 24 |
| Finished | Sep 18 06:27:18 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379870979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.379870979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.285929659 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2133269968 ps |
| CPU time | 3.38 seconds |
| Started | Sep 18 06:27:06 AM UTC 24 |
| Finished | Sep 18 06:27:11 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285929659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.285929659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.4162328011 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 6789680130 ps |
| CPU time | 6.29 seconds |
| Started | Sep 18 06:27:14 AM UTC 24 |
| Finished | Sep 18 06:27:22 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162328011 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.4162328011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.208438614 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 4960861371 ps |
| CPU time | 22.12 seconds |
| Started | Sep 18 06:27:13 AM UTC 24 |
| Finished | Sep 18 06:27:36 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=208438614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.208438614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1643968324 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 6423311392 ps |
| CPU time | 8.9 seconds |
| Started | Sep 18 06:27:12 AM UTC 24 |
| Finished | Sep 18 06:27:22 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643968324 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.1643968324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.249159313 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2013160719 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 06:27:22 AM UTC 24 |
| Finished | Sep 18 06:27:28 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249159313 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.249159313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3565782345 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3176484706 ps |
| CPU time | 4.38 seconds |
| Started | Sep 18 06:27:19 AM UTC 24 |
| Finished | Sep 18 06:27:24 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565782345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.3565782345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.371760712 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 198822662029 ps |
| CPU time | 735.49 seconds |
| Started | Sep 18 06:27:20 AM UTC 24 |
| Finished | Sep 18 06:39:43 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371760712 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.371760712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3827552127 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 41125561730 ps |
| CPU time | 86.93 seconds |
| Started | Sep 18 06:27:22 AM UTC 24 |
| Finished | Sep 18 06:28:51 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827552127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.3827552127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1021351668 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3545696908 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 06:27:19 AM UTC 24 |
| Finished | Sep 18 06:27:21 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021351668 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.1021351668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.1171712908 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3165262174 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 06:27:21 AM UTC 24 |
| Finished | Sep 18 06:27:24 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171712908 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.1171712908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.4041450547 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2628319894 ps |
| CPU time | 3.88 seconds |
| Started | Sep 18 06:27:17 AM UTC 24 |
| Finished | Sep 18 06:27:22 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041450547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.4041450547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2550705094 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 2460044842 ps |
| CPU time | 3.67 seconds |
| Started | Sep 18 06:27:16 AM UTC 24 |
| Finished | Sep 18 06:27:20 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550705094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.2550705094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.221538201 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2344915334 ps |
| CPU time | 1.74 seconds |
| Started | Sep 18 06:27:16 AM UTC 24 |
| Finished | Sep 18 06:27:18 AM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221538201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.221538201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.848817301 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2513733640 ps |
| CPU time | 10.43 seconds |
| Started | Sep 18 06:27:17 AM UTC 24 |
| Finished | Sep 18 06:27:28 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848817301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.848817301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.34677420 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2119590964 ps |
| CPU time | 5.8 seconds |
| Started | Sep 18 06:27:14 AM UTC 24 |
| Finished | Sep 18 06:27:21 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34677420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.34677420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3482658280 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 74111104720 ps |
| CPU time | 217.56 seconds |
| Started | Sep 18 06:27:22 AM UTC 24 |
| Finished | Sep 18 06:31:03 AM UTC 24 |
| Peak memory | 211808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482658280 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.3482658280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1368591130 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 21775650074 ps |
| CPU time | 15.09 seconds |
| Started | Sep 18 06:27:22 AM UTC 24 |
| Finished | Sep 18 06:27:38 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1368591130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.1368591130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1624913860 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 15035037911 ps |
| CPU time | 3.37 seconds |
| Started | Sep 18 06:27:19 AM UTC 24 |
| Finished | Sep 18 06:27:23 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624913860 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.1624913860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.4221717371 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2013589411 ps |
| CPU time | 5.78 seconds |
| Started | Sep 18 06:27:28 AM UTC 24 |
| Finished | Sep 18 06:27:35 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221717371 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.4221717371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.391905459 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3315723388 ps |
| CPU time | 4.46 seconds |
| Started | Sep 18 06:27:25 AM UTC 24 |
| Finished | Sep 18 06:27:30 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391905459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.391905459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.844891605 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 109759383293 ps |
| CPU time | 289.59 seconds |
| Started | Sep 18 06:27:25 AM UTC 24 |
| Finished | Sep 18 06:32:18 AM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844891605 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.844891605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3603951513 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 49554040446 ps |
| CPU time | 130.06 seconds |
| Started | Sep 18 06:27:27 AM UTC 24 |
| Finished | Sep 18 06:29:39 AM UTC 24 |
| Peak memory | 211812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603951513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_with_pre_cond.3603951513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2239171798 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4217156577 ps |
| CPU time | 11.26 seconds |
| Started | Sep 18 06:27:24 AM UTC 24 |
| Finished | Sep 18 06:27:36 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239171798 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.2239171798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.3197199309 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5467522385 ps |
| CPU time | 15.6 seconds |
| Started | Sep 18 06:27:25 AM UTC 24 |
| Finished | Sep 18 06:27:42 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197199309 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.3197199309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.137727426 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2622408432 ps |
| CPU time | 3.4 seconds |
| Started | Sep 18 06:27:24 AM UTC 24 |
| Finished | Sep 18 06:27:28 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137727426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.137727426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1836699790 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2466426769 ps |
| CPU time | 9.94 seconds |
| Started | Sep 18 06:27:24 AM UTC 24 |
| Finished | Sep 18 06:27:35 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836699790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.1836699790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.3329031636 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2065919899 ps |
| CPU time | 1.9 seconds |
| Started | Sep 18 06:27:24 AM UTC 24 |
| Finished | Sep 18 06:27:26 AM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329031636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3329031636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.414365485 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2538421907 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 06:27:24 AM UTC 24 |
| Finished | Sep 18 06:27:28 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414365485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.414365485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.1071907258 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2111345724 ps |
| CPU time | 6.65 seconds |
| Started | Sep 18 06:27:22 AM UTC 24 |
| Finished | Sep 18 06:27:30 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071907258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1071907258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.2731125092 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 13968020405 ps |
| CPU time | 16.21 seconds |
| Started | Sep 18 06:27:28 AM UTC 24 |
| Finished | Sep 18 06:27:46 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731125092 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.2731125092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2516518585 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 5426736667 ps |
| CPU time | 26.81 seconds |
| Started | Sep 18 06:27:27 AM UTC 24 |
| Finished | Sep 18 06:27:55 AM UTC 24 |
| Peak memory | 222164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2516518585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2516518585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.3255335910 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2038383934 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 06:27:37 AM UTC 24 |
| Finished | Sep 18 06:27:41 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255335910 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.3255335910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3855391198 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 67243352497 ps |
| CPU time | 54.96 seconds |
| Started | Sep 18 06:27:33 AM UTC 24 |
| Finished | Sep 18 06:28:29 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855391198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.3855391198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.117292065 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 29883821794 ps |
| CPU time | 43.27 seconds |
| Started | Sep 18 06:27:36 AM UTC 24 |
| Finished | Sep 18 06:28:21 AM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117292065 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.117292065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.4105101117 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 46259060652 ps |
| CPU time | 21.59 seconds |
| Started | Sep 18 06:27:37 AM UTC 24 |
| Finished | Sep 18 06:28:00 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105101117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_with_pre_cond.4105101117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1294572988 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 4389070065 ps |
| CPU time | 19.18 seconds |
| Started | Sep 18 06:27:32 AM UTC 24 |
| Finished | Sep 18 06:27:52 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294572988 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.1294572988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3403939040 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4466683709 ps |
| CPU time | 5.3 seconds |
| Started | Sep 18 06:27:37 AM UTC 24 |
| Finished | Sep 18 06:27:43 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403939040 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.3403939040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1096065835 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2635564905 ps |
| CPU time | 3.94 seconds |
| Started | Sep 18 06:27:32 AM UTC 24 |
| Finished | Sep 18 06:27:37 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096065835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.1096065835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3006346701 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2538146711 ps |
| CPU time | 1.88 seconds |
| Started | Sep 18 06:27:29 AM UTC 24 |
| Finished | Sep 18 06:27:32 AM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006346701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3006346701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.360554306 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2198861364 ps |
| CPU time | 8.45 seconds |
| Started | Sep 18 06:27:30 AM UTC 24 |
| Finished | Sep 18 06:27:39 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360554306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.360554306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.1434717383 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 2509407161 ps |
| CPU time | 11.35 seconds |
| Started | Sep 18 06:27:31 AM UTC 24 |
| Finished | Sep 18 06:27:43 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434717383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1434717383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2216084086 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2114192101 ps |
| CPU time | 5.72 seconds |
| Started | Sep 18 06:27:29 AM UTC 24 |
| Finished | Sep 18 06:27:36 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216084086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2216084086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3927871458 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 9302177793 ps |
| CPU time | 11.08 seconds |
| Started | Sep 18 06:27:37 AM UTC 24 |
| Finished | Sep 18 06:27:49 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927871458 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.3927871458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2367285608 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 21459081464 ps |
| CPU time | 15.72 seconds |
| Started | Sep 18 06:27:37 AM UTC 24 |
| Finished | Sep 18 06:27:54 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2367285608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2367285608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1579361470 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1670538758783 ps |
| CPU time | 560.05 seconds |
| Started | Sep 18 06:27:35 AM UTC 24 |
| Finished | Sep 18 06:37:01 AM UTC 24 |
| Peak memory | 213256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579361470 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.1579361470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1714457838 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2011476793 ps |
| CPU time | 9.94 seconds |
| Started | Sep 18 06:27:50 AM UTC 24 |
| Finished | Sep 18 06:28:02 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714457838 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.1714457838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1143192064 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 3328975852 ps |
| CPU time | 14.78 seconds |
| Started | Sep 18 06:27:44 AM UTC 24 |
| Finished | Sep 18 06:28:00 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143192064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.1143192064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.1633135069 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 38239054228 ps |
| CPU time | 107.24 seconds |
| Started | Sep 18 06:27:45 AM UTC 24 |
| Finished | Sep 18 06:29:34 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633135069 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.1633135069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.425154535 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 61010445412 ps |
| CPU time | 133.3 seconds |
| Started | Sep 18 06:27:46 AM UTC 24 |
| Finished | Sep 18 06:30:02 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425154535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_with_pre_cond.425154535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.72639708 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4410440194 ps |
| CPU time | 25.4 seconds |
| Started | Sep 18 06:27:43 AM UTC 24 |
| Finished | Sep 18 06:28:09 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72639708 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.72639708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.3358218289 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3285507090 ps |
| CPU time | 4.81 seconds |
| Started | Sep 18 06:27:45 AM UTC 24 |
| Finished | Sep 18 06:27:51 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358218289 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.3358218289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2874396212 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2618365813 ps |
| CPU time | 6.68 seconds |
| Started | Sep 18 06:27:42 AM UTC 24 |
| Finished | Sep 18 06:27:49 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874396212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.2874396212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.1310714690 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2449979044 ps |
| CPU time | 8.05 seconds |
| Started | Sep 18 06:27:39 AM UTC 24 |
| Finished | Sep 18 06:27:49 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310714690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1310714690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3904110701 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 2099270385 ps |
| CPU time | 10.73 seconds |
| Started | Sep 18 06:27:39 AM UTC 24 |
| Finished | Sep 18 06:27:51 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904110701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3904110701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.907020689 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2536615857 ps |
| CPU time | 2.43 seconds |
| Started | Sep 18 06:27:41 AM UTC 24 |
| Finished | Sep 18 06:27:44 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907020689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.907020689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.2691987842 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2122828309 ps |
| CPU time | 3.72 seconds |
| Started | Sep 18 06:27:39 AM UTC 24 |
| Finished | Sep 18 06:27:44 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691987842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2691987842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.563826887 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 77116320602 ps |
| CPU time | 81.35 seconds |
| Started | Sep 18 06:27:49 AM UTC 24 |
| Finished | Sep 18 06:29:12 AM UTC 24 |
| Peak memory | 211660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563826887 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.563826887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3719447770 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4419705299 ps |
| CPU time | 20.4 seconds |
| Started | Sep 18 06:27:49 AM UTC 24 |
| Finished | Sep 18 06:28:11 AM UTC 24 |
| Peak memory | 228128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3719447770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.3719447770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2922157250 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 5204805778 ps |
| CPU time | 3.81 seconds |
| Started | Sep 18 06:27:44 AM UTC 24 |
| Finished | Sep 18 06:27:49 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922157250 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.2922157250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.413058231 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2077641355 ps |
| CPU time | 1.9 seconds |
| Started | Sep 18 06:28:00 AM UTC 24 |
| Finished | Sep 18 06:28:03 AM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413058231 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.413058231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.937864679 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 3924399774 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 06:27:56 AM UTC 24 |
| Finished | Sep 18 06:27:59 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937864679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.937864679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.1640490259 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 43552480675 ps |
| CPU time | 42.33 seconds |
| Started | Sep 18 06:27:58 AM UTC 24 |
| Finished | Sep 18 06:28:42 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640490259 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.1640490259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1695141910 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 60180135731 ps |
| CPU time | 44.32 seconds |
| Started | Sep 18 06:27:59 AM UTC 24 |
| Finished | Sep 18 06:28:45 AM UTC 24 |
| Peak memory | 211808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695141910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.1695141910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3965696399 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3453719963 ps |
| CPU time | 12.54 seconds |
| Started | Sep 18 06:27:55 AM UTC 24 |
| Finished | Sep 18 06:28:08 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965696399 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.3965696399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2360275068 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2550182650 ps |
| CPU time | 12.16 seconds |
| Started | Sep 18 06:27:59 AM UTC 24 |
| Finished | Sep 18 06:28:12 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360275068 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.2360275068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2830909826 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2626551951 ps |
| CPU time | 2.83 seconds |
| Started | Sep 18 06:27:55 AM UTC 24 |
| Finished | Sep 18 06:27:59 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830909826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.2830909826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.801591780 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2485620054 ps |
| CPU time | 2.46 seconds |
| Started | Sep 18 06:27:51 AM UTC 24 |
| Finished | Sep 18 06:27:55 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801591780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.801591780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.3236084701 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2133699503 ps |
| CPU time | 7.81 seconds |
| Started | Sep 18 06:27:53 AM UTC 24 |
| Finished | Sep 18 06:28:01 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236084701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.3236084701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.556297298 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2527769262 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 06:27:53 AM UTC 24 |
| Finished | Sep 18 06:27:57 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556297298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.556297298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.3529856949 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2137288030 ps |
| CPU time | 2.83 seconds |
| Started | Sep 18 06:27:50 AM UTC 24 |
| Finished | Sep 18 06:27:54 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529856949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.3529856949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1191993740 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 11032795382 ps |
| CPU time | 20.79 seconds |
| Started | Sep 18 06:27:59 AM UTC 24 |
| Finished | Sep 18 06:28:21 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191993740 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.1191993740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2456934918 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 6336345863 ps |
| CPU time | 10.22 seconds |
| Started | Sep 18 06:27:59 AM UTC 24 |
| Finished | Sep 18 06:28:11 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2456934918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2456934918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3292144487 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2040762460 ps |
| CPU time | 2.9 seconds |
| Started | Sep 18 06:28:11 AM UTC 24 |
| Finished | Sep 18 06:28:16 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292144487 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.3292144487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3435066608 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3636784302 ps |
| CPU time | 9.55 seconds |
| Started | Sep 18 06:28:04 AM UTC 24 |
| Finished | Sep 18 06:28:15 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435066608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.3435066608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.3106845925 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 109722758126 ps |
| CPU time | 49.54 seconds |
| Started | Sep 18 06:28:05 AM UTC 24 |
| Finished | Sep 18 06:28:56 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106845925 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.3106845925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2625925195 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4266752475 ps |
| CPU time | 17.58 seconds |
| Started | Sep 18 06:28:03 AM UTC 24 |
| Finished | Sep 18 06:28:22 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625925195 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.2625925195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.375804339 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3359735583 ps |
| CPU time | 12.82 seconds |
| Started | Sep 18 06:28:06 AM UTC 24 |
| Finished | Sep 18 06:28:20 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375804339 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.375804339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1979706126 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 2610225998 ps |
| CPU time | 10.99 seconds |
| Started | Sep 18 06:28:02 AM UTC 24 |
| Finished | Sep 18 06:28:14 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979706126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1979706126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.3288707856 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2498644406 ps |
| CPU time | 3.69 seconds |
| Started | Sep 18 06:28:01 AM UTC 24 |
| Finished | Sep 18 06:28:05 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288707856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3288707856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.1707823699 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2149148975 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 06:28:01 AM UTC 24 |
| Finished | Sep 18 06:28:05 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707823699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1707823699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.1920534978 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2515702030 ps |
| CPU time | 5.85 seconds |
| Started | Sep 18 06:28:01 AM UTC 24 |
| Finished | Sep 18 06:28:07 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920534978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.1920534978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.1607967427 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2177501905 ps |
| CPU time | 1.61 seconds |
| Started | Sep 18 06:28:01 AM UTC 24 |
| Finished | Sep 18 06:28:03 AM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607967427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1607967427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.4244005398 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 94574968435 ps |
| CPU time | 29.63 seconds |
| Started | Sep 18 06:28:10 AM UTC 24 |
| Finished | Sep 18 06:28:41 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244005398 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.4244005398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2506658908 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 6943416962 ps |
| CPU time | 18.26 seconds |
| Started | Sep 18 06:28:09 AM UTC 24 |
| Finished | Sep 18 06:28:29 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2506658908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.2506658908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3853299928 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 4069228004 ps |
| CPU time | 8.86 seconds |
| Started | Sep 18 06:28:04 AM UTC 24 |
| Finished | Sep 18 06:28:14 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853299928 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.3853299928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.4026548306 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2043438357 ps |
| CPU time | 3.19 seconds |
| Started | Sep 18 06:28:20 AM UTC 24 |
| Finished | Sep 18 06:28:25 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026548306 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.4026548306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.4007759689 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3576506503 ps |
| CPU time | 5.1 seconds |
| Started | Sep 18 06:28:16 AM UTC 24 |
| Finished | Sep 18 06:28:22 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007759689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.4007759689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.2574306714 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 154895261069 ps |
| CPU time | 451.03 seconds |
| Started | Sep 18 06:28:17 AM UTC 24 |
| Finished | Sep 18 06:35:54 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574306714 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.2574306714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3725020983 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 27849315791 ps |
| CPU time | 18.86 seconds |
| Started | Sep 18 06:28:19 AM UTC 24 |
| Finished | Sep 18 06:28:39 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725020983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_with_pre_cond.3725020983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.755500939 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 1282347594252 ps |
| CPU time | 722.37 seconds |
| Started | Sep 18 06:28:15 AM UTC 24 |
| Finished | Sep 18 06:40:25 AM UTC 24 |
| Peak memory | 213320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755500939 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.755500939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.4199726172 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3510375966 ps |
| CPU time | 10.34 seconds |
| Started | Sep 18 06:28:17 AM UTC 24 |
| Finished | Sep 18 06:28:29 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199726172 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.4199726172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3947799064 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 2616645563 ps |
| CPU time | 6.75 seconds |
| Started | Sep 18 06:28:15 AM UTC 24 |
| Finished | Sep 18 06:28:23 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947799064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.3947799064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.987350385 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2482301267 ps |
| CPU time | 3.11 seconds |
| Started | Sep 18 06:28:12 AM UTC 24 |
| Finished | Sep 18 06:28:16 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987350385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.987350385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.800411224 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2266426081 ps |
| CPU time | 3.47 seconds |
| Started | Sep 18 06:28:14 AM UTC 24 |
| Finished | Sep 18 06:28:18 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800411224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.800411224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.3395506069 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2527415031 ps |
| CPU time | 3.44 seconds |
| Started | Sep 18 06:28:15 AM UTC 24 |
| Finished | Sep 18 06:28:19 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395506069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.3395506069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.92968510 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2133040356 ps |
| CPU time | 3.23 seconds |
| Started | Sep 18 06:28:12 AM UTC 24 |
| Finished | Sep 18 06:28:16 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92968510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.92968510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.33788771 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 16004449322 ps |
| CPU time | 29.58 seconds |
| Started | Sep 18 06:28:20 AM UTC 24 |
| Finished | Sep 18 06:28:51 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33788771 -assert nopostproc +UVM_TESTNA ME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.33788771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2689683301 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 6419349050 ps |
| CPU time | 8.06 seconds |
| Started | Sep 18 06:28:19 AM UTC 24 |
| Finished | Sep 18 06:28:29 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2689683301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.2689683301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3397959986 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4989887324 ps |
| CPU time | 11.34 seconds |
| Started | Sep 18 06:28:16 AM UTC 24 |
| Finished | Sep 18 06:28:29 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397959986 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.3397959986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3075436797 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 2022820323 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 06:28:29 AM UTC 24 |
| Finished | Sep 18 06:28:35 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075436797 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.3075436797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2985832936 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3529739095 ps |
| CPU time | 4.93 seconds |
| Started | Sep 18 06:28:26 AM UTC 24 |
| Finished | Sep 18 06:28:32 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985832936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.2985832936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.1858926025 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 146279109910 ps |
| CPU time | 227.18 seconds |
| Started | Sep 18 06:28:28 AM UTC 24 |
| Finished | Sep 18 06:32:19 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858926025 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.1858926025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2189953212 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 31489693393 ps |
| CPU time | 59.16 seconds |
| Started | Sep 18 06:28:29 AM UTC 24 |
| Finished | Sep 18 06:29:30 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189953212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_with_pre_cond.2189953212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1931316870 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3353253396 ps |
| CPU time | 4.57 seconds |
| Started | Sep 18 06:28:24 AM UTC 24 |
| Finished | Sep 18 06:28:30 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931316870 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.1931316870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.2183703797 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3295241721 ps |
| CPU time | 3.52 seconds |
| Started | Sep 18 06:28:28 AM UTC 24 |
| Finished | Sep 18 06:28:33 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183703797 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.2183703797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2699631457 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2716820981 ps |
| CPU time | 1.78 seconds |
| Started | Sep 18 06:28:23 AM UTC 24 |
| Finished | Sep 18 06:28:26 AM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699631457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.2699631457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.2531029893 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2472779160 ps |
| CPU time | 4.55 seconds |
| Started | Sep 18 06:28:23 AM UTC 24 |
| Finished | Sep 18 06:28:28 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531029893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2531029893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.1403536393 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2262794778 ps |
| CPU time | 3.25 seconds |
| Started | Sep 18 06:28:23 AM UTC 24 |
| Finished | Sep 18 06:28:27 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403536393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.1403536393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3891525660 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 2524613679 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 06:28:23 AM UTC 24 |
| Finished | Sep 18 06:28:27 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891525660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3891525660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.480352612 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 2114127348 ps |
| CPU time | 6.97 seconds |
| Started | Sep 18 06:28:21 AM UTC 24 |
| Finished | Sep 18 06:28:30 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480352612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.480352612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.1583526849 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 15389719478 ps |
| CPU time | 20.63 seconds |
| Started | Sep 18 06:28:29 AM UTC 24 |
| Finished | Sep 18 06:28:51 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583526849 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.1583526849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3969667193 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 6405523736 ps |
| CPU time | 11.78 seconds |
| Started | Sep 18 06:28:27 AM UTC 24 |
| Finished | Sep 18 06:28:40 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969667193 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.3969667193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.2909522720 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 2010933619 ps |
| CPU time | 9.62 seconds |
| Started | Sep 18 06:28:37 AM UTC 24 |
| Finished | Sep 18 06:28:48 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909522720 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.2909522720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1680203931 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3217738652 ps |
| CPU time | 3.27 seconds |
| Started | Sep 18 06:28:34 AM UTC 24 |
| Finished | Sep 18 06:28:38 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680203931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.1680203931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.2596416384 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 147700395821 ps |
| CPU time | 372.11 seconds |
| Started | Sep 18 06:28:35 AM UTC 24 |
| Finished | Sep 18 06:34:51 AM UTC 24 |
| Peak memory | 211788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596416384 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.2596416384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3773966723 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 44397172593 ps |
| CPU time | 116.7 seconds |
| Started | Sep 18 06:28:35 AM UTC 24 |
| Finished | Sep 18 06:30:34 AM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773966723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.3773966723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3460829207 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 2553017601 ps |
| CPU time | 7.09 seconds |
| Started | Sep 18 06:28:33 AM UTC 24 |
| Finished | Sep 18 06:28:41 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460829207 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.3460829207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.1952361625 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4222301943 ps |
| CPU time | 1.69 seconds |
| Started | Sep 18 06:28:35 AM UTC 24 |
| Finished | Sep 18 06:28:38 AM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952361625 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.1952361625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2341960830 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 2641844422 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 06:28:31 AM UTC 24 |
| Finished | Sep 18 06:28:34 AM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341960830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.2341960830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.195227700 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2468539274 ps |
| CPU time | 2.65 seconds |
| Started | Sep 18 06:28:31 AM UTC 24 |
| Finished | Sep 18 06:28:34 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195227700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.195227700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.3981948563 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 2207171297 ps |
| CPU time | 1.49 seconds |
| Started | Sep 18 06:28:31 AM UTC 24 |
| Finished | Sep 18 06:28:33 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981948563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.3981948563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.3862252747 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2512511145 ps |
| CPU time | 15.55 seconds |
| Started | Sep 18 06:28:31 AM UTC 24 |
| Finished | Sep 18 06:28:48 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862252747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.3862252747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.1698741932 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 2127203122 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 06:28:31 AM UTC 24 |
| Finished | Sep 18 06:28:35 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698741932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.1698741932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.656717492 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 12871205950 ps |
| CPU time | 10.16 seconds |
| Started | Sep 18 06:28:36 AM UTC 24 |
| Finished | Sep 18 06:28:48 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656717492 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.656717492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3506674715 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 11075893267 ps |
| CPU time | 9.25 seconds |
| Started | Sep 18 06:28:35 AM UTC 24 |
| Finished | Sep 18 06:28:45 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3506674715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3506674715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3731332399 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 13595029528 ps |
| CPU time | 8.87 seconds |
| Started | Sep 18 06:28:34 AM UTC 24 |
| Finished | Sep 18 06:28:44 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731332399 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.3731332399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.230802688 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2015315108 ps |
| CPU time | 8.36 seconds |
| Started | Sep 18 06:22:54 AM UTC 24 |
| Finished | Sep 18 06:23:04 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230802688 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.230802688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.4089548816 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3247455312 ps |
| CPU time | 10.45 seconds |
| Started | Sep 18 06:22:50 AM UTC 24 |
| Finished | Sep 18 06:23:01 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089548816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.4089548816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.3042131654 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 68562138025 ps |
| CPU time | 175.09 seconds |
| Started | Sep 18 06:22:51 AM UTC 24 |
| Finished | Sep 18 06:25:48 AM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042131654 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.3042131654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3445795599 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 35703228913 ps |
| CPU time | 36.14 seconds |
| Started | Sep 18 06:22:52 AM UTC 24 |
| Finished | Sep 18 06:23:29 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445795599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.3445795599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.4237821650 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3562551966 ps |
| CPU time | 7.01 seconds |
| Started | Sep 18 06:22:48 AM UTC 24 |
| Finished | Sep 18 06:22:56 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237821650 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.4237821650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3292178589 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2632948328 ps |
| CPU time | 3.13 seconds |
| Started | Sep 18 06:22:48 AM UTC 24 |
| Finished | Sep 18 06:22:53 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292178589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.3292178589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.1646251408 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2465147849 ps |
| CPU time | 8.59 seconds |
| Started | Sep 18 06:22:47 AM UTC 24 |
| Finished | Sep 18 06:22:57 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646251408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1646251408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.621298094 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2229483977 ps |
| CPU time | 2.15 seconds |
| Started | Sep 18 06:22:47 AM UTC 24 |
| Finished | Sep 18 06:22:50 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621298094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.621298094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.1229784831 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2510349979 ps |
| CPU time | 8.95 seconds |
| Started | Sep 18 06:22:47 AM UTC 24 |
| Finished | Sep 18 06:22:57 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229784831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1229784831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.810508729 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2162346182 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 06:22:47 AM UTC 24 |
| Finished | Sep 18 06:22:50 AM UTC 24 |
| Peak memory | 209008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810508729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.810508729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.2576460186 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 132637068402 ps |
| CPU time | 83.99 seconds |
| Started | Sep 18 06:22:53 AM UTC 24 |
| Finished | Sep 18 06:24:19 AM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576460186 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.2576460186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1551749030 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5657668158 ps |
| CPU time | 17.55 seconds |
| Started | Sep 18 06:22:53 AM UTC 24 |
| Finished | Sep 18 06:23:12 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1551749030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.1551749030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2301261855 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 7355144427 ps |
| CPU time | 6.94 seconds |
| Started | Sep 18 06:22:51 AM UTC 24 |
| Finished | Sep 18 06:22:59 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301261855 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.2301261855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1228088234 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 23584086630 ps |
| CPU time | 97.13 seconds |
| Started | Sep 18 06:28:39 AM UTC 24 |
| Finished | Sep 18 06:30:18 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228088234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.1228088234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.4122452426 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 56933764804 ps |
| CPU time | 18.1 seconds |
| Started | Sep 18 06:28:40 AM UTC 24 |
| Finished | Sep 18 06:28:59 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122452426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.4122452426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3111079149 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 90747308428 ps |
| CPU time | 249.85 seconds |
| Started | Sep 18 06:28:40 AM UTC 24 |
| Finished | Sep 18 06:32:53 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111079149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_with_pre_cond.3111079149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3598139583 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 51579481607 ps |
| CPU time | 202.83 seconds |
| Started | Sep 18 06:28:41 AM UTC 24 |
| Finished | Sep 18 06:32:07 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598139583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.3598139583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.956594254 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 24081677944 ps |
| CPU time | 70.76 seconds |
| Started | Sep 18 06:28:42 AM UTC 24 |
| Finished | Sep 18 06:29:54 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956594254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.956594254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.973030340 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 49988394411 ps |
| CPU time | 95.33 seconds |
| Started | Sep 18 06:28:42 AM UTC 24 |
| Finished | Sep 18 06:30:19 AM UTC 24 |
| Peak memory | 211860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973030340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.973030340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3077697439 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 32928456451 ps |
| CPU time | 40.94 seconds |
| Started | Sep 18 06:28:43 AM UTC 24 |
| Finished | Sep 18 06:29:25 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077697439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_with_pre_cond.3077697439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3644033640 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 111771569783 ps |
| CPU time | 84.28 seconds |
| Started | Sep 18 06:28:43 AM UTC 24 |
| Finished | Sep 18 06:30:09 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644033640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_with_pre_cond.3644033640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.1819243487 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2037992656 ps |
| CPU time | 2.33 seconds |
| Started | Sep 18 06:23:01 AM UTC 24 |
| Finished | Sep 18 06:23:05 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819243487 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.1819243487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.183065471 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3199871257 ps |
| CPU time | 4.91 seconds |
| Started | Sep 18 06:22:58 AM UTC 24 |
| Finished | Sep 18 06:23:03 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183065471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.183065471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2348829082 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 79868089275 ps |
| CPU time | 249.59 seconds |
| Started | Sep 18 06:23:01 AM UTC 24 |
| Finished | Sep 18 06:27:14 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348829082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.2348829082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.868820670 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4087880407 ps |
| CPU time | 6.71 seconds |
| Started | Sep 18 06:22:58 AM UTC 24 |
| Finished | Sep 18 06:23:05 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868820670 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.868820670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.3048268908 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4577877761 ps |
| CPU time | 10.38 seconds |
| Started | Sep 18 06:23:01 AM UTC 24 |
| Finished | Sep 18 06:23:13 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048268908 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.3048268908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2089296298 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2613286660 ps |
| CPU time | 6.93 seconds |
| Started | Sep 18 06:22:58 AM UTC 24 |
| Finished | Sep 18 06:23:05 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089296298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.2089296298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.504396494 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2491354452 ps |
| CPU time | 3.11 seconds |
| Started | Sep 18 06:22:56 AM UTC 24 |
| Finished | Sep 18 06:23:00 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504396494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.504396494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.3286388052 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2031281191 ps |
| CPU time | 7.73 seconds |
| Started | Sep 18 06:22:56 AM UTC 24 |
| Finished | Sep 18 06:23:05 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286388052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3286388052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.1962113118 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2552020156 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 06:22:57 AM UTC 24 |
| Finished | Sep 18 06:23:00 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962113118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.1962113118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.3975072003 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2115964324 ps |
| CPU time | 3.57 seconds |
| Started | Sep 18 06:22:55 AM UTC 24 |
| Finished | Sep 18 06:23:00 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975072003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3975072003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.171275080 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 177970100183 ps |
| CPU time | 365.1 seconds |
| Started | Sep 18 06:23:01 AM UTC 24 |
| Finished | Sep 18 06:29:11 AM UTC 24 |
| Peak memory | 213236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171275080 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.171275080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.611438248 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 11100444775 ps |
| CPU time | 10.02 seconds |
| Started | Sep 18 06:23:01 AM UTC 24 |
| Finished | Sep 18 06:23:12 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=611438248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.611438248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2814478048 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4628492537 ps |
| CPU time | 7.56 seconds |
| Started | Sep 18 06:22:59 AM UTC 24 |
| Finished | Sep 18 06:23:07 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814478048 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.2814478048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3088729332 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 70216314277 ps |
| CPU time | 79.04 seconds |
| Started | Sep 18 06:28:43 AM UTC 24 |
| Finished | Sep 18 06:30:04 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088729332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_with_pre_cond.3088729332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.369755744 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 96381786521 ps |
| CPU time | 255.7 seconds |
| Started | Sep 18 06:28:43 AM UTC 24 |
| Finished | Sep 18 06:33:02 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369755744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with_pre_cond.369755744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2687268937 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 49549475825 ps |
| CPU time | 149.07 seconds |
| Started | Sep 18 06:28:47 AM UTC 24 |
| Finished | Sep 18 06:31:18 AM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687268937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_with_pre_cond.2687268937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.709759546 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 78641183490 ps |
| CPU time | 325.28 seconds |
| Started | Sep 18 06:28:49 AM UTC 24 |
| Finished | Sep 18 06:34:18 AM UTC 24 |
| Peak memory | 211792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709759546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.709759546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3688247367 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 152729758990 ps |
| CPU time | 441.64 seconds |
| Started | Sep 18 06:28:49 AM UTC 24 |
| Finished | Sep 18 06:36:15 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688247367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_with_pre_cond.3688247367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.599550094 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 28607076802 ps |
| CPU time | 13.34 seconds |
| Started | Sep 18 06:28:49 AM UTC 24 |
| Finished | Sep 18 06:29:03 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599550094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.599550094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.201345558 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 105774453319 ps |
| CPU time | 109.83 seconds |
| Started | Sep 18 06:28:53 AM UTC 24 |
| Finished | Sep 18 06:30:45 AM UTC 24 |
| Peak memory | 211728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201345558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.201345558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.1990072622 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2027450578 ps |
| CPU time | 4.11 seconds |
| Started | Sep 18 06:23:08 AM UTC 24 |
| Finished | Sep 18 06:23:13 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990072622 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.1990072622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3694050641 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3531404518 ps |
| CPU time | 4.57 seconds |
| Started | Sep 18 06:23:06 AM UTC 24 |
| Finished | Sep 18 06:23:11 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694050641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.3694050641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.3370386288 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 188316649449 ps |
| CPU time | 530.02 seconds |
| Started | Sep 18 06:23:06 AM UTC 24 |
| Finished | Sep 18 06:32:02 AM UTC 24 |
| Peak memory | 213232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370386288 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.3370386288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2830118786 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 78294153274 ps |
| CPU time | 223.31 seconds |
| Started | Sep 18 06:23:07 AM UTC 24 |
| Finished | Sep 18 06:26:53 AM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830118786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_with_pre_cond.2830118786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2196338442 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5110781074 ps |
| CPU time | 5.05 seconds |
| Started | Sep 18 06:23:06 AM UTC 24 |
| Finished | Sep 18 06:23:12 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196338442 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.2196338442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.3431466409 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2383503636 ps |
| CPU time | 13.31 seconds |
| Started | Sep 18 06:23:07 AM UTC 24 |
| Finished | Sep 18 06:23:21 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431466409 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.3431466409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4037733935 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2611855242 ps |
| CPU time | 7.34 seconds |
| Started | Sep 18 06:23:04 AM UTC 24 |
| Finished | Sep 18 06:23:13 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037733935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.4037733935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.85047346 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2441587868 ps |
| CPU time | 5.12 seconds |
| Started | Sep 18 06:23:02 AM UTC 24 |
| Finished | Sep 18 06:23:09 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85047346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.85047346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.1878414668 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2205529688 ps |
| CPU time | 8.14 seconds |
| Started | Sep 18 06:23:02 AM UTC 24 |
| Finished | Sep 18 06:23:12 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878414668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1878414668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.2772120090 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2510982739 ps |
| CPU time | 11.19 seconds |
| Started | Sep 18 06:23:04 AM UTC 24 |
| Finished | Sep 18 06:23:17 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772120090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2772120090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.4143569947 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2111186021 ps |
| CPU time | 12.04 seconds |
| Started | Sep 18 06:23:02 AM UTC 24 |
| Finished | Sep 18 06:23:16 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143569947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.4143569947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2812081767 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 9611785441 ps |
| CPU time | 4.37 seconds |
| Started | Sep 18 06:23:08 AM UTC 24 |
| Finished | Sep 18 06:23:13 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812081767 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.2812081767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1259656805 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4769736154 ps |
| CPU time | 19 seconds |
| Started | Sep 18 06:23:08 AM UTC 24 |
| Finished | Sep 18 06:23:28 AM UTC 24 |
| Peak memory | 222292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1259656805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1259656805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4213370508 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 9213357891 ps |
| CPU time | 5.83 seconds |
| Started | Sep 18 06:23:06 AM UTC 24 |
| Finished | Sep 18 06:23:13 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213370508 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.4213370508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.202497795 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 165927953829 ps |
| CPU time | 260.92 seconds |
| Started | Sep 18 06:28:53 AM UTC 24 |
| Finished | Sep 18 06:33:18 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202497795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_with_pre_cond.202497795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.209816889 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 26335312232 ps |
| CPU time | 103.32 seconds |
| Started | Sep 18 06:28:56 AM UTC 24 |
| Finished | Sep 18 06:30:42 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209816889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_with_pre_cond.209816889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3117421244 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 66479991204 ps |
| CPU time | 165.28 seconds |
| Started | Sep 18 06:28:58 AM UTC 24 |
| Finished | Sep 18 06:31:46 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117421244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_with_pre_cond.3117421244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1071320074 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 50090752948 ps |
| CPU time | 102.38 seconds |
| Started | Sep 18 06:29:04 AM UTC 24 |
| Finished | Sep 18 06:30:48 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071320074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_with_pre_cond.1071320074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4288645384 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 25449134427 ps |
| CPU time | 20.41 seconds |
| Started | Sep 18 06:29:05 AM UTC 24 |
| Finished | Sep 18 06:29:26 AM UTC 24 |
| Peak memory | 211792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288645384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.4288645384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3602381416 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 73817566833 ps |
| CPU time | 51.26 seconds |
| Started | Sep 18 06:29:12 AM UTC 24 |
| Finished | Sep 18 06:30:05 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602381416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.3602381416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1839185692 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 117843800154 ps |
| CPU time | 360.52 seconds |
| Started | Sep 18 06:29:13 AM UTC 24 |
| Finished | Sep 18 06:35:18 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839185692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_with_pre_cond.1839185692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.509551117 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 21080780232 ps |
| CPU time | 71.36 seconds |
| Started | Sep 18 06:29:14 AM UTC 24 |
| Finished | Sep 18 06:30:27 AM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509551117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.509551117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2417752382 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2013920103 ps |
| CPU time | 5.27 seconds |
| Started | Sep 18 06:23:14 AM UTC 24 |
| Finished | Sep 18 06:23:20 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417752382 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.2417752382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2418632430 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3304345122 ps |
| CPU time | 3.74 seconds |
| Started | Sep 18 06:23:13 AM UTC 24 |
| Finished | Sep 18 06:23:18 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418632430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2418632430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.2017338042 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 167783787445 ps |
| CPU time | 259.71 seconds |
| Started | Sep 18 06:23:13 AM UTC 24 |
| Finished | Sep 18 06:27:36 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017338042 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.2017338042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2708624946 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 76514796057 ps |
| CPU time | 88.32 seconds |
| Started | Sep 18 06:23:13 AM UTC 24 |
| Finished | Sep 18 06:24:43 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708624946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.2708624946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.123367136 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2984954615 ps |
| CPU time | 3 seconds |
| Started | Sep 18 06:23:12 AM UTC 24 |
| Finished | Sep 18 06:23:16 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123367136 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.123367136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1433857475 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2611469080 ps |
| CPU time | 7.37 seconds |
| Started | Sep 18 06:23:11 AM UTC 24 |
| Finished | Sep 18 06:23:19 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433857475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1433857475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2685503930 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2490239783 ps |
| CPU time | 3.3 seconds |
| Started | Sep 18 06:23:08 AM UTC 24 |
| Finished | Sep 18 06:23:13 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685503930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.2685503930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.409191429 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2186188158 ps |
| CPU time | 7.24 seconds |
| Started | Sep 18 06:23:09 AM UTC 24 |
| Finished | Sep 18 06:23:18 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409191429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.409191429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.489112450 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2515109409 ps |
| CPU time | 4.61 seconds |
| Started | Sep 18 06:23:11 AM UTC 24 |
| Finished | Sep 18 06:23:16 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489112450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.489112450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.1355757152 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2115251298 ps |
| CPU time | 6.11 seconds |
| Started | Sep 18 06:23:08 AM UTC 24 |
| Finished | Sep 18 06:23:15 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355757152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.1355757152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4013651432 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3561978281 ps |
| CPU time | 12.39 seconds |
| Started | Sep 18 06:23:14 AM UTC 24 |
| Finished | Sep 18 06:23:28 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4013651432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.4013651432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.279956279 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 24609046976 ps |
| CPU time | 18.4 seconds |
| Started | Sep 18 06:29:14 AM UTC 24 |
| Finished | Sep 18 06:29:34 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279956279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.279956279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2906673958 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 85248361576 ps |
| CPU time | 85.32 seconds |
| Started | Sep 18 06:29:15 AM UTC 24 |
| Finished | Sep 18 06:30:42 AM UTC 24 |
| Peak memory | 211736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906673958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_with_pre_cond.2906673958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3770103836 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 214324430627 ps |
| CPU time | 156.62 seconds |
| Started | Sep 18 06:29:21 AM UTC 24 |
| Finished | Sep 18 06:32:00 AM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770103836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_with_pre_cond.3770103836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2889318558 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 66014860220 ps |
| CPU time | 132.97 seconds |
| Started | Sep 18 06:29:26 AM UTC 24 |
| Finished | Sep 18 06:31:42 AM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889318558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_with_pre_cond.2889318558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.865301610 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 46048397727 ps |
| CPU time | 69.82 seconds |
| Started | Sep 18 06:29:27 AM UTC 24 |
| Finished | Sep 18 06:30:39 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865301610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_with_pre_cond.865301610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.203473978 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 47349652452 ps |
| CPU time | 163.12 seconds |
| Started | Sep 18 06:29:31 AM UTC 24 |
| Finished | Sep 18 06:32:16 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203473978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_with_pre_cond.203473978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3796136855 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 136164439560 ps |
| CPU time | 374.69 seconds |
| Started | Sep 18 06:29:34 AM UTC 24 |
| Finished | Sep 18 06:35:53 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796136855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_with_pre_cond.3796136855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4123769047 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 88129637128 ps |
| CPU time | 92.1 seconds |
| Started | Sep 18 06:29:35 AM UTC 24 |
| Finished | Sep 18 06:31:09 AM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123769047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.4123769047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.4142320014 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 124539702729 ps |
| CPU time | 207.55 seconds |
| Started | Sep 18 06:29:35 AM UTC 24 |
| Finished | Sep 18 06:33:05 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142320014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.4142320014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.730589954 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2016072936 ps |
| CPU time | 6.1 seconds |
| Started | Sep 18 06:23:19 AM UTC 24 |
| Finished | Sep 18 06:23:26 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730589954 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.730589954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.4202406369 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3541984373 ps |
| CPU time | 16.57 seconds |
| Started | Sep 18 06:23:17 AM UTC 24 |
| Finished | Sep 18 06:23:35 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202406369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.4202406369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3106455650 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 58429875999 ps |
| CPU time | 167.48 seconds |
| Started | Sep 18 06:23:18 AM UTC 24 |
| Finished | Sep 18 06:26:08 AM UTC 24 |
| Peak memory | 212044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106455650 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.3106455650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1431517712 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 67477392041 ps |
| CPU time | 214.11 seconds |
| Started | Sep 18 06:23:19 AM UTC 24 |
| Finished | Sep 18 06:26:56 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431517712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.1431517712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.405091364 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4810298618 ps |
| CPU time | 4.61 seconds |
| Started | Sep 18 06:23:17 AM UTC 24 |
| Finished | Sep 18 06:23:22 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405091364 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.405091364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.1167917941 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4861345215 ps |
| CPU time | 7.11 seconds |
| Started | Sep 18 06:23:19 AM UTC 24 |
| Finished | Sep 18 06:23:27 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167917941 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.1167917941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2664585793 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2623728625 ps |
| CPU time | 5.19 seconds |
| Started | Sep 18 06:23:16 AM UTC 24 |
| Finished | Sep 18 06:23:23 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664585793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.2664585793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.1484716268 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2459763548 ps |
| CPU time | 5.25 seconds |
| Started | Sep 18 06:23:14 AM UTC 24 |
| Finished | Sep 18 06:23:20 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484716268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1484716268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.228354809 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2252097731 ps |
| CPU time | 2.15 seconds |
| Started | Sep 18 06:23:14 AM UTC 24 |
| Finished | Sep 18 06:23:18 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228354809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.228354809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.3891009829 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2508807172 ps |
| CPU time | 6.1 seconds |
| Started | Sep 18 06:23:14 AM UTC 24 |
| Finished | Sep 18 06:23:22 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891009829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3891009829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.4176337953 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2108226903 ps |
| CPU time | 6.57 seconds |
| Started | Sep 18 06:23:14 AM UTC 24 |
| Finished | Sep 18 06:23:22 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176337953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.4176337953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.2209453459 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 13875809862 ps |
| CPU time | 6.18 seconds |
| Started | Sep 18 06:23:19 AM UTC 24 |
| Finished | Sep 18 06:23:26 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209453459 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.2209453459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.362031555 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 8203066305 ps |
| CPU time | 8.17 seconds |
| Started | Sep 18 06:23:19 AM UTC 24 |
| Finished | Sep 18 06:23:28 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=362031555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.362031555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1896486125 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 8476613043 ps |
| CPU time | 8.8 seconds |
| Started | Sep 18 06:23:17 AM UTC 24 |
| Finished | Sep 18 06:23:27 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896486125 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.1896486125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2369324341 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 103551789424 ps |
| CPU time | 77.4 seconds |
| Started | Sep 18 06:29:37 AM UTC 24 |
| Finished | Sep 18 06:30:56 AM UTC 24 |
| Peak memory | 211928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369324341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_with_pre_cond.2369324341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3129625472 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 54088071304 ps |
| CPU time | 74.57 seconds |
| Started | Sep 18 06:29:40 AM UTC 24 |
| Finished | Sep 18 06:30:56 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129625472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.3129625472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2625170009 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 53808648497 ps |
| CPU time | 11.86 seconds |
| Started | Sep 18 06:29:45 AM UTC 24 |
| Finished | Sep 18 06:29:58 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625170009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.2625170009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2975391127 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 35047059420 ps |
| CPU time | 16.45 seconds |
| Started | Sep 18 06:29:55 AM UTC 24 |
| Finished | Sep 18 06:30:13 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975391127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_with_pre_cond.2975391127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2351422068 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 149441609723 ps |
| CPU time | 206.19 seconds |
| Started | Sep 18 06:29:58 AM UTC 24 |
| Finished | Sep 18 06:33:27 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351422068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_with_pre_cond.2351422068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3969011360 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 54153555445 ps |
| CPU time | 144.42 seconds |
| Started | Sep 18 06:30:05 AM UTC 24 |
| Finished | Sep 18 06:32:32 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969011360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.3969011360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.247298814 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 41580008945 ps |
| CPU time | 66.44 seconds |
| Started | Sep 18 06:30:06 AM UTC 24 |
| Finished | Sep 18 06:31:14 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247298814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.247298814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3145106519 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 27336458434 ps |
| CPU time | 33.07 seconds |
| Started | Sep 18 06:30:14 AM UTC 24 |
| Finished | Sep 18 06:30:48 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145106519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_with_pre_cond.3145106519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest |
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