Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.31	93.48	90.91		83.33	90.48	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.31	93.48	90.91		83.33	90.48	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T1 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T15 T31 T59 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T15 T30 T31 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T15 T30 T31 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T15 T31 T59 
149        1/1                    cnt_en = 1'b1;
           Tests:       T15 T31 T59 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T15 T31 T59 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T15 T31 T59 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T15 T31 T59 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T31 T59 
167        1/1                    if (trigger_active) begin
           Tests:       T15 T31 T59 
168        1/1                      state_d = DetectSt;
           Tests:       T15 T31 T61 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T15 T59 T148 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T15 T31 T61 
182        1/1                  cnt_en = 1'b1;
           Tests:       T15 T31 T61 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T15 T31 T61 
186        1/1                    state_d = IdleSt;
           Tests:       T62 T116 T130 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T62 T116 T130 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T15 T31 T61 
191        1/1                      state_d = StableSt;
           Tests:       T15 T31 T61 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T15 T31 T61 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T15 T31 T61 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T15 T31 T61 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T15 T31 T61 
206        1/1                    state_d = IdleSt;
           Tests:       T15 T31 T61 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T15 T31 T61 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T31,T59

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T31,T59

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T31,T61

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T31,T59
1	0	Covered	T5,T1,T13
1	1	Covered	T15,T31,T59

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T31,T61
0	1	Covered	T62,T116,T130
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T31,T61
0	1	Covered	T15,T31,T61
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T31,T61
1	-	Covered	T15,T31,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T31,T59
DetectSt	168	Covered	T15,T31,T61
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T15,T31,T61

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T31,T61
DebounceSt->IdleSt	163	Covered	T15,T59,T34
DetectSt->IdleSt	186	Covered	T62,T116,T130
DetectSt->StableSt	191	Covered	T15,T31,T61
IdleSt->DebounceSt	148	Covered	T15,T31,T59
StableSt->IdleSt	206	Covered	T15,T31,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T31,T59
0	1	Covered	T15,T31,T59
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T15,T31,T61
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T31,T59
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T31,T61
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T59,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T31,T59
DetectSt	-	-	-	-	1	-	-	Covered	T62,T116,T130
DetectSt	-	-	-	-	0	1	-	Covered	T15,T31,T61
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T31,T61
StableSt	-	-	-	-	-	-	0	Covered	T15,T31,T61
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	195	0	0
CntIncr_A	6662990	291680	0	0
CntNoWrap_A	6662990	6215981	0	0
DetectStDropOut_A	6662990	3	0	0
DetectedOut_A	6662990	595	0	0
DetectedPulseOut_A	6662990	85	0	0
DisabledIdleSt_A	6662990	5919942	0	0
DisabledNoDetection_A	6662990	5921721	0	0
EnterDebounceSt_A	6662990	107	0	0
EnterDetectSt_A	6662990	88	0	0
EnterStableSt_A	6662990	85	0	0
PulseIsPulse_A	6662990	85	0	0
StayInStableSt	6662990	510	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6662990	5362	0	0
gen_low_level_sva.LowLevelEvent_A	6662990	6217992	0	0
gen_not_sticky_sva.StableStDropOut_A	6662990	85	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	195	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	3	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	4	0	0
T34	0	1	0	0
T35	0	1	0	0
T59	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	4	0	0
T64	0	4	0	0
T65	504	0	0	0
T120	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	291680	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	122	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	81	0	0
T34	0	15	0	0
T35	0	39	0	0
T59	0	21	0	0
T61	0	100	0	0
T62	0	67	0	0
T63	0	163	0	0
T64	0	80	0	0
T65	504	0	0	0
T120	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6215981	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	235	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	3	0	0
T33	24338	0	0	0
T62	680	1	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T116	0	1	0	0
T130	0	1	0	0
T133	603	0	0	0
T134	524	0	0	0
T135	746	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	595	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	12	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	19	0	0
T61	0	11	0	0
T63	0	18	0	0
T64	0	14	0	0
T65	504	0	0	0
T120	0	6	0	0
T140	0	15	0	0
T141	0	13	0	0
T142	0	7	0	0
T143	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	85	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	2	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	504	0	0	0
T120	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5919942	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	48	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5921721	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	48	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	107	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	2	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	504	0	0	0
T120	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	88	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	504	0	0	0
T120	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	85	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	2	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	504	0	0	0
T120	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	85	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	2	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	504	0	0	0
T120	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	510	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	11	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	17	0	0
T61	0	10	0	0
T63	0	16	0	0
T64	0	12	0	0
T65	504	0	0	0
T120	0	5	0	0
T140	0	13	0	0
T141	0	12	0	0
T142	0	5	0	0
T143	0	2	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5362	0	0
T1	613	1	0	0
T2	1420	9	0	0
T3	504	0	0	0
T5	522	4	0	0
T13	495	8	0	0
T14	423	2	0	0
T15	639	3	0	0
T16	431	1	0	0
T17	435	3	0	0
T18	403	0	0	0
T28	0	6	0	0
T29	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	85	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T15	639	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T31	0	2	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	504	0	0	0
T120	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T1 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T10 T25 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T24 T10 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T24 T10 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T10 T25 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T10 T25 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T25 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T10 T25 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T10 T25 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T25 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T10 T25 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T10 T25 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T71 T149 T150 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T10 T25 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T25 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T10 T25 
186        1/1                    state_d = IdleSt;
           Tests:       T2 T119 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T119 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T10 T25 
191        1/1                      state_d = StableSt;
           Tests:       T2 T10 T25 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T10 T25 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T10 T25 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T10 T25 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T10 T25 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T10 T25 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T10 T25 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T25
1	0	Covered	T5,T1,T13
1	1	Covered	T2,T10,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T25
0	1	Covered	T2,T119
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T25
0	1	Unreachable
1	0	Covered	T2,T10,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T25
DetectSt	168	Covered	T2,T10,T25
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T10,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T25
DebounceSt->IdleSt	163	Covered	T34,T35,T71
DetectSt->IdleSt	186	Covered	T2,T119
DetectSt->StableSt	191	Covered	T2,T10,T25
IdleSt->DebounceSt	148	Covered	T2,T10,T25
StableSt->IdleSt	206	Covered	T2,T10,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T10,T25
0	1	Covered	T2,T10,T25
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T25
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T149,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T25
DetectSt	-	-	-	-	1	-	-	Covered	T2,T119
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T25
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	89	0	0
CntIncr_A	6662990	3246	0	0
CntNoWrap_A	6662990	6216087	0	0
DetectStDropOut_A	6662990	4	0	0
DetectedOut_A	6662990	4057	0	0
DetectedPulseOut_A	6662990	26	0	0
DisabledIdleSt_A	6662990	5802394	0	0
DisabledNoDetection_A	6662990	5804208	0	0
EnterDebounceSt_A	6662990	61	0	0
EnterDetectSt_A	6662990	30	0	0
EnterStableSt_A	6662990	26	0	0
PulseIsPulse_A	6662990	26	0	0
StayInStableSt	6662990	4031	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6662990	5362	0	0
gen_low_level_sva.LowLevelEvent_A	6662990	6217992	0	0
gen_sticky_sva.StableStDropOut_A	6662990	253955	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	89	0	0
T2	1420	4	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	2	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	2	0	0
T28	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	3246	0	0
T2	1420	42	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	88	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	83	0	0
T28	502	0	0	0
T34	0	48	0	0
T35	0	55	0	0
T70	0	28	0	0
T71	0	70	0	0
T72	0	16	0	0
T107	0	30	0	0
T108	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6216087	0	0
T1	613	212	0	0
T2	1420	1015	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	4	0	0
T2	1420	1	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T119	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	4057	0	0
T2	1420	45	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	317	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	123	0	0
T28	502	0	0	0
T70	0	55	0	0
T72	0	10	0	0
T107	0	194	0	0
T108	0	102	0	0
T118	0	66	0	0
T144	0	205	0	0
T145	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	26	0	0
T2	1420	1	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T70	0	1	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T118	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5802394	0	0
T1	613	212	0	0
T2	1420	562	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5804208	0	0
T1	613	213	0	0
T2	1420	563	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	61	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	30	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T70	0	1	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T118	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	26	0	0
T2	1420	1	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T70	0	1	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T118	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	26	0	0
T2	1420	1	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T70	0	1	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T118	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	4031	0	0
T2	1420	44	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	316	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	122	0	0
T28	502	0	0	0
T70	0	54	0	0
T72	0	9	0	0
T107	0	193	0	0
T108	0	101	0	0
T118	0	65	0	0
T144	0	204	0	0
T145	0	29	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5362	0	0
T1	613	1	0	0
T2	1420	9	0	0
T3	504	0	0	0
T5	522	4	0	0
T13	495	8	0	0
T14	423	2	0	0
T15	639	3	0	0
T16	431	1	0	0
T17	435	3	0	0
T18	403	0	0	0
T28	0	6	0	0
T29	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	253955	0	0
T2	1420	250	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	243	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	110	0	0
T28	502	0	0	0
T70	0	95150	0	0
T72	0	186	0	0
T107	0	324	0	0
T108	0	55	0	0
T118	0	32	0	0
T144	0	248	0	0
T145	0	90	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T1 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T5 T1 T13 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T10 T25 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T24 T10 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T24 T10 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T1 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T1 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T1 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T1 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T1 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T1 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T1 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T1 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T10 T25 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T10 T25 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T25 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T10 T25 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T10 T25 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T25 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T10 T25 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T10 T25 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T70 T147 T151 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T10 T25 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T25 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T10 T25 
186        1/1                    state_d = IdleSt;
           Tests:       T10 T71 T118 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T71 T118 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T10 T25 
191        1/1                      state_d = StableSt;
           Tests:       T2 T10 T25 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T10 T25 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T10 T25 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T10 T25 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T10 T25 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T10 T25 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T10 T25 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T13
1	1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T25
1	0	Covered	T5,T1,T13
1	1	Covered	T2,T10,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T25
0	1	Covered	T10,T71,T118
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T25
0	1	Unreachable
1	0	Covered	T2,T10,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T25
DetectSt	168	Covered	T2,T10,T25
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T10,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T25
DebounceSt->IdleSt	163	Covered	T34,T35,T70
DetectSt->IdleSt	186	Covered	T10,T71,T118
DetectSt->StableSt	191	Covered	T2,T10,T25
IdleSt->DebounceSt	148	Covered	T2,T10,T25
StableSt->IdleSt	206	Covered	T2,T10,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T10,T25
0	1	Covered	T2,T10,T25
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T25
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T25
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T70,T147,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T25
DetectSt	-	-	-	-	1	-	-	Covered	T10,T71,T118
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T25
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	102	0	0
CntIncr_A	6662990	287504	0	0
CntNoWrap_A	6662990	6216074	0	0
DetectStDropOut_A	6662990	12	0	0
DetectedOut_A	6662990	119359	0	0
DetectedPulseOut_A	6662990	27	0	0
DisabledIdleSt_A	6662990	5802394	0	0
DisabledNoDetection_A	6662990	5804208	0	0
EnterDebounceSt_A	6662990	65	0	0
EnterDetectSt_A	6662990	39	0	0
EnterStableSt_A	6662990	27	0	0
PulseIsPulse_A	6662990	27	0	0
StayInStableSt	6662990	119332	0	0
gen_high_level_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_sticky_sva.StableStDropOut_A	6662990	4071	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	102	0	0
T2	1420	4	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	4	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	2	0	0
T28	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T70	0	2	0	0
T71	0	4	0	0
T72	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	287504	0	0
T2	1420	94	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	86	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	97	0	0
T28	502	0	0	0
T34	0	49	0	0
T35	0	54	0	0
T70	0	95182	0	0
T71	0	178	0	0
T72	0	42	0	0
T107	0	43	0	0
T108	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6216074	0	0
T1	613	212	0	0
T2	1420	1015	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	12	0	0
T10	2403	1	0	0
T11	587	0	0	0
T57	436	0	0	0
T58	462	0	0	0
T59	611	0	0	0
T71	0	2	0	0
T76	906	0	0	0
T80	1536	0	0	0
T90	507	0	0	0
T91	521	0	0	0
T112	0	4	0	0
T118	0	1	0	0
T147	0	2	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	119359	0	0
T2	1420	230	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	45	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	168	0	0
T28	502	0	0	0
T72	0	25	0	0
T107	0	283	0	0
T108	0	74	0	0
T111	0	52	0	0
T144	0	349	0	0
T145	0	87	0	0
T146	0	45083	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	27	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T111	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5802394	0	0
T1	613	212	0	0
T2	1420	562	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5804208	0	0
T1	613	213	0	0
T2	1420	563	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	65	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	2	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	39	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	2	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T71	0	2	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T118	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	27	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T111	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	27	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T111	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	119332	0	0
T2	1420	228	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	44	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	167	0	0
T28	502	0	0	0
T72	0	24	0	0
T107	0	282	0	0
T108	0	73	0	0
T111	0	51	0	0
T144	0	348	0	0
T145	0	86	0	0
T146	0	45082	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	4071	0	0
T2	1420	83	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	351	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	47	0	0
T28	502	0	0	0
T72	0	137	0	0
T107	0	228	0	0
T108	0	143	0	0
T111	0	27	0	0
T144	0	60	0	0
T145	0	40	0	0
T146	0	47	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T1 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T5 T1 T13 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T10 T25 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T24 T10 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T24 T10 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T1 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T1 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T1 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T1 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T1 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T1 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T1 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T1 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T10 T25 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T10 T25 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T25 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T10 T25 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T10 T25 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T25 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T10 T25 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T25 T71 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T10 T70 T108 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T25 T71 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T25 T71 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T25 T71 
186        1/1                    state_d = IdleSt;
           Tests:       T111 T112 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T111 T112 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T25 T71 
191        1/1                      state_d = StableSt;
           Tests:       T2 T25 T71 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T25 T71 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T25 T71 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T25 T71 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T25 T71 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T25 T71 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T25 T71 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T10,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T25,T71

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T25
1	0	Covered	T5,T1,T13
1	1	Covered	T2,T10,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T25,T71
0	1	Covered	T111,T112
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T25,T71
0	1	Unreachable
1	0	Covered	T2,T25,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T25
DetectSt	168	Covered	T2,T25,T71
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T25,T71

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T25,T71
DebounceSt->IdleSt	163	Covered	T10,T34,T35
DetectSt->IdleSt	186	Covered	T111,T112
DetectSt->StableSt	191	Covered	T2,T25,T71
IdleSt->DebounceSt	148	Covered	T2,T10,T25
StableSt->IdleSt	206	Covered	T2,T25,T71

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T10,T25
0	1	Covered	T2,T10,T25
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T25,T71
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T25
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T25,T71
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T70,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T25
DetectSt	-	-	-	-	1	-	-	Covered	T111,T112
DetectSt	-	-	-	-	0	1	-	Covered	T2,T25,T71
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T25,T71
StableSt	-	-	-	-	-	-	0	Covered	T2,T25,T71
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	85	0	0
CntIncr_A	6662990	3581	0	0
CntNoWrap_A	6662990	6216091	0	0
DetectStDropOut_A	6662990	2	0	0
DetectedOut_A	6662990	5306	0	0
DetectedPulseOut_A	6662990	29	0	0
DisabledIdleSt_A	6662990	5802394	0	0
DisabledNoDetection_A	6662990	5804208	0	0
EnterDebounceSt_A	6662990	56	0	0
EnterDetectSt_A	6662990	31	0	0
EnterStableSt_A	6662990	29	0	0
PulseIsPulse_A	6662990	29	0	0
StayInStableSt	6662990	5277	0	0
gen_high_event_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_high_level_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_sticky_sva.StableStDropOut_A	6662990	177914	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	85	0	0
T2	1420	4	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	3	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	2	0	0
T28	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	3581	0	0
T2	1420	20	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	267	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	93	0	0
T28	502	0	0	0
T34	0	51	0	0
T35	0	58	0	0
T70	0	148	0	0
T71	0	78	0	0
T72	0	99	0	0
T107	0	86	0	0
T108	0	186	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6216091	0	0
T1	613	212	0	0
T2	1420	1015	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	2	0	0
T111	611	1	0	0
T112	0	1	0	0
T154	812	0	0	0
T155	6960	0	0	0
T156	512	0	0	0
T157	573	0	0	0
T158	521	0	0	0
T159	402	0	0	0
T160	435	0	0	0
T161	424	0	0	0
T162	508	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5306	0	0
T2	1420	38	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	154	0	0
T28	502	0	0	0
T71	0	103	0	0
T72	0	93	0	0
T107	0	417	0	0
T118	0	10	0	0
T144	0	142	0	0
T145	0	88	0	0
T146	0	175	0	0
T147	0	606	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	29	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T107	0	1	0	0
T118	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5802394	0	0
T1	613	212	0	0
T2	1420	562	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5804208	0	0
T1	613	213	0	0
T2	1420	563	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	56	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T10	0	3	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	31	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T107	0	1	0	0
T111	0	1	0	0
T118	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	29	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T107	0	1	0	0
T118	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	29	0	0
T2	1420	2	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	1	0	0
T28	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T107	0	1	0	0
T118	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5277	0	0
T2	1420	36	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	153	0	0
T28	502	0	0	0
T71	0	102	0	0
T72	0	92	0	0
T107	0	416	0	0
T118	0	9	0	0
T144	0	141	0	0
T145	0	87	0	0
T146	0	174	0	0
T147	0	605	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	177914	0	0
T2	1420	385	0	0
T3	504	0	0	0
T7	490	0	0	0
T8	511	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T25	0	78	0	0
T28	502	0	0	0
T71	0	52	0	0
T72	0	26	0	0
T107	0	57	0	0
T118	0	166	0	0
T144	0	318	0	0
T145	0	37	0	0
T146	0	75515	0	0
T147	0	64	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T11 T53 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T11 T53 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T11 T53 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T11 T53 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T11 T53 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T11 T53 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T11 T53 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T11 T53 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T11 T53 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T11 T53 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T11 T53 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T11 T53 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T11 T53 
191        1/1                      state_d = StableSt;
           Tests:       T1 T11 T53 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T11 T53 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T11 T53 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T11 T53 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T11 T53 
206        1/1                    state_d = IdleSt;
           Tests:       T53 T52 T35 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T11 T53 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T11,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T11,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T11,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T53
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T11,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T53
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T53
0	1	Covered	T53,T52,T163
1	0	Covered	T35

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T53
1	-	Covered	T53,T52,T163

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T53
DetectSt	168	Covered	T1,T11,T53
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T11,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T53
DebounceSt->IdleSt	163	Covered	T34
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T11,T53
IdleSt->DebounceSt	148	Covered	T1,T11,T53
StableSt->IdleSt	206	Covered	T53,T52,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T11,T53
0	1	Covered	T1,T11,T53
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T53
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T53
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T53
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T53,T52,T35
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	49	0	0
CntIncr_A	6662990	58633	0	0
CntNoWrap_A	6662990	6216127	0	0
DetectStDropOut_A	6662990	0	0	0
DetectedOut_A	6662990	8285	0	0
DetectedPulseOut_A	6662990	24	0	0
DisabledIdleSt_A	6662990	5869609	0	0
DisabledNoDetection_A	6662990	5871394	0	0
EnterDebounceSt_A	6662990	25	0	0
EnterDetectSt_A	6662990	24	0	0
EnterStableSt_A	6662990	24	0	0
PulseIsPulse_A	6662990	24	0	0
StayInStableSt	6662990	8248	0	0
gen_high_level_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_not_sticky_sva.StableStDropOut_A	6662990	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	49	0	0
T1	613	2	0	0
T2	1420	0	0	0
T3	504	0	0	0
T7	490	0	0	0
T11	0	2	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T49	0	2	0	0
T52	0	4	0	0
T53	0	4	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	58633	0	0
T1	613	22	0	0
T2	1420	0	0	0
T3	504	0	0	0
T7	490	0	0	0
T11	0	75	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T34	0	21	0	0
T35	0	42	0	0
T49	0	45	0	0
T52	0	78	0	0
T53	0	28	0	0
T163	0	51	0	0
T164	0	47	0	0
T165	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6216127	0	0
T1	613	210	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	8285	0	0
T1	613	52	0	0
T2	1420	0	0	0
T3	504	0	0	0
T7	490	0	0	0
T11	0	45	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T35	0	2	0	0
T49	0	44	0	0
T52	0	107	0	0
T53	0	74	0	0
T163	0	42	0	0
T164	0	46	0	0
T165	0	100	0	0
T166	0	165	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	24	0	0
T1	613	1	0	0
T2	1420	0	0	0
T3	504	0	0	0
T7	490	0	0	0
T11	0	1	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5869609	0	0
T1	613	4	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5871394	0	0
T1	613	4	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	25	0	0
T1	613	1	0	0
T2	1420	0	0	0
T3	504	0	0	0
T7	490	0	0	0
T11	0	1	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	24	0	0
T1	613	1	0	0
T2	1420	0	0	0
T3	504	0	0	0
T7	490	0	0	0
T11	0	1	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	24	0	0
T1	613	1	0	0
T2	1420	0	0	0
T3	504	0	0	0
T7	490	0	0	0
T11	0	1	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	24	0	0
T1	613	1	0	0
T2	1420	0	0	0
T3	504	0	0	0
T7	490	0	0	0
T11	0	1	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	8248	0	0
T1	613	50	0	0
T2	1420	0	0	0
T3	504	0	0	0
T7	490	0	0	0
T11	0	43	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T35	0	1	0	0
T49	0	42	0	0
T52	0	105	0	0
T53	0	71	0	0
T163	0	41	0	0
T164	0	44	0	0
T165	0	98	0	0
T166	0	163	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	10	0	0
T33	24338	0	0	0
T52	0	2	0	0
T53	638	1	0	0
T62	680	0	0	0
T82	491	0	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T125	0	1	0	0
T133	603	0	0	0
T134	524	0	0	0
T135	746	0	0	0
T163	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	2	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T50 T52 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T50 T52 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T50 T52 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T50 T52 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T50 T52 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T50 T52 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T50 T52 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T50 T52 
168        1/1                      state_d = DetectSt;
           Tests:       T50 T52 T35 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T11 T171 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T50 T52 T35 
182        1/1                  cnt_en = 1'b1;
           Tests:       T50 T52 T35 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T50 T52 T35 
186        1/1                    state_d = IdleSt;
           Tests:       T109 T172 T169 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T109 T172 T169 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T50 T52 T35 
191        1/1                      state_d = StableSt;
           Tests:       T50 T52 T35 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T50 T52 T35 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T50 T52 T35 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T50 T52 T35 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T50 T52 T35 
206        1/1                    state_d = IdleSt;
           Tests:       T50 T52 T35 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T50 T52 T35 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T50,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T50,T52

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T50,T52,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T50
1	0	Covered	T5,T1,T13
1	1	Covered	T11,T50,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T52,T35
0	1	Covered	T109,T172,T169
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T50,T52,T35
0	1	Covered	T50,T52,T109
1	0	Covered	T35

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T50,T52,T35
1	-	Covered	T50,T52,T109

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T50,T52
DetectSt	168	Covered	T50,T52,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T50,T52,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T50,T52,T35
DebounceSt->IdleSt	163	Covered	T11,T34,T171
DetectSt->IdleSt	186	Covered	T109,T172,T169
DetectSt->StableSt	191	Covered	T50,T52,T35
IdleSt->DebounceSt	148	Covered	T11,T50,T52
StableSt->IdleSt	206	Covered	T50,T52,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T50,T52
0	1	Covered	T11,T50,T52
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T50,T52,T35
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T50,T52
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T52,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T171
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T50,T52
DetectSt	-	-	-	-	1	-	-	Covered	T109,T172,T169
DetectSt	-	-	-	-	0	1	-	Covered	T50,T52,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T50,T52,T35
StableSt	-	-	-	-	-	-	0	Covered	T50,T52,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	93	0	0
CntIncr_A	6662990	2844	0	0
CntNoWrap_A	6662990	6216083	0	0
DetectStDropOut_A	6662990	3	0	0
DetectedOut_A	6662990	4286	0	0
DetectedPulseOut_A	6662990	42	0	0
DisabledIdleSt_A	6662990	6204140	0	0
DisabledNoDetection_A	6662990	6205921	0	0
EnterDebounceSt_A	6662990	48	0	0
EnterDetectSt_A	6662990	45	0	0
EnterStableSt_A	6662990	42	0	0
PulseIsPulse_A	6662990	42	0	0
StayInStableSt	6662990	4223	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6662990	1547	0	0
gen_low_level_sva.LowLevelEvent_A	6662990	6217992	0	0
gen_not_sticky_sva.StableStDropOut_A	6662990	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	93	0	0
T11	587	1	0	0
T12	511	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	6	0	0
T60	441	0	0	0
T80	1536	0	0	0
T81	490	0	0	0
T91	521	0	0	0
T109	0	4	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	2	0	0
T176	648	0	0	0
T177	427	0	0	0
T178	402	0	0	0
T179	448	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	2844	0	0
T11	587	75	0	0
T12	511	0	0	0
T34	0	21	0	0
T35	0	42	0	0
T50	0	45	0	0
T51	0	98	0	0
T52	0	117	0	0
T60	441	0	0	0
T80	1536	0	0	0
T81	490	0	0	0
T91	521	0	0	0
T109	0	164	0	0
T173	0	98	0	0
T174	0	11	0	0
T175	0	46	0	0
T176	648	0	0	0
T177	427	0	0	0
T178	402	0	0	0
T179	448	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6216083	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	3	0	0
T70	95688	0	0	0
T93	5883	0	0	0
T94	16126	0	0	0
T109	902	1	0	0
T137	408	0	0	0
T138	423	0	0	0
T139	410	0	0	0
T140	6929	0	0	0
T169	0	1	0	0
T172	0	1	0	0
T180	524	0	0	0
T181	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	4286	0	0
T19	6727	0	0	0
T35	0	2	0	0
T50	688	113	0	0
T51	0	204	0	0
T52	0	98	0	0
T53	638	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T109	0	77	0	0
T165	0	212	0	0
T173	0	68	0	0
T174	0	61	0	0
T175	0	81	0	0
T182	0	476	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	42	0	0
T19	6727	0	0	0
T35	0	1	0	0
T50	688	1	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	638	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T109	0	1	0	0
T165	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6204140	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6205921	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	48	0	0
T11	587	1	0	0
T12	511	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	3	0	0
T60	441	0	0	0
T80	1536	0	0	0
T81	490	0	0	0
T91	521	0	0	0
T109	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	648	0	0	0
T177	427	0	0	0
T178	402	0	0	0
T179	448	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	45	0	0
T19	6727	0	0	0
T35	0	1	0	0
T50	688	1	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	638	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T109	0	2	0	0
T165	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	42	0	0
T19	6727	0	0	0
T35	0	1	0	0
T50	688	1	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	638	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T109	0	1	0	0
T165	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	42	0	0
T19	6727	0	0	0
T35	0	1	0	0
T50	688	1	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	638	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T109	0	1	0	0
T165	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	4223	0	0
T19	6727	0	0	0
T35	0	1	0	0
T50	688	112	0	0
T51	0	202	0	0
T52	0	94	0	0
T53	638	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T109	0	76	0	0
T165	0	211	0	0
T173	0	66	0	0
T174	0	59	0	0
T175	0	79	0	0
T182	0	474	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1547	0	0
T1	613	1	0	0
T2	1420	0	0	0
T3	504	0	0	0
T5	522	5	0	0
T13	495	4	0	0
T14	423	2	0	0
T15	639	0	0	0
T16	431	3	0	0
T17	435	4	0	0
T18	403	0	0	0
T28	0	6	0	0
T29	0	5	0	0
T65	0	4	0	0
T86	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	20	0	0
T19	6727	0	0	0
T50	688	1	0	0
T52	0	2	0	0
T53	638	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T109	0	1	0	0
T125	0	2	0	0
T163	0	1	0	0
T165	0	1	0	0
T167	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0