Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T4 T5 T1
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T1
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T1
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T1
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T15 T31
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T4 T1 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T4 T1 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T1
139
140 1/1 unique case (state_q)
Tests: T4 T5 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T1
148 1/1 state_d = DebounceSt;
Tests: T2 T15 T31
149 1/1 cnt_en = 1'b1;
Tests: T2 T15 T31
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T15 T31
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T15 T31
163 1/1 state_d = IdleSt;
Tests: T34 T35
164 1/1 cnt_clr = 1'b1;
Tests: T34 T35
165 1/1 end else if (cnt_done) begin
Tests: T2 T15 T31
166 1/1 cnt_clr = 1'b1;
Tests: T2 T15 T31
167 1/1 if (trigger_active) begin
Tests: T2 T15 T31
168 1/1 state_d = DetectSt;
Tests: T2 T15 T31
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T15 T59 T11
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T15 T31
182 1/1 cnt_en = 1'b1;
Tests: T2 T15 T31
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T15 T31
186 1/1 state_d = IdleSt;
Tests: T2 T62 T109
187 1/1 cnt_clr = 1'b1;
Tests: T2 T62 T109
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T15 T31
191 1/1 state_d = StableSt;
Tests: T2 T15 T31
192 1/1 cnt_clr = 1'b1;
Tests: T2 T15 T31
193 1/1 event_detected_o = 1'b1;
Tests: T2 T15 T31
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T15 T31
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T15 T31
206 1/1 state_d = IdleSt;
Tests: T2 T15 T31
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T15 T31
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T1
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T1
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T1
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T1
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T2 T9
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T4 T1 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T4 T1 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T1
139
140 1/1 unique case (state_q)
Tests: T4 T5 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T1
148 1/1 state_d = DebounceSt;
Tests: T1 T2 T9
149 1/1 cnt_en = 1'b1;
Tests: T1 T2 T9
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T2 T9
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T2 T9
163 1/1 state_d = IdleSt;
Tests: T34 T35
164 1/1 cnt_clr = 1'b1;
Tests: T34 T35
165 1/1 end else if (cnt_done) begin
Tests: T1 T2 T9
166 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T9
167 1/1 if (trigger_active) begin
Tests: T1 T2 T9
168 1/1 state_d = DetectSt;
Tests: T1 T2 T9
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T51 T70 T110
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T2 T9
182 1/1 cnt_en = 1'b1;
Tests: T1 T2 T9
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T2 T9
186 1/1 state_d = IdleSt;
Tests: T10 T109 T71
187 1/1 cnt_clr = 1'b1;
Tests: T10 T109 T71
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T2 T9
191 1/1 state_d = StableSt;
Tests: T1 T2 T9
192 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T9
193 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T9
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T2 T9
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T2 T9
206 1/1 state_d = IdleSt;
Tests: T2 T10 T50
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T9
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T5 T1 T13
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T5 T1 T13
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T10 T25
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T2 T24 T10
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T2 T24 T10
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T5 T1 T13
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T5 T1 T13
129 1/1 cnt_en = 1'b0;
Tests: T5 T1 T13
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T5 T1 T13
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T5 T1 T13
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T5 T1 T13
139
140 1/1 unique case (state_q)
Tests: T5 T1 T13
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T5 T1 T13
148 1/1 state_d = DebounceSt;
Tests: T2 T10 T25
149 1/1 cnt_en = 1'b1;
Tests: T2 T10 T25
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T10 T25
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T10 T25
163 1/1 state_d = IdleSt;
Tests: T34 T35
164 1/1 cnt_clr = 1'b1;
Tests: T34 T35
165 1/1 end else if (cnt_done) begin
Tests: T2 T10 T25
166 1/1 cnt_clr = 1'b1;
Tests: T2 T10 T25
167 1/1 if (trigger_active) begin
Tests: T2 T10 T25
168 1/1 state_d = DetectSt;
Tests: T2 T25 T71
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T10 T70 T108
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T25 T71
182 1/1 cnt_en = 1'b1;
Tests: T2 T25 T71
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T25 T71
186 1/1 state_d = IdleSt;
Tests: T111 T112
187 1/1 cnt_clr = 1'b1;
Tests: T111 T112
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T25 T71
191 1/1 state_d = StableSt;
Tests: T2 T25 T71
192 1/1 cnt_clr = 1'b1;
Tests: T2 T25 T71
193 1/1 event_detected_o = 1'b1;
Tests: T2 T25 T71
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T25 T71
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T25 T71
206 1/1 state_d = IdleSt;
Tests: T2 T25 T71
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T25 T71
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T33 T34 T35
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T33 T34 T35
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T3 T8 T32
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T4 T1 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T4 T1 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T3 T8 T32
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T3 T8 T32
129 1/1 cnt_en = 1'b0;
Tests: T3 T8 T32
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T3 T8 T32
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T3 T8 T32
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T3 T8 T32
139
140 1/1 unique case (state_q)
Tests: T3 T8 T32
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T3 T8 T32
148 1/1 state_d = DebounceSt;
Tests: T3 T8 T32
149 1/1 cnt_en = 1'b1;
Tests: T3 T8 T32
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T3 T8 T32
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T3 T8 T32
163 1/1 state_d = IdleSt;
Tests: T34 T35
164 1/1 cnt_clr = 1'b1;
Tests: T34 T35
165 1/1 end else if (cnt_done) begin
Tests: T3 T8 T32
166 1/1 cnt_clr = 1'b1;
Tests: T3 T8 T32
167 1/1 if (trigger_active) begin
Tests: T3 T8 T32
168 1/1 state_d = DetectSt;
Tests: T3 T8 T32
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T34 T35 T95
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T3 T8 T32
182 1/1 cnt_en = 1'b1;
Tests: T3 T8 T32
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T3 T8 T32
186 1/1 state_d = IdleSt;
Tests: T34 T35 T54
187 1/1 cnt_clr = 1'b1;
Tests: T34 T35 T54
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T3 T8 T32
191 1/1 state_d = StableSt;
Tests: T3 T8 T32
192 1/1 cnt_clr = 1'b1;
Tests: T3 T8 T32
193 1/1 event_detected_o = 1'b1;
Tests: T3 T8 T32
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T3 T8 T32
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T3 T8 T32
206 1/1 state_d = IdleSt;
Tests: T33 T34 T35
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T3 T8 T32
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T3 T7
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T1
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T1
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T1
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T4 T3 T7
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T4 T1 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T4 T1 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T1
139
140 1/1 unique case (state_q)
Tests: T4 T5 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T1
148 1/1 state_d = DebounceSt;
Tests: T4 T3 T7
149 1/1 cnt_en = 1'b1;
Tests: T4 T3 T7
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T4 T3 T7
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T4 T3 T7
163 1/1 state_d = IdleSt;
Tests: T34 T35
164 1/1 cnt_clr = 1'b1;
Tests: T34 T35
165 1/1 end else if (cnt_done) begin
Tests: T4 T3 T7
166 1/1 cnt_clr = 1'b1;
Tests: T4 T3 T7
167 1/1 if (trigger_active) begin
Tests: T4 T3 T7
168 1/1 state_d = DetectSt;
Tests: T3 T7 T8
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T4 T32 T56
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T3 T7 T8
182 1/1 cnt_en = 1'b1;
Tests: T3 T7 T8
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T3 T7 T8
186 1/1 state_d = IdleSt;
Tests: T19 T34 T35
187 1/1 cnt_clr = 1'b1;
Tests: T19 T34 T35
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T3 T7 T8
191 1/1 state_d = StableSt;
Tests: T3 T7 T8
192 1/1 cnt_clr = 1'b1;
Tests: T3 T7 T8
193 1/1 event_detected_o = 1'b1;
Tests: T3 T7 T8
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T3 T7 T8
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T3 T7 T8
206 1/1 state_d = IdleSt;
Tests: T3 T7 T8
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T3 T7 T8
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T3,T7 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T3,T7 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T3,T7 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T3,T7 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T3,T7,T8 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T3,T7 |
| 1 | 0 | Covered | T113,T87,T114 |
| 1 | 1 | Covered | T4,T3,T7 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T7,T8 |
| 0 | 1 | Covered | T19,T35,T55 |
| 1 | 0 | Covered | T34,T35 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T7,T8 |
| 0 | 1 | Covered | T3,T7,T8 |
| 1 | 0 | Covered | T34,T115 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T3,T7,T8 |
| 1 | - | Covered | T3,T7,T8 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T15,T6 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T15,T6 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T15,T31 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T15,T6 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T1,T15,T6 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T15,T31 |
| 0 | 1 | Covered | T62,T109,T116 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T15,T31 |
| 0 | 1 | Covered | T1,T15,T31 |
| 1 | 0 | Covered | T35 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T15,T31 |
| 1 | - | Covered | T1,T15,T31 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T33,T34,T35 |
| 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T3,T8,T32 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T3,T8,T32 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T3,T8,T32 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T33,T34,T35 |
| 1 | 0 | Covered | T33,T34,T35 |
| 1 | 1 | Covered | T3,T8,T32 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T8,T32 |
| 0 | 1 | Covered | T34,T35,T54 |
| 1 | 0 | Covered | T34,T35,T54 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T8,T32 |
| 0 | 1 | Covered | T33,T34,T35 |
| 1 | 0 | Covered | T33,T34,T35 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T3,T8,T32 |
| 1 | - | Covered | T33,T34,T35 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T1,T13 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T25,T71 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T10,T25 |
| 1 | 0 | Covered | T5,T1,T13 |
| 1 | 1 | Covered | T2,T10,T25 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T25,T71 |
| 0 | 1 | Covered | T111,T112 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T25,T71 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T25,T71 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T6,T9 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T6,T9 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T6,T9 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T6,T9 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T1,T6,T9 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T6,T9 |
| 0 | 1 | Covered | T109,T117 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T6,T9 |
| 0 | 1 | Covered | T50,T53,T52 |
| 1 | 0 | Covered | T35 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T6,T9 |
| 1 | - | Covered | T50,T53,T52 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T1,T13 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T5,T1,T13 |
| 1 | 1 | Covered | T5,T1,T13 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T10,T25 |
| 1 | 0 | Covered | T5,T1,T13 |
| 1 | 1 | Covered | T2,T10,T25 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T10,T25 |
| 0 | 1 | Covered | T10,T71,T118 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T10,T25 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T10,T25 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T1,T13 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T1,T13 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T10,T25 |
| 1 | 0 | Covered | T5,T1,T13 |
| 1 | 1 | Covered | T2,T10,T25 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T10,T25 |
| 0 | 1 | Covered | T2,T119 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T10,T25 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T10,T25 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T1,T15,T6 |
| DetectSt |
168 |
Covered |
T1,T15,T31 |
| IdleSt |
163 |
Covered |
T4,T5,T1 |
| StableSt |
191 |
Covered |
T1,T15,T31 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T1,T15,T31 |
| DebounceSt->IdleSt |
163 |
Covered |
T15,T59,T11 |
| DetectSt->IdleSt |
186 |
Covered |
T2,T10,T62 |
| DetectSt->StableSt |
191 |
Covered |
T1,T15,T31 |
| IdleSt->DebounceSt |
148 |
Covered |
T1,T15,T6 |
| StableSt->IdleSt |
206 |
Covered |
T1,T15,T31 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T15,T6 |
| 0 |
1 |
Covered |
T1,T15,T6 |
| 0 |
0 |
Covered |
T4,T5,T1 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T15,T31 |
| 0 |
Covered |
T4,T5,T1 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T15,T6 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T1 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T34,T35 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T1,T15,T31 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T15,T59,T11 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T15,T6 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T2,T10,T62 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T15,T31 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T3,T7,T8 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T15,T31 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T15,T31 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T2,T3,T8 |
| 0 |
1 |
Covered |
T2,T3,T8 |
| 0 |
0 |
Covered |
T4,T5,T1 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T8 |
| 0 |
Covered |
T4,T5,T1 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T8 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T1,T13 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T34,T35 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T2,T3,T8 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T10,T34,T35 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T2,T3,T8 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T34,T35,T54 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T2,T3,T8 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T3,T8,T32 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T2,T33,T25 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T2,T3,T8 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
16013 |
0 |
0 |
| T1 |
613 |
0 |
0 |
0 |
| T2 |
1420 |
0 |
0 |
0 |
| T3 |
1512 |
4 |
0 |
0 |
| T4 |
446 |
1 |
0 |
0 |
| T5 |
522 |
0 |
0 |
0 |
| T7 |
980 |
2 |
0 |
0 |
| T8 |
1022 |
4 |
0 |
0 |
| T12 |
0 |
4 |
0 |
0 |
| T13 |
495 |
0 |
0 |
0 |
| T14 |
423 |
0 |
0 |
0 |
| T15 |
1278 |
3 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
806 |
0 |
0 |
0 |
| T19 |
6727 |
0 |
0 |
0 |
| T28 |
1004 |
0 |
0 |
0 |
| T29 |
1042 |
0 |
0 |
0 |
| T31 |
0 |
4 |
0 |
0 |
| T32 |
0 |
3 |
0 |
0 |
| T33 |
0 |
32 |
0 |
0 |
| T34 |
0 |
17 |
0 |
0 |
| T35 |
0 |
17 |
0 |
0 |
| T54 |
0 |
48 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T59 |
0 |
1 |
0 |
0 |
| T61 |
0 |
5 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
0 |
4 |
0 |
0 |
| T64 |
0 |
4 |
0 |
0 |
| T65 |
1008 |
0 |
0 |
0 |
| T66 |
4402 |
0 |
0 |
0 |
| T67 |
409 |
0 |
0 |
0 |
| T68 |
427 |
0 |
0 |
0 |
| T73 |
573 |
0 |
0 |
0 |
| T120 |
0 |
2 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
2363071 |
0 |
0 |
| T1 |
613 |
0 |
0 |
0 |
| T2 |
1420 |
0 |
0 |
0 |
| T3 |
1512 |
46 |
0 |
0 |
| T4 |
446 |
20 |
0 |
0 |
| T5 |
522 |
0 |
0 |
0 |
| T7 |
980 |
25 |
0 |
0 |
| T8 |
1022 |
46 |
0 |
0 |
| T12 |
0 |
46 |
0 |
0 |
| T13 |
495 |
0 |
0 |
0 |
| T14 |
423 |
0 |
0 |
0 |
| T15 |
1278 |
122 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
806 |
0 |
0 |
0 |
| T19 |
6727 |
0 |
0 |
0 |
| T28 |
1004 |
0 |
0 |
0 |
| T29 |
1042 |
0 |
0 |
0 |
| T31 |
0 |
81 |
0 |
0 |
| T32 |
0 |
41 |
0 |
0 |
| T33 |
0 |
864 |
0 |
0 |
| T34 |
0 |
329 |
0 |
0 |
| T35 |
0 |
782 |
0 |
0 |
| T54 |
0 |
1536 |
0 |
0 |
| T56 |
0 |
20 |
0 |
0 |
| T57 |
0 |
20 |
0 |
0 |
| T58 |
0 |
41 |
0 |
0 |
| T59 |
0 |
21 |
0 |
0 |
| T61 |
0 |
145 |
0 |
0 |
| T62 |
0 |
67 |
0 |
0 |
| T63 |
0 |
163 |
0 |
0 |
| T64 |
0 |
80 |
0 |
0 |
| T65 |
1008 |
0 |
0 |
0 |
| T66 |
4402 |
0 |
0 |
0 |
| T67 |
409 |
0 |
0 |
0 |
| T68 |
427 |
0 |
0 |
0 |
| T73 |
573 |
0 |
0 |
0 |
| T120 |
0 |
52 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
161604563 |
0 |
0 |
| T1 |
15938 |
5494 |
0 |
0 |
| T2 |
36920 |
26482 |
0 |
0 |
| T3 |
13104 |
2674 |
0 |
0 |
| T4 |
11596 |
1169 |
0 |
0 |
| T5 |
13572 |
3146 |
0 |
0 |
| T13 |
12870 |
2444 |
0 |
0 |
| T14 |
10998 |
572 |
0 |
0 |
| T15 |
16614 |
6185 |
0 |
0 |
| T16 |
11206 |
780 |
0 |
0 |
| T17 |
11310 |
884 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
1549 |
0 |
0 |
| T33 |
24338 |
0 |
0 |
0 |
| T34 |
6335 |
1 |
0 |
0 |
| T35 |
0 |
1 |
0 |
0 |
| T43 |
0 |
10 |
0 |
0 |
| T47 |
0 |
2 |
0 |
0 |
| T55 |
10527 |
2 |
0 |
0 |
| T62 |
680 |
1 |
0 |
0 |
| T70 |
95688 |
0 |
0 |
0 |
| T83 |
496 |
0 |
0 |
0 |
| T92 |
0 |
10 |
0 |
0 |
| T93 |
5883 |
8 |
0 |
0 |
| T94 |
16126 |
0 |
0 |
0 |
| T97 |
440 |
0 |
0 |
0 |
| T98 |
424 |
0 |
0 |
0 |
| T99 |
403 |
0 |
0 |
0 |
| T100 |
504 |
0 |
0 |
0 |
| T109 |
902 |
0 |
0 |
0 |
| T116 |
0 |
1 |
0 |
0 |
| T121 |
0 |
7 |
0 |
0 |
| T122 |
0 |
14 |
0 |
0 |
| T123 |
0 |
18 |
0 |
0 |
| T124 |
0 |
7 |
0 |
0 |
| T125 |
0 |
4 |
0 |
0 |
| T126 |
0 |
5 |
0 |
0 |
| T127 |
0 |
2 |
0 |
0 |
| T128 |
0 |
3 |
0 |
0 |
| T129 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
7 |
0 |
0 |
| T132 |
0 |
7 |
0 |
0 |
| T133 |
603 |
0 |
0 |
0 |
| T134 |
524 |
0 |
0 |
0 |
| T135 |
746 |
0 |
0 |
0 |
| T136 |
679 |
0 |
0 |
0 |
| T137 |
408 |
0 |
0 |
0 |
| T138 |
423 |
0 |
0 |
0 |
| T139 |
410 |
0 |
0 |
0 |
| T140 |
6929 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
1211712 |
0 |
0 |
| T3 |
1512 |
81 |
0 |
0 |
| T7 |
1470 |
3 |
0 |
0 |
| T8 |
1533 |
89 |
0 |
0 |
| T12 |
0 |
88 |
0 |
0 |
| T15 |
639 |
12 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
1209 |
0 |
0 |
0 |
| T19 |
0 |
32 |
0 |
0 |
| T28 |
1506 |
0 |
0 |
0 |
| T29 |
1563 |
0 |
0 |
0 |
| T31 |
0 |
19 |
0 |
0 |
| T32 |
0 |
31 |
0 |
0 |
| T33 |
24338 |
3034 |
0 |
0 |
| T34 |
0 |
449 |
0 |
0 |
| T35 |
0 |
576 |
0 |
0 |
| T52 |
814 |
0 |
0 |
0 |
| T54 |
0 |
2034 |
0 |
0 |
| T58 |
0 |
36 |
0 |
0 |
| T61 |
0 |
14 |
0 |
0 |
| T63 |
0 |
18 |
0 |
0 |
| T64 |
0 |
14 |
0 |
0 |
| T65 |
1512 |
0 |
0 |
0 |
| T73 |
1146 |
0 |
0 |
0 |
| T83 |
496 |
0 |
0 |
0 |
| T97 |
440 |
0 |
0 |
0 |
| T98 |
424 |
0 |
0 |
0 |
| T99 |
403 |
0 |
0 |
0 |
| T100 |
504 |
0 |
0 |
0 |
| T101 |
1144 |
0 |
0 |
0 |
| T102 |
522 |
0 |
0 |
0 |
| T103 |
675 |
0 |
0 |
0 |
| T120 |
0 |
6 |
0 |
0 |
| T140 |
0 |
15 |
0 |
0 |
| T141 |
0 |
13 |
0 |
0 |
| T142 |
0 |
7 |
0 |
0 |
| T143 |
0 |
3 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
5527 |
0 |
0 |
| T3 |
1512 |
2 |
0 |
0 |
| T7 |
1470 |
1 |
0 |
0 |
| T8 |
1533 |
2 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T15 |
639 |
1 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
1209 |
0 |
0 |
0 |
| T19 |
0 |
2 |
0 |
0 |
| T28 |
1506 |
0 |
0 |
0 |
| T29 |
1563 |
0 |
0 |
0 |
| T31 |
0 |
2 |
0 |
0 |
| T32 |
0 |
1 |
0 |
0 |
| T33 |
24338 |
22 |
0 |
0 |
| T34 |
0 |
6 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T52 |
814 |
0 |
0 |
0 |
| T54 |
0 |
27 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
1512 |
0 |
0 |
0 |
| T73 |
1146 |
0 |
0 |
0 |
| T83 |
496 |
0 |
0 |
0 |
| T97 |
440 |
0 |
0 |
0 |
| T98 |
424 |
0 |
0 |
0 |
| T99 |
403 |
0 |
0 |
0 |
| T100 |
504 |
0 |
0 |
0 |
| T101 |
1144 |
0 |
0 |
0 |
| T102 |
522 |
0 |
0 |
0 |
| T103 |
675 |
0 |
0 |
0 |
| T120 |
0 |
1 |
0 |
0 |
| T140 |
0 |
2 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
| T142 |
0 |
2 |
0 |
0 |
| T143 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
151766057 |
0 |
0 |
| T1 |
15938 |
3848 |
0 |
0 |
| T2 |
36920 |
25123 |
0 |
0 |
| T3 |
13104 |
2502 |
0 |
0 |
| T4 |
11596 |
1128 |
0 |
0 |
| T5 |
13572 |
3146 |
0 |
0 |
| T13 |
12870 |
2444 |
0 |
0 |
| T14 |
10998 |
572 |
0 |
0 |
| T15 |
16614 |
5998 |
0 |
0 |
| T16 |
11206 |
780 |
0 |
0 |
| T17 |
11310 |
884 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
151809626 |
0 |
0 |
| T1 |
15938 |
3866 |
0 |
0 |
| T2 |
36920 |
25149 |
0 |
0 |
| T3 |
13104 |
2526 |
0 |
0 |
| T4 |
11596 |
1153 |
0 |
0 |
| T5 |
13572 |
3172 |
0 |
0 |
| T13 |
12870 |
2470 |
0 |
0 |
| T14 |
10998 |
598 |
0 |
0 |
| T15 |
16614 |
6023 |
0 |
0 |
| T16 |
11206 |
806 |
0 |
0 |
| T17 |
11310 |
910 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
8218 |
0 |
0 |
| T1 |
613 |
0 |
0 |
0 |
| T2 |
1420 |
0 |
0 |
0 |
| T3 |
1512 |
2 |
0 |
0 |
| T4 |
446 |
1 |
0 |
0 |
| T5 |
522 |
0 |
0 |
0 |
| T7 |
980 |
1 |
0 |
0 |
| T8 |
1022 |
2 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T13 |
495 |
0 |
0 |
0 |
| T14 |
423 |
0 |
0 |
0 |
| T15 |
1278 |
2 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
806 |
0 |
0 |
0 |
| T19 |
6727 |
0 |
0 |
0 |
| T28 |
1004 |
0 |
0 |
0 |
| T29 |
1042 |
0 |
0 |
0 |
| T31 |
0 |
2 |
0 |
0 |
| T32 |
0 |
2 |
0 |
0 |
| T33 |
0 |
16 |
0 |
0 |
| T34 |
0 |
10 |
0 |
0 |
| T35 |
0 |
10 |
0 |
0 |
| T54 |
0 |
24 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
1 |
0 |
0 |
| T61 |
0 |
3 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
1008 |
0 |
0 |
0 |
| T66 |
4402 |
0 |
0 |
0 |
| T67 |
409 |
0 |
0 |
0 |
| T68 |
427 |
0 |
0 |
0 |
| T73 |
573 |
0 |
0 |
0 |
| T120 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
7806 |
0 |
0 |
| T3 |
1512 |
2 |
0 |
0 |
| T7 |
1470 |
1 |
0 |
0 |
| T8 |
1533 |
2 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T15 |
639 |
1 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
1209 |
0 |
0 |
0 |
| T19 |
6727 |
2 |
0 |
0 |
| T28 |
1506 |
0 |
0 |
0 |
| T29 |
1563 |
0 |
0 |
0 |
| T31 |
0 |
2 |
0 |
0 |
| T32 |
0 |
1 |
0 |
0 |
| T33 |
0 |
22 |
0 |
0 |
| T34 |
0 |
10 |
0 |
0 |
| T35 |
0 |
10 |
0 |
0 |
| T53 |
638 |
0 |
0 |
0 |
| T54 |
0 |
27 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
680 |
1 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
1512 |
0 |
0 |
0 |
| T66 |
4402 |
0 |
0 |
0 |
| T67 |
409 |
0 |
0 |
0 |
| T68 |
427 |
0 |
0 |
0 |
| T73 |
1146 |
0 |
0 |
0 |
| T82 |
491 |
0 |
0 |
0 |
| T104 |
4452 |
0 |
0 |
0 |
| T105 |
402 |
0 |
0 |
0 |
| T106 |
509 |
0 |
0 |
0 |
| T120 |
0 |
1 |
0 |
0 |
| T140 |
0 |
2 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
| T142 |
0 |
2 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
5527 |
0 |
0 |
| T3 |
1512 |
2 |
0 |
0 |
| T7 |
1470 |
1 |
0 |
0 |
| T8 |
1533 |
2 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T15 |
639 |
1 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
1209 |
0 |
0 |
0 |
| T19 |
0 |
2 |
0 |
0 |
| T28 |
1506 |
0 |
0 |
0 |
| T29 |
1563 |
0 |
0 |
0 |
| T31 |
0 |
2 |
0 |
0 |
| T32 |
0 |
1 |
0 |
0 |
| T33 |
24338 |
22 |
0 |
0 |
| T34 |
0 |
6 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T52 |
814 |
0 |
0 |
0 |
| T54 |
0 |
27 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
1512 |
0 |
0 |
0 |
| T73 |
1146 |
0 |
0 |
0 |
| T83 |
496 |
0 |
0 |
0 |
| T97 |
440 |
0 |
0 |
0 |
| T98 |
424 |
0 |
0 |
0 |
| T99 |
403 |
0 |
0 |
0 |
| T100 |
504 |
0 |
0 |
0 |
| T101 |
1144 |
0 |
0 |
0 |
| T102 |
522 |
0 |
0 |
0 |
| T103 |
675 |
0 |
0 |
0 |
| T120 |
0 |
1 |
0 |
0 |
| T140 |
0 |
2 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
| T142 |
0 |
2 |
0 |
0 |
| T143 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
5527 |
0 |
0 |
| T3 |
1512 |
2 |
0 |
0 |
| T7 |
1470 |
1 |
0 |
0 |
| T8 |
1533 |
2 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T15 |
639 |
1 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
1209 |
0 |
0 |
0 |
| T19 |
0 |
2 |
0 |
0 |
| T28 |
1506 |
0 |
0 |
0 |
| T29 |
1563 |
0 |
0 |
0 |
| T31 |
0 |
2 |
0 |
0 |
| T32 |
0 |
1 |
0 |
0 |
| T33 |
24338 |
22 |
0 |
0 |
| T34 |
0 |
6 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T52 |
814 |
0 |
0 |
0 |
| T54 |
0 |
27 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
1512 |
0 |
0 |
0 |
| T73 |
1146 |
0 |
0 |
0 |
| T83 |
496 |
0 |
0 |
0 |
| T97 |
440 |
0 |
0 |
0 |
| T98 |
424 |
0 |
0 |
0 |
| T99 |
403 |
0 |
0 |
0 |
| T100 |
504 |
0 |
0 |
0 |
| T101 |
1144 |
0 |
0 |
0 |
| T102 |
522 |
0 |
0 |
0 |
| T103 |
675 |
0 |
0 |
0 |
| T120 |
0 |
1 |
0 |
0 |
| T140 |
0 |
2 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
| T142 |
0 |
2 |
0 |
0 |
| T143 |
0 |
1 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173237740 |
1205351 |
0 |
0 |
| T3 |
1512 |
78 |
0 |
0 |
| T7 |
1470 |
2 |
0 |
0 |
| T8 |
1533 |
86 |
0 |
0 |
| T12 |
0 |
85 |
0 |
0 |
| T15 |
639 |
11 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
1209 |
0 |
0 |
0 |
| T19 |
0 |
30 |
0 |
0 |
| T28 |
1506 |
0 |
0 |
0 |
| T29 |
1563 |
0 |
0 |
0 |
| T31 |
0 |
17 |
0 |
0 |
| T32 |
0 |
29 |
0 |
0 |
| T33 |
24338 |
3006 |
0 |
0 |
| T34 |
0 |
443 |
0 |
0 |
| T35 |
0 |
570 |
0 |
0 |
| T52 |
814 |
0 |
0 |
0 |
| T54 |
0 |
2003 |
0 |
0 |
| T58 |
0 |
34 |
0 |
0 |
| T61 |
0 |
12 |
0 |
0 |
| T63 |
0 |
16 |
0 |
0 |
| T64 |
0 |
12 |
0 |
0 |
| T65 |
1512 |
0 |
0 |
0 |
| T73 |
1146 |
0 |
0 |
0 |
| T83 |
496 |
0 |
0 |
0 |
| T97 |
440 |
0 |
0 |
0 |
| T98 |
424 |
0 |
0 |
0 |
| T99 |
403 |
0 |
0 |
0 |
| T100 |
504 |
0 |
0 |
0 |
| T101 |
1144 |
0 |
0 |
0 |
| T102 |
522 |
0 |
0 |
0 |
| T103 |
675 |
0 |
0 |
0 |
| T120 |
0 |
5 |
0 |
0 |
| T140 |
0 |
13 |
0 |
0 |
| T141 |
0 |
12 |
0 |
0 |
| T142 |
0 |
5 |
0 |
0 |
| T143 |
0 |
2 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
59966910 |
39212 |
0 |
0 |
| T1 |
5517 |
9 |
0 |
0 |
| T2 |
12780 |
36 |
0 |
0 |
| T3 |
4536 |
3 |
0 |
0 |
| T4 |
1338 |
3 |
0 |
0 |
| T5 |
4698 |
42 |
0 |
0 |
| T7 |
0 |
3 |
0 |
0 |
| T8 |
0 |
3 |
0 |
0 |
| T13 |
4455 |
63 |
0 |
0 |
| T14 |
3807 |
20 |
0 |
0 |
| T15 |
5751 |
9 |
0 |
0 |
| T16 |
3879 |
17 |
0 |
0 |
| T17 |
3915 |
30 |
0 |
0 |
| T18 |
2418 |
0 |
0 |
0 |
| T28 |
0 |
35 |
0 |
0 |
| T29 |
0 |
31 |
0 |
0 |
| T65 |
0 |
13 |
0 |
0 |
| T73 |
0 |
5 |
0 |
0 |
| T86 |
0 |
4 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
33314950 |
31089960 |
0 |
0 |
| T1 |
3065 |
1065 |
0 |
0 |
| T2 |
7100 |
5100 |
0 |
0 |
| T3 |
2520 |
520 |
0 |
0 |
| T4 |
2230 |
230 |
0 |
0 |
| T5 |
2610 |
610 |
0 |
0 |
| T13 |
2475 |
475 |
0 |
0 |
| T14 |
2115 |
115 |
0 |
0 |
| T15 |
3195 |
1195 |
0 |
0 |
| T16 |
2155 |
155 |
0 |
0 |
| T17 |
2175 |
175 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
113270830 |
105705864 |
0 |
0 |
| T1 |
10421 |
3621 |
0 |
0 |
| T2 |
24140 |
17340 |
0 |
0 |
| T3 |
8568 |
1768 |
0 |
0 |
| T4 |
7582 |
782 |
0 |
0 |
| T5 |
8874 |
2074 |
0 |
0 |
| T13 |
8415 |
1615 |
0 |
0 |
| T14 |
7191 |
391 |
0 |
0 |
| T15 |
10863 |
4063 |
0 |
0 |
| T16 |
7327 |
527 |
0 |
0 |
| T17 |
7395 |
595 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
59966910 |
55961928 |
0 |
0 |
| T1 |
5517 |
1917 |
0 |
0 |
| T2 |
12780 |
9180 |
0 |
0 |
| T3 |
4536 |
936 |
0 |
0 |
| T4 |
4014 |
414 |
0 |
0 |
| T5 |
4698 |
1098 |
0 |
0 |
| T13 |
4455 |
855 |
0 |
0 |
| T14 |
3807 |
207 |
0 |
0 |
| T15 |
5751 |
2151 |
0 |
0 |
| T16 |
3879 |
279 |
0 |
0 |
| T17 |
3915 |
315 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
153248770 |
4537 |
0 |
0 |
| T3 |
1008 |
1 |
0 |
0 |
| T7 |
980 |
1 |
0 |
0 |
| T8 |
1022 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T15 |
639 |
1 |
0 |
0 |
| T16 |
862 |
0 |
0 |
0 |
| T17 |
870 |
0 |
0 |
0 |
| T18 |
806 |
0 |
0 |
0 |
| T19 |
0 |
2 |
0 |
0 |
| T28 |
1004 |
0 |
0 |
0 |
| T29 |
1042 |
0 |
0 |
0 |
| T31 |
0 |
2 |
0 |
0 |
| T33 |
24338 |
16 |
0 |
0 |
| T34 |
0 |
5 |
0 |
0 |
| T35 |
0 |
5 |
0 |
0 |
| T44 |
0 |
20 |
0 |
0 |
| T52 |
814 |
0 |
0 |
0 |
| T54 |
0 |
23 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
1008 |
0 |
0 |
0 |
| T73 |
573 |
0 |
0 |
0 |
| T83 |
496 |
0 |
0 |
0 |
| T94 |
0 |
6 |
0 |
0 |
| T97 |
440 |
0 |
0 |
0 |
| T98 |
424 |
0 |
0 |
0 |
| T99 |
403 |
0 |
0 |
0 |
| T100 |
504 |
0 |
0 |
0 |
| T101 |
1144 |
0 |
0 |
0 |
| T102 |
522 |
0 |
0 |
0 |
| T103 |
675 |
0 |
0 |
0 |
| T120 |
0 |
1 |
0 |
0 |
| T140 |
0 |
2 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
| T142 |
0 |
2 |
0 |
0 |
| T143 |
0 |
1 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
19988970 |
435940 |
0 |
0 |
| T2 |
4260 |
718 |
0 |
0 |
| T3 |
1512 |
0 |
0 |
0 |
| T7 |
1470 |
0 |
0 |
0 |
| T8 |
1533 |
0 |
0 |
0 |
| T10 |
0 |
594 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1917 |
0 |
0 |
0 |
| T16 |
1293 |
0 |
0 |
0 |
| T17 |
1305 |
0 |
0 |
0 |
| T18 |
1209 |
0 |
0 |
0 |
| T25 |
0 |
235 |
0 |
0 |
| T28 |
1506 |
0 |
0 |
0 |
| T70 |
0 |
95150 |
0 |
0 |
| T71 |
0 |
52 |
0 |
0 |
| T72 |
0 |
349 |
0 |
0 |
| T107 |
0 |
609 |
0 |
0 |
| T108 |
0 |
198 |
0 |
0 |
| T111 |
0 |
27 |
0 |
0 |
| T118 |
0 |
198 |
0 |
0 |
| T144 |
0 |
626 |
0 |
0 |
| T145 |
0 |
167 |
0 |
0 |
| T146 |
0 |
75562 |
0 |
0 |
| T147 |
0 |
64 |
0 |
0 |
