Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T33 T34 T35 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T33 T34 T35 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T8 T32 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T3 T8 T32 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T3 T8 T32 
129        1/1              cnt_en = 1'b0;
           Tests:       T3 T8 T32 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T3 T8 T32 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T3 T8 T32 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T3 T8 T32 
139                     
140        1/1              unique case (state_q)
           Tests:       T3 T8 T32 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T3 T8 T32 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T8 T32 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T8 T32 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T32 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T8 T32 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T8 T32 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T8 T32 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T8 T32 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T8 T32 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T35 T95 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T8 T32 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T32 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T8 T32 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T92 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T92 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T8 T32 
191        1/1                      state_d = StableSt;
           Tests:       T3 T8 T32 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T8 T32 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T8 T32 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T8 T32 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T8 T32 
206        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T35 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T8 T32 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T33,T34,T35
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T33,T34,T35
1	1	Covered	T3,T8,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T32
0	1	Covered	T34,T35,T92
1	0	Covered	T34,T35,T122

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T32
0	1	Covered	T33,T34,T35
1	0	Covered	T34,T239

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T32
1	-	Covered	T33,T34,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T32
DetectSt	168	Covered	T3,T8,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T8,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T32
DebounceSt->IdleSt	163	Covered	T34,T35,T95
DetectSt->IdleSt	186	Covered	T34,T35,T92
DetectSt->StableSt	191	Covered	T3,T8,T32
IdleSt->DebounceSt	148	Covered	T3,T8,T32
StableSt->IdleSt	206	Covered	T33,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T8,T32
0	1	Covered	T3,T8,T32
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T32
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T32
IdleSt	0	-	-	-	-	-	-	Covered	T33,T34,T35
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T35,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T32
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T92
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T32
DetectSt	-	-	-	-	0	0	-	Covered	T3,T8,T32
StableSt	-	-	-	-	-	-	1	Covered	T33,T34,T35
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	2987	0	0
CntIncr_A	6662990	109300	0	0
CntNoWrap_A	6662990	6213189	0	0
DetectStDropOut_A	6662990	410	0	0
DetectedOut_A	6662990	77102	0	0
DetectedPulseOut_A	6662990	923	0	0
DisabledIdleSt_A	6662990	5742710	0	0
DisabledNoDetection_A	6662990	5744325	0	0
EnterDebounceSt_A	6662990	1508	0	0
EnterDetectSt_A	6662990	1479	0	0
EnterStableSt_A	6662990	923	0	0
PulseIsPulse_A	6662990	923	0	0
StayInStableSt	6662990	76068	0	0
gen_high_event_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_high_level_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_not_sticky_sva.StableStDropOut_A	6662990	799	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	2987	0	0
T3	504	2	0	0
T7	490	0	0	0
T8	511	2	0	0
T12	0	2	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T32	0	2	0	0
T33	0	32	0	0
T34	0	16	0	0
T35	0	16	0	0
T44	0	42	0	0
T54	0	48	0	0
T58	0	2	0	0
T65	504	0	0	0
T73	573	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	109300	0	0
T3	504	21	0	0
T7	490	0	0	0
T8	511	21	0	0
T12	0	21	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T32	0	21	0	0
T33	0	864	0	0
T34	0	314	0	0
T35	0	743	0	0
T44	0	1365	0	0
T54	0	1536	0	0
T58	0	21	0	0
T65	504	0	0	0
T73	573	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6213189	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	101	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	410	0	0
T34	6335	1	0	0
T35	8501	1	0	0
T47	0	2	0	0
T63	742	0	0	0
T64	676	0	0	0
T84	488	0	0	0
T92	0	10	0	0
T93	0	8	0	0
T122	0	14	0	0
T123	0	18	0	0
T126	0	5	0	0
T207	431	0	0	0
T208	402	0	0	0
T209	525	0	0	0
T210	422	0	0	0
T240	0	28	0	0
T241	0	10	0	0
T242	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	77102	0	0
T3	504	78	0	0
T7	490	0	0	0
T8	511	86	0	0
T12	0	85	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T32	0	31	0	0
T33	0	2723	0	0
T34	0	335	0	0
T35	0	463	0	0
T44	0	3959	0	0
T54	0	1771	0	0
T58	0	36	0	0
T65	504	0	0	0
T73	573	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	923	0	0
T3	504	1	0	0
T7	490	0	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T32	0	1	0	0
T33	0	16	0	0
T34	0	5	0	0
T35	0	5	0	0
T44	0	21	0	0
T54	0	24	0	0
T58	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5742710	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	4	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5744325	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	4	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1508	0	0
T3	504	1	0	0
T7	490	0	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T32	0	1	0	0
T33	0	16	0	0
T34	0	9	0	0
T35	0	9	0	0
T44	0	21	0	0
T54	0	24	0	0
T58	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1479	0	0
T3	504	1	0	0
T7	490	0	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T32	0	1	0	0
T33	0	16	0	0
T34	0	7	0	0
T35	0	7	0	0
T44	0	21	0	0
T54	0	24	0	0
T58	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	923	0	0
T3	504	1	0	0
T7	490	0	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T32	0	1	0	0
T33	0	16	0	0
T34	0	5	0	0
T35	0	5	0	0
T44	0	21	0	0
T54	0	24	0	0
T58	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	923	0	0
T3	504	1	0	0
T7	490	0	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T32	0	1	0	0
T33	0	16	0	0
T34	0	5	0	0
T35	0	5	0	0
T44	0	21	0	0
T54	0	24	0	0
T58	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	76068	0	0
T3	504	76	0	0
T7	490	0	0	0
T8	511	84	0	0
T12	0	83	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T28	502	0	0	0
T29	521	0	0	0
T32	0	29	0	0
T33	0	2701	0	0
T34	0	330	0	0
T35	0	458	0	0
T44	0	3934	0	0
T54	0	1745	0	0
T58	0	34	0	0
T65	504	0	0	0
T73	573	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	799	0	0
T33	24338	10	0	0
T34	0	4	0	0
T35	0	5	0	0
T44	0	17	0	0
T52	814	0	0	0
T54	0	22	0	0
T83	496	0	0	0
T94	0	6	0	0
T96	0	7	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T198	0	24	0	0
T243	0	22	0	0
T244	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T3 T7 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T4 T3 T7 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T4 T3 T7 
149        1/1                    cnt_en = 1'b1;
           Tests:       T4 T3 T7 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T4 T3 T7 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T4 T3 T7 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T4 T3 T7 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T4 T3 T7 
167        1/1                    if (trigger_active) begin
           Tests:       T4 T3 T7 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T7 T8 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T4 T32 T56 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T7 T8 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T8 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T7 T8 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T55 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T55 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T7 T8 
191        1/1                      state_d = StableSt;
           Tests:       T3 T7 T8 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T7 T8 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T7 T8 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T7 T8 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T7 T8 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T7 T8 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T7 T8 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T3,T7
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T7
1	0	Covered	T113,T87,T114
1	1	Covered	T4,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T55,T121,T43
1	0	Covered	T34,T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T115

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T3,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T3,T7
DetectSt	168	Covered	T3,T7,T8
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T8
DebounceSt->IdleSt	163	Covered	T4,T32,T56
DetectSt->IdleSt	186	Covered	T34,T35,T55
DetectSt->StableSt	191	Covered	T3,T7,T8
IdleSt->DebounceSt	148	Covered	T4,T3,T7
StableSt->IdleSt	206	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T3,T7
0	1	Covered	T4,T3,T7
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T32,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T55
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	825	0	0
CntIncr_A	6662990	43957	0	0
CntNoWrap_A	6662990	6215351	0	0
DetectStDropOut_A	6662990	70	0	0
DetectedOut_A	6662990	13194	0	0
DetectedPulseOut_A	6662990	313	0	0
DisabledIdleSt_A	6662990	5891218	0	0
DisabledNoDetection_A	6662990	5892428	0	0
EnterDebounceSt_A	6662990	439	0	0
EnterDetectSt_A	6662990	387	0	0
EnterStableSt_A	6662990	313	0	0
PulseIsPulse_A	6662990	313	0	0
StayInStableSt	6662990	12850	0	0
gen_high_level_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_not_sticky_sva.StableStDropOut_A	6662990	279	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	825	0	0
T1	613	0	0	0
T2	1420	0	0	0
T3	504	2	0	0
T4	446	1	0	0
T5	522	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T12	0	2	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T32	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	43957	0	0
T1	613	0	0	0
T2	1420	0	0	0
T3	504	25	0	0
T4	446	20	0	0
T5	522	0	0	0
T7	0	25	0	0
T8	0	25	0	0
T12	0	25	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T32	0	20	0	0
T56	0	20	0	0
T57	0	20	0	0
T58	0	20	0	0
T61	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6215351	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	101	0	0
T4	446	44	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	70	0	0
T43	0	10	0	0
T55	10527	2	0	0
T70	95688	0	0	0
T93	5883	0	0	0
T94	16126	0	0	0
T109	902	0	0	0
T121	0	7	0	0
T124	0	7	0	0
T125	0	4	0	0
T127	0	2	0	0
T128	0	3	0	0
T129	0	1	0	0
T131	0	7	0	0
T132	0	7	0	0
T136	679	0	0	0
T137	408	0	0	0
T138	423	0	0	0
T139	410	0	0	0
T140	6929	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	13194	0	0
T3	504	3	0	0
T7	490	3	0	0
T8	511	3	0	0
T12	0	3	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T19	0	32	0	0
T28	502	0	0	0
T29	521	0	0	0
T33	0	311	0	0
T34	0	114	0	0
T35	0	113	0	0
T54	0	263	0	0
T61	0	3	0	0
T65	504	0	0	0
T73	573	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	313	0	0
T3	504	1	0	0
T7	490	1	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T19	0	2	0	0
T28	502	0	0	0
T29	521	0	0	0
T33	0	6	0	0
T34	0	1	0	0
T35	0	1	0	0
T54	0	3	0	0
T61	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5891218	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	26	0	0
T4	446	3	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5892428	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	26	0	0
T4	446	3	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	439	0	0
T1	613	0	0	0
T2	1420	0	0	0
T3	504	1	0	0
T4	446	1	0	0
T5	522	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	0	1	0	0
T13	495	0	0	0
T14	423	0	0	0
T15	639	0	0	0
T16	431	0	0	0
T17	435	0	0	0
T32	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	387	0	0
T3	504	1	0	0
T7	490	1	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T19	0	2	0	0
T28	502	0	0	0
T29	521	0	0	0
T33	0	6	0	0
T34	0	3	0	0
T35	0	3	0	0
T54	0	3	0	0
T61	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	313	0	0
T3	504	1	0	0
T7	490	1	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T19	0	2	0	0
T28	502	0	0	0
T29	521	0	0	0
T33	0	6	0	0
T34	0	1	0	0
T35	0	1	0	0
T54	0	3	0	0
T61	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	313	0	0
T3	504	1	0	0
T7	490	1	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T19	0	2	0	0
T28	502	0	0	0
T29	521	0	0	0
T33	0	6	0	0
T34	0	1	0	0
T35	0	1	0	0
T54	0	3	0	0
T61	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	12850	0	0
T3	504	2	0	0
T7	490	2	0	0
T8	511	2	0	0
T12	0	2	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T19	0	30	0	0
T28	502	0	0	0
T29	521	0	0	0
T33	0	305	0	0
T34	0	113	0	0
T35	0	112	0	0
T54	0	258	0	0
T61	0	2	0	0
T65	504	0	0	0
T73	573	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	279	0	0
T3	504	1	0	0
T7	490	1	0	0
T8	511	1	0	0
T12	0	1	0	0
T16	431	0	0	0
T17	435	0	0	0
T18	403	0	0	0
T19	0	2	0	0
T28	502	0	0	0
T29	521	0	0	0
T33	0	6	0	0
T34	0	1	0	0
T44	0	3	0	0
T54	0	1	0	0
T61	0	1	0	0
T65	504	0	0	0
T73	573	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T33 T34 T35 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T33 T34 T35 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T33 T34 T35 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T33 T34 T35 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T33 T34 T35 
129        1/1              cnt_en = 1'b0;
           Tests:       T33 T34 T35 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T33 T34 T35 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T33 T34 T35 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T33 T34 T35 
139                     
140        1/1              unique case (state_q)
           Tests:       T33 T34 T35 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T33 T34 T35 
148        1/1                    state_d = DebounceSt;
           Tests:       T33 T34 T35 
149        1/1                    cnt_en = 1'b1;
           Tests:       T33 T34 T35 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T33 T34 T35 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T33 T34 T35 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T33 T34 T35 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
167        1/1                    if (trigger_active) begin
           Tests:       T33 T34 T35 
168        1/1                      state_d = DetectSt;
           Tests:       T33 T34 T35 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T35 T95 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T33 T34 T35 
182        1/1                  cnt_en = 1'b1;
           Tests:       T33 T34 T35 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T33 T34 T35 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T54 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T54 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T33 T34 T35 
191        1/1                      state_d = StableSt;
           Tests:       T33 T34 T35 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T33 T34 T35 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T33 T34 T35 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T33 T34 T35 
206        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T35 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T33 T34 T35 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T33,T34,T35
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T33,T34,T35
1	1	Covered	T33,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T35,T54,T44
1	0	Covered	T34,T35,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T33,T34,T35
1	0	Covered	T245

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T34,T35
1	-	Covered	T33,T34,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T33,T34,T35
DetectSt	168	Covered	T33,T34,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T33,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T34,T35
DebounceSt->IdleSt	163	Covered	T34,T35,T95
DetectSt->IdleSt	186	Covered	T34,T35,T54
DetectSt->StableSt	191	Covered	T33,T34,T35
IdleSt->DebounceSt	148	Covered	T33,T34,T35
StableSt->IdleSt	206	Covered	T33,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T33,T34,T35
0	1	Covered	T33,T34,T35
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T35
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T33,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T33,T34,T35
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T35,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T54
DetectSt	-	-	-	-	0	1	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	0	0	-	Covered	T33,T34,T35
StableSt	-	-	-	-	-	-	1	Covered	T33,T34,T35
StableSt	-	-	-	-	-	-	0	Covered	T33,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	2924	0	0
CntIncr_A	6662990	104832	0	0
CntNoWrap_A	6662990	6213252	0	0
DetectStDropOut_A	6662990	272	0	0
DetectedOut_A	6662990	88768	0	0
DetectedPulseOut_A	6662990	958	0	0
DisabledIdleSt_A	6662990	5734136	0	0
DisabledNoDetection_A	6662990	5735734	0	0
EnterDebounceSt_A	6662990	1479	0	0
EnterDetectSt_A	6662990	1445	0	0
EnterStableSt_A	6662990	958	0	0
PulseIsPulse_A	6662990	958	0	0
StayInStableSt	6662990	87682	0	0
gen_high_event_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_high_level_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_not_sticky_sva.StableStDropOut_A	6662990	828	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	2924	0	0
T33	24338	16	0	0
T34	0	15	0	0
T35	0	16	0	0
T44	0	44	0	0
T52	814	0	0	0
T54	0	26	0	0
T83	496	0	0	0
T92	0	24	0	0
T93	0	38	0	0
T94	0	48	0	0
T95	0	17	0	0
T96	0	32	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	104832	0	0
T33	24338	448	0	0
T34	0	253	0	0
T35	0	626	0	0
T44	0	1946	0	0
T52	814	0	0	0
T54	0	996	0	0
T83	496	0	0	0
T92	0	510	0	0
T93	0	1211	0	0
T94	0	600	0	0
T95	0	799	0	0
T96	0	944	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6213252	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	272	0	0
T35	8501	1	0	0
T44	0	7	0	0
T51	712	0	0	0
T54	16854	3	0	0
T64	676	0	0	0
T84	488	0	0	0
T92	0	12	0	0
T93	0	19	0	0
T123	0	6	0	0
T198	0	4	0	0
T207	431	0	0	0
T208	402	0	0	0
T209	525	0	0	0
T210	422	0	0	0
T240	0	13	0	0
T241	0	9	0	0
T242	502	0	0	0
T246	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	88768	0	0
T33	24338	981	0	0
T34	0	307	0	0
T35	0	448	0	0
T47	0	1876	0	0
T52	814	0	0	0
T83	496	0	0	0
T94	0	1559	0	0
T96	0	2686	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	1221	0	0
T243	0	2787	0	0
T244	0	877	0	0
T247	0	266	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	958	0	0
T33	24338	8	0	0
T34	0	5	0	0
T35	0	5	0	0
T47	0	14	0	0
T52	814	0	0	0
T83	496	0	0	0
T94	0	24	0	0
T96	0	16	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	11	0	0
T243	0	22	0	0
T244	0	27	0	0
T247	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5734136	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5735734	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1479	0	0
T33	24338	8	0	0
T34	0	9	0	0
T35	0	9	0	0
T44	0	22	0	0
T52	814	0	0	0
T54	0	13	0	0
T83	496	0	0	0
T92	0	12	0	0
T93	0	19	0	0
T94	0	24	0	0
T95	0	17	0	0
T96	0	16	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1445	0	0
T33	24338	8	0	0
T34	0	6	0	0
T35	0	7	0	0
T44	0	22	0	0
T52	814	0	0	0
T54	0	13	0	0
T83	496	0	0	0
T92	0	12	0	0
T93	0	19	0	0
T94	0	24	0	0
T96	0	16	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T243	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	958	0	0
T33	24338	8	0	0
T34	0	5	0	0
T35	0	5	0	0
T47	0	14	0	0
T52	814	0	0	0
T83	496	0	0	0
T94	0	24	0	0
T96	0	16	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	11	0	0
T243	0	22	0	0
T244	0	27	0	0
T247	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	958	0	0
T33	24338	8	0	0
T34	0	5	0	0
T35	0	5	0	0
T47	0	14	0	0
T52	814	0	0	0
T83	496	0	0	0
T94	0	24	0	0
T96	0	16	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	11	0	0
T243	0	22	0	0
T244	0	27	0	0
T247	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	87682	0	0
T33	24338	972	0	0
T34	0	302	0	0
T35	0	443	0	0
T47	0	1856	0	0
T52	814	0	0	0
T83	496	0	0	0
T94	0	1530	0	0
T96	0	2664	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	1206	0	0
T243	0	2765	0	0
T244	0	850	0	0
T247	0	259	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	828	0	0
T33	24338	7	0	0
T34	0	5	0	0
T35	0	5	0	0
T47	0	8	0	0
T52	814	0	0	0
T83	496	0	0	0
T94	0	19	0	0
T96	0	10	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	7	0	0
T243	0	22	0	0
T244	0	27	0	0
T247	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T19 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T19 T33 T34 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T19 T33 T34 
149        1/1                    cnt_en = 1'b1;
           Tests:       T19 T33 T34 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T19 T33 T34 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T19 T33 T34 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T19 T33 T34 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T19 T33 T34 
167        1/1                    if (trigger_active) begin
           Tests:       T19 T33 T34 
168        1/1                      state_d = DetectSt;
           Tests:       T19 T33 T34 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T94 T45 T96 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T19 T33 T34 
182        1/1                  cnt_en = 1'b1;
           Tests:       T19 T33 T34 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T19 T33 T34 
186        1/1                    state_d = IdleSt;
           Tests:       T19 T34 T35 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T19 T34 T35 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T19 T33 T34 
191        1/1                      state_d = StableSt;
           Tests:       T33 T34 T35 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T33 T34 T35 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T33 T34 T35 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T33 T34 T35 
206        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T35 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T33 T34 T35 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T33,T34
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T33,T34
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T33,T34
1	0	Covered	T113,T87,T114
1	1	Covered	T19,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T33,T34
0	1	Covered	T19,T35,T248
1	0	Covered	T34,T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T33,T55,T45
1	0	Covered	T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T34,T35
1	-	Covered	T33,T35,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T33,T34
DetectSt	168	Covered	T19,T33,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T33,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T33,T34
DebounceSt->IdleSt	163	Covered	T34,T35,T94
DetectSt->IdleSt	186	Covered	T19,T34,T35
DetectSt->StableSt	191	Covered	T33,T34,T35
IdleSt->DebounceSt	148	Covered	T19,T33,T34
StableSt->IdleSt	206	Covered	T33,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T33,T34
0	1	Covered	T19,T33,T34
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T19,T33,T34
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T33,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T45,T96
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T19,T34,T35
DetectSt	-	-	-	-	0	1	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	0	0	-	Covered	T19,T33,T34
StableSt	-	-	-	-	-	-	1	Covered	T33,T34,T35
StableSt	-	-	-	-	-	-	0	Covered	T33,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	743	0	0
CntIncr_A	6662990	40993	0	0
CntNoWrap_A	6662990	6215433	0	0
DetectStDropOut_A	6662990	58	0	0
DetectedOut_A	6662990	11998	0	0
DetectedPulseOut_A	6662990	291	0	0
DisabledIdleSt_A	6662990	5886112	0	0
DisabledNoDetection_A	6662990	5887335	0	0
EnterDebounceSt_A	6662990	391	0	0
EnterDetectSt_A	6662990	352	0	0
EnterStableSt_A	6662990	291	0	0
PulseIsPulse_A	6662990	291	0	0
StayInStableSt	6662990	11655	0	0
gen_high_level_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_not_sticky_sva.StableStDropOut_A	6662990	237	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	743	0	0
T19	6727	6	0	0
T33	0	2	0	0
T34	0	8	0	0
T35	0	8	0	0
T41	0	4	0	0
T45	0	22	0	0
T53	638	0	0	0
T55	0	2	0	0
T62	680	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T94	0	7	0	0
T96	0	13	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T249	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	40993	0	0
T19	6727	453	0	0
T33	0	52	0	0
T34	0	125	0	0
T35	0	262	0	0
T41	0	342	0	0
T45	0	1066	0	0
T53	638	0	0	0
T55	0	127	0	0
T62	680	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T94	0	110	0	0
T96	0	598	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T249	0	320	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6215433	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	58	0	0
T19	6727	3	0	0
T35	0	1	0	0
T53	638	0	0	0
T62	680	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T248	0	1	0	0
T250	0	2	0	0
T251	0	13	0	0
T252	0	6	0	0
T253	0	15	0	0
T254	0	6	0	0
T255	0	7	0	0
T256	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	11998	0	0
T33	24338	93	0	0
T34	0	114	0	0
T35	0	113	0	0
T41	0	38	0	0
T42	0	27	0	0
T45	0	891	0	0
T52	814	0	0	0
T55	0	7	0	0
T83	496	0	0	0
T94	0	79	0	0
T96	0	332	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T249	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	291	0	0
T33	24338	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T41	0	2	0	0
T42	0	5	0	0
T45	0	10	0	0
T52	814	0	0	0
T55	0	1	0	0
T83	496	0	0	0
T94	0	3	0	0
T96	0	6	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T249	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5886112	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5887335	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	391	0	0
T19	6727	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T35	0	5	0	0
T41	0	2	0	0
T45	0	12	0	0
T53	638	0	0	0
T55	0	1	0	0
T62	680	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T94	0	4	0	0
T96	0	7	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T249	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	352	0	0
T19	6727	3	0	0
T33	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T41	0	2	0	0
T45	0	10	0	0
T53	638	0	0	0
T55	0	1	0	0
T62	680	0	0	0
T66	4402	0	0	0
T67	409	0	0	0
T68	427	0	0	0
T82	491	0	0	0
T94	0	3	0	0
T96	0	6	0	0
T104	4452	0	0	0
T105	402	0	0	0
T106	509	0	0	0
T249	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	291	0	0
T33	24338	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T41	0	2	0	0
T42	0	5	0	0
T45	0	10	0	0
T52	814	0	0	0
T55	0	1	0	0
T83	496	0	0	0
T94	0	3	0	0
T96	0	6	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T249	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	291	0	0
T33	24338	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T41	0	2	0	0
T42	0	5	0	0
T45	0	10	0	0
T52	814	0	0	0
T55	0	1	0	0
T83	496	0	0	0
T94	0	3	0	0
T96	0	6	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T249	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	11655	0	0
T33	24338	92	0	0
T34	0	113	0	0
T35	0	112	0	0
T41	0	36	0	0
T42	0	22	0	0
T45	0	881	0	0
T52	814	0	0	0
T55	0	6	0	0
T83	496	0	0	0
T94	0	73	0	0
T96	0	320	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T249	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	237	0	0
T33	24338	1	0	0
T41	0	2	0	0
T42	0	5	0	0
T43	0	1	0	0
T45	0	10	0	0
T46	0	6	0	0
T52	814	0	0	0
T55	0	1	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	4	0	0
T249	0	2	0	0
T257	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T33 T34 T35 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T33 T34 T35 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T33 T34 T35 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T33 T34 T35 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T33 T34 T35 
129        1/1              cnt_en = 1'b0;
           Tests:       T33 T34 T35 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T33 T34 T35 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T33 T34 T35 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T33 T34 T35 
139                     
140        1/1              unique case (state_q)
           Tests:       T33 T34 T35 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T33 T34 T35 
148        1/1                    state_d = DebounceSt;
           Tests:       T33 T34 T35 
149        1/1                    cnt_en = 1'b1;
           Tests:       T33 T34 T35 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T33 T34 T35 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T33 T34 T35 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T33 T34 T35 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
167        1/1                    if (trigger_active) begin
           Tests:       T33 T34 T35 
168        1/1                      state_d = DetectSt;
           Tests:       T33 T34 T35 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T35 T95 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T33 T34 T35 
182        1/1                  cnt_en = 1'b1;
           Tests:       T33 T34 T35 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T33 T34 T35 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T92 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T92 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T33 T34 T35 
191        1/1                      state_d = StableSt;
           Tests:       T33 T34 T35 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T33 T34 T35 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T33 T34 T35 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T33 T34 T35 
206        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T35 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T33 T34 T35 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T33,T34,T35
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T33,T34,T35
1	1	Covered	T33,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T34,T35,T92
1	0	Covered	T34,T35,T94

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T33,T34,T35
1	0	Covered	T35,T258,T259

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T34,T35
1	-	Covered	T33,T34,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T33,T34,T35
DetectSt	168	Covered	T33,T34,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T33,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T34,T35
DebounceSt->IdleSt	163	Covered	T34,T35,T95
DetectSt->IdleSt	186	Covered	T34,T35,T92
DetectSt->StableSt	191	Covered	T33,T34,T35
IdleSt->DebounceSt	148	Covered	T33,T34,T35
StableSt->IdleSt	206	Covered	T33,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T33,T34,T35
0	1	Covered	T33,T34,T35
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T35
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T33,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T33,T34,T35
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T35,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T92
DetectSt	-	-	-	-	0	1	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	0	0	-	Covered	T33,T34,T35
StableSt	-	-	-	-	-	-	1	Covered	T33,T34,T35
StableSt	-	-	-	-	-	-	0	Covered	T33,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	2997	0	0
CntIncr_A	6662990	106067	0	0
CntNoWrap_A	6662990	6213179	0	0
DetectStDropOut_A	6662990	353	0	0
DetectedOut_A	6662990	82577	0	0
DetectedPulseOut_A	6662990	1003	0	0
DisabledIdleSt_A	6662990	5734759	0	0
DisabledNoDetection_A	6662990	5736364	0	0
EnterDebounceSt_A	6662990	1516	0	0
EnterDetectSt_A	6662990	1482	0	0
EnterStableSt_A	6662990	1003	0	0
PulseIsPulse_A	6662990	1003	0	0
StayInStableSt	6662990	81453	0	0
gen_high_event_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_high_level_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_not_sticky_sva.StableStDropOut_A	6662990	859	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	2997	0	0
T33	24338	18	0	0
T34	0	16	0	0
T35	0	16	0	0
T44	0	44	0	0
T52	814	0	0	0
T54	0	42	0	0
T83	496	0	0	0
T92	0	20	0	0
T93	0	30	0	0
T94	0	58	0	0
T95	0	9	0	0
T96	0	22	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	106067	0	0
T33	24338	504	0	0
T34	0	449	0	0
T35	0	513	0	0
T44	0	1584	0	0
T52	814	0	0	0
T54	0	1512	0	0
T83	496	0	0	0
T92	0	423	0	0
T93	0	955	0	0
T94	0	1405	0	0
T95	0	423	0	0
T96	0	752	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6213179	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	353	0	0
T34	6335	1	0	0
T35	8501	1	0	0
T63	742	0	0	0
T64	676	0	0	0
T84	488	0	0	0
T92	0	10	0	0
T93	0	15	0	0
T94	0	15	0	0
T96	0	5	0	0
T123	0	5	0	0
T207	431	0	0	0
T208	402	0	0	0
T209	525	0	0	0
T210	422	0	0	0
T240	0	15	0	0
T241	0	5	0	0
T242	502	0	0	0
T246	0	20	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	82577	0	0
T33	24338	1337	0	0
T34	0	339	0	0
T35	0	519	0	0
T44	0	1471	0	0
T47	0	2814	0	0
T52	814	0	0	0
T54	0	1720	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	2216	0	0
T126	0	134	0	0
T198	0	1446	0	0
T244	0	855	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1003	0	0
T33	24338	9	0	0
T34	0	5	0	0
T35	0	5	0	0
T44	0	22	0	0
T47	0	28	0	0
T52	814	0	0	0
T54	0	21	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	14	0	0
T126	0	14	0	0
T198	0	25	0	0
T244	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5734759	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5736364	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1516	0	0
T33	24338	9	0	0
T34	0	9	0	0
T35	0	9	0	0
T44	0	22	0	0
T52	814	0	0	0
T54	0	21	0	0
T83	496	0	0	0
T92	0	10	0	0
T93	0	15	0	0
T94	0	29	0	0
T95	0	9	0	0
T96	0	11	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1482	0	0
T33	24338	9	0	0
T34	0	7	0	0
T35	0	7	0	0
T44	0	22	0	0
T52	814	0	0	0
T54	0	21	0	0
T83	496	0	0	0
T92	0	10	0	0
T93	0	15	0	0
T94	0	29	0	0
T96	0	11	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T243	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1003	0	0
T33	24338	9	0	0
T34	0	5	0	0
T35	0	5	0	0
T44	0	22	0	0
T47	0	28	0	0
T52	814	0	0	0
T54	0	21	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	14	0	0
T126	0	14	0	0
T198	0	25	0	0
T244	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	1003	0	0
T33	24338	9	0	0
T34	0	5	0	0
T35	0	5	0	0
T44	0	22	0	0
T47	0	28	0	0
T52	814	0	0	0
T54	0	21	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	14	0	0
T126	0	14	0	0
T198	0	25	0	0
T244	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	81453	0	0
T33	24338	1325	0	0
T34	0	334	0	0
T35	0	514	0	0
T44	0	1447	0	0
T47	0	2779	0	0
T52	814	0	0	0
T54	0	1695	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	2198	0	0
T126	0	120	0	0
T198	0	1421	0	0
T244	0	840	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	859	0	0
T33	24338	6	0	0
T34	0	5	0	0
T35	0	4	0	0
T44	0	20	0	0
T47	0	21	0	0
T52	814	0	0	0
T54	0	17	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T122	0	10	0	0
T126	0	14	0	0
T198	0	25	0	0
T244	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T19 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T33 T34 T35 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T33 T34 T35 
149        1/1                    cnt_en = 1'b1;
           Tests:       T33 T34 T35 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T33 T34 T35 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T33 T34 T35 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T33 T34 T35 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
167        1/1                    if (trigger_active) begin
           Tests:       T33 T34 T35 
168        1/1                      state_d = DetectSt;
           Tests:       T33 T34 T35 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T42 T43 T124 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T33 T34 T35 
182        1/1                  cnt_en = 1'b1;
           Tests:       T33 T34 T35 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T33 T34 T35 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T260 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T260 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T33 T34 T35 
191        1/1                      state_d = StableSt;
           Tests:       T33 T34 T35 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T33 T34 T35 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T33 T34 T35 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T33 T34 T35 
206        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T35 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T33 T34 T35 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T33,T34
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T33,T34
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T33,T34
1	0	Covered	T113,T87,T114
1	1	Covered	T33,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T35,T260,T248
1	0	Covered	T34,T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T33,T35,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T34,T35
1	-	Covered	T33,T34,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T33,T34,T35
DetectSt	168	Covered	T33,T34,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T33,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T34,T35
DebounceSt->IdleSt	163	Covered	T34,T35,T42
DetectSt->IdleSt	186	Covered	T34,T35,T260
DetectSt->StableSt	191	Covered	T33,T34,T35
IdleSt->DebounceSt	148	Covered	T33,T34,T35
StableSt->IdleSt	206	Covered	T33,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T33,T34,T35
0	1	Covered	T33,T34,T35
0	0	Covered	T4,T5,T1

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T35
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T33,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T35
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T43,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T260
DetectSt	-	-	-	-	0	1	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	0	0	-	Covered	T33,T34,T35
StableSt	-	-	-	-	-	-	1	Covered	T33,T34,T35
StableSt	-	-	-	-	-	-	0	Covered	T33,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6662990	793	0	0
CntIncr_A	6662990	45563	0	0
CntNoWrap_A	6662990	6215383	0	0
DetectStDropOut_A	6662990	29	0	0
DetectedOut_A	6662990	13898	0	0
DetectedPulseOut_A	6662990	343	0	0
DisabledIdleSt_A	6662990	5887327	0	0
DisabledNoDetection_A	6662990	5888560	0	0
EnterDebounceSt_A	6662990	418	0	0
EnterDetectSt_A	6662990	376	0	0
EnterStableSt_A	6662990	343	0	0
PulseIsPulse_A	6662990	343	0	0
StayInStableSt	6662990	13490	0	0
gen_high_level_sva.HighLevelEvent_A	6662990	6217992	0	0
gen_not_sticky_sva.StableStDropOut_A	6662990	277	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	793	0	0
T33	24338	6	0	0
T34	0	8	0	0
T35	0	8	0	0
T41	0	8	0	0
T44	0	4	0	0
T45	0	12	0	0
T52	814	0	0	0
T54	0	8	0	0
T55	0	4	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	2	0	0
T261	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	45563	0	0
T33	24338	168	0	0
T34	0	157	0	0
T35	0	333	0	0
T41	0	396	0	0
T44	0	130	0	0
T45	0	972	0	0
T52	814	0	0	0
T54	0	328	0	0
T55	0	260	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	88	0	0
T261	0	168	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6215383	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	29	0	0
T35	8501	1	0	0
T51	712	0	0	0
T54	16854	0	0	0
T64	676	0	0	0
T84	488	0	0	0
T129	0	5	0	0
T207	431	0	0	0
T208	402	0	0	0
T209	525	0	0	0
T210	422	0	0	0
T242	502	0	0	0
T248	0	6	0	0
T255	0	5	0	0
T256	0	3	0	0
T260	0	1	0	0
T262	0	6	0	0
T263	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	13898	0	0
T33	24338	268	0	0
T34	0	113	0	0
T35	0	114	0	0
T41	0	364	0	0
T44	0	387	0	0
T45	0	104	0	0
T52	814	0	0	0
T54	0	282	0	0
T55	0	8	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	9	0	0
T261	0	164	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	343	0	0
T33	24338	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T41	0	4	0	0
T44	0	2	0	0
T45	0	6	0	0
T52	814	0	0	0
T54	0	4	0	0
T55	0	2	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	1	0	0
T261	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5887327	0	0
T1	613	212	0	0
T2	1420	1019	0	0
T3	504	103	0	0
T4	446	45	0	0
T5	522	121	0	0
T13	495	94	0	0
T14	423	22	0	0
T15	639	238	0	0
T16	431	30	0	0
T17	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	5888560	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	418	0	0
T33	24338	3	0	0
T34	0	5	0	0
T35	0	5	0	0
T41	0	4	0	0
T44	0	2	0	0
T45	0	6	0	0
T52	814	0	0	0
T54	0	4	0	0
T55	0	2	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	1	0	0
T261	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	376	0	0
T33	24338	3	0	0
T34	0	3	0	0
T35	0	3	0	0
T41	0	4	0	0
T44	0	2	0	0
T45	0	6	0	0
T52	814	0	0	0
T54	0	4	0	0
T55	0	2	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	1	0	0
T261	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	343	0	0
T33	24338	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T41	0	4	0	0
T44	0	2	0	0
T45	0	6	0	0
T52	814	0	0	0
T54	0	4	0	0
T55	0	2	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	1	0	0
T261	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	343	0	0
T33	24338	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T41	0	4	0	0
T44	0	2	0	0
T45	0	6	0	0
T52	814	0	0	0
T54	0	4	0	0
T55	0	2	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	1	0	0
T261	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	13490	0	0
T33	24338	265	0	0
T34	0	112	0	0
T35	0	113	0	0
T41	0	360	0	0
T44	0	385	0	0
T45	0	98	0	0
T52	814	0	0	0
T54	0	274	0	0
T55	0	6	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	8	0	0
T261	0	161	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	6217992	0	0
T1	613	213	0	0
T2	1420	1020	0	0
T3	504	104	0	0
T4	446	46	0	0
T5	522	122	0	0
T13	495	95	0	0
T14	423	23	0	0
T15	639	239	0	0
T16	431	31	0	0
T17	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6662990	277	0	0
T33	24338	3	0	0
T35	0	1	0	0
T41	0	4	0	0
T42	0	7	0	0
T44	0	2	0	0
T45	0	6	0	0
T52	814	0	0	0
T55	0	2	0	0
T83	496	0	0	0
T97	440	0	0	0
T98	424	0	0	0
T99	403	0	0	0
T100	504	0	0	0
T101	1144	0	0	0
T102	522	0	0	0
T103	675	0	0	0
T121	0	1	0	0
T249	0	4	0	0
T261	0	3	0	0