Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1807

1

T13

8

T34

8

T42

17

auto[1]

618

1

T13

8

T21

10

T34

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1845

1

T13

12

T42

21

T96

23

auto[1]

580

1

T13

4

T21

10

T34

11

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1891

1

T13

8

T21

9

T34

3

auto[1]

534

1

T13

8

T21

1

T34

8

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1839

1

T13

12

T21

6

T34

5

auto[1]

586

1

T13

4

T21

4

T34

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2265

1

T13

16

T21

10

T34

11

auto[1]

160

1

T42

3

T41

13

T254

6

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2216

1

T13

12

T21

10

T34

11

auto[1]

209

1

T13

4

T42

4

T40

10

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2237

1

T13

16

T21

10

T34

11

auto[1]

188

1

T42

3

T40

3

T41

16

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2192

1

T13

16

T21

10

T34

11

auto[1]

233

1

T42

3

T93

1

T44

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2198

1

T13

12

T21

10

T34

11

auto[1]

227

1

T13

4

T42

4

T40

10

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1935

1

T13

16

T21

9

T42

24

auto[1]

490

1

T21

1

T34

11

T96

5

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	831	1			T21	10		T34	11		T96	23
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	19	1			T42	3		T41	7		T396	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	87	1			T13	4		T41	9		T266	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	19	1			T397	1		T396	3		T398	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	84	1			T93	1		T107	5		T294	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	25	1			T257	6		T375	3		T399	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	27	1			T44	2		T255	10		T281	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T400	3		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	59	1			T41	10		T44	4		T401	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	24	1			T294	3		T375	5		T402	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	17	1			T107	2		T294	3		T281	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	11	1			T41	6		T105	1		T403	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	22	1			T42	3		T282	1		T397	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T282	1		T404	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T405	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	66	1			T13	4		T257	4		T282	8
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	29	1			T254	6		T282	4		T406	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	29	1			T42	4		T40	7		T280	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T407	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	30	1			T408	8		T409	1		T407	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	3	1			T410	2		T411	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	4	1			T397	3		T412	1		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	13	1			T397	4		T413	3		T403	6
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T108	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	6	1			T40	3		T414	3		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	3	1			T415	3		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T385	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

129

1

T41

9

T44

2

T255

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

109

1

T257

6

T282

4

T253

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

73

1

T96

3

T168

5

T283

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

134

1

T96

12

T40

3

T280

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

80

1

T42

4

T96

6

T41

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T115

7

T108

1

T119

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T43

4

T285

2

T289

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

129

1

T42

3

T40

7

T254

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

56

1

T13

4

T255

5

T281

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T168

7

T280

4

T381

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T372

3

T286

6

T287

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T97

10

T244

4

T226

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T261

2

T121

3

T385

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

32

1

T96

2

T41

7

T43

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T113

2

T416

1

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

106

1

T41

6

T107

2

T377

15

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

77

1

T21

5

T42

3

T43

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

36

1

T384

2

T282

1

T376

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T417

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T244

3

T283

4

T281

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T21

4

T97

3

T43

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T97

3

T294

3

T384

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T34

3

T258

1

T284

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T418

7

T409

1

T397

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T258

6

T294

4

T280

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T34

5

T172

3

T284

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T21

1

T93

1

T283

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

20

1

T285

4

T114

2

T377

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T13

4

T281

3

T372

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T34

3

T263

1

T293

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T382

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded