Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

612

1

T15

11

T84

12

T85

8

auto[1]

596

1

T15

9

T84

8

T85

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

300

1

T15

6

T84

6

T85

4

from_0to1

300

1

T15

7

T84

6

T85

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

601

1

T15

10

T84

12

T85

11

auto[1]

607

1

T15

10

T84

8

T85

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

594

1

T15

7

T84

12

T85

12

auto[1]

614

1

T15

13

T84

8

T85

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

37

1

T15

3

T84

2

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

48

1

T84

1

T85

1

T66

1

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T15

1

T84

1

T239

1

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T15

1

T85

1

T66

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T15

1

T87

1

T277

1

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T15

2

T84

1

T85

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T277

2

T125

1

T211

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T15

2

T84

2

T85

1

auto[1]

from_1to0

auto[0]

auto[0]

30

1

T84

2

T85

1

T87

1

auto[1]

from_1to0

auto[0]

auto[1]

35

1

T66

1

T239

2

T61

4

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T66

1

T277

1

T125

2

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T15

1

T85

1

T87

2

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T85

1

T66

1

T87

1

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T15

1

T84

1

T277

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T84

2

T85

1

T66

1

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T15

1

T85

1

T87

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T15

12

T84

11

T85

10

auto[1]

592

1

T15

8

T84

9

T85

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

290

1

T15

3

T84

3

T85

4

from_0to1

293

1

T15

3

T84

3

T85

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

581

1

T15

9

T84

11

T85

13

auto[1]

627

1

T15

11

T84

9

T85

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

611

1

T15

13

T84

7

T85

9

auto[1]

597

1

T15

7

T84

13

T85

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T66

1

T125

1

T239

1

auto[0]

from_1to0

auto[0]

auto[1]

30

1

T84

1

T66

2

T277

1

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T15

1

T84

1

T87

2

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T84

1

T66

1

T239

1

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T66

1

T87

1

T277

1

auto[0]

from_0to1

auto[0]

auto[1]

31

1

T85

1

T66

1

T87

2

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T85

1

T66

2

T277

1

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T15

1

T84

1

T85

1

auto[1]

from_1to0

auto[0]

auto[0]

36

1

T85

1

T87

2

T125

1

auto[1]

from_1to0

auto[0]

auto[1]

33

1

T15

1

T85

1

T87

1

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T85

1

T66

1

T277

1

auto[1]

from_1to0

auto[1]

auto[1]

29

1

T15

1

T85

1

T87

1

auto[1]

from_0to1

auto[0]

auto[0]

27

1

T277

1

T211

1

T436

2

auto[1]

from_0to1

auto[0]

auto[1]

32

1

T84

1

T87

1

T159

1

auto[1]

from_0to1

auto[1]

auto[0]

45

1

T15

2

T84

1

T66

1

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T277

1

T125

2

T239

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

590

1

T15

8

T84

11

T85

15

auto[1]

618

1

T15

12

T84

9

T85

5

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

253

1

T15

3

T84

3

T85

4

from_0to1

260

1

T15

4

T84

4

T85

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

612

1

T15

12

T84

13

T85

15

auto[1]

596

1

T15

8

T84

7

T85

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

591

1

T15

11

T84

12

T85

11

auto[1]

617

1

T15

9

T84

8

T85

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

32

1

T15

2

T84

1

T277

1

auto[0]

from_1to0

auto[0]

auto[1]

32

1

T85

3

T277

1

T125

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T84

1

T87

2

T277

1

auto[0]

from_1to0

auto[1]

auto[1]

17

1

T235

1

T437

1

T336

1

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T15

1

T85

2

T239

2

auto[0]

from_0to1

auto[0]

auto[1]

32

1

T84

1

T85

1

T61

2

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T84

1

T85

1

T87

2

auto[0]

from_0to1

auto[1]

auto[1]

29

1

T66

1

T277

1

T61

1

auto[1]

from_1to0

auto[0]

auto[0]

28

1

T84

1

T85

1

T277

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T66

1

T87

1

T239

1

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T66

2

T61

1

T235

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T15

1

T87

1

T239

1

auto[1]

from_0to1

auto[0]

auto[0]

28

1

T15

2

T87

1

T277

1

auto[1]

from_0to1

auto[0]

auto[1]

31

1

T15

1

T84

1

T66

2

auto[1]

from_0to1

auto[1]

auto[0]

30

1

T125

1

T61

4

T437

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T84

1

T87

1

T277

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630

1

T15

11

T84

7

T85

11

auto[1]

578

1

T15

9

T84

13

T85

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

275

1

T15

6

T84

3

T85

6

from_0to1

281

1

T15

5

T84

3

T85

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

596

1

T15

15

T84

8

T85

13

auto[1]

612

1

T15

5

T84

12

T85

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T15

11

T84

14

T85

12

auto[1]

566

1

T15

9

T84

6

T85

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

26

1

T15

1

T85

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

35

1

T15

1

T85

1

T277

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T15

1

T84

1

T85

1

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T15

1

T125

2

T239

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T15

1

T85

3

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

29

1

T239

1

T61

1

T235

1

auto[0]

from_0to1

auto[1]

auto[0]

34

1

T66

2

T87

1

T211

1

auto[0]

from_0to1

auto[1]

auto[1]

31

1

T277

1

T239

2

T235

1

auto[1]

from_1to0

auto[0]

auto[0]

42

1

T15

1

T84

1

T85

1

auto[1]

from_1to0

auto[0]

auto[1]

27

1

T84

1

T85

1

T66

1

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T85

1

T61

2

T211

1

auto[1]

from_1to0

auto[1]

auto[1]

29

1

T15

1

T87

1

T211

1

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T15

2

T84

1

T87

2

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T15

2

T85

1

T87

1

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T84

2

T66

1

T277

1

auto[1]

from_0to1

auto[1]

auto[1]

34

1

T85

2

T66

2

T239

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

633

1

T15

10

T84

13

T85

13

auto[1]

575

1

T15

10

T84

7

T85

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

282

1

T15

5

T84

4

T85

3

from_0to1

281

1

T15

5

T84

5

T85

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

608

1

T15

12

T84

9

T85

10

auto[1]

600

1

T15

8

T84

11

T85

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T15

12

T84

5

T85

11

auto[1]

604

1

T15

8

T84

15

T85

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T15

1

T84

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

34

1

T15

1

T84

2

T87

1

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T15

1

T85

2

T66

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T84

1

T66

1

T239

2

auto[0]

from_0to1

auto[0]

auto[0]

29

1

T66

1

T159

1

T437

1

auto[0]

from_0to1

auto[0]

auto[1]

43

1

T15

1

T85

3

T87

1

auto[0]

from_0to1

auto[1]

auto[0]

31

1

T87

1

T277

1

T239

2

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T84

2

T66

1

T87

2

auto[1]

from_1to0

auto[0]

auto[0]

29

1

T15

1

T239

2

T235

1

auto[1]

from_1to0

auto[0]

auto[1]

33

1

T66

3

T277

1

T125

1

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T87

1

T125

1

T239

1

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T15

1

T85

1

T66

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T15

1

T84

1

T66

2

auto[1]

from_0to1

auto[0]

auto[1]

24

1

T15

1

T66

1

T277

2

auto[1]

from_0to1

auto[1]

auto[0]

42

1

T15

2

T66

1

T239

3

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T84

2

T85

1

T66

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

594

1

T15

11

T84

6

T85

9

auto[1]

614

1

T15

9

T84

14

T85

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

294

1

T15

3

T84

5

T85

5

from_0to1

288

1

T15

4

T84

5

T85

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620

1

T15

13

T84

9

T85

11

auto[1]

588

1

T15

7

T84

11

T85

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

601

1

T15

10

T84

9

T85

8

auto[1]

607

1

T15

10

T84

11

T85

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

31

1

T15

1

T85

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T66

1

T87

2

T277

2

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T85

1

T87

1

T125

1

auto[0]

from_1to0

auto[1]

auto[1]

29

1

T84

4

T66

1

T277

1

auto[0]

from_0to1

auto[0]

auto[0]

29

1

T277

1

T61

1

T235

1

auto[0]

from_0to1

auto[0]

auto[1]

28

1

T85

1

T87

1

T277

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T277

1

T125

2

T239

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T15

1

T85

1

T87

1

auto[1]

from_1to0

auto[0]

auto[0]

44

1

T85

1

T87

2

T277

1

auto[1]

from_1to0

auto[0]

auto[1]

34

1

T84

1

T87

1

T239

1

auto[1]

from_1to0

auto[1]

auto[0]

35

1

T15

1

T66

1

T125

2

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T15

1

T85

2

T277

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T15

2

T84

2

T85

1

auto[1]

from_0to1

auto[0]

auto[1]

28

1

T84

1

T85

1

T61

2

auto[1]

from_0to1

auto[1]

auto[0]

28

1

T85

1

T87

1

T277

2

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T15

1

T84

2

T66

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

615

1

T15

13

T84

12

T85

12

auto[1]

593

1

T15

7

T84

8

T85

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

282

1

T15

4

T84

4

T85

5

from_0to1

291

1

T15

4

T84

4

T85

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609

1

T15

9

T84

9

T85

11

auto[1]

599

1

T15

11

T84

11

T85

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T15

17

T84

10

T85

10

auto[1]

592

1

T15

3

T84

10

T85

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T15

2

T84

2

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T85

1

T61

3

T235

1

auto[0]

from_1to0

auto[1]

auto[0]

30

1

T15

2

T87

1

T125

1

auto[0]

from_1to0

auto[1]

auto[1]

28

1

T87

2

T239

2

T61

2

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T15

2

T66

2

T87

1

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T84

1

T85

3

T87

2

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T61

2

T211

1

T436

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T15

1

T84

1

T125

2

auto[1]

from_1to0

auto[0]

auto[0]

26

1

T85

1

T66

1

T87

1

auto[1]

from_1to0

auto[0]

auto[1]

33

1

T87

1

T61

1

T235

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T84

1

T85

2

T66

3

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T84

1

T85

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T84

1

T66

1

T125

1

auto[1]

from_0to1

auto[0]

auto[1]

27

1

T87

1

T277

2

T61

2

auto[1]

from_0to1

auto[1]

auto[0]

42

1

T15

1

T85

2

T66

2

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T84

1

T85

1

T87

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

594

1

T15

10

T84

12

T85

8

auto[1]

614

1

T15

10

T84

8

T85

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

283

1

T15

3

T84

3

T85

6

from_0to1

284

1

T15

3

T84

4

T85

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

626

1

T15

14

T84

10

T85

9

auto[1]

582

1

T15

6

T84

10

T85

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

615

1

T15

12

T84

13

T85

10

auto[1]

593

1

T15

8

T84

7

T85

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T15

1

T84

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

32

1

T84

1

T66

1

T277

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T85

2

T125

2

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

38

1

T84

1

T66

1

T87

1

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T85

1

T66

1

T87

1

auto[0]

from_0to1

auto[0]

auto[1]

30

1

T277

1

T125

2

T239

1

auto[0]

from_0to1

auto[1]

auto[0]

32

1

T84

1

T277

1

T125

1

auto[0]

from_0to1

auto[1]

auto[1]

31

1

T15

1

T85

1

T61

1

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T15

2

T85

1

T66

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T85

2

T66

1

T125

1

auto[1]

from_1to0

auto[1]

auto[0]

35

1

T87

1

T277

1

T61

2

auto[1]

from_1to0

auto[1]

auto[1]

29

1

T85

1

T66

1

T87

1

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T66

2

T125

1

T239

1

auto[1]

from_0to1

auto[0]

auto[1]

34

1

T84

1

T85

1

T66

1

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T15

2

T84

2

T85

1

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T85

2

T66

1

T277

2