Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	137828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

107891

1

T4

1

T5

7

T6

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	127664	1			T4	2		T5	3		T6	22
values[0x0]	58664	1			T5	5		T22	4		T23	8
values[0x1]	59391	1			T4	1		T5	4		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	111274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

134445

1

T4

3

T5

8

T6

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2244	1			T20	2		T71	1		T9	1
valid_sources[0x01]	904	1			T14	1		T20	2		T3	1
valid_sources[0x02]	644	1			T20	1		T66	1		T79	7
valid_sources[0x03]	842	1			T14	2		T182	1		T13	16
valid_sources[0x04]	1693	1			T22	1		T104	9		T182	3
valid_sources[0x05]	859	1			T20	2		T77	3		T10	1
valid_sources[0x06]	775	1			T14	2		T20	4		T71	2
valid_sources[0x07]	788	1			T20	1		T104	4		T71	2
valid_sources[0x08]	888	1			T10	1		T35	5		T241	2
valid_sources[0x09]	741	1			T20	3		T104	5		T182	1
valid_sources[0x0a]	828	1			T14	1		T20	3		T84	2
valid_sources[0x0b]	871	1			T20	2		T10	3		T151	2
valid_sources[0x0c]	828	1			T20	2		T84	1		T10	1
valid_sources[0x0d]	849	1			T2	2		T18	4		T20	1
valid_sources[0x0e]	848	1			T14	1		T10	1		T65	1
valid_sources[0x0f]	1032	1			T20	1		T84	2		T77	2
valid_sources[0x10]	1526	1			T29	1		T7	1		T66	2
valid_sources[0x11]	937	1			T14	1		T20	1		T9	1
valid_sources[0x12]	909	1			T104	7		T65	1		T317	1
valid_sources[0x13]	1033	1			T20	2		T70	2		T10	3
valid_sources[0x14]	836	1			T29	1		T104	1		T71	1
valid_sources[0x15]	2394	1			T20	2		T84	1		T71	1
valid_sources[0x16]	937	1			T20	1		T71	1		T66	1
valid_sources[0x17]	754	1			T14	1		T20	1		T85	6
valid_sources[0x18]	631	1			T20	1		T84	2		T56	2
valid_sources[0x19]	1045	1			T20	1		T31	1		T10	5
valid_sources[0x1a]	725	1			T71	2		T85	1		T10	2
valid_sources[0x1b]	835	1			T85	1		T57	1		T277	1
valid_sources[0x1c]	770	1			T2	1		T20	1		T10	1
valid_sources[0x1d]	746	1			T56	2		T104	2		T85	5
valid_sources[0x1e]	910	1			T66	1		T79	1		T34	7
valid_sources[0x1f]	936	1			T29	1		T144	1		T10	1
valid_sources[0x20]	1759	1			T14	2		T20	2		T3	2
valid_sources[0x21]	888	1			T4	1		T14	1		T20	1
valid_sources[0x22]	1217	1			T20	1		T84	2		T104	4
valid_sources[0x23]	832	1			T32	4		T77	3		T10	2
valid_sources[0x24]	819	1			T3	1		T104	4		T10	2
valid_sources[0x25]	709	1			T1	1		T20	2		T84	1
valid_sources[0x26]	883	1			T20	1		T29	2		T66	1
valid_sources[0x27]	978	1			T14	1		T29	1		T66	1
valid_sources[0x28]	844	1			T20	3		T71	2		T10	1
valid_sources[0x29]	881	1			T23	3		T20	1		T84	1
valid_sources[0x2a]	691	1			T182	1		T85	1		T10	2
valid_sources[0x2b]	985	1			T20	1		T35	6		T125	1
valid_sources[0x2c]	1030	1			T23	7		T29	1		T10	2
valid_sources[0x2d]	784	1			T20	1		T84	2		T182	1
valid_sources[0x2e]	791	1			T20	3		T84	2		T182	1
valid_sources[0x2f]	717	1			T84	1		T31	1		T65	1
valid_sources[0x30]	665	1			T22	1		T77	2		T277	1
valid_sources[0x31]	1110	1			T20	1		T84	1		T69	6
valid_sources[0x32]	977	1			T70	1		T77	2		T10	1
valid_sources[0x33]	1077	1			T4	1		T20	1		T10	2
valid_sources[0x34]	1067	1			T29	2		T13	116		T275	1
valid_sources[0x35]	966	1			T20	1		T84	3		T104	7
valid_sources[0x36]	876	1			T2	4		T20	1		T182	1
valid_sources[0x37]	825	1			T1	2		T18	17		T20	1
valid_sources[0x38]	892	1			T20	3		T85	2		T35	1
valid_sources[0x39]	758	1			T20	2		T29	1		T58	1
valid_sources[0x3a]	911	1			T18	7		T20	1		T77	4
valid_sources[0x3b]	1021	1			T20	1		T182	1		T31	2
valid_sources[0x3c]	693	1			T14	1		T65	1		T35	2
valid_sources[0x3d]	867	1			T20	1		T71	1		T10	1
valid_sources[0x3e]	948	1			T1	10		T29	1		T104	2
valid_sources[0x3f]	817	1			T23	5		T20	1		T84	1
valid_sources[0x40]	838	1			T14	1		T2	1		T20	1
valid_sources[0x41]	859	1			T84	3		T10	1		T275	1
valid_sources[0x42]	753	1			T20	1		T10	2		T66	1
valid_sources[0x43]	1700	1			T84	1		T71	1		T10	1
valid_sources[0x44]	710	1			T20	1		T56	1		T10	1
valid_sources[0x45]	1896	1			T14	1		T84	2		T10	4
valid_sources[0x46]	759	1			T20	1		T3	1		T84	1
valid_sources[0x47]	788	1			T20	1		T84	1		T56	2
valid_sources[0x48]	847	1			T20	1		T7	1		T10	1
valid_sources[0x49]	1603	1			T71	2		T35	1		T61	10
valid_sources[0x4a]	731	1			T16	2		T20	1		T71	1
valid_sources[0x4b]	982	1			T20	1		T84	1		T10	3
valid_sources[0x4c]	793	1			T29	1		T10	1		T12	1
valid_sources[0x4d]	1668	1			T20	1		T104	2		T65	1
valid_sources[0x4e]	753	1			T6	23		T3	2		T84	1
valid_sources[0x4f]	870	1			T14	1		T18	21		T29	1
valid_sources[0x50]	2229	1			T23	9		T20	1		T84	1
valid_sources[0x51]	675	1			T20	1		T10	1		T35	2
valid_sources[0x52]	1363	1			T20	2		T77	4		T35	2
valid_sources[0x53]	678	1			T1	1		T20	1		T29	1
valid_sources[0x54]	924	1			T20	1		T29	1		T58	1
valid_sources[0x55]	985	1			T23	3		T14	1		T20	1
valid_sources[0x56]	843	1			T20	2		T29	1		T71	1
valid_sources[0x57]	826	1			T14	1		T84	1		T66	2
valid_sources[0x58]	1310	1			T14	1		T20	3		T84	1
valid_sources[0x59]	1689	1			T84	1		T104	4		T65	1
valid_sources[0x5a]	1002	1			T20	1		T71	2		T10	1
valid_sources[0x5b]	829	1			T3	1		T84	4		T31	1
valid_sources[0x5c]	683	1			T4	1		T23	2		T20	1
valid_sources[0x5d]	803	1			T84	1		T10	2		T58	1
valid_sources[0x5e]	834	1			T20	1		T84	2		T72	3
valid_sources[0x5f]	828	1			T1	3		T20	1		T182	1
valid_sources[0x60]	963	1			T84	1		T182	1		T10	3
valid_sources[0x61]	978	1			T20	2		T84	2		T31	1
valid_sources[0x62]	1655	1			T20	2		T84	1		T71	1
valid_sources[0x63]	688	1			T84	1		T65	1		T66	1
valid_sources[0x64]	1763	1			T20	3		T84	1		T29	1
valid_sources[0x65]	693	1			T22	1		T20	3		T326	3
valid_sources[0x66]	717	1			T14	1		T2	1		T20	1
valid_sources[0x67]	723	1			T1	4		T20	1		T85	1
valid_sources[0x68]	730	1			T10	1		T277	1		T35	2
valid_sources[0x69]	1037	1			T14	2		T20	2		T71	2
valid_sources[0x6a]	1080	1			T20	2		T71	1		T10	1
valid_sources[0x6b]	870	1			T24	17		T84	1		T10	3
valid_sources[0x6c]	1053	1			T84	2		T104	15		T71	1
valid_sources[0x6d]	816	1			T77	1		T88	11		T275	1
valid_sources[0x6e]	699	1			T1	4		T20	1		T84	1
valid_sources[0x6f]	824	1			T20	3		T84	1		T85	1
valid_sources[0x70]	1731	1			T20	1		T30	45		T10	1
valid_sources[0x71]	1140	1			T10	1		T12	1		T95	20
valid_sources[0x72]	734	1			T20	1		T71	1		T10	1
valid_sources[0x73]	716	1			T14	1		T20	2		T85	1
valid_sources[0x74]	1273	1			T20	1		T9	1		T10	2
valid_sources[0x75]	963	1			T20	1		T29	2		T104	1
valid_sources[0x76]	943	1			T20	1		T104	4		T71	1
valid_sources[0x77]	802	1			T22	1		T20	2		T84	1
valid_sources[0x78]	666	1			T20	1		T84	1		T71	1
valid_sources[0x79]	618	1			T20	1		T104	2		T70	2
valid_sources[0x7a]	817	1			T2	1		T29	1		T275	1
valid_sources[0x7b]	709	1			T10	1		T66	2		T94	2
valid_sources[0x7c]	799	1			T71	2		T85	6		T65	1
valid_sources[0x7d]	655	1			T20	1		T84	1		T29	2
valid_sources[0x7e]	802	1			T22	1		T14	1		T20	2
valid_sources[0x7f]	946	1			T14	1		T20	1		T66	3
valid_sources[0x80]	816	1			T16	1		T84	2		T85	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

58104

1

T4

1

T5

3

T6

15

values[0x0]

all_enables

biggest_size

28975

1

T5

3

T23

3

T24

5

values[0x1]

all_enables

biggest_size

20812

1

T5

1

T22

1

T23

1