Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78	95.65	90.91		83.33	95.24	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78	95.65	90.91		83.33	95.24	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T6 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T24 T31 T32 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T24 T31 T32 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T24 T31 T32 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T24 T31 T32 
149        1/1                    cnt_en = 1'b1;
           Tests:       T24 T31 T32 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T24 T31 T32 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T24 T31 T32 
163        1/1                    state_d = IdleSt;
           Tests:       T10 T90 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T90 
165        1/1                  end else if (cnt_done) begin
           Tests:       T24 T31 T32 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T31 T32 
167        1/1                    if (trigger_active) begin
           Tests:       T24 T31 T32 
168        1/1                      state_d = DetectSt;
           Tests:       T24 T31 T32 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T62 T63 T100 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T24 T31 T32 
182        1/1                  cnt_en = 1'b1;
           Tests:       T24 T31 T32 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T24 T31 T32 
186        1/1                    state_d = IdleSt;
           Tests:       T100 T117 T118 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T100 T117 T118 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T24 T31 T32 
191        1/1                      state_d = StableSt;
           Tests:       T24 T31 T32 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T24 T31 T32 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T24 T31 T32 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T24 T31 T32 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T24 T31 T32 
206        1/1                    state_d = IdleSt;
           Tests:       T24 T31 T32 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T24 T31 T32 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T31,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T31,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T31,T32
1	0	Covered	T4,T6,T23
1	1	Covered	T24,T31,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T31,T32
0	1	Covered	T100,T117,T118
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T31,T32
0	1	Covered	T24,T31,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T31,T32
1	-	Covered	T24,T31,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T31,T32
DetectSt	168	Covered	T24,T31,T32
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T24,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T31,T32
DebounceSt->IdleSt	163	Covered	T10,T62,T63
DetectSt->IdleSt	186	Covered	T100,T117,T118
DetectSt->StableSt	191	Covered	T24,T31,T32
IdleSt->DebounceSt	148	Covered	T24,T31,T32
StableSt->IdleSt	206	Covered	T24,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T31,T32
0	1	Covered	T24,T31,T32
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T31,T32
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T31,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T10,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T62,T63,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T31,T32
DetectSt	-	-	-	-	1	-	-	Covered	T100,T117,T118
DetectSt	-	-	-	-	0	1	-	Covered	T24,T31,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T24,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9770838	195	0	0
CntIncr_A	9770838	259003	0	0
CntNoWrap_A	9770838	9328950	0	0
DetectStDropOut_A	9770838	5	0	0
DetectedOut_A	9770838	512	0	0
DetectedPulseOut_A	9770838	84	0	0
DisabledIdleSt_A	9770838	9065698	0	0
DisabledNoDetection_A	9770838	9067515	0	0
EnterDebounceSt_A	9770838	108	0	0
EnterDetectSt_A	9770838	89	0	0
EnterStableSt_A	9770838	84	0	0
PulseIsPulse_A	9770838	84	0	0
StayInStableSt	9770838	428	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9770838	5354	0	0
gen_low_level_sva.LowLevelEvent_A	9770838	9330998	0	0
gen_not_sticky_sva.StableStDropOut_A	9770838	84	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	195	0	0
T1	1054	0	0	0
T2	644	0	0	0
T10	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	2	0	0
T31	0	4	0	0
T32	0	2	0	0
T59	0	4	0	0
T61	0	4	0	0
T62	0	5	0	0
T63	0	3	0	0
T64	0	2	0	0
T112	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	259003	0	0
T1	1054	0	0	0
T2	644	0	0	0
T10	0	37	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	77	0	0
T31	0	111	0	0
T32	0	26	0	0
T59	0	176	0	0
T61	0	188	0	0
T62	0	230	0	0
T63	0	31584	0	0
T64	0	96	0	0
T112	0	109	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9328950	0	0
T1	1054	653	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	254	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5	0	0
T100	3560	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T120	0	1	0	0
T123	0	1	0	0
T131	647	0	0	0
T132	417	0	0	0
T133	617	0	0	0
T134	421	0	0	0
T135	506	0	0	0
T136	495	0	0	0
T137	1267	0	0	0
T138	666	0	0	0
T139	400975	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	512	0	0
T1	1054	0	0	0
T2	644	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	6	0	0
T31	0	20	0	0
T32	0	6	0	0
T59	0	12	0	0
T61	0	19	0	0
T62	0	3	0	0
T63	0	5	0	0
T64	0	3	0	0
T112	0	16	0	0
T142	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	84	0	0
T1	1054	0	0	0
T2	644	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T112	0	2	0	0
T142	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9065698	0	0
T1	1054	653	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	129	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9067515	0	0
T1	1054	654	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	130	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	108	0	0
T1	1054	0	0	0
T2	644	0	0	0
T10	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	0	3	0	0
T63	0	2	0	0
T64	0	1	0	0
T112	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	89	0	0
T1	1054	0	0	0
T2	644	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T112	0	2	0	0
T142	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	84	0	0
T1	1054	0	0	0
T2	644	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T112	0	2	0	0
T142	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	84	0	0
T1	1054	0	0	0
T2	644	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T112	0	2	0	0
T142	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	428	0	0
T1	1054	0	0	0
T2	644	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	5	0	0
T31	0	18	0	0
T32	0	5	0	0
T59	0	10	0	0
T61	0	17	0	0
T62	0	1	0	0
T63	0	4	0	0
T64	0	2	0	0
T112	0	14	0	0
T142	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5354	0	0
T1	1054	4	0	0
T2	644	1	0	0
T4	428	1	0	0
T5	469	0	0	0
T6	427	2	0	0
T14	522	5	0	0
T15	502	6	0	0
T16	0	4	0	0
T18	0	6	0	0
T22	444	0	0	0
T23	491	7	0	0
T24	657	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9330998	0	0
T1	1054	654	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	84	0	0
T1	1054	0	0	0
T2	644	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T24	657	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T112	0	2	0	0
T142	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T6 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T10 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T10 T11 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T10 T11 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T10 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T10 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T10 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T10 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T10 T90 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T90 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T10 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T11 T39 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T11 T39 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T11 T39 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T50 T75 T147 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T11 T39 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T11 T39 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T11 T39 
186        1/1                    state_d = IdleSt;
           Tests:       T99 T110 T111 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T99 T110 T111 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T11 T39 
191        1/1                      state_d = StableSt;
           Tests:       T1 T11 T39 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T11 T39 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T11 T39 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T11 T39 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T11 T39 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T11 T39 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T11 T39 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T11,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T4,T6,T23
1	1	Covered	T1,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T39
0	1	Covered	T99,T110,T111
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T39
0	1	Unreachable
1	0	Covered	T1,T11,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T11
DetectSt	168	Covered	T1,T11,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T11,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T39
DebounceSt->IdleSt	163	Covered	T10,T50,T75
DetectSt->IdleSt	186	Covered	T99,T110,T111
DetectSt->StableSt	191	Covered	T1,T11,T39
IdleSt->DebounceSt	148	Covered	T1,T10,T11
StableSt->IdleSt	206	Covered	T1,T11,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T10,T11
0	1	Covered	T1,T10,T11
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T39
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T10,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T75,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T99,T110,T111
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9770838	135	0	0
CntIncr_A	9770838	602839	0	0
CntNoWrap_A	9770838	9329010	0	0
DetectStDropOut_A	9770838	5	0	0
DetectedOut_A	9770838	996844	0	0
DetectedPulseOut_A	9770838	41	0	0
DisabledIdleSt_A	9770838	5765111	0	0
DisabledNoDetection_A	9770838	5766964	0	0
EnterDebounceSt_A	9770838	90	0	0
EnterDetectSt_A	9770838	46	0	0
EnterStableSt_A	9770838	41	0	0
PulseIsPulse_A	9770838	41	0	0
StayInStableSt	9770838	996803	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9770838	5354	0	0
gen_low_level_sva.LowLevelEvent_A	9770838	9330998	0	0
gen_sticky_sva.StableStDropOut_A	9770838	930380	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	135	0	0
T1	1054	2	0	0
T2	644	0	0	0
T3	847	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	2	0	0
T50	0	2	0	0
T68	0	4	0	0
T75	0	1	0	0
T76	0	2	0	0
T90	0	1	0	0
T98	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	602839	0	0
T1	1054	61	0	0
T2	644	0	0	0
T3	847	0	0	0
T10	0	42	0	0
T11	0	12	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	12	0	0
T50	0	172	0	0
T68	0	82488	0	0
T75	0	21	0	0
T76	0	63	0	0
T90	0	60	0	0
T98	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9329010	0	0
T1	1054	651	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5	0	0
T99	64016	1	0	0
T100	3560	0	0	0
T110	0	3	0	0
T111	0	1	0	0
T131	647	0	0	0
T132	417	0	0	0
T133	617	0	0	0
T134	421	0	0	0
T135	506	0	0	0
T152	610	0	0	0
T153	1284	0	0	0
T154	435	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	996844	0	0
T1	1054	56	0	0
T2	644	0	0	0
T3	847	0	0	0
T11	0	47	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	18	0	0
T68	0	365384	0	0
T76	0	478	0	0
T98	0	65	0	0
T137	0	149	0	0
T139	0	54959	0	0
T146	0	70	0	0
T148	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	41	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T11	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0
T98	0	1	0	0
T137	0	3	0	0
T139	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5765111	0	0
T1	1054	480	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5766964	0	0
T1	1054	481	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	90	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T50	0	2	0	0
T68	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T90	0	2	0	0
T98	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	46	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T11	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T137	0	3	0	0
T139	0	2	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	41	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T11	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0
T98	0	1	0	0
T137	0	3	0	0
T139	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	41	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T11	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0
T98	0	1	0	0
T137	0	3	0	0
T139	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	996803	0	0
T1	1054	55	0	0
T2	644	0	0	0
T3	847	0	0	0
T11	0	46	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	17	0	0
T68	0	365382	0	0
T76	0	477	0	0
T98	0	64	0	0
T137	0	146	0	0
T139	0	54957	0	0
T146	0	69	0	0
T149	0	27	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5354	0	0
T1	1054	4	0	0
T2	644	1	0	0
T4	428	1	0	0
T5	469	0	0	0
T6	427	2	0	0
T14	522	5	0	0
T15	502	6	0	0
T16	0	4	0	0
T18	0	6	0	0
T22	444	0	0	0
T23	491	7	0	0
T24	657	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9330998	0	0
T1	1054	654	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	930380	0	0
T1	1054	35	0	0
T2	644	0	0	0
T3	847	0	0	0
T11	0	262	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	186	0	0
T68	0	142	0	0
T76	0	142	0	0
T98	0	264	0	0
T137	0	492	0	0
T139	0	83	0	0
T146	0	622	0	0
T148	0	49	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T6 T23 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T6 T23 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T10 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T10 T11 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T10 T11 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T6 T23 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T6 T23 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T6 T23 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T6 T23 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T6 T23 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T6 T23 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T6 T23 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T6 T23 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T10 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T10 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T10 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T10 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T10 T90 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T90 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T10 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T11 T39 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T11 T39 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T39 T68 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T1 T139 T109 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T39 T68 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T39 T68 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T39 T68 
186        1/1                    state_d = IdleSt;
           Tests:       T75 T102 T109 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T75 T102 T109 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T39 T68 
191        1/1                      state_d = StableSt;
           Tests:       T11 T39 T68 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T39 T68 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T39 T68 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T39 T68 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T39 T68 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T39 T68 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T39 T68 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T23
1	1	Covered	T4,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T39,T68

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T4,T6,T23
1	1	Covered	T1,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T39,T68
0	1	Covered	T75,T102,T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T39,T68
0	1	Unreachable
1	0	Covered	T11,T39,T68

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T11
DetectSt	168	Covered	T11,T39,T68
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T39,T68

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T39,T68
DebounceSt->IdleSt	163	Covered	T1,T10,T90
DetectSt->IdleSt	186	Covered	T75,T102,T109
DetectSt->StableSt	191	Covered	T11,T39,T68
IdleSt->DebounceSt	148	Covered	T1,T10,T11
StableSt->IdleSt	206	Covered	T11,T39,T68

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T10,T11
0	1	Covered	T1,T10,T11
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T39,T68
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T10,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T39,T68
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T139,T109
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T75,T102,T109
DetectSt	-	-	-	-	0	1	-	Covered	T11,T39,T68
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T39,T68
StableSt	-	-	-	-	-	-	0	Covered	T11,T39,T68
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9770838	130	0	0
CntIncr_A	9770838	302540	0	0
CntNoWrap_A	9770838	9329015	0	0
DetectStDropOut_A	9770838	9	0	0
DetectedOut_A	9770838	311906	0	0
DetectedPulseOut_A	9770838	46	0	0
DisabledIdleSt_A	9770838	5765111	0	0
DisabledNoDetection_A	9770838	5766964	0	0
EnterDebounceSt_A	9770838	76	0	0
EnterDetectSt_A	9770838	55	0	0
EnterStableSt_A	9770838	46	0	0
PulseIsPulse_A	9770838	46	0	0
StayInStableSt	9770838	311860	0	0
gen_high_level_sva.HighLevelEvent_A	9770838	9330998	0	0
gen_sticky_sva.StableStDropOut_A	9770838	1879857	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	130	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	2	0	0
T50	0	2	0	0
T68	0	4	0	0
T75	0	2	0	0
T76	0	2	0	0
T90	0	1	0	0
T98	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	302540	0	0
T1	1054	65	0	0
T2	644	0	0	0
T3	847	0	0	0
T10	0	42	0	0
T11	0	11	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	21	0	0
T50	0	38	0	0
T68	0	122	0	0
T75	0	55	0	0
T76	0	75	0	0
T90	0	61	0	0
T98	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9329015	0	0
T1	1054	652	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9	0	0
T75	686	1	0	0
T76	1563	0	0	0
T96	31435	0	0	0
T102	0	2	0	0
T109	0	1	0	0
T112	682	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	2	0	0
T158	528	0	0	0
T159	506	0	0	0
T160	404	0	0	0
T161	498	0	0	0
T162	422	0	0	0
T163	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	311906	0	0
T11	783	46	0	0
T12	632	0	0	0
T13	10538	0	0	0
T39	0	51	0	0
T50	0	40	0	0
T66	503	0	0	0
T67	677	0	0	0
T68	0	512	0	0
T76	0	509	0	0
T88	466	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T98	0	104	0	0
T99	0	28	0	0
T137	0	364	0	0
T146	0	272	0	0
T147	0	824	0	0
T150	420	0	0	0
T151	404	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	46	0	0
T11	783	1	0	0
T12	632	0	0	0
T13	10538	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T66	503	0	0	0
T67	677	0	0	0
T68	0	2	0	0
T76	0	1	0	0
T88	466	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T98	0	1	0	0
T99	0	1	0	0
T137	0	3	0	0
T146	0	1	0	0
T147	0	1	0	0
T150	420	0	0	0
T151	404	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5765111	0	0
T1	1054	480	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5766964	0	0
T1	1054	481	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	76	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T68	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T90	0	2	0	0
T98	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	55	0	0
T11	783	1	0	0
T12	632	0	0	0
T13	10538	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T66	503	0	0	0
T67	677	0	0	0
T68	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T88	466	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T98	0	1	0	0
T99	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T150	420	0	0	0
T151	404	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	46	0	0
T11	783	1	0	0
T12	632	0	0	0
T13	10538	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T66	503	0	0	0
T67	677	0	0	0
T68	0	2	0	0
T76	0	1	0	0
T88	466	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T98	0	1	0	0
T99	0	1	0	0
T137	0	3	0	0
T146	0	1	0	0
T147	0	1	0	0
T150	420	0	0	0
T151	404	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	46	0	0
T11	783	1	0	0
T12	632	0	0	0
T13	10538	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T66	503	0	0	0
T67	677	0	0	0
T68	0	2	0	0
T76	0	1	0	0
T88	466	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T98	0	1	0	0
T99	0	1	0	0
T137	0	3	0	0
T146	0	1	0	0
T147	0	1	0	0
T150	420	0	0	0
T151	404	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	311860	0	0
T11	783	45	0	0
T12	632	0	0	0
T13	10538	0	0	0
T39	0	50	0	0
T50	0	39	0	0
T66	503	0	0	0
T67	677	0	0	0
T68	0	510	0	0
T76	0	508	0	0
T88	466	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T98	0	103	0	0
T99	0	27	0	0
T137	0	361	0	0
T146	0	271	0	0
T147	0	823	0	0
T150	420	0	0	0
T151	404	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9330998	0	0
T1	1054	654	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	1879857	0	0
T11	783	267	0	0
T12	632	0	0	0
T13	10538	0	0	0
T39	0	160	0	0
T50	0	170	0	0
T66	503	0	0	0
T67	677	0	0	0
T68	0	447371	0	0
T76	0	85	0	0
T88	466	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T98	0	192	0	0
T99	0	62369	0	0
T137	0	159	0	0
T146	0	390	0	0
T147	0	82	0	0
T150	420	0	0	0
T151	404	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T6 T23 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T6 T23 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T10 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T10 T11 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T10 T11 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T6 T23 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T6 T23 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T6 T23 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T6 T23 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T6 T23 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T6 T23 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T6 T23 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T6 T23 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T10 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T10 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T10 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T10 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T10 T90 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T90 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T10 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T11 T39 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T11 T39 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T39 T68 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T11 T75 T98 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T39 T68 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T39 T68 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T39 T68 
186        1/1                    state_d = IdleSt;
           Tests:       T101 T102 T103 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T101 T102 T103 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T39 T68 
191        1/1                      state_d = StableSt;
           Tests:       T1 T39 T68 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T39 T68 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T39 T68 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T39 T68 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T39 T68 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T39 T68 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T39 T68 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T39,T68

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T4,T6,T23
1	1	Covered	T1,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T39,T68
0	1	Covered	T101,T102,T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T39,T68
0	1	Unreachable
1	0	Covered	T1,T39,T68

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T11
DetectSt	168	Covered	T1,T39,T68
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T39,T68

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T39,T68
DebounceSt->IdleSt	163	Covered	T10,T11,T75
DetectSt->IdleSt	186	Covered	T101,T102,T103
DetectSt->StableSt	191	Covered	T1,T39,T68
IdleSt->DebounceSt	148	Covered	T1,T10,T11
StableSt->IdleSt	206	Covered	T1,T39,T68

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T10,T11
0	1	Covered	T1,T10,T11
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T39,T68
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T10,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T39,T68
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T75,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T101,T102,T103
DetectSt	-	-	-	-	0	1	-	Covered	T1,T39,T68
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T39,T68
StableSt	-	-	-	-	-	-	0	Covered	T1,T39,T68
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9770838	132	0	0
CntIncr_A	9770838	292979	0	0
CntNoWrap_A	9770838	9329013	0	0
DetectStDropOut_A	9770838	5	0	0
DetectedOut_A	9770838	1071267	0	0
DetectedPulseOut_A	9770838	41	0	0
DisabledIdleSt_A	9770838	5765111	0	0
DisabledNoDetection_A	9770838	5766964	0	0
EnterDebounceSt_A	9770838	87	0	0
EnterDetectSt_A	9770838	46	0	0
EnterStableSt_A	9770838	41	0	0
PulseIsPulse_A	9770838	41	0	0
StayInStableSt	9770838	1071226	0	0
gen_high_event_sva.HighLevelEvent_A	9770838	9330998	0	0
gen_high_level_sva.HighLevelEvent_A	9770838	9330998	0	0
gen_sticky_sva.StableStDropOut_A	9770838	1977620	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	132	0	0
T1	1054	2	0	0
T2	644	0	0	0
T3	847	0	0	0
T10	0	2	0	0
T11	0	3	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	2	0	0
T50	0	2	0	0
T68	0	4	0	0
T75	0	1	0	0
T76	0	2	0	0
T90	0	1	0	0
T98	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	292979	0	0
T1	1054	95	0	0
T2	644	0	0	0
T3	847	0	0	0
T10	0	42	0	0
T11	0	300	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	82	0	0
T50	0	15	0	0
T68	0	180	0	0
T75	0	27	0	0
T76	0	31	0	0
T90	0	62	0	0
T98	0	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9329013	0	0
T1	1054	651	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5	0	0
T101	2586	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T164	3081	0	0	0
T165	523	0	0	0
T166	415	0	0	0
T167	704	0	0	0
T168	35514	0	0	0
T169	502	0	0	0
T170	524	0	0	0
T171	437	0	0	0
T172	19015	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	1071267	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	120	0	0
T50	0	39	0	0
T68	0	519	0	0
T76	0	197	0	0
T99	0	7458	0	0
T139	0	70	0	0
T147	0	538	0	0
T148	0	20	0	0
T149	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	41	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0
T99	0	1	0	0
T139	0	2	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5765111	0	0
T1	1054	480	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	5766964	0	0
T1	1054	481	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	87	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T10	0	2	0	0
T11	0	3	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T68	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T90	0	2	0	0
T98	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	46	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0
T99	0	1	0	0
T139	0	2	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	41	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0
T99	0	1	0	0
T139	0	2	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	41	0	0
T1	1054	1	0	0
T2	644	0	0	0
T3	847	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	1	0	0
T50	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0
T99	0	1	0	0
T139	0	2	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	1071226	0	0
T39	1110	119	0	0
T50	0	38	0	0
T52	2144	0	0	0
T68	448508	517	0	0
T76	0	196	0	0
T82	493	0	0	0
T99	0	7457	0	0
T139	0	68	0	0
T147	0	537	0	0
T148	0	19	0	0
T149	0	105	0	0
T173	0	111	0	0
T174	423	0	0	0
T175	525	0	0	0
T176	4402	0	0	0
T177	411	0	0	0
T178	423	0	0	0
T179	1814	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9330998	0	0
T1	1054	654	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9330998	0	0
T1	1054	654	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	1977620	0	0
T1	1054	71	0	0
T2	644	0	0	0
T3	847	0	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T39	0	32	0	0
T50	0	203	0	0
T68	0	447341	0	0
T76	0	457	0	0
T99	0	27	0	0
T139	0	114198	0	0
T147	0	368	0	0
T148	0	44	0	0
T149	0	124	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T3 T10 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T22 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T22 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T3 T10 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T3 T10 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T3 T10 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T3 T10 
163        1/1                    state_d = IdleSt;
           Tests:       T90 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T90 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T3 T10 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T10 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T3 T10 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T3 T10 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T3 T10 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T3 T10 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T3 T10 
186        1/1                    state_d = IdleSt;
           Tests:       T3 T180 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T180 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T3 T10 
191        1/1                      state_d = StableSt;
           Tests:       T2 T3 T10 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T3 T10 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T3 T10 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T3 T10 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T3 T10 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T10 T46 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T3 T10 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T10
0	1	Covered	T3,T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T10
0	1	Covered	T3,T46,T52
1	0	Covered	T10

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T10
1	-	Covered	T3,T46,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T10
DetectSt	168	Covered	T2,T3,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T10
DebounceSt->IdleSt	163	Covered	T90
DetectSt->IdleSt	186	Covered	T3,T180
DetectSt->StableSt	191	Covered	T2,T3,T10
IdleSt->DebounceSt	148	Covered	T2,T3,T10
StableSt->IdleSt	206	Covered	T3,T10,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T10
0	1	Covered	T2,T3,T10
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T10
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T10
DetectSt	-	-	-	-	1	-	-	Covered	T3,T180
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T46
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9770838	47	0	0
CntIncr_A	9770838	1039	0	0
CntNoWrap_A	9770838	9329098	0	0
DetectStDropOut_A	9770838	2	0	0
DetectedOut_A	9770838	1930	0	0
DetectedPulseOut_A	9770838	21	0	0
DisabledIdleSt_A	9770838	9320049	0	0
DisabledNoDetection_A	9770838	9321869	0	0
EnterDebounceSt_A	9770838	24	0	0
EnterDetectSt_A	9770838	23	0	0
EnterStableSt_A	9770838	21	0	0
PulseIsPulse_A	9770838	21	0	0
StayInStableSt	9770838	1896	0	0
gen_high_level_sva.HighLevelEvent_A	9770838	9330998	0	0
gen_not_sticky_sva.StableStDropOut_A	9770838	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	47	0	0
T2	644	2	0	0
T3	847	4	0	0
T10	0	2	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T43	0	2	0	0
T46	0	2	0	0
T49	0	2	0	0
T52	0	2	0	0
T56	451	0	0	0
T84	502	0	0	0
T90	0	1	0	0
T138	0	2	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	1039	0	0
T2	644	28	0	0
T3	847	88	0	0
T10	0	37	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T43	0	10	0	0
T46	0	21	0	0
T49	0	49	0	0
T52	0	10	0	0
T56	451	0	0	0
T84	502	0	0	0
T90	0	26	0	0
T138	0	35	0	0
T181	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9329098	0	0
T1	1054	653	0	0
T2	644	241	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	2	0	0
T3	847	1	0	0
T29	492	0	0	0
T30	497	0	0	0
T31	689	0	0	0
T56	451	0	0	0
T69	556	0	0	0
T84	502	0	0	0
T104	1093	0	0	0
T180	0	1	0	0
T182	428	0	0	0
T183	441	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	1930	0	0
T2	644	171	0	0
T3	847	123	0	0
T10	0	6	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T43	0	47	0	0
T46	0	5	0	0
T49	0	240	0	0
T52	0	74	0	0
T56	451	0	0	0
T84	502	0	0	0
T138	0	41	0	0
T181	0	42	0	0
T184	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	21	0	0
T2	644	1	0	0
T3	847	1	0	0
T10	0	1	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T56	451	0	0	0
T84	502	0	0	0
T138	0	1	0	0
T181	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9320049	0	0
T1	1054	653	0	0
T2	644	3	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9321869	0	0
T1	1054	654	0	0
T2	644	3	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	24	0	0
T2	644	1	0	0
T3	847	2	0	0
T10	0	1	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T56	451	0	0	0
T84	502	0	0	0
T90	0	1	0	0
T138	0	1	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	23	0	0
T2	644	1	0	0
T3	847	2	0	0
T10	0	1	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T56	451	0	0	0
T84	502	0	0	0
T138	0	1	0	0
T181	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	21	0	0
T2	644	1	0	0
T3	847	1	0	0
T10	0	1	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T56	451	0	0	0
T84	502	0	0	0
T138	0	1	0	0
T181	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	21	0	0
T2	644	1	0	0
T3	847	1	0	0
T10	0	1	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T56	451	0	0	0
T84	502	0	0	0
T138	0	1	0	0
T181	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	1896	0	0
T2	644	169	0	0
T3	847	122	0	0
T10	0	5	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	463	0	0	0
T18	526	0	0	0
T19	402	0	0	0
T20	1181	0	0	0
T43	0	45	0	0
T46	0	4	0	0
T49	0	238	0	0
T52	0	73	0	0
T56	451	0	0	0
T84	502	0	0	0
T138	0	39	0	0
T181	0	40	0	0
T184	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9330998	0	0
T1	1054	654	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	7	0	0
T3	847	1	0	0
T29	492	0	0	0
T30	497	0	0	0
T31	689	0	0	0
T46	0	1	0	0
T52	0	1	0	0
T56	451	0	0	0
T69	556	0	0	0
T84	502	0	0	0
T104	1093	0	0	0
T182	428	0	0	0
T183	441	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T10 T51 T46 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T22 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T22 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T10 T51 T46 
149        1/1                    cnt_en = 1'b1;
           Tests:       T10 T51 T46 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T10 T51 T46 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T10 T51 T46 
163        1/1                    state_d = IdleSt;
           Tests:       T90 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T90 
165        1/1                  end else if (cnt_done) begin
           Tests:       T10 T51 T46 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T51 T46 
167        1/1                    if (trigger_active) begin
           Tests:       T10 T51 T46 
168        1/1                      state_d = DetectSt;
           Tests:       T10 T51 T46 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T189 T184 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T10 T51 T46 
182        1/1                  cnt_en = 1'b1;
           Tests:       T10 T51 T46 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T10 T51 T46 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T10 T51 T46 
191        1/1                      state_d = StableSt;
           Tests:       T10 T51 T46 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T10 T51 T46 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T10 T51 T46 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T10 T51 T46 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T10 T51 T46 
206        1/1                    state_d = IdleSt;
           Tests:       T10 T46 T52 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T10 T51 T46 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T51,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T51,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T51,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T51
1	0	Covered	T4,T6,T23
1	1	Covered	T10,T51,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T51,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T51,T46
0	1	Covered	T46,T52,T55
1	0	Covered	T10

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T51,T46
1	-	Covered	T46,T52,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T51,T46
DetectSt	168	Covered	T10,T51,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T51,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T51,T46
DebounceSt->IdleSt	163	Covered	T90,T189,T184
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T51,T46
IdleSt->DebounceSt	148	Covered	T10,T51,T46
StableSt->IdleSt	206	Covered	T10,T46,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T10,T51,T46
0	1	Covered	T10,T51,T46
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T51,T46
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T51,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T51,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T189,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T51,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T51,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T46,T52
StableSt	-	-	-	-	-	-	0	Covered	T10,T51,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9770838	83	0	0
CntIncr_A	9770838	32669	0	0
CntNoWrap_A	9770838	9329062	0	0
DetectStDropOut_A	9770838	0	0	0
DetectedOut_A	9770838	2741	0	0
DetectedPulseOut_A	9770838	40	0	0
DisabledIdleSt_A	9770838	9088859	0	0
DisabledNoDetection_A	9770838	9090679	0	0
EnterDebounceSt_A	9770838	43	0	0
EnterDetectSt_A	9770838	40	0	0
EnterStableSt_A	9770838	40	0	0
PulseIsPulse_A	9770838	40	0	0
StayInStableSt	9770838	2685	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9770838	1489	0	0
gen_low_level_sva.LowLevelEvent_A	9770838	9330998	0	0
gen_not_sticky_sva.StableStDropOut_A	9770838	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	83	0	0
T10	8125	2	0	0
T11	783	0	0	0
T12	632	0	0	0
T13	10538	0	0	0
T46	0	4	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	4	0	0
T55	0	2	0	0
T58	470	0	0	0
T65	522	0	0	0
T66	503	0	0	0
T67	677	0	0	0
T90	0	1	0	0
T94	427	0	0	0
T95	1341	0	0	0
T100	0	2	0	0
T131	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	32669	0	0
T10	8125	37	0	0
T11	783	0	0	0
T12	632	0	0	0
T13	10538	0	0	0
T46	0	42	0	0
T48	0	60	0	0
T50	0	14	0	0
T51	0	44	0	0
T52	0	20	0	0
T55	0	32	0	0
T58	470	0	0	0
T65	522	0	0	0
T66	503	0	0	0
T67	677	0	0	0
T90	0	27	0	0
T94	427	0	0	0
T95	1341	0	0	0
T100	0	98	0	0
T131	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9329062	0	0
T1	1054	653	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	2741	0	0
T10	8125	6	0	0
T11	783	0	0	0
T12	632	0	0	0
T13	10538	0	0	0
T46	0	112	0	0
T48	0	246	0	0
T50	0	40	0	0
T51	0	84	0	0
T52	0	75	0	0
T55	0	12	0	0
T58	470	0	0	0
T65	522	0	0	0
T66	503	0	0	0
T67	677	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T100	0	46	0	0
T131	0	10	0	0
T133	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	40	0	0
T10	8125	1	0	0
T11	783	0	0	0
T12	632	0	0	0
T13	10538	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0
T58	470	0	0	0
T65	522	0	0	0
T66	503	0	0	0
T67	677	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T100	0	1	0	0
T131	0	1	0	0
T133	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9088859	0	0
T1	1054	653	0	0
T2	644	243	0	0
T4	428	27	0	0
T5	469	68	0	0
T6	427	26	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	444	43	0	0
T23	491	90	0	0
T24	657	256	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9090679	0	0
T1	1054	654	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	43	0	0
T10	8125	1	0	0
T11	783	0	0	0
T12	632	0	0	0
T13	10538	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0
T58	470	0	0	0
T65	522	0	0	0
T66	503	0	0	0
T67	677	0	0	0
T90	0	1	0	0
T94	427	0	0	0
T95	1341	0	0	0
T100	0	1	0	0
T131	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	40	0	0
T10	8125	1	0	0
T11	783	0	0	0
T12	632	0	0	0
T13	10538	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0
T58	470	0	0	0
T65	522	0	0	0
T66	503	0	0	0
T67	677	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T100	0	1	0	0
T131	0	1	0	0
T133	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	40	0	0
T10	8125	1	0	0
T11	783	0	0	0
T12	632	0	0	0
T13	10538	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0
T58	470	0	0	0
T65	522	0	0	0
T66	503	0	0	0
T67	677	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T100	0	1	0	0
T131	0	1	0	0
T133	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	40	0	0
T10	8125	1	0	0
T11	783	0	0	0
T12	632	0	0	0
T13	10538	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0
T58	470	0	0	0
T65	522	0	0	0
T66	503	0	0	0
T67	677	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T100	0	1	0	0
T131	0	1	0	0
T133	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	2685	0	0
T10	8125	5	0	0
T11	783	0	0	0
T12	632	0	0	0
T13	10538	0	0	0
T46	0	109	0	0
T48	0	244	0	0
T50	0	38	0	0
T51	0	82	0	0
T52	0	72	0	0
T55	0	11	0	0
T58	470	0	0	0
T65	522	0	0	0
T66	503	0	0	0
T67	677	0	0	0
T94	427	0	0	0
T95	1341	0	0	0
T100	0	45	0	0
T131	0	9	0	0
T133	0	76	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	1489	0	0
T1	1054	0	0	0
T2	644	1	0	0
T3	0	3	0	0
T4	428	4	0	0
T5	469	0	0	0
T6	427	2	0	0
T14	522	5	0	0
T15	502	6	0	0
T16	0	1	0	0
T18	0	6	0	0
T22	444	0	0	0
T23	491	4	0	0
T24	657	0	0	0
T84	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	9330998	0	0
T1	1054	654	0	0
T2	644	244	0	0
T4	428	28	0	0
T5	469	69	0	0
T6	427	27	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	444	44	0	0
T23	491	91	0	0
T24	657	257	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9770838	23	0	0
T39	1110	0	0	0
T46	592	1	0	0
T48	937	0	0	0
T52	2144	1	0	0
T55	0	1	0	0
T68	448508	0	0	0
T82	493	0	0	0
T100	0	1	0	0
T131	0	1	0	0
T133	0	1	0	0
T138	0	1	0	0
T174	423	0	0	0
T175	525	0	0	0
T176	4402	0	0	0
T177	411	0	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	2	0	0