Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1401201797 10250 0 0
auto_block_debounce_ctl_rd_A 1401201797 1442 0 0
auto_block_out_ctl_rd_A 1401201797 1797 0 0
com_det_ctl_0_rd_A 1401201797 3447 0 0
com_det_ctl_1_rd_A 1401201797 3482 0 0
com_det_ctl_2_rd_A 1401201797 3345 0 0
com_det_ctl_3_rd_A 1401201797 3260 0 0
com_out_ctl_0_rd_A 1401201797 3811 0 0
com_out_ctl_1_rd_A 1401201797 3712 0 0
com_out_ctl_2_rd_A 1401201797 3870 0 0
com_out_ctl_3_rd_A 1401201797 3692 0 0
com_pre_det_ctl_0_rd_A 1401201797 1237 0 0
com_pre_det_ctl_1_rd_A 1401201797 1075 0 0
com_pre_det_ctl_2_rd_A 1401201797 1182 0 0
com_pre_det_ctl_3_rd_A 1401201797 1159 0 0
com_pre_sel_ctl_0_rd_A 1401201797 3908 0 0
com_pre_sel_ctl_1_rd_A 1401201797 4125 0 0
com_pre_sel_ctl_2_rd_A 1401201797 3891 0 0
com_pre_sel_ctl_3_rd_A 1401201797 3864 0 0
com_sel_ctl_0_rd_A 1401201797 3833 0 0
com_sel_ctl_1_rd_A 1401201797 4055 0 0
com_sel_ctl_2_rd_A 1401201797 4173 0 0
com_sel_ctl_3_rd_A 1401201797 3798 0 0
ec_rst_ctl_rd_A 1401201797 1948 0 0
intr_enable_rd_A 1401201797 1706 0 0
key_intr_ctl_rd_A 1401201797 3012 0 0
key_intr_debounce_ctl_rd_A 1401201797 1156 0 0
key_invert_ctl_rd_A 1401201797 3634 0 0
pin_allowed_ctl_rd_A 1401201797 4405 0 0
pin_out_ctl_rd_A 1401201797 2829 0 0
pin_out_value_rd_A 1401201797 3120 0 0
regwen_rd_A 1401201797 1506 0 0
ulp_ac_debounce_ctl_rd_A 1401201797 1150 0 0
ulp_ctl_rd_A 1401201797 1472 0 0
ulp_lid_debounce_ctl_rd_A 1401201797 1322 0 0
ulp_pwrb_debounce_ctl_rd_A 1401201797 1300 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 10250 0 0
T3 41173 0 0 0
T20 230394 5 0 0
T29 236324 0 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T35 0 19 0 0
T52 0 19 0 0
T56 225530 0 0 0
T61 0 7 0 0
T69 277840 0 0 0
T84 241028 0 0 0
T95 0 5 0 0
T104 120289 8 0 0
T179 0 3 0 0
T182 210206 0 0 0
T236 0 4 0 0
T320 0 12 0 0
T321 0 4 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1442 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T32 0 15 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 20 0 0
T167 0 16 0 0
T179 0 13 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 33 0 0
T297 201043 0 0 0
T321 0 13 0 0
T322 0 15 0 0
T323 0 33 0 0
T324 0 4 0 0
T325 0 1 0 0
T326 211122 0 0 0
T327 48759 0 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1797 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T32 0 14 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 6 0 0
T167 0 10 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 10 0 0
T297 201043 0 0 0
T321 0 15 0 0
T322 0 11 0 0
T323 0 38 0 0
T324 0 6 0 0
T325 0 18 0 0
T326 211122 0 0 0
T327 48759 0 0 0
T328 0 34 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3447 0 0
T21 0 50 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 30 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 15 0 0
T179 0 10 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 24 0 0
T244 0 80 0 0
T254 0 13 0 0
T266 0 43 0 0
T297 201043 0 0 0
T321 0 17 0 0
T323 0 45 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3482 0 0
T21 0 34 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 29 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 17 0 0
T179 0 16 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 13 0 0
T244 0 87 0 0
T254 0 17 0 0
T266 0 50 0 0
T297 201043 0 0 0
T321 0 22 0 0
T323 0 33 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3345 0 0
T21 0 43 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 27 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 10 0 0
T179 0 20 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 26 0 0
T244 0 78 0 0
T254 0 19 0 0
T266 0 56 0 0
T297 201043 0 0 0
T321 0 17 0 0
T323 0 29 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3260 0 0
T21 0 26 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 22 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 15 0 0
T179 0 10 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 30 0 0
T244 0 70 0 0
T254 0 18 0 0
T266 0 36 0 0
T297 201043 0 0 0
T321 0 39 0 0
T323 0 13 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3811 0 0
T21 0 49 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 42 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 12 0 0
T179 0 12 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 33 0 0
T244 0 71 0 0
T254 0 25 0 0
T266 0 54 0 0
T297 201043 0 0 0
T321 0 22 0 0
T323 0 50 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3712 0 0
T21 0 47 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 33 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 14 0 0
T179 0 14 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 22 0 0
T244 0 78 0 0
T254 0 16 0 0
T266 0 47 0 0
T297 201043 0 0 0
T321 0 20 0 0
T323 0 42 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3870 0 0
T21 0 31 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 43 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 13 0 0
T179 0 11 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 34 0 0
T244 0 56 0 0
T254 0 20 0 0
T266 0 51 0 0
T297 201043 0 0 0
T321 0 25 0 0
T323 0 43 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3692 0 0
T21 0 30 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 45 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 7 0 0
T179 0 16 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 33 0 0
T244 0 62 0 0
T254 0 17 0 0
T266 0 42 0 0
T297 201043 0 0 0
T321 0 13 0 0
T323 0 29 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1237 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 19 0 0
T179 0 3 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 31 0 0
T297 201043 0 0 0
T321 0 16 0 0
T323 0 47 0 0
T326 211122 0 0 0
T327 48759 0 0 0
T328 0 55 0 0
T329 0 14 0 0
T330 0 30 0 0
T331 0 45 0 0
T332 0 49 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1075 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 10 0 0
T179 0 11 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 27 0 0
T297 201043 0 0 0
T321 0 17 0 0
T323 0 31 0 0
T326 211122 0 0 0
T327 48759 0 0 0
T328 0 36 0 0
T329 0 25 0 0
T330 0 29 0 0
T331 0 42 0 0
T332 0 36 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1182 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 18 0 0
T179 0 12 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 25 0 0
T297 201043 0 0 0
T321 0 24 0 0
T323 0 32 0 0
T326 211122 0 0 0
T327 48759 0 0 0
T328 0 23 0 0
T329 0 22 0 0
T330 0 22 0 0
T331 0 47 0 0
T332 0 21 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1159 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 13 0 0
T179 0 1 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 25 0 0
T297 201043 0 0 0
T321 0 26 0 0
T323 0 51 0 0
T326 211122 0 0 0
T327 48759 0 0 0
T328 0 26 0 0
T329 0 18 0 0
T330 0 14 0 0
T331 0 29 0 0
T332 0 25 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3908 0 0
T21 0 35 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 22 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 9 0 0
T179 0 10 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 27 0 0
T244 0 70 0 0
T254 0 11 0 0
T266 0 49 0 0
T297 201043 0 0 0
T321 0 26 0 0
T323 0 52 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 4125 0 0
T21 0 43 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 36 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 10 0 0
T179 0 8 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 58 0 0
T244 0 68 0 0
T254 0 39 0 0
T266 0 55 0 0
T297 201043 0 0 0
T321 0 22 0 0
T323 0 37 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3891 0 0
T21 0 50 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 12 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 17 0 0
T179 0 9 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 21 0 0
T244 0 70 0 0
T254 0 6 0 0
T266 0 57 0 0
T297 201043 0 0 0
T321 0 11 0 0
T323 0 48 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3864 0 0
T21 0 38 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 13 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 13 0 0
T179 0 7 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 43 0 0
T244 0 62 0 0
T254 0 13 0 0
T266 0 53 0 0
T297 201043 0 0 0
T321 0 25 0 0
T323 0 39 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3833 0 0
T21 0 46 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 44 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 22 0 0
T107 0 68 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 33 0 0
T244 0 71 0 0
T254 0 17 0 0
T266 0 47 0 0
T297 201043 0 0 0
T321 0 19 0 0
T323 0 32 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 4055 0 0
T21 0 36 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 48 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 14 0 0
T179 0 12 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 23 0 0
T244 0 66 0 0
T254 0 18 0 0
T266 0 70 0 0
T297 201043 0 0 0
T321 0 18 0 0
T323 0 44 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 4173 0 0
T21 0 36 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 39 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 19 0 0
T179 0 8 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 37 0 0
T244 0 91 0 0
T254 0 17 0 0
T266 0 53 0 0
T297 201043 0 0 0
T321 0 14 0 0
T323 0 40 0 0
T326 211122 0 0 0
T327 48759 0 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3798 0 0
T21 0 42 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T44 0 21 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 10 0 0
T179 0 6 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 12 0 0
T244 0 68 0 0
T254 0 39 0 0
T266 0 48 0 0
T297 201043 0 0 0
T321 0 10 0 0
T323 0 51 0 0
T326 211122 0 0 0
T327 48759 0 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1948 0 0
T21 0 25 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T69 277840 4 0 0
T70 417240 2 0 0
T71 178231 0 0 0
T104 120289 18 0 0
T179 0 3 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T209 0 1 0 0
T237 0 1 0 0
T297 201043 0 0 0
T321 0 25 0 0
T323 0 47 0 0
T326 211122 0 0 0
T333 0 7 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1706 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 12 0 0
T145 0 8 0 0
T155 0 1 0 0
T179 0 8 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 40 0 0
T297 201043 0 0 0
T321 0 29 0 0
T323 0 25 0 0
T326 211122 0 0 0
T327 48759 0 0 0
T328 0 45 0 0
T329 0 33 0 0
T330 0 19 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3012 0 0
T3 41173 5 0 0
T29 236324 0 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T46 0 1 0 0
T49 0 6 0 0
T53 0 2 0 0
T56 225530 0 0 0
T69 277840 0 0 0
T84 241028 0 0 0
T104 120289 8 0 0
T131 0 4 0 0
T179 0 15 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T191 0 3 0 0
T321 0 24 0 0
T323 0 44 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1156 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 15 0 0
T179 0 24 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 39 0 0
T297 201043 0 0 0
T321 0 20 0 0
T323 0 25 0 0
T326 211122 0 0 0
T327 48759 0 0 0
T328 0 31 0 0
T329 0 17 0 0
T330 0 33 0 0
T331 0 37 0 0
T332 0 35 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3634 0 0
T29 236324 37 0 0
T30 59696 65 0 0
T31 344623 0 0 0
T69 277840 0 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T82 0 64 0 0
T83 0 80 0 0
T104 120289 12 0 0
T161 0 51 0 0
T179 0 5 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T297 201043 0 0 0
T321 0 22 0 0
T334 0 43 0 0
T335 0 78 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 4405 0 0
T3 41173 0 0 0
T15 243321 79 0 0
T16 99747 0 0 0
T17 34762 0 0 0
T18 63250 0 0 0
T19 193333 0 0 0
T20 230394 0 0 0
T29 236324 0 0 0
T56 225530 0 0 0
T84 241028 0 0 0
T104 0 13 0 0
T179 0 8 0 0
T219 0 22 0 0
T321 0 8 0 0
T323 0 31 0 0
T336 0 69 0 0
T337 0 76 0 0
T338 0 58 0 0
T339 0 43 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 2829 0 0
T3 41173 0 0 0
T15 243321 64 0 0
T16 99747 0 0 0
T17 34762 0 0 0
T18 63250 0 0 0
T19 193333 0 0 0
T20 230394 0 0 0
T29 236324 0 0 0
T56 225530 0 0 0
T84 241028 0 0 0
T104 0 8 0 0
T179 0 15 0 0
T219 0 52 0 0
T321 0 9 0 0
T323 0 46 0 0
T336 0 63 0 0
T337 0 89 0 0
T338 0 35 0 0
T339 0 52 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 3120 0 0
T3 41173 0 0 0
T15 243321 72 0 0
T16 99747 0 0 0
T17 34762 0 0 0
T18 63250 0 0 0
T19 193333 0 0 0
T20 230394 0 0 0
T29 236324 0 0 0
T56 225530 0 0 0
T84 241028 0 0 0
T104 0 19 0 0
T179 0 13 0 0
T219 0 47 0 0
T321 0 25 0 0
T323 0 43 0 0
T336 0 99 0 0
T337 0 63 0 0
T338 0 35 0 0
T339 0 49 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1506 0 0
T30 59696 0 0 0
T31 344623 0 0 0
T70 417240 0 0 0
T71 178231 0 0 0
T104 120289 23 0 0
T179 0 5 0 0
T182 210206 0 0 0
T183 52981 0 0 0
T219 0 23 0 0
T297 201043 0 0 0
T321 0 19 0 0
T323 0 29 0 0
T326 211122 0 0 0
T327 48759 0 0 0
T328 0 39 0 0
T329 0 36 0 0
T330 0 35 0 0
T331 0 46 0 0
T332 0 46 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1150 0 0
T1 56687 15 0 0
T2 65978 0 0 0
T3 41173 0 0 0
T14 148830 0 0 0
T15 243321 0 0 0
T16 99747 0 0 0
T17 34762 0 0 0
T18 63250 0 0 0
T19 193333 0 0 0
T20 230394 0 0 0
T74 0 5 0 0
T98 0 6 0 0
T104 0 10 0 0
T139 0 19 0 0
T148 0 2 0 0
T179 0 8 0 0
T321 0 17 0 0
T323 0 53 0 0
T340 0 6 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1472 0 0
T1 56687 4 0 0
T2 65978 0 0 0
T3 41173 0 0 0
T14 148830 0 0 0
T15 243321 0 0 0
T16 99747 0 0 0
T17 34762 0 0 0
T18 63250 0 0 0
T19 193333 0 0 0
T20 230394 0 0 0
T74 0 13 0 0
T98 0 5 0 0
T104 0 15 0 0
T139 0 16 0 0
T148 0 6 0 0
T179 0 23 0 0
T321 0 16 0 0
T340 0 2 0 0
T341 0 1 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1322 0 0
T1 56687 9 0 0
T2 65978 0 0 0
T3 41173 0 0 0
T14 148830 0 0 0
T15 243321 0 0 0
T16 99747 0 0 0
T17 34762 0 0 0
T18 63250 0 0 0
T19 193333 0 0 0
T20 230394 0 0 0
T74 0 11 0 0
T98 0 9 0 0
T104 0 15 0 0
T139 0 9 0 0
T148 0 4 0 0
T179 0 17 0 0
T321 0 28 0 0
T340 0 1 0 0
T341 0 1 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1401201797 1300 0 0
T1 56687 8 0 0
T2 65978 0 0 0
T3 41173 0 0 0
T14 148830 0 0 0
T15 243321 0 0 0
T16 99747 0 0 0
T17 34762 0 0 0
T18 63250 0 0 0
T19 193333 0 0 0
T20 230394 0 0 0
T74 0 12 0 0
T98 0 7 0 0
T104 0 7 0 0
T148 0 1 0 0
T179 0 12 0 0
T321 0 10 0 0
T323 0 41 0 0
T340 0 10 0 0
T341 0 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%