dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_reg.u_pin_in_value_ac_present

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.59 77.78 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.59 77.78 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_pin_in_value_flash_wp_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.59 77.78 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg.u_pin_in_value_ac_present
tb.dut.u_reg.u_pin_in_value_ec_rst_l
tb.dut.u_reg.u_pin_in_value_flash_wp_l
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h
tb.dut.u_reg.u_key_intr_debounce_ctl
tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0
tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0
tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0
tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0
tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0
tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1
tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1
tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1
tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1
tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1
tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2
tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2
tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2
tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2
tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2
tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3
tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3
tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3
tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3
tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3
tb.dut.u_reg.u_com_pre_det_ctl_0
tb.dut.u_reg.u_com_pre_det_ctl_1
tb.dut.u_reg.u_com_pre_det_ctl_2
tb.dut.u_reg.u_com_pre_det_ctl_3
tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ac_present
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ac_present
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ac_present
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==> (Excluded)

Branches:
-1-StatusTestsExclude Annotation
1 Covered T4,T5,T6
0 Excluded VC_COV_UNR 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==> (Excluded)

Branches:
-1-StatusTestsExclude Annotation
1 Covered T4,T5,T6
0 Excluded VC_COV_UNR 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_flash_wp_l
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_flash_wp_l
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_flash_wp_l
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==> (Excluded)

Branches:
-1-StatusTestsExclude Annotation
1 Covered T4,T5,T6
0 Excluded VC_COV_UNR 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T2 T3 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T3 T7 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T2 T10 T51 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T3 T7 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T2 T3 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T2 T3 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T12 T51 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T3 T7 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T47 T45 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T2 T10 T12 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T12 T51 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T2 T3 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T2 T7 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T2 T3 T7 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T2 T3 T7 
65         1/1            assign qe = wr_en;
           Tests:       T2 T3 T7 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T2 T3 T7 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T7
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T2,T3,T7
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T22 T2 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T22 T2 
65         1/1            assign qe = wr_en;
           Tests:       T5 T22 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T5 T22 T2 
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T22,T2
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T22,T2
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T22,T2
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T24 T31 T32 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T24 T31 T32 
65         1/1            assign qe = wr_en;
           Tests:       T24 T31 T32 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T24 T31 T32 
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T31,T32
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T24,T31,T32
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T24,T31,T32
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T24 T31 T32 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T24 T31 T32 
65         1/1            assign qe = wr_en;
           Tests:       T24 T31 T32 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T24 T31 T32 
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T31,T32
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T24,T31,T32
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T24,T31,T32
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T24 T31 T32 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T24 T31 T32 
65         1/1            assign qe = wr_en;
           Tests:       T24 T31 T32 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T24 T31 T32 
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T31,T32
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T24,T31,T32
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T24,T31,T32
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T24 T31 T32 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T24 T31 T32 
65         1/1            assign qe = wr_en;
           Tests:       T24 T31 T32 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T24 T31 T32 
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T31,T32
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T24,T31,T32
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T24,T31,T32
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T24 T31 T32 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T24 T31 T32 
65         1/1            assign qe = wr_en;
           Tests:       T24 T31 T32 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T24 T31 T32 
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T31,T32
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T24,T31,T32
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T24,T31,T32
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T24 T31 T32 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T24 T31 T32 
65         1/1            assign qe = wr_en;
           Tests:       T24 T31 T32 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T24 T31 T32 
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T31,T32
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T24,T31,T32
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T24,T31,T32
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T24 T31 T32 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T24 T31 T32 
65         1/1            assign qe = wr_en;
           Tests:       T24 T31 T32 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T24 T31 T32 
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T31,T32
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T24,T31,T32
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T24,T31,T32
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T24 T31 T32 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T24 T31 T32 
65         1/1            assign qe = wr_en;
           Tests:       T24 T31 T32 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T24 T31 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T31,T32
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T24,T31,T32
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T24,T31,T32
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T17 T8 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T17 T8 
65         1/1            assign qe = wr_en;
           Tests:       T5 T17 T8 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T13 T89 T90 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T17,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T17,T8
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T17,T8
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T17 T8 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T17 T8 
65         1/1            assign qe = wr_en;
           Tests:       T5 T17 T8 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T89 T90 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T17,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T17,T8
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T17,T8
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T17 T8 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T17 T8 
65         1/1            assign qe = wr_en;
           Tests:       T5 T17 T8 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T89 T90 T91 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T17,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T17,T8
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T17,T8
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T17 T8 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T17 T8 
65         1/1            assign qe = wr_en;
           Tests:       T5 T17 T8 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T5 T17 T8 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T17,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T17,T8
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T17,T8
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T17 T8 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T17 T8 
65         1/1            assign qe = wr_en;
           Tests:       T5 T17 T8 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T42 T41 T254 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T17,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T17,T8
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T17,T8
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T13 T42 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T13 T33 T40 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T13 T89 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T42 T89 T90 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T89 T107 T294 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T89 T92 T254 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T42 T90 T91 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T42 T89 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T13 T33 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T40 T93 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T42 T89 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T33 T42 T93 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T13 T90 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T33 T90 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T42 T90 T40 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T17 T8 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T17 T8 
65         1/1            assign qe = wr_en;
           Tests:       T5 T17 T8 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T5 T17 T8 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T17,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T17,T8
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T17,T8
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T13 T33 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T13 T33 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T33 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T33 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T33 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T13 T33 
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T33
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T33
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T33
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T22 T17 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T22 T17 
65         1/1            assign qe = wr_en;
           Tests:       T5 T22 T17 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T5 T22 T17 
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T22,T17
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T22,T17
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T22,T17
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T22 T17 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T22 T17 
65         1/1            assign qe = wr_en;
           Tests:       T5 T22 T17 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T5 T22 T17 
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T22,T17
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T22,T17
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T22,T17
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T22 T17 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T22 T17 
65         1/1            assign qe = wr_en;
           Tests:       T5 T22 T17 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T5 T22 T17 
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T22,T17
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T22,T17
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T22,T17
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T22 T17 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T22 T17 
65         1/1            assign qe = wr_en;
           Tests:       T5 T22 T17 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T90 T93 T41 
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T22,T17
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T22,T17
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T22,T17
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T5 T22 T17 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T5 T22 T17 
65         1/1            assign qe = wr_en;
           Tests:       T5 T22 T17 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T13 T21 
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T22,T17
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T5,T22,T17
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T5,T22,T17
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T21 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T21 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T21 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T21 T34 T33 
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T21
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T21
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T21
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T21 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T21 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T21 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T96 T90 T97 
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T21
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T21
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T21
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T21 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T21 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T21 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T21 T34 T33 
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T21
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T21
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T21
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T10 T13 T21 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T10 T13 T21 
65         1/1            assign qe = wr_en;
           Tests:       T10 T13 T21 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T10 T13 T34 
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT10,T13,T21
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T10,T13,T21
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T10,T13,T21
0 0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%