Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T1
1	0	Covered	T5,T22,T1
1	1	Covered	T1,T10,T74

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T1
1	0	Covered	T1,T10,T74
1	1	Covered	T5,T22,T1

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	200958	0	0
SrcPulseCheck_M	2147483647	204107	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	200958
T1	173223	0
T2	199866	0
T5	61570	2
T6	43197	0
T8	0	2
T9	0	2
T10	972077	33
T11	43884	0
T12	53460	0
T13	0	3
T14	448056	0
T15	731469	0
T16	300513	0
T17	70450	2
T18	127552	0
T19	387470	0
T20	463150	2
T21	0	6
T22	53793	2
T23	123210	0
T24	61122	16
T31	0	18
T32	0	14
T56	0	2
T57	0	2
T58	115310	2
T59	0	14
T60	0	10
T61	0	34
T62	0	14
T63	0	16
T64	0	16
T65	261236	0
T66	125914	0
T67	159306	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	204107
T1	173223	0
T2	199866	0
T5	61570	2
T6	43197	0
T8	0	2
T9	0	2
T10	8125	33
T11	783	0
T12	632	0
T13	0	3
T14	448056	0
T15	731469	0
T16	300513	0
T17	70450	2
T18	127552	0
T19	387470	0
T20	463150	2
T21	0	6
T22	53793	2
T23	123210	0
T24	61122	16
T31	0	18
T32	0	14
T56	0	2
T57	0	2
T58	470	2
T59	0	14
T60	0	10
T61	0	36
T62	0	14
T63	0	16
T64	0	16
T65	522	0
T66	503	0
T67	677	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T5 T22 T17

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T5,T22,T17
1	1	Covered	T37,T306,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T37,T306,T25
1	1	Covered	T5,T22,T17

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1685	0	0
SrcPulseCheck_M	1401201797	1778	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1685
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1
T69	0	1
T70	0	1
T71	0	1
T72	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1778
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1
T69	0	1
T70	0	1
T71	0	1
T72	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T5,T22,T17
1	1	Covered	T37,T306,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T37,T306,T25
1	1	Covered	T5,T22,T17

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1770	0	0
SrcPulseCheck_M	10013830	1770	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1770
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1
T69	0	1
T70	0	1
T71	0	1
T72	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1770
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1
T69	0	1
T70	0	1
T71	0	1
T72	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T10 T11

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T74,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T74,T39
1	1	Covered	T1,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	867	0	0
SrcPulseCheck_M	1401201797	955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	867
T1	1054	3
T2	644	0
T3	847	0
T10	0	1
T11	0	1
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	955
T1	56687	3
T2	65978	0
T3	41173	0
T10	0	1
T11	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T74,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T74,T39
1	1	Covered	T1,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	945	0	0
SrcPulseCheck_M	10013830	945	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	945
T1	56687	3
T2	65978	0
T3	41173	0
T10	0	1
T11	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	945
T1	1054	3
T2	644	0
T3	847	0
T10	0	1
T11	0	1
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T10 T11

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T74,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T74,T39
1	1	Covered	T1,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	846	0	0
SrcPulseCheck_M	1401201797	940	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	846
T1	1054	3
T2	644	0
T3	847	0
T10	0	1
T11	0	1
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	940
T1	56687	3
T2	65978	0
T3	41173	0
T10	0	1
T11	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T74,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T74,T39
1	1	Covered	T1,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	932	0	0
SrcPulseCheck_M	10013830	932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	932
T1	56687	3
T2	65978	0
T3	41173	0
T10	0	1
T11	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	932
T1	1054	3
T2	644	0
T3	847	0
T10	0	1
T11	0	1
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T10 T11

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T74,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T74,T39
1	1	Covered	T1,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	852	0	0
SrcPulseCheck_M	1401201797	939	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	852
T1	1054	3
T2	644	0
T3	847	0
T10	0	1
T11	0	1
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	939
T1	56687	3
T2	65978	0
T3	41173	0
T10	0	1
T11	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T74,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T74,T39
1	1	Covered	T1,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	931	0	0
SrcPulseCheck_M	10013830	931	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	931
T1	56687	3
T2	65978	0
T3	41173	0
T10	0	1
T11	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	931
T1	1054	3
T2	644	0
T3	847	0
T10	0	1
T11	0	1
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T39	0	2
T50	0	1
T68	0	2
T73	0	1
T74	0	3
T75	0	2
T76	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T10 T11

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T10,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	875	0	0
SrcPulseCheck_M	1401201797	968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	875
T1	1054	2
T2	644	0
T3	847	0
T10	0	4
T11	0	2
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T39	0	2
T50	0	2
T68	0	4
T75	0	2
T76	0	2
T90	0	4
T98	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	968
T1	56687	2
T2	65978	0
T3	41173	0
T10	0	4
T11	0	2
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T39	0	2
T50	0	2
T68	0	4
T75	0	2
T76	0	2
T90	0	4
T98	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T10,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	960	0	0
SrcPulseCheck_M	10013830	960	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	960
T1	56687	2
T2	65978	0
T3	41173	0
T10	0	4
T11	0	2
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T39	0	2
T50	0	2
T68	0	4
T75	0	2
T76	0	2
T90	0	4
T98	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	960
T1	1054	2
T2	644	0
T3	847	0
T10	0	4
T11	0	2
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T39	0	2
T50	0	2
T68	0	4
T75	0	2
T76	0	2
T90	0	4
T98	0	2

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T10 T11

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11
1	1	Covered	T34,T42,T68

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T11
1	0	Covered	T34,T42,T68
1	1	Covered	T1,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1045	0	0
SrcPulseCheck_M	1401201797	1135	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1045
T1	1054	1
T2	644	0
T3	847	0
T10	0	1
T11	0	1
T13	0	2
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T21	0	4
T34	0	5
T39	0	1
T42	0	4
T50	0	1
T68	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1135
T1	56687	1
T2	65978	0
T3	41173	0
T10	0	1
T11	0	1
T13	0	2
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T21	0	4
T34	0	5
T39	0	1
T42	0	4
T50	0	1
T68	0	2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T23 T29 T30

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T29,T30
1	0	Covered	T23,T29,T30
1	1	Covered	T23,T29,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T29,T30
1	0	Covered	T23,T29,T30
1	1	Covered	T23,T29,T30

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1862	0	0
SrcPulseCheck_M	1401201797	1955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1862
T1	1054	0
T2	644	0
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T23	491	20
T24	657	0
T29	0	20
T30	0	20
T77	0	20
T78	0	20
T79	0	20
T80	0	20
T81	0	20
T82	0	20
T83	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1955
T1	56687	0
T2	65978	0
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T23	122719	20
T24	19717	0
T29	0	20
T30	0	20
T77	0	20
T78	0	20
T79	0	20
T80	0	20
T81	0	20
T82	0	20
T83	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T29,T30
1	0	Covered	T23,T29,T30
1	1	Covered	T23,T29,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T29,T30
1	0	Covered	T23,T29,T30
1	1	Covered	T23,T29,T30

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1949	0	0
SrcPulseCheck_M	10013830	1949	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1949
T1	56687	0
T2	65978	0
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T23	122719	20
T24	19717	0
T29	0	20
T30	0	20
T77	0	20
T78	0	20
T79	0	20
T80	0	20
T81	0	20
T82	0	20
T83	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1949
T1	1054	0
T2	644	0
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T23	491	20
T24	657	0
T29	0	20
T30	0	20
T77	0	20
T78	0	20
T79	0	20
T80	0	20
T81	0	20
T82	0	20
T83	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T23 T14 T15

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T14,T15
1	0	Covered	T23,T14,T15
1	1	Covered	T14,T15,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T14,T15
1	0	Covered	T14,T15,T18
1	1	Covered	T23,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	3860	0	0
SrcPulseCheck_M	1401201797	3956	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	3860
T1	1054	0
T2	644	0
T14	522	20
T15	502	20
T16	424	0
T17	463	0
T18	526	20
T19	402	0
T23	491	1
T24	657	0
T29	0	1
T30	0	1
T71	0	20
T84	0	20
T85	0	20
T86	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	3956
T1	56687	0
T2	65978	0
T14	148830	20
T15	243321	20
T16	99747	0
T17	34762	0
T18	63250	20
T19	193333	0
T23	122719	1
T24	19717	0
T29	0	1
T30	0	1
T71	0	20
T84	0	20
T85	0	20
T86	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T14,T15
1	0	Covered	T23,T14,T15
1	1	Covered	T14,T15,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T14,T15
1	0	Covered	T14,T15,T18
1	1	Covered	T23,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	3945	0	0
SrcPulseCheck_M	10013830	3945	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	3945
T1	56687	0
T2	65978	0
T14	148830	20
T15	243321	20
T16	99747	0
T17	34762	0
T18	63250	20
T19	193333	0
T23	122719	1
T24	19717	0
T29	0	1
T30	0	1
T71	0	20
T84	0	20
T85	0	20
T86	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	3945
T1	1054	0
T2	644	0
T14	522	20
T15	502	20
T16	424	0
T17	463	0
T18	526	20
T19	402	0
T23	491	1
T24	657	0
T29	0	1
T30	0	1
T71	0	20
T84	0	20
T85	0	20
T86	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T5 T22 T23

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T23
1	0	Covered	T5,T22,T23
1	1	Covered	T14,T15,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T23
1	0	Covered	T14,T15,T18
1	1	Covered	T5,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	4811	0	0
SrcPulseCheck_M	1401201797	4909	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	4811
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T14	522	20
T15	502	20
T16	424	0
T17	0	1
T18	0	20
T20	0	1
T22	444	1
T23	491	1
T24	657	0
T56	0	1
T84	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	4909
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T14	148830	20
T15	243321	20
T16	99747	0
T17	0	1
T18	0	20
T20	0	1
T22	53349	1
T23	122719	1
T24	19717	0
T56	0	1
T84	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T23
1	0	Covered	T5,T22,T23
1	1	Covered	T14,T15,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T23
1	0	Covered	T14,T15,T18
1	1	Covered	T5,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	4898	0	0
SrcPulseCheck_M	10013830	4898	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	4898
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T14	148830	20
T15	243321	20
T16	99747	0
T17	0	1
T18	0	20
T20	0	1
T22	53349	1
T23	122719	1
T24	19717	0
T56	0	1
T84	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	4898
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T14	522	20
T15	502	20
T16	424	0
T17	0	1
T18	0	20
T20	0	1
T22	444	1
T23	491	1
T24	657	0
T56	0	1
T84	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T14 T15 T18

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T14,T15,T18
1	0	Covered	T14,T15,T18
1	1	Covered	T14,T15,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T14,T15,T18
1	0	Covered	T14,T15,T18
1	1	Covered	T14,T15,T18

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	3807	0	0
SrcPulseCheck_M	1401201797	3899	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	3807
T2	644	0
T3	847	0
T14	522	20
T15	502	20
T16	424	0
T17	463	0
T18	526	20
T19	402	0
T20	1181	0
T65	0	20
T66	0	20
T71	0	20
T84	502	20
T85	0	20
T86	0	20
T87	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	3899
T2	65978	0
T3	41173	0
T14	148830	20
T15	243321	20
T16	99747	0
T17	34762	0
T18	63250	20
T19	193333	0
T20	230394	0
T65	0	20
T66	0	20
T71	0	20
T84	241028	20
T85	0	20
T86	0	20
T87	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T14,T15,T18
1	0	Covered	T14,T15,T18
1	1	Covered	T14,T15,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T14,T15,T18
1	0	Covered	T14,T15,T18
1	1	Covered	T14,T15,T18

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	3886	0	0
SrcPulseCheck_M	10013830	3886	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	3886
T2	65978	0
T3	41173	0
T14	148830	20
T15	243321	20
T16	99747	0
T17	34762	0
T18	63250	20
T19	193333	0
T20	230394	0
T65	0	20
T66	0	20
T71	0	20
T84	241028	20
T85	0	20
T86	0	20
T87	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	3886
T2	644	0
T3	847	0
T14	522	20
T15	502	20
T16	424	0
T17	463	0
T18	526	20
T19	402	0
T20	1181	0
T65	0	20
T66	0	20
T71	0	20
T84	502	20
T85	0	20
T86	0	20
T87	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T2 T3 T7

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T10,T90,T37
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	846	0	0
SrcPulseCheck_M	1401201797	939	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	846
T2	644	1
T3	847	1
T7	0	1
T10	0	28
T12	0	1
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T45	0	1
T46	0	1
T47	0	1
T51	0	1
T54	0	1
T56	451	0
T84	502	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	939
T2	65978	1
T3	41173	1
T7	0	1
T10	0	28
T12	0	1
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T45	0	1
T46	0	1
T47	0	1
T51	0	1
T54	0	1
T56	225530	0
T84	241028	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T10,T90,T37
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	930	0	0
SrcPulseCheck_M	10013830	930	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	930
T2	65978	1
T3	41173	1
T7	0	1
T10	0	28
T12	0	1
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T45	0	1
T46	0	1
T47	0	1
T51	0	1
T54	0	1
T56	225530	0
T84	241028	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	930
T2	644	1
T3	847	1
T7	0	1
T10	0	28
T12	0	1
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T45	0	1
T46	0	1
T47	0	1
T51	0	1
T54	0	1
T56	451	0
T84	502	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T5 T22 T2

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T2
1	0	Covered	T5,T22,T2
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T2
1	0	Covered	T10,T90,T37
1	1	Covered	T5,T22,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1738	0	0
SrcPulseCheck_M	1401201797	1832	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1738
T1	1054	0
T2	644	1
T3	0	1
T5	469	1
T6	427	0
T7	0	1
T8	0	1
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1832
T1	56687	0
T2	65978	1
T3	0	1
T5	61101	1
T6	42770	0
T7	0	1
T8	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T2
1	0	Covered	T5,T22,T2
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T2
1	0	Covered	T10,T90,T37
1	1	Covered	T5,T22,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1823	0	0
SrcPulseCheck_M	10013830	1823	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1823
T1	56687	0
T2	65978	1
T3	0	1
T5	61101	1
T6	42770	0
T7	0	1
T8	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1823
T1	1054	0
T2	644	1
T3	0	1
T5	469	1
T6	427	0
T7	0	1
T8	0	1
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T24 T31 T32

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T31,T32
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T31,T32
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1061	0	0
SrcPulseCheck_M	1401201797	1151	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1061
T1	1054	0
T2	644	0
T10	0	2
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T24	657	5
T31	0	6
T32	0	4
T59	0	4
T60	0	3
T61	0	11
T62	0	4
T63	0	5
T64	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1151
T1	56687	0
T2	65978	0
T10	0	2
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T24	19717	5
T31	0	6
T32	0	4
T59	0	4
T60	0	3
T61	0	12
T62	0	4
T63	0	5
T64	0	5

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T31,T32
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T31,T32
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1143	0	0
SrcPulseCheck_M	10013830	1143	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1143
T1	56687	0
T2	65978	0
T10	0	2
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T24	19717	5
T31	0	6
T32	0	4
T59	0	4
T60	0	3
T61	0	11
T62	0	4
T63	0	5
T64	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1143
T1	1054	0
T2	644	0
T10	0	2
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T24	657	5
T31	0	6
T32	0	4
T59	0	4
T60	0	3
T61	0	11
T62	0	4
T63	0	5
T64	0	5

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T24 T31 T32

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T31,T32
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T31,T32
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	941	0	0
SrcPulseCheck_M	1401201797	1035	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	941
T1	1054	0
T2	644	0
T10	0	1
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T24	657	3
T31	0	3
T32	0	3
T59	0	3
T60	0	2
T61	0	6
T62	0	3
T63	0	3
T64	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1035
T1	56687	0
T2	65978	0
T10	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T24	19717	3
T31	0	3
T32	0	3
T59	0	3
T60	0	2
T61	0	7
T62	0	3
T63	0	3
T64	0	3

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T31,T32
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T31,T32
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1025	0	0
SrcPulseCheck_M	10013830	1025	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1025
T1	56687	0
T2	65978	0
T10	0	1
T14	148830	0
T15	243321	0
T16	99747	0
T17	34762	0
T18	63250	0
T19	193333	0
T20	230394	0
T24	19717	3
T31	0	3
T32	0	3
T59	0	3
T60	0	2
T61	0	6
T62	0	3
T63	0	3
T64	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1025
T1	1054	0
T2	644	0
T10	0	1
T14	522	0
T15	502	0
T16	424	0
T17	463	0
T18	526	0
T19	402	0
T20	1181	0
T24	657	3
T31	0	3
T32	0	3
T59	0	3
T60	0	2
T61	0	6
T62	0	3
T63	0	3
T64	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T5 T17 T8

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T17,T8
1	0	Covered	T5,T17,T8
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T17,T8
1	0	Covered	T10,T13,T33
1	1	Covered	T5,T17,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	6847	0	0
SrcPulseCheck_M	1401201797	6941	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	6847
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T10	0	11
T13	0	72
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T22	444	0
T23	491	0
T24	657	0
T33	0	51
T42	0	71
T58	0	1
T88	0	1
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	6941
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T10	0	11
T13	0	72
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T22	53349	0
T23	122719	0
T24	19717	0
T33	0	51
T42	0	71
T58	0	1
T88	0	1
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T17,T8
1	0	Covered	T5,T17,T8
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T17,T8
1	0	Covered	T10,T13,T33
1	1	Covered	T5,T17,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	6934	0	0
SrcPulseCheck_M	10013830	6934	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	6934
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T10	0	11
T13	0	72
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T22	53349	0
T23	122719	0
T24	19717	0
T33	0	51
T42	0	71
T58	0	1
T88	0	1
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	6934
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T10	0	11
T13	0	72
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T22	444	0
T23	491	0
T24	657	0
T33	0	51
T42	0	71
T58	0	1
T88	0	1
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T33

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	6895	0	0
SrcPulseCheck_M	1401201797	6992	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	6895
T10	8125	11
T11	783	0
T12	632	0
T13	10538	88
T33	0	51
T40	0	63
T42	0	75
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T91	0	51
T92	0	73
T93	0	70
T94	427	0
T95	1341	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	6992
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	88
T33	0	51
T40	0	63
T42	0	75
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T91	0	51
T92	0	73
T93	0	70
T94	42805	0
T95	509844	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	6981	0	0
SrcPulseCheck_M	10013830	6981	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	6981
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	88
T33	0	51
T40	0	63
T42	0	75
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T91	0	51
T92	0	73
T93	0	70
T94	42805	0
T95	509844	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	6981
T10	8125	11
T11	783	0
T12	632	0
T13	10538	88
T33	0	51
T40	0	63
T42	0	75
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T91	0	51
T92	0	73
T93	0	70
T94	427	0
T95	1341	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T33

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	6829	0	0
SrcPulseCheck_M	1401201797	6918	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	6829
T10	8125	11
T11	783	0
T12	632	0
T13	10538	71
T33	0	51
T40	0	67
T42	0	74
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T91	0	51
T92	0	83
T93	0	80
T94	427	0
T95	1341	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	6918
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	71
T33	0	51
T40	0	67
T42	0	74
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T91	0	51
T92	0	83
T93	0	80
T94	42805	0
T95	509844	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	6909	0	0
SrcPulseCheck_M	10013830	6909	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	6909
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	71
T33	0	51
T40	0	67
T42	0	74
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T91	0	51
T92	0	83
T93	0	80
T94	42805	0
T95	509844	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	6909
T10	8125	11
T11	783	0
T12	632	0
T13	10538	71
T33	0	51
T40	0	67
T42	0	74
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T91	0	51
T92	0	83
T93	0	80
T94	427	0
T95	1341	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T33

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	6839	0	0
SrcPulseCheck_M	1401201797	6934	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	6839
T10	8125	11
T11	783	0
T12	632	0
T13	10538	72
T33	0	51
T40	0	67
T42	0	84
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T91	0	51
T92	0	56
T93	0	80
T94	427	0
T95	1341	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	6934
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	72
T33	0	51
T40	0	67
T42	0	84
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T91	0	51
T92	0	56
T93	0	80
T94	42805	0
T95	509844	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	6927	0	0
SrcPulseCheck_M	10013830	6927	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	6927
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	72
T33	0	51
T40	0	67
T42	0	84
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T91	0	51
T92	0	56
T93	0	80
T94	42805	0
T95	509844	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	6927
T10	8125	11
T11	783	0
T12	632	0
T13	10538	72
T33	0	51
T40	0	67
T42	0	84
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T91	0	51
T92	0	56
T93	0	80
T94	427	0
T95	1341	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T5 T17 T8

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T17,T8
1	0	Covered	T5,T17,T8
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T17,T8
1	0	Covered	T10,T90,T37
1	1	Covered	T5,T17,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1082	0	0
SrcPulseCheck_M	1401201797	1172	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1082
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T10	0	9
T13	0	3
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T22	444	0
T23	491	0
T24	657	0
T33	0	1
T42	0	4
T58	0	1
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1172
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T10	0	9
T13	0	3
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T22	53349	0
T23	122719	0
T24	19717	0
T33	0	1
T42	0	4
T58	0	1
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T17,T8
1	0	Covered	T5,T17,T8
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T17,T8
1	0	Covered	T10,T90,T37
1	1	Covered	T5,T17,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1166	0	0
SrcPulseCheck_M	10013830	1166	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1166
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T10	0	9
T13	0	3
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T22	53349	0
T23	122719	0
T24	19717	0
T33	0	1
T42	0	4
T58	0	1
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1166
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T10	0	9
T13	0	3
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T22	444	0
T23	491	0
T24	657	0
T33	0	1
T42	0	4
T58	0	1
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T33

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1096	0	0
SrcPulseCheck_M	1401201797	1189	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1096
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T33	0	1
T40	0	8
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	427	0
T95	1341	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1189
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T33	0	1
T40	0	8
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	42805	0
T95	509844	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1180	0	0
SrcPulseCheck_M	10013830	1180	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1180
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T33	0	1
T40	0	8
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	42805	0
T95	509844	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1180
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T33	0	1
T40	0	8
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	427	0
T95	1341	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T33

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1085	0	0
SrcPulseCheck_M	1401201797	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1085
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T33	0	1
T40	0	8
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	427	0
T95	1341	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1177
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T33	0	1
T40	0	8
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	42805	0
T95	509844	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1170	0	0
SrcPulseCheck_M	10013830	1170	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1170
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T33	0	1
T40	0	8
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	42805	0
T95	509844	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1170
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T33	0	1
T40	0	8
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	427	0
T95	1341	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T33

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1103	0	0
SrcPulseCheck_M	1401201797	1193	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1103
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T33	0	1
T40	0	8
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	427	0
T95	1341	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1193
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T33	0	1
T40	0	8
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	42805	0
T95	509844	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T33
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1182	0	0
SrcPulseCheck_M	10013830	1182	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1182
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T33	0	1
T40	0	8
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	42805	0
T95	509844	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1182
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T33	0	1
T40	0	8
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T91	0	1
T92	0	1
T93	0	2
T94	427	0
T95	1341	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T5 T22 T17

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T5,T22,T17
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T10,T13,T33
1	1	Covered	T5,T22,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	7424	0	0
SrcPulseCheck_M	1401201797	7517	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	7424
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T9	0	1
T10	0	11
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	7517
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T9	0	1
T10	0	11
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T5,T22,T17
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T10,T13,T33
1	1	Covered	T5,T22,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	7508	0	0
SrcPulseCheck_M	10013830	7508	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	7508
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T9	0	1
T10	0	11
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	7508
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T9	0	1
T10	0	11
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T21

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	7418	0	0
SrcPulseCheck_M	1401201797	7515	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	7418
T10	8125	11
T11	783	0
T12	632	0
T13	10538	88
T21	0	6
T33	0	51
T34	0	6
T42	0	75
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	7515
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	88
T21	0	6
T33	0	51
T34	0	6
T42	0	75
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	7506	0	0
SrcPulseCheck_M	10013830	7506	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	7506
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	88
T21	0	6
T33	0	51
T34	0	6
T42	0	75
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	7506
T10	8125	11
T11	783	0
T12	632	0
T13	10538	88
T21	0	6
T33	0	51
T34	0	6
T42	0	75
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T21

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	7357	0	0
SrcPulseCheck_M	1401201797	7451	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	7357
T10	8125	11
T11	783	0
T12	632	0
T13	10538	71
T21	0	6
T33	0	51
T34	0	6
T42	0	74
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	7451
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	71
T21	0	6
T33	0	51
T34	0	6
T42	0	74
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	7441	0	0
SrcPulseCheck_M	10013830	7441	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	7441
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	71
T21	0	6
T33	0	51
T34	0	6
T42	0	74
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	7441
T10	8125	11
T11	783	0
T12	632	0
T13	10538	71
T21	0	6
T33	0	51
T34	0	6
T42	0	74
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T21

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	7376	0	0
SrcPulseCheck_M	1401201797	7472	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	7376
T10	8125	11
T11	783	0
T12	632	0
T13	10538	72
T21	0	6
T33	0	51
T34	0	6
T42	0	84
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	7472
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	72
T21	0	6
T33	0	51
T34	0	6
T42	0	84
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T13,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T33
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	7459	0	0
SrcPulseCheck_M	10013830	7459	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	7459
T10	972077	11
T11	43884	0
T12	53460	0
T13	126456	72
T21	0	6
T33	0	51
T34	0	6
T42	0	84
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	51
T90	0	11
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	7459
T10	8125	11
T11	783	0
T12	632	0
T13	10538	72
T21	0	6
T33	0	51
T34	0	6
T42	0	84
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	51
T90	0	11
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T5 T22 T17

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T5,T22,T17
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T10,T90,T37
1	1	Covered	T5,T22,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1664	0	0
SrcPulseCheck_M	1401201797	1759	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1664
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T9	0	1
T10	0	9
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1759
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T9	0	1
T10	0	9
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T5,T22,T17
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T10,T90,T37
1	1	Covered	T5,T22,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1749	0	0
SrcPulseCheck_M	10013830	1749	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1749
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T9	0	1
T10	0	9
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1749
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T9	0	1
T10	0	9
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T21

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1651	0	0
SrcPulseCheck_M	1401201797	1738	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1651
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1738
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1729	0	0
SrcPulseCheck_M	10013830	1729	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1729
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1729
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T21

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1675	0	0
SrcPulseCheck_M	1401201797	1761	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1675
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1761
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1754	0	0
SrcPulseCheck_M	10013830	1754	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1754
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1754
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T21

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1630	0	0
SrcPulseCheck_M	1401201797	1723	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1630
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1723
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1713	0	0
SrcPulseCheck_M	10013830	1713	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1713
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1713
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T5 T22 T17

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T5,T22,T17
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T10,T90,T37
1	1	Covered	T5,T22,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1667	0	0
SrcPulseCheck_M	1401201797	1763	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1667
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T9	0	1
T10	0	9
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1763
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T9	0	1
T10	0	9
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T5,T22,T17
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T22,T17
1	0	Covered	T10,T90,T37
1	1	Covered	T5,T22,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1753	0	0
SrcPulseCheck_M	10013830	1753	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1753
T1	56687	0
T2	65978	0
T5	61101	1
T6	42770	0
T8	0	1
T9	0	1
T10	0	9
T14	148830	0
T15	243321	0
T16	99747	0
T17	0	1
T20	0	1
T22	53349	1
T23	122719	0
T24	19717	0
T56	0	1
T57	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1753
T1	1054	0
T2	644	0
T5	469	1
T6	427	0
T8	0	1
T9	0	1
T10	0	9
T14	522	0
T15	502	0
T16	424	0
T17	0	1
T20	0	1
T22	444	1
T23	491	0
T24	657	0
T56	0	1
T57	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T21

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1650	0	0
SrcPulseCheck_M	1401201797	1741	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1650
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1741
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1730	0	0
SrcPulseCheck_M	10013830	1730	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1730
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1730
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T21

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1629	0	0
SrcPulseCheck_M	1401201797	1720	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1629
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1720
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1711	0	0
SrcPulseCheck_M	10013830	1711	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1711
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1711
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T10 T13 T21

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	10013830	1610	0	0
SrcPulseCheck_M	1401201797	1705	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	10013830	1610
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1401201797	1705
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T13,T21
1	1	Covered	T10,T90,T37

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T13,T21
1	0	Covered	T10,T90,T37
1	1	Covered	T10,T13,T21

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1401201797	1696	0	0
SrcPulseCheck_M	10013830	1696	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1401201797	1696
T10	972077	9
T11	43884	0
T12	53460	0
T13	126456	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	115310	0
T65	261236	0
T66	125914	0
T67	159306	0
T89	0	1
T90	0	9
T94	42805	0
T95	509844	0
T96	0	13
T97	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10013830	1696
T10	8125	9
T11	783	0
T12	632	0
T13	10538	3
T21	0	6
T33	0	1
T34	0	6
T42	0	4
T58	470	0
T65	522	0
T66	503	0
T67	677	0
T89	0	1
T90	0	9
T94	427	0
T95	1341	0
T96	0	13
T97	0	11

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_lid_debounce_ctl_cdc