Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.39	93.48	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.39	93.48	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T2 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T5 T24 T8 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T5 T24 T8 
149        1/1                    cnt_en = 1'b1;
           Tests:       T5 T24 T8 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T5 T24 T8 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T5 T24 T8 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T5 T24 T8 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T5 T8 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T5 T8 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T5 T8 T31 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T43 T94 T237 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T5 T8 T31 
182        1/1                  cnt_en = 1'b1;
           Tests:       T5 T8 T31 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T5 T8 T31 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T5 T8 T31 
191        1/1                      state_d = StableSt;
           Tests:       T5 T8 T31 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T5 T8 T31 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T5 T8 T31 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T5 T8 T31 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T5 T8 T31 
206        1/1                    state_d = IdleSt;
           Tests:       T5 T31 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T5 T8 T31 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T8,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T8
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T24,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T31
0	1	Covered	T5,T45,T48
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T8,T31
1	-	Covered	T5,T45,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T24,T8
DetectSt	168	Covered	T5,T8,T31
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T8,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T8,T31
DebounceSt->IdleSt	163	Covered	T24,T43,T94
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5,T8,T31
IdleSt->DebounceSt	148	Covered	T5,T24,T8
StableSt->IdleSt	206	Covered	T5,T31,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T24,T8
0	1	Covered	T5,T24,T8
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T31
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T24,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T8,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T94,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T24,T8
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T5,T8,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T31,T45
StableSt	-	-	-	-	-	-	0	Covered	T5,T8,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	71	0	0
CntIncr_A	5947631	54652	0	0
CntNoWrap_A	5947631	5481169	0	0
DetectStDropOut_A	5947631	0	0	0
DetectedOut_A	5947631	160304	0	0
DetectedPulseOut_A	5947631	33	0	0
DisabledIdleSt_A	5947631	5155033	0	0
DisabledNoDetection_A	5947631	5156827	0	0
EnterDebounceSt_A	5947631	38	0	0
EnterDetectSt_A	5947631	33	0	0
EnterStableSt_A	5947631	33	0	0
PulseIsPulse_A	5947631	33	0	0
StayInStableSt	5947631	160255	0	0
gen_high_level_sva.HighLevelEvent_A	5947631	5483067	0	0
gen_not_sticky_sva.StableStDropOut_A	5947631	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	71	0	0
T5	790	2	0	0
T6	480	0	0	0
T8	0	2	0	0
T24	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T170	404	0	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	54652	0	0
T5	790	35	0	0
T6	480	0	0	0
T8	0	31	0	0
T24	0	24	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	29	0	0
T43	0	45	0	0
T45	0	65	0	0
T48	0	102	0	0
T49	0	32	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	74	0	0
T170	404	0	0	0
T178	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481169	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	160304	0	0
T5	790	13	0	0
T6	480	0	0	0
T8	0	82	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	18	0	0
T45	0	27	0	0
T48	0	292	0	0
T49	0	77	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T167	0	4	0	0
T170	404	0	0	0
T172	0	76	0	0
T178	0	115	0	0
T188	0	224	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	33	0	0
T5	790	1	0	0
T6	480	0	0	0
T8	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T45	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T167	0	1	0	0
T170	404	0	0	0
T172	0	2	0	0
T178	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5155033	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5156827	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	38	0	0
T5	790	1	0	0
T6	480	0	0	0
T8	0	1	0	0
T24	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T170	404	0	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	33	0	0
T5	790	1	0	0
T6	480	0	0	0
T8	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T45	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T167	0	1	0	0
T170	404	0	0	0
T172	0	2	0	0
T178	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	33	0	0
T5	790	1	0	0
T6	480	0	0	0
T8	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T45	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T167	0	1	0	0
T170	404	0	0	0
T172	0	2	0	0
T178	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	33	0	0
T5	790	1	0	0
T6	480	0	0	0
T8	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T45	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T167	0	1	0	0
T170	404	0	0	0
T172	0	2	0	0
T178	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	160255	0	0
T5	790	12	0	0
T6	480	0	0	0
T8	0	80	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	17	0	0
T45	0	26	0	0
T48	0	289	0	0
T49	0	75	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T167	0	3	0	0
T170	404	0	0	0
T172	0	73	0	0
T178	0	113	0	0
T188	0	222	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	16	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T167	0	1	0	0
T170	404	0	0	0
T172	0	1	0	0
T211	0	1	0	0
T222	0	1	0	0
T238	0	1	0	0
T239	0	1	0	0
T240	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T2 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T5 T24 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T5 T24 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T5 T24 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T5 T24 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T5 T24 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T5 T24 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T5 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T5 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T5 T31 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T5 T31 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T5 T31 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T5 T31 
186        1/1                    state_d = IdleSt;
           Tests:       T105 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T105 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T5 T31 
191        1/1                      state_d = StableSt;
           Tests:       T2 T5 T31 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T5 T31 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T5 T31 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T5 T31 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T5 T31 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T31 T46 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T5 T31 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T24
1	0	Covered	T1,T4,T12
1	1	Covered	T2,T5,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T31
0	1	Covered	T105
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T31
0	1	Covered	T2,T46,T48
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T5,T31
1	-	Covered	T2,T46,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T5,T24
DetectSt	168	Covered	T2,T5,T31
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T5,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T5,T31
DebounceSt->IdleSt	163	Covered	T24
DetectSt->IdleSt	186	Covered	T105
DetectSt->StableSt	191	Covered	T2,T5,T31
IdleSt->DebounceSt	148	Covered	T2,T5,T24
StableSt->IdleSt	206	Covered	T2,T31,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T24
0	1	Covered	T2,T5,T24
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T31
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T5,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T5,T31
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T5,T24
DetectSt	-	-	-	-	1	-	-	Covered	T105
DetectSt	-	-	-	-	0	1	-	Covered	T2,T5,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T31,T46
StableSt	-	-	-	-	-	-	0	Covered	T2,T5,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	65	0	0
CntIncr_A	5947631	1649	0	0
CntNoWrap_A	5947631	5481175	0	0
DetectStDropOut_A	5947631	1	0	0
DetectedOut_A	5947631	2443	0	0
DetectedPulseOut_A	5947631	31	0	0
DisabledIdleSt_A	5947631	5078654	0	0
DisabledNoDetection_A	5947631	5080444	0	0
EnterDebounceSt_A	5947631	33	0	0
EnterDetectSt_A	5947631	32	0	0
EnterStableSt_A	5947631	31	0	0
PulseIsPulse_A	5947631	31	0	0
StayInStableSt	5947631	2392	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5947631	4932	0	0
gen_low_level_sva.LowLevelEvent_A	5947631	5483067	0	0
gen_not_sticky_sva.StableStDropOut_A	5947631	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	65	0	0
T2	681	2	0	0
T3	1327	0	0	0
T5	0	2	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	1	0	0
T31	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	4	0	0
T48	0	2	0	0
T51	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1649	0	0
T2	681	40	0	0
T3	1327	0	0	0
T5	0	35	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	24	0	0
T31	0	29	0	0
T43	0	45	0	0
T44	0	16	0	0
T45	0	65	0	0
T46	0	102	0	0
T48	0	51	0	0
T51	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481175	0	0
T1	483	82	0	0
T2	681	278	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1	0	0
T102	20624	0	0	0
T105	628	1	0	0
T114	16747	0	0	0
T222	1121	0	0	0
T241	942	0	0	0
T242	1121	0	0	0
T243	632	0	0	0
T244	932	0	0	0
T245	406	0	0	0
T246	492	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	2443	0	0
T2	681	9	0	0
T3	1327	0	0	0
T5	0	47	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	18	0	0
T43	0	197	0	0
T44	0	61	0	0
T45	0	185	0	0
T46	0	146	0	0
T48	0	42	0	0
T51	0	50	0	0
T169	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	31	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	1	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5078654	0	0
T1	483	82	0	0
T2	681	3	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5080444	0	0
T1	483	83	0	0
T2	681	3	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	33	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	1	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	1	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	32	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	1	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	31	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	1	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	31	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	1	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	2392	0	0
T2	681	8	0	0
T3	1327	0	0	0
T5	0	45	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	17	0	0
T43	0	195	0	0
T44	0	59	0	0
T45	0	183	0	0
T46	0	143	0	0
T48	0	41	0	0
T51	0	48	0	0
T169	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	4932	0	0
T1	483	1	0	0
T2	681	1	0	0
T4	420	1	0	0
T5	0	1	0	0
T12	527	3	0	0
T13	422	2	0	0
T14	452	1	0	0
T15	502	4	0	0
T16	716	0	0	0
T17	491	5	0	0
T18	1786	0	0	0
T29	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	10	0	0
T2	681	1	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T167	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T193	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T213	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T2 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T24 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T24 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T24 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T24 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T24 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T24 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T31 T47 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T31 T47 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T31 T47 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T50 T187 T105 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T31 T47 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T31 T47 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T31 T47 
186        1/1                    state_d = IdleSt;
           Tests:       T96 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T96 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T31 T47 
191        1/1                      state_d = StableSt;
           Tests:       T2 T31 T47 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T31 T47 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T31 T47 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T31 T47 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T31 T47 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T31 T47 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T31 T47 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T24,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T24,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T31,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T24,T31
1	0	Covered	T1,T4,T12
1	1	Covered	T2,T24,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T31,T47
0	1	Covered	T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T31,T47
0	1	Covered	T2,T47,T43
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T31,T47
1	-	Covered	T2,T47,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T24,T31
DetectSt	168	Covered	T2,T31,T47
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T31,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T31,T47
DebounceSt->IdleSt	163	Covered	T24,T50,T187
DetectSt->IdleSt	186	Covered	T96
DetectSt->StableSt	191	Covered	T2,T31,T47
IdleSt->DebounceSt	148	Covered	T2,T24,T31
StableSt->IdleSt	206	Covered	T2,T31,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T24,T31
0	1	Covered	T2,T24,T31
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T31,T47
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T24,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T31,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T187,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T24,T31
DetectSt	-	-	-	-	1	-	-	Covered	T96
DetectSt	-	-	-	-	0	1	-	Covered	T2,T31,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T31,T47
StableSt	-	-	-	-	-	-	0	Covered	T2,T31,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	86	0	0
CntIncr_A	5947631	54765	0	0
CntNoWrap_A	5947631	5481154	0	0
DetectStDropOut_A	5947631	1	0	0
DetectedOut_A	5947631	2527	0	0
DetectedPulseOut_A	5947631	39	0	0
DisabledIdleSt_A	5947631	5080178	0	0
DisabledNoDetection_A	5947631	5081969	0	0
EnterDebounceSt_A	5947631	47	0	0
EnterDetectSt_A	5947631	40	0	0
EnterStableSt_A	5947631	39	0	0
PulseIsPulse_A	5947631	39	0	0
StayInStableSt	5947631	2472	0	0
gen_high_level_sva.HighLevelEvent_A	5947631	5483067	0	0
gen_not_sticky_sva.StableStDropOut_A	5947631	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	86	0	0
T2	681	2	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	1	0	0
T31	0	2	0	0
T43	0	2	0	0
T47	0	4	0	0
T48	0	4	0	0
T50	0	5	0	0
T51	0	2	0	0
T95	0	4	0	0
T169	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	54765	0	0
T2	681	40	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	23	0	0
T31	0	29	0	0
T43	0	45	0	0
T47	0	62	0	0
T48	0	102	0	0
T50	0	81	0	0
T51	0	94	0	0
T95	0	42	0	0
T169	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481154	0	0
T1	483	82	0	0
T2	681	278	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1	0	0
T96	706	1	0	0
T191	1057	0	0	0
T247	611	0	0	0
T248	558	0	0	0
T249	9068	0	0	0
T250	629	0	0	0
T251	14344	0	0	0
T252	506	0	0	0
T253	493	0	0	0
T254	706	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	2527	0	0
T2	681	16	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	18	0	0
T43	0	42	0	0
T47	0	83	0	0
T48	0	71	0	0
T50	0	75	0	0
T51	0	43	0	0
T95	0	137	0	0
T167	0	2	0	0
T169	0	138	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	39	0	0
T2	681	1	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T95	0	2	0	0
T167	0	1	0	0
T169	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5080178	0	0
T1	483	82	0	0
T2	681	3	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5081969	0	0
T1	483	83	0	0
T2	681	3	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	47	0	0
T2	681	1	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	1	0	0
T31	0	1	0	0
T43	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T50	0	3	0	0
T51	0	1	0	0
T95	0	2	0	0
T169	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	40	0	0
T2	681	1	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T95	0	2	0	0
T167	0	1	0	0
T169	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	39	0	0
T2	681	1	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T95	0	2	0	0
T167	0	1	0	0
T169	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	39	0	0
T2	681	1	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T95	0	2	0	0
T167	0	1	0	0
T169	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	2472	0	0
T2	681	15	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	17	0	0
T43	0	41	0	0
T47	0	80	0	0
T48	0	68	0	0
T50	0	72	0	0
T51	0	42	0	0
T95	0	134	0	0
T167	0	1	0	0
T169	0	135	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	22	0	0
T2	681	1	0	0
T3	1327	0	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T95	0	1	0	0
T167	0	1	0	0
T169	0	1	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T2 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T5 T24 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T5 T24 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T5 T24 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T5 T24 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T5 T24 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T5 T24 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T5 T31 T43 
167        1/1                    if (trigger_active) begin
           Tests:       T5 T31 T43 
168        1/1                      state_d = DetectSt;
           Tests:       T5 T31 T43 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T5 T31 T43 
182        1/1                  cnt_en = 1'b1;
           Tests:       T5 T31 T43 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T5 T31 T43 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T5 T31 T43 
191        1/1                      state_d = StableSt;
           Tests:       T5 T31 T43 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T5 T31 T43 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T5 T31 T43 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T5 T31 T43 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T5 T31 T43 
206        1/1                    state_d = IdleSt;
           Tests:       T5 T31 T46 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T5 T31 T43 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T31,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T31
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T24,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T43
0	1	Covered	T5,T46,T45
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T31,T43
1	-	Covered	T5,T46,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T24,T31
DetectSt	168	Covered	T5,T31,T43
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T31,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T31,T43
DebounceSt->IdleSt	163	Covered	T24
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5,T31,T43
IdleSt->DebounceSt	148	Covered	T5,T24,T31
StableSt->IdleSt	206	Covered	T5,T31,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T24,T31
0	1	Covered	T5,T24,T31
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T31,T43
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T24,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T31,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T24,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T5,T31,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T31,T46
StableSt	-	-	-	-	-	-	0	Covered	T5,T31,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	57	0	0
CntIncr_A	5947631	54132	0	0
CntNoWrap_A	5947631	5481183	0	0
DetectStDropOut_A	5947631	0	0	0
DetectedOut_A	5947631	107921	0	0
DetectedPulseOut_A	5947631	28	0	0
DisabledIdleSt_A	5947631	5079241	0	0
DisabledNoDetection_A	5947631	5081033	0	0
EnterDebounceSt_A	5947631	29	0	0
EnterDetectSt_A	5947631	28	0	0
EnterStableSt_A	5947631	28	0	0
PulseIsPulse_A	5947631	28	0	0
StayInStableSt	5947631	107880	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5947631	4977	0	0
gen_low_level_sva.LowLevelEvent_A	5947631	5483067	0	0
gen_not_sticky_sva.StableStDropOut_A	5947631	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	57	0	0
T5	790	2	0	0
T6	480	0	0	0
T24	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T50	0	4	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	2	0	0
T167	0	4	0	0
T170	404	0	0	0
T172	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	54132	0	0
T5	790	35	0	0
T6	480	0	0	0
T24	0	22	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	29	0	0
T43	0	45	0	0
T45	0	65	0	0
T46	0	51	0	0
T50	0	54	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	85	0	0
T167	0	88	0	0
T170	404	0	0	0
T172	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481183	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	107921	0	0
T5	790	205	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	16	0	0
T43	0	108	0	0
T45	0	80	0	0
T46	0	127	0	0
T50	0	82	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	469	0	0
T167	0	129	0	0
T170	404	0	0	0
T172	0	157	0	0
T210	0	204	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	28	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T167	0	2	0	0
T170	404	0	0	0
T172	0	1	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5079241	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5081033	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	29	0	0
T5	790	1	0	0
T6	480	0	0	0
T24	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T167	0	2	0	0
T170	404	0	0	0
T172	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	28	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T167	0	2	0	0
T170	404	0	0	0
T172	0	1	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	28	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T167	0	2	0	0
T170	404	0	0	0
T172	0	1	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	28	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T167	0	2	0	0
T170	404	0	0	0
T172	0	1	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	107880	0	0
T5	790	204	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	15	0	0
T43	0	106	0	0
T45	0	79	0	0
T46	0	126	0	0
T50	0	80	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	467	0	0
T167	0	126	0	0
T170	404	0	0	0
T172	0	155	0	0
T210	0	202	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	4977	0	0
T1	483	1	0	0
T2	681	1	0	0
T4	420	3	0	0
T5	0	1	0	0
T12	527	4	0	0
T13	422	2	0	0
T14	452	1	0	0
T15	502	7	0	0
T16	716	0	0	0
T17	491	9	0	0
T18	1786	0	0	0
T29	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	14	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T167	0	1	0	0
T170	404	0	0	0
T173	0	2	0	0
T192	0	1	0	0
T193	0	1	0	0
T213	0	2	0	0
T240	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T2 T12 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T2 T12 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T5 T24 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T2 T12 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T2 T12 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T2 T12 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T2 T12 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T2 T12 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T2 T12 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T2 T12 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T2 T12 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T5 T24 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T5 T24 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T5 T24 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T5 T24 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T5 T24 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T5 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T5 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T5 T31 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T45 T94 T193 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T5 T31 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T5 T31 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T5 T31 
186        1/1                    state_d = IdleSt;
           Tests:       T97 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T97 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T5 T31 
191        1/1                      state_d = StableSt;
           Tests:       T2 T5 T31 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T5 T31 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T5 T31 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T5 T31 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T5 T31 
206        1/1                    state_d = IdleSt;
           Tests:       T5 T31 T46 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T5 T31 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T4,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T4,T2,T12
1	1	Covered	T4,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T24
1	0	Covered	T4,T12,T13
1	1	Covered	T2,T5,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T31
0	1	Covered	T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T31
0	1	Covered	T5,T46,T45
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T5,T31
1	-	Covered	T5,T46,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T5,T24
DetectSt	168	Covered	T2,T5,T31
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T5,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T5,T31
DebounceSt->IdleSt	163	Covered	T24,T45,T94
DetectSt->IdleSt	186	Covered	T97
DetectSt->StableSt	191	Covered	T2,T5,T31
IdleSt->DebounceSt	148	Covered	T2,T5,T24
StableSt->IdleSt	206	Covered	T5,T31,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T24
0	1	Covered	T2,T5,T24
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T31
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T5,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T5,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T94,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T5,T24
DetectSt	-	-	-	-	1	-	-	Covered	T97
DetectSt	-	-	-	-	0	1	-	Covered	T2,T5,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T31,T46
StableSt	-	-	-	-	-	-	0	Covered	T2,T5,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	94	0	0
CntIncr_A	5947631	107628	0	0
CntNoWrap_A	5947631	5481146	0	0
DetectStDropOut_A	5947631	1	0	0
DetectedOut_A	5947631	57742	0	0
DetectedPulseOut_A	5947631	44	0	0
DisabledIdleSt_A	5947631	5153017	0	0
DisabledNoDetection_A	5947631	5154812	0	0
EnterDebounceSt_A	5947631	49	0	0
EnterDetectSt_A	5947631	45	0	0
EnterStableSt_A	5947631	44	0	0
PulseIsPulse_A	5947631	44	0	0
StayInStableSt	5947631	57683	0	0
gen_high_level_sva.HighLevelEvent_A	5947631	5483067	0	0
gen_not_sticky_sva.StableStDropOut_A	5947631	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	94	0	0
T2	681	2	0	0
T3	1327	0	0	0
T5	0	4	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	1	0	0
T31	0	2	0	0
T45	0	3	0	0
T46	0	4	0	0
T48	0	4	0	0
T50	0	4	0	0
T51	0	2	0	0
T169	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	107628	0	0
T2	681	40	0	0
T3	1327	0	0	0
T5	0	70	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	23	0	0
T31	0	29	0	0
T45	0	130	0	0
T46	0	102	0	0
T48	0	102	0	0
T50	0	54	0	0
T51	0	94	0	0
T169	0	114	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481146	0	0
T1	483	82	0	0
T2	681	278	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1	0	0
T97	909	1	0	0
T255	495	0	0	0
T256	422	0	0	0
T257	404	0	0	0
T258	1935	0	0	0
T259	536	0	0	0
T260	46162	0	0	0
T261	543	0	0	0
T262	512	0	0	0
T263	740	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	57742	0	0
T2	681	232	0	0
T3	1327	0	0	0
T5	0	94	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	16	0	0
T45	0	259	0	0
T46	0	232	0	0
T48	0	291	0	0
T50	0	87	0	0
T51	0	44	0	0
T94	0	412	0	0
T169	0	71	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	44	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	2	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T94	0	1	0	0
T169	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5153017	0	0
T1	483	82	0	0
T2	681	3	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5154812	0	0
T1	483	83	0	0
T2	681	3	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	49	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	2	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	1	0	0
T31	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T169	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	45	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	2	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T94	0	1	0	0
T169	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	44	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	2	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T94	0	1	0	0
T169	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	44	0	0
T2	681	1	0	0
T3	1327	0	0	0
T5	0	2	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T94	0	1	0	0
T169	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	57683	0	0
T2	681	230	0	0
T3	1327	0	0	0
T5	0	92	0	0
T12	527	0	0	0
T13	422	0	0	0
T14	452	0	0	0
T15	502	0	0	0
T16	716	0	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T31	0	15	0	0
T45	0	258	0	0
T46	0	229	0	0
T48	0	288	0	0
T50	0	84	0	0
T51	0	43	0	0
T94	0	411	0	0
T169	0	67	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	28	0	0
T5	790	2	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T167	0	2	0	0
T169	0	2	0	0
T170	404	0	0	0
T171	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T2 T12 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T24 T31 T43 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T24 T31 T43 
149        1/1                    cnt_en = 1'b1;
           Tests:       T24 T31 T43 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T24 T31 T43 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T24 T31 T43 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T24 T31 T43 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T43 T44 
167        1/1                    if (trigger_active) begin
           Tests:       T31 T43 T44 
168        1/1                      state_d = DetectSt;
           Tests:       T31 T43 T44 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T31 T43 T44 
182        1/1                  cnt_en = 1'b1;
           Tests:       T31 T43 T44 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T31 T43 T44 
186        1/1                    state_d = IdleSt;
           Tests:       T168 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T168 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T31 T43 T44 
191        1/1                      state_d = StableSt;
           Tests:       T31 T43 T44 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T31 T43 T44 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T31 T43 T44 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T31 T43 T44 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T31 T43 T44 
206        1/1                    state_d = IdleSt;
           Tests:       T31 T43 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T31 T43 T44 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T12
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T31,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T31,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T31,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T24,T31
1	0	Covered	T4,T12,T13
1	1	Covered	T24,T31,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T43,T44
0	1	Covered	T168
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T43,T44
0	1	Covered	T43,T45,T48
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T43,T44
1	-	Covered	T43,T45,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T31,T43
DetectSt	168	Covered	T31,T43,T44
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T31,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T43,T44
DebounceSt->IdleSt	163	Covered	T24
DetectSt->IdleSt	186	Covered	T168
DetectSt->StableSt	191	Covered	T31,T43,T44
IdleSt->DebounceSt	148	Covered	T24,T31,T43
StableSt->IdleSt	206	Covered	T31,T43,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T31,T43
0	1	Covered	T24,T31,T43
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T43,T44
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T31,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T43,T44
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T31,T43
DetectSt	-	-	-	-	1	-	-	Covered	T168
DetectSt	-	-	-	-	0	1	-	Covered	T31,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T43,T45
StableSt	-	-	-	-	-	-	0	Covered	T31,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	67	0	0
CntIncr_A	5947631	106789	0	0
CntNoWrap_A	5947631	5481173	0	0
DetectStDropOut_A	5947631	1	0	0
DetectedOut_A	5947631	54370	0	0
DetectedPulseOut_A	5947631	32	0	0
DisabledIdleSt_A	5947631	5151522	0	0
DisabledNoDetection_A	5947631	5153308	0	0
EnterDebounceSt_A	5947631	34	0	0
EnterDetectSt_A	5947631	33	0	0
EnterStableSt_A	5947631	32	0	0
PulseIsPulse_A	5947631	32	0	0
StayInStableSt	5947631	54323	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5947631	5398	0	0
gen_low_level_sva.LowLevelEvent_A	5947631	5483067	0	0
gen_not_sticky_sva.StableStDropOut_A	5947631	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	67	0	0
T8	522	0	0	0
T9	492	0	0	0
T24	6838	1	0	0
T31	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	4	0	0
T48	0	2	0	0
T50	0	2	0	0
T54	751	0	0	0
T55	471	0	0	0
T64	897	0	0	0
T65	540	0	0	0
T84	559	0	0	0
T90	1161	0	0	0
T91	434	0	0	0
T94	0	2	0	0
T169	0	4	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	106789	0	0
T8	522	0	0	0
T9	492	0	0	0
T24	6838	23	0	0
T31	0	29	0	0
T43	0	45	0	0
T44	0	16	0	0
T45	0	130	0	0
T48	0	51	0	0
T50	0	27	0	0
T54	751	0	0	0
T55	471	0	0	0
T64	897	0	0	0
T65	540	0	0	0
T84	559	0	0	0
T90	1161	0	0	0
T91	434	0	0	0
T94	0	85	0	0
T169	0	76	0	0
T209	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481173	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1	0	0
T168	4480	1	0	0
T264	501	0	0	0
T265	452	0	0	0
T266	406	0	0	0
T267	505	0	0	0
T268	526	0	0	0
T269	627	0	0	0
T270	498	0	0	0
T271	422	0	0	0
T272	707	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	54370	0	0
T31	8213	17	0	0
T43	0	13	0	0
T44	0	118	0	0
T45	0	81	0	0
T47	645	0	0	0
T48	0	42	0	0
T50	0	98	0	0
T74	497	0	0	0
T85	1511	0	0	0
T86	521	0	0	0
T87	508	0	0	0
T94	0	186	0	0
T167	0	46	0	0
T169	0	148	0	0
T205	404	0	0	0
T206	432	0	0	0
T207	504	0	0	0
T208	437	0	0	0
T209	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	32	0	0
T31	8213	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	645	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T74	497	0	0	0
T85	1511	0	0	0
T86	521	0	0	0
T87	508	0	0	0
T94	0	1	0	0
T167	0	1	0	0
T169	0	2	0	0
T205	404	0	0	0
T206	432	0	0	0
T207	504	0	0	0
T208	437	0	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5151522	0	0
T1	483	82	0	0
T2	681	3	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5153308	0	0
T1	483	83	0	0
T2	681	3	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	34	0	0
T8	522	0	0	0
T9	492	0	0	0
T24	6838	1	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T54	751	0	0	0
T55	471	0	0	0
T64	897	0	0	0
T65	540	0	0	0
T84	559	0	0	0
T90	1161	0	0	0
T91	434	0	0	0
T94	0	1	0	0
T169	0	2	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	33	0	0
T31	8213	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	645	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T74	497	0	0	0
T85	1511	0	0	0
T86	521	0	0	0
T87	508	0	0	0
T94	0	1	0	0
T167	0	1	0	0
T169	0	2	0	0
T205	404	0	0	0
T206	432	0	0	0
T207	504	0	0	0
T208	437	0	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	32	0	0
T31	8213	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	645	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T74	497	0	0	0
T85	1511	0	0	0
T86	521	0	0	0
T87	508	0	0	0
T94	0	1	0	0
T167	0	1	0	0
T169	0	2	0	0
T205	404	0	0	0
T206	432	0	0	0
T207	504	0	0	0
T208	437	0	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	32	0	0
T31	8213	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	645	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T74	497	0	0	0
T85	1511	0	0	0
T86	521	0	0	0
T87	508	0	0	0
T94	0	1	0	0
T167	0	1	0	0
T169	0	2	0	0
T205	404	0	0	0
T206	432	0	0	0
T207	504	0	0	0
T208	437	0	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	54323	0	0
T31	8213	16	0	0
T43	0	12	0	0
T44	0	116	0	0
T45	0	78	0	0
T47	645	0	0	0
T48	0	41	0	0
T50	0	97	0	0
T74	497	0	0	0
T85	1511	0	0	0
T86	521	0	0	0
T87	508	0	0	0
T94	0	184	0	0
T167	0	44	0	0
T169	0	146	0	0
T205	404	0	0	0
T206	432	0	0	0
T207	504	0	0	0
T208	437	0	0	0
T209	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5398	0	0
T2	681	0	0	0
T3	0	7	0	0
T4	420	1	0	0
T5	0	2	0	0
T12	527	4	0	0
T13	422	2	0	0
T14	452	0	0	0
T15	502	2	0	0
T16	716	3	0	0
T17	491	8	0	0
T18	1786	12	0	0
T23	710	0	0	0
T25	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	16	0	0
T43	656	1	0	0
T44	641	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T60	703	0	0	0
T76	493	0	0	0
T169	0	2	0	0
T204	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T222	0	2	0	0
T223	0	1	0	0
T273	402	0	0	0
T274	522	0	0	0
T275	4405	0	0	0
T276	406	0	0	0
T277	426	0	0	0
T278	502	0	0	0