Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T1 T4 T2
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T4 T2
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T4 T2
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T4 T2
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T16 T3 T5
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T14
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T14
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T4 T2
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T4 T2
129 1/1 cnt_en = 1'b0;
Tests: T1 T4 T2
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T4 T2
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T4 T2
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T4 T2
139
140 1/1 unique case (state_q)
Tests: T1 T4 T2
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T4 T2
148 1/1 state_d = DebounceSt;
Tests: T16 T3 T5
149 1/1 cnt_en = 1'b1;
Tests: T16 T3 T5
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T16 T3 T5
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T16 T3 T5
163 1/1 state_d = IdleSt;
Tests: T24 T31
164 1/1 cnt_clr = 1'b1;
Tests: T24 T31
165 1/1 end else if (cnt_done) begin
Tests: T16 T3 T5
166 1/1 cnt_clr = 1'b1;
Tests: T16 T3 T5
167 1/1 if (trigger_active) begin
Tests: T16 T3 T5
168 1/1 state_d = DetectSt;
Tests: T16 T3 T5
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T66 T46 T51
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T16 T3 T5
182 1/1 cnt_en = 1'b1;
Tests: T16 T3 T5
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T16 T3 T5
186 1/1 state_d = IdleSt;
Tests: T49 T68 T94
187 1/1 cnt_clr = 1'b1;
Tests: T49 T68 T94
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T16 T3 T5
191 1/1 state_d = StableSt;
Tests: T16 T3 T5
192 1/1 cnt_clr = 1'b1;
Tests: T16 T3 T5
193 1/1 event_detected_o = 1'b1;
Tests: T16 T3 T5
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T16 T3 T5
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T16 T3 T5
206 1/1 state_d = IdleSt;
Tests: T16 T3 T5
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T16 T3 T5
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T4 T2
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T4 T2
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T4 T2
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T4 T2
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T3 T5
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T14
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T14
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T4 T2
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T4 T2
129 1/1 cnt_en = 1'b0;
Tests: T1 T4 T2
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T4 T2
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T4 T2
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T4 T2
139
140 1/1 unique case (state_q)
Tests: T1 T4 T2
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T4 T2
148 1/1 state_d = DebounceSt;
Tests: T2 T3 T5
149 1/1 cnt_en = 1'b1;
Tests: T2 T3 T5
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T3 T5
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T3 T5
163 1/1 state_d = IdleSt;
Tests: T24 T31
164 1/1 cnt_clr = 1'b1;
Tests: T24 T31
165 1/1 end else if (cnt_done) begin
Tests: T2 T3 T5
166 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T5
167 1/1 if (trigger_active) begin
Tests: T2 T3 T5
168 1/1 state_d = DetectSt;
Tests: T2 T3 T5
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T43 T45 T95
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T3 T5
182 1/1 cnt_en = 1'b1;
Tests: T2 T3 T5
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T3 T5
186 1/1 state_d = IdleSt;
Tests: T96 T97 T98
187 1/1 cnt_clr = 1'b1;
Tests: T96 T97 T98
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T3 T5
191 1/1 state_d = StableSt;
Tests: T2 T3 T5
192 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T5
193 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T5
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T3 T5
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T3 T5
206 1/1 state_d = IdleSt;
Tests: T2 T3 T5
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T5
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T2 T12
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T4 T2 T12
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T3 T24 T10
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T18 T3 T24
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T18 T3 T24
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T2 T12
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T2 T12
129 1/1 cnt_en = 1'b0;
Tests: T4 T2 T12
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T2 T12
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T2 T12
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T2 T12
139
140 1/1 unique case (state_q)
Tests: T4 T2 T12
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T2 T12
148 1/1 state_d = DebounceSt;
Tests: T3 T24 T10
149 1/1 cnt_en = 1'b1;
Tests: T3 T24 T10
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T3 T24 T10
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T3 T24 T10
163 1/1 state_d = IdleSt;
Tests: T24 T31
164 1/1 cnt_clr = 1'b1;
Tests: T24 T31
165 1/1 end else if (cnt_done) begin
Tests: T3 T24 T10
166 1/1 cnt_clr = 1'b1;
Tests: T3 T10 T11
167 1/1 if (trigger_active) begin
Tests: T3 T10 T11
168 1/1 state_d = DetectSt;
Tests: T3 T10 T11
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T68 T99 T100
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T3 T10 T11
182 1/1 cnt_en = 1'b1;
Tests: T3 T10 T11
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T3 T10 T11
186 1/1 state_d = IdleSt;
Tests: T101 T102 T103
187 1/1 cnt_clr = 1'b1;
Tests: T101 T102 T103
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T3 T10 T11
191 1/1 state_d = StableSt;
Tests: T3 T10 T11
192 1/1 cnt_clr = 1'b1;
Tests: T3 T10 T11
193 1/1 event_detected_o = 1'b1;
Tests: T3 T10 T11
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T3 T10 T11
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T3 T10 T11
206 1/1 state_d = IdleSt;
Tests: T3 T10 T11
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T3 T10 T11
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T24 T31 T32
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T24 T31 T32
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T14 T29 T30
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T14
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T14
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T14 T29 T30
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T14 T29 T30
129 1/1 cnt_en = 1'b0;
Tests: T14 T29 T30
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T14 T29 T30
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T14 T29 T30
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T14 T29 T30
139
140 1/1 unique case (state_q)
Tests: T14 T29 T30
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T14 T29 T30
148 1/1 state_d = DebounceSt;
Tests: T14 T29 T30
149 1/1 cnt_en = 1'b1;
Tests: T14 T29 T30
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T14 T29 T30
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T14 T29 T30
163 1/1 state_d = IdleSt;
Tests: T24 T31
164 1/1 cnt_clr = 1'b1;
Tests: T24 T31
165 1/1 end else if (cnt_done) begin
Tests: T14 T29 T30
166 1/1 cnt_clr = 1'b1;
Tests: T14 T29 T30
167 1/1 if (trigger_active) begin
Tests: T14 T29 T30
168 1/1 state_d = DetectSt;
Tests: T14 T29 T30
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T24 T31 T104
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T14 T29 T30
182 1/1 cnt_en = 1'b1;
Tests: T14 T29 T30
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T14 T29 T30
186 1/1 state_d = IdleSt;
Tests: T24 T31 T32
187 1/1 cnt_clr = 1'b1;
Tests: T24 T31 T32
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T14 T29 T30
191 1/1 state_d = StableSt;
Tests: T14 T29 T30
192 1/1 cnt_clr = 1'b1;
Tests: T14 T29 T30
193 1/1 event_detected_o = 1'b1;
Tests: T14 T29 T30
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T14 T29 T30
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T14 T29 T30
206 1/1 state_d = IdleSt;
Tests: T24 T31 T32
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T14 T29 T30
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T14 T29
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T4 T2
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T4 T2
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T4 T2
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T14 T29
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T14
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T14
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T4 T2
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T4 T2
129 1/1 cnt_en = 1'b0;
Tests: T1 T4 T2
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T4 T2
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T4 T2
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T4 T2
139
140 1/1 unique case (state_q)
Tests: T1 T4 T2
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T4 T2
148 1/1 state_d = DebounceSt;
Tests: T1 T14 T29
149 1/1 cnt_en = 1'b1;
Tests: T1 T14 T29
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T14 T29
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T14 T29
163 1/1 state_d = IdleSt;
Tests: T24 T31
164 1/1 cnt_clr = 1'b1;
Tests: T24 T31
165 1/1 end else if (cnt_done) begin
Tests: T1 T14 T29
166 1/1 cnt_clr = 1'b1;
Tests: T1 T14 T29
167 1/1 if (trigger_active) begin
Tests: T1 T14 T29
168 1/1 state_d = DetectSt;
Tests: T1 T6 T7
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T14 T29 T30
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T6 T7
182 1/1 cnt_en = 1'b1;
Tests: T1 T6 T7
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T6 T7
186 1/1 state_d = IdleSt;
Tests: T24 T31 T52
187 1/1 cnt_clr = 1'b1;
Tests: T24 T31 T52
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T6 T7
191 1/1 state_d = StableSt;
Tests: T1 T6 T7
192 1/1 cnt_clr = 1'b1;
Tests: T1 T6 T7
193 1/1 event_detected_o = 1'b1;
Tests: T1 T6 T7
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T6 T7
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T6 T7
206 1/1 state_d = IdleSt;
Tests: T1 T6 T7
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T6 T7
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T14,T29 |
| 1 | Covered | T1,T4,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T14,T29 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T14,T29 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T14,T29 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T6,T7 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T14,T29 |
| 1 | 0 | Covered | T81,T24,T64 |
| 1 | 1 | Covered | T1,T14,T29 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T6,T7 |
| 0 | 1 | Covered | T24,T52,T53 |
| 1 | 0 | Covered | T24,T31 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T6,T7 |
| 0 | 1 | Covered | T1,T6,T7 |
| 1 | 0 | Covered | T24,T31,T58 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T6,T7 |
| 1 | - | Covered | T1,T6,T7 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T4,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T2 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T16,T5,T24 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T16,T5,T24 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T16,T5,T54 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T5,T24 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T16,T5,T24 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T5,T54 |
| 0 | 1 | Covered | T49,T94,T105 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T5,T54 |
| 0 | 1 | Covered | T16,T5,T54 |
| 1 | 0 | Covered | T31 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T16,T5,T54 |
| 1 | - | Covered | T16,T5,T54 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T24,T31,T32 |
| 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T14,T29,T30 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T14,T29,T30 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T14,T29,T30 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T24,T31,T32 |
| 1 | 0 | Covered | T24,T31,T32 |
| 1 | 1 | Covered | T14,T29,T30 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T14,T29,T30 |
| 0 | 1 | Covered | T24,T31,T32 |
| 1 | 0 | Covered | T24,T31,T32 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T14,T29,T30 |
| 0 | 1 | Covered | T24,T31,T32 |
| 1 | 0 | Covered | T24,T31,T106 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T14,T29,T30 |
| 1 | - | Covered | T24,T31,T32 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T4,T2,T12 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T24,T10 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T24,T10 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T10,T11 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T24,T10 |
| 1 | 0 | Covered | T4,T2,T12 |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T10,T11 |
| 0 | 1 | Covered | T101,T102,T103 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T10,T11 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T10,T11 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T4,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T2 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T2,T5,T24 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T2,T5,T24 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T2,T5,T31 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T24 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T2,T5,T24 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T5,T31 |
| 0 | 1 | Covered | T96,T97 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T5,T31 |
| 0 | 1 | Covered | T2,T5,T44 |
| 1 | 0 | Covered | T31 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T2,T5,T31 |
| 1 | - | Covered | T2,T5,T44 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T4,T2,T12 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T2 |
| 1 | 0 | Covered | T4,T2,T12 |
| 1 | 1 | Covered | T4,T2,T12 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T24,T10 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T24,T10 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T10,T11 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T24,T10 |
| 1 | 0 | Covered | T4,T2,T12 |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T10,T11 |
| 0 | 1 | Covered | T98 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T10,T11 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T10,T11 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T2,T12 |
| 1 | Covered | T1,T4,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T2,T12 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T24,T10 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T24,T10 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T10,T11 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T24,T10 |
| 1 | 0 | Covered | T4,T12,T13 |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T10,T11 |
| 0 | 1 | Covered | T68,T107 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T10,T11 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T10,T11 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T16,T5,T24 |
| DetectSt |
168 |
Covered |
T16,T5,T54 |
| IdleSt |
163 |
Covered |
T1,T4,T2 |
| StableSt |
191 |
Covered |
T16,T5,T54 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T16,T5,T54 |
| DebounceSt->IdleSt |
163 |
Covered |
T24,T46,T45 |
| DetectSt->IdleSt |
186 |
Covered |
T24,T31,T49 |
| DetectSt->StableSt |
191 |
Covered |
T16,T5,T54 |
| IdleSt->DebounceSt |
148 |
Covered |
T16,T5,T24 |
| StableSt->IdleSt |
206 |
Covered |
T16,T5,T54 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T5,T24 |
| 0 |
1 |
Covered |
T16,T5,T24 |
| 0 |
0 |
Covered |
T1,T4,T2 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T5,T54 |
| 0 |
Covered |
T1,T4,T2 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T16,T5,T24 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T2 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T24,T31 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T16,T5,T54 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T46,T45,T51 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T16,T5,T24 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T24,T31,T49 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T16,T5,T54 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T6,T7 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T16,T5,T54 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T16,T5,T54 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T14,T3,T29 |
| 0 |
1 |
Covered |
T14,T3,T29 |
| 0 |
0 |
Covered |
T1,T4,T2 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T14,T3,T29 |
| 0 |
Covered |
T1,T4,T2 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T14,T3,T29 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T2,T12 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T24,T31 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T14,T3,T29 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T24,T31,T68 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T14,T3,T29 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T24,T31,T32 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T14,T3,T29 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T14,T29,T30 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T3,T24,T10 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T14,T3,T29 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
15670 |
0 |
0 |
| T1 |
483 |
2 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
2654 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
1580 |
0 |
0 |
0 |
| T6 |
0 |
2 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
2 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
904 |
3 |
0 |
0 |
| T15 |
1004 |
0 |
0 |
0 |
| T16 |
2148 |
4 |
0 |
0 |
| T17 |
1473 |
0 |
0 |
0 |
| T18 |
5358 |
0 |
0 |
0 |
| T23 |
1420 |
0 |
0 |
0 |
| T24 |
6838 |
25 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
3 |
0 |
0 |
| T30 |
0 |
3 |
0 |
0 |
| T31 |
0 |
26 |
0 |
0 |
| T32 |
0 |
12 |
0 |
0 |
| T54 |
0 |
2 |
0 |
0 |
| T55 |
0 |
3 |
0 |
0 |
| T56 |
0 |
4 |
0 |
0 |
| T57 |
0 |
2 |
0 |
0 |
| T58 |
0 |
50 |
0 |
0 |
| T59 |
0 |
4 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
808 |
0 |
0 |
0 |
| T63 |
1450 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T108 |
0 |
2 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
2026003 |
0 |
0 |
| T1 |
483 |
25 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
2654 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
1580 |
0 |
0 |
0 |
| T6 |
0 |
25 |
0 |
0 |
| T7 |
0 |
25 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
25 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
904 |
41 |
0 |
0 |
| T15 |
1004 |
0 |
0 |
0 |
| T16 |
2148 |
69 |
0 |
0 |
| T17 |
1473 |
0 |
0 |
0 |
| T18 |
5358 |
0 |
0 |
0 |
| T23 |
1420 |
0 |
0 |
0 |
| T24 |
6838 |
684 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
41 |
0 |
0 |
| T30 |
0 |
41 |
0 |
0 |
| T31 |
0 |
907 |
0 |
0 |
| T32 |
0 |
405 |
0 |
0 |
| T54 |
0 |
95 |
0 |
0 |
| T55 |
0 |
41 |
0 |
0 |
| T56 |
0 |
105 |
0 |
0 |
| T57 |
0 |
67 |
0 |
0 |
| T58 |
0 |
2226 |
0 |
0 |
| T59 |
0 |
58 |
0 |
0 |
| T60 |
0 |
62 |
0 |
0 |
| T61 |
0 |
17 |
0 |
0 |
| T62 |
808 |
0 |
0 |
0 |
| T63 |
1450 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
21 |
0 |
0 |
| T108 |
0 |
19 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
142496570 |
0 |
0 |
| T1 |
12558 |
2130 |
0 |
0 |
| T2 |
17706 |
7268 |
0 |
0 |
| T4 |
10920 |
494 |
0 |
0 |
| T12 |
13702 |
3276 |
0 |
0 |
| T13 |
10972 |
546 |
0 |
0 |
| T14 |
11752 |
1323 |
0 |
0 |
| T15 |
13052 |
2626 |
0 |
0 |
| T16 |
18616 |
8186 |
0 |
0 |
| T17 |
12766 |
2340 |
0 |
0 |
| T18 |
46436 |
36010 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
1865 |
0 |
0 |
| T8 |
1044 |
0 |
0 |
0 |
| T9 |
984 |
0 |
0 |
0 |
| T24 |
13676 |
2 |
0 |
0 |
| T31 |
0 |
1 |
0 |
0 |
| T32 |
0 |
4 |
0 |
0 |
| T41 |
0 |
4 |
0 |
0 |
| T52 |
14250 |
4 |
0 |
0 |
| T54 |
1502 |
0 |
0 |
0 |
| T55 |
942 |
0 |
0 |
0 |
| T58 |
0 |
22 |
0 |
0 |
| T64 |
1794 |
0 |
0 |
0 |
| T65 |
1080 |
0 |
0 |
0 |
| T84 |
1118 |
0 |
0 |
0 |
| T90 |
2322 |
0 |
0 |
0 |
| T91 |
868 |
0 |
0 |
0 |
| T104 |
0 |
5 |
0 |
0 |
| T106 |
19294 |
0 |
0 |
0 |
| T109 |
0 |
2 |
0 |
0 |
| T110 |
0 |
24 |
0 |
0 |
| T111 |
0 |
14 |
0 |
0 |
| T112 |
0 |
8 |
0 |
0 |
| T113 |
0 |
26 |
0 |
0 |
| T114 |
0 |
3 |
0 |
0 |
| T115 |
0 |
5 |
0 |
0 |
| T116 |
667 |
1 |
0 |
0 |
| T117 |
25836 |
1 |
0 |
0 |
| T118 |
0 |
7 |
0 |
0 |
| T119 |
0 |
13 |
0 |
0 |
| T120 |
0 |
3 |
0 |
0 |
| T121 |
0 |
3 |
0 |
0 |
| T122 |
0 |
2 |
0 |
0 |
| T123 |
425 |
0 |
0 |
0 |
| T124 |
1334 |
0 |
0 |
0 |
| T125 |
446 |
0 |
0 |
0 |
| T126 |
521 |
0 |
0 |
0 |
| T127 |
19239 |
0 |
0 |
0 |
| T128 |
603 |
0 |
0 |
0 |
| T129 |
951 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
2212759 |
0 |
0 |
| T1 |
483 |
4 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
2654 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
1580 |
0 |
0 |
0 |
| T6 |
0 |
3 |
0 |
0 |
| T7 |
0 |
3 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
3 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
904 |
26 |
0 |
0 |
| T15 |
1004 |
0 |
0 |
0 |
| T16 |
2148 |
16 |
0 |
0 |
| T17 |
1473 |
0 |
0 |
0 |
| T18 |
5358 |
0 |
0 |
0 |
| T23 |
1420 |
0 |
0 |
0 |
| T24 |
6838 |
445 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
46 |
0 |
0 |
| T31 |
0 |
569 |
0 |
0 |
| T37 |
0 |
840 |
0 |
0 |
| T53 |
0 |
63 |
0 |
0 |
| T54 |
0 |
13 |
0 |
0 |
| T56 |
0 |
21 |
0 |
0 |
| T57 |
0 |
5 |
0 |
0 |
| T59 |
0 |
21 |
0 |
0 |
| T60 |
0 |
8 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
808 |
0 |
0 |
0 |
| T63 |
1450 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
85 |
0 |
0 |
| T108 |
0 |
8 |
0 |
0 |
| T130 |
0 |
5 |
0 |
0 |
| T131 |
0 |
3 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
5095 |
0 |
0 |
| T1 |
483 |
1 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
2654 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
1580 |
0 |
0 |
0 |
| T6 |
0 |
1 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
904 |
1 |
0 |
0 |
| T15 |
1004 |
0 |
0 |
0 |
| T16 |
2148 |
2 |
0 |
0 |
| T17 |
1473 |
0 |
0 |
0 |
| T18 |
5358 |
0 |
0 |
0 |
| T23 |
1420 |
0 |
0 |
0 |
| T24 |
6838 |
6 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
1 |
0 |
0 |
| T31 |
0 |
7 |
0 |
0 |
| T37 |
0 |
16 |
0 |
0 |
| T53 |
0 |
1 |
0 |
0 |
| T54 |
0 |
1 |
0 |
0 |
| T56 |
0 |
2 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
808 |
0 |
0 |
0 |
| T63 |
1450 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
131376376 |
0 |
0 |
| T1 |
12558 |
2054 |
0 |
0 |
| T2 |
17706 |
5064 |
0 |
0 |
| T4 |
10920 |
494 |
0 |
0 |
| T12 |
13702 |
3276 |
0 |
0 |
| T13 |
10972 |
546 |
0 |
0 |
| T14 |
11752 |
1254 |
0 |
0 |
| T15 |
13052 |
2626 |
0 |
0 |
| T16 |
18616 |
8027 |
0 |
0 |
| T17 |
12766 |
2340 |
0 |
0 |
| T18 |
46436 |
36010 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
131420183 |
0 |
0 |
| T1 |
12558 |
2079 |
0 |
0 |
| T2 |
17706 |
5082 |
0 |
0 |
| T4 |
10920 |
520 |
0 |
0 |
| T12 |
13702 |
3302 |
0 |
0 |
| T13 |
10972 |
572 |
0 |
0 |
| T14 |
11752 |
1278 |
0 |
0 |
| T15 |
13052 |
2652 |
0 |
0 |
| T16 |
18616 |
8052 |
0 |
0 |
| T17 |
12766 |
2366 |
0 |
0 |
| T18 |
46436 |
36036 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
8094 |
0 |
0 |
| T1 |
483 |
1 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
2654 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
1580 |
0 |
0 |
0 |
| T6 |
0 |
1 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
904 |
2 |
0 |
0 |
| T15 |
1004 |
0 |
0 |
0 |
| T16 |
2148 |
2 |
0 |
0 |
| T17 |
1473 |
0 |
0 |
0 |
| T18 |
5358 |
0 |
0 |
0 |
| T23 |
1420 |
0 |
0 |
0 |
| T24 |
6838 |
15 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
2 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T31 |
0 |
15 |
0 |
0 |
| T32 |
0 |
6 |
0 |
0 |
| T54 |
0 |
1 |
0 |
0 |
| T55 |
0 |
2 |
0 |
0 |
| T56 |
0 |
2 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T58 |
0 |
25 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
808 |
0 |
0 |
0 |
| T63 |
1450 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
1 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
7586 |
0 |
0 |
| T1 |
483 |
1 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
2654 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
1580 |
0 |
0 |
0 |
| T6 |
0 |
1 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
904 |
1 |
0 |
0 |
| T15 |
1004 |
0 |
0 |
0 |
| T16 |
2148 |
2 |
0 |
0 |
| T17 |
1473 |
0 |
0 |
0 |
| T18 |
5358 |
0 |
0 |
0 |
| T23 |
1420 |
0 |
0 |
0 |
| T24 |
6838 |
10 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
1 |
0 |
0 |
| T31 |
0 |
11 |
0 |
0 |
| T37 |
0 |
16 |
0 |
0 |
| T52 |
0 |
1 |
0 |
0 |
| T54 |
0 |
1 |
0 |
0 |
| T56 |
0 |
2 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
808 |
0 |
0 |
0 |
| T63 |
1450 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
5095 |
0 |
0 |
| T1 |
483 |
1 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
2654 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
1580 |
0 |
0 |
0 |
| T6 |
0 |
1 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
904 |
1 |
0 |
0 |
| T15 |
1004 |
0 |
0 |
0 |
| T16 |
2148 |
2 |
0 |
0 |
| T17 |
1473 |
0 |
0 |
0 |
| T18 |
5358 |
0 |
0 |
0 |
| T23 |
1420 |
0 |
0 |
0 |
| T24 |
6838 |
6 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
1 |
0 |
0 |
| T31 |
0 |
7 |
0 |
0 |
| T37 |
0 |
16 |
0 |
0 |
| T53 |
0 |
1 |
0 |
0 |
| T54 |
0 |
1 |
0 |
0 |
| T56 |
0 |
2 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
808 |
0 |
0 |
0 |
| T63 |
1450 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
5095 |
0 |
0 |
| T1 |
483 |
1 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
2654 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
1580 |
0 |
0 |
0 |
| T6 |
0 |
1 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
904 |
1 |
0 |
0 |
| T15 |
1004 |
0 |
0 |
0 |
| T16 |
2148 |
2 |
0 |
0 |
| T17 |
1473 |
0 |
0 |
0 |
| T18 |
5358 |
0 |
0 |
0 |
| T23 |
1420 |
0 |
0 |
0 |
| T24 |
6838 |
6 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
1 |
0 |
0 |
| T31 |
0 |
7 |
0 |
0 |
| T37 |
0 |
16 |
0 |
0 |
| T53 |
0 |
1 |
0 |
0 |
| T54 |
0 |
1 |
0 |
0 |
| T56 |
0 |
2 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
808 |
0 |
0 |
0 |
| T63 |
1450 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
154638406 |
2206883 |
0 |
0 |
| T1 |
483 |
3 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
2654 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
1580 |
0 |
0 |
0 |
| T6 |
0 |
2 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
2 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
904 |
24 |
0 |
0 |
| T15 |
1004 |
0 |
0 |
0 |
| T16 |
2148 |
14 |
0 |
0 |
| T17 |
1473 |
0 |
0 |
0 |
| T18 |
5358 |
0 |
0 |
0 |
| T23 |
1420 |
0 |
0 |
0 |
| T24 |
6838 |
439 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
44 |
0 |
0 |
| T31 |
0 |
562 |
0 |
0 |
| T37 |
0 |
823 |
0 |
0 |
| T53 |
0 |
62 |
0 |
0 |
| T54 |
0 |
12 |
0 |
0 |
| T56 |
0 |
19 |
0 |
0 |
| T57 |
0 |
4 |
0 |
0 |
| T59 |
0 |
19 |
0 |
0 |
| T60 |
0 |
7 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
808 |
0 |
0 |
0 |
| T63 |
1450 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
82 |
0 |
0 |
| T108 |
0 |
7 |
0 |
0 |
| T130 |
0 |
4 |
0 |
0 |
| T131 |
0 |
2 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
53528679 |
39801 |
0 |
0 |
| T1 |
966 |
2 |
0 |
0 |
| T2 |
6129 |
4 |
0 |
0 |
| T3 |
0 |
28 |
0 |
0 |
| T4 |
3780 |
15 |
0 |
0 |
| T5 |
0 |
14 |
0 |
0 |
| T12 |
4743 |
38 |
0 |
0 |
| T13 |
3798 |
18 |
0 |
0 |
| T14 |
4068 |
3 |
0 |
0 |
| T15 |
4518 |
37 |
0 |
0 |
| T16 |
6444 |
9 |
0 |
0 |
| T17 |
4419 |
62 |
0 |
0 |
| T18 |
16074 |
48 |
0 |
0 |
| T23 |
4970 |
3 |
0 |
0 |
| T25 |
0 |
53 |
0 |
0 |
| T27 |
0 |
10 |
0 |
0 |
| T29 |
0 |
3 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T69 |
0 |
6 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
29738155 |
27415335 |
0 |
0 |
| T1 |
2415 |
415 |
0 |
0 |
| T2 |
3405 |
1405 |
0 |
0 |
| T4 |
2100 |
100 |
0 |
0 |
| T12 |
2635 |
635 |
0 |
0 |
| T13 |
2110 |
110 |
0 |
0 |
| T14 |
2260 |
260 |
0 |
0 |
| T15 |
2510 |
510 |
0 |
0 |
| T16 |
3580 |
1580 |
0 |
0 |
| T17 |
2455 |
455 |
0 |
0 |
| T18 |
8930 |
6930 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
101109727 |
93212139 |
0 |
0 |
| T1 |
8211 |
1411 |
0 |
0 |
| T2 |
11577 |
4777 |
0 |
0 |
| T4 |
7140 |
340 |
0 |
0 |
| T12 |
8959 |
2159 |
0 |
0 |
| T13 |
7174 |
374 |
0 |
0 |
| T14 |
7684 |
884 |
0 |
0 |
| T15 |
8534 |
1734 |
0 |
0 |
| T16 |
12172 |
5372 |
0 |
0 |
| T17 |
8347 |
1547 |
0 |
0 |
| T18 |
30362 |
23562 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
53528679 |
49347603 |
0 |
0 |
| T1 |
4347 |
747 |
0 |
0 |
| T2 |
6129 |
2529 |
0 |
0 |
| T4 |
3780 |
180 |
0 |
0 |
| T12 |
4743 |
1143 |
0 |
0 |
| T13 |
3798 |
198 |
0 |
0 |
| T14 |
4068 |
468 |
0 |
0 |
| T15 |
4518 |
918 |
0 |
0 |
| T16 |
6444 |
2844 |
0 |
0 |
| T17 |
4419 |
819 |
0 |
0 |
| T18 |
16074 |
12474 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
136795513 |
4141 |
0 |
0 |
| T1 |
483 |
1 |
0 |
0 |
| T2 |
681 |
0 |
0 |
0 |
| T3 |
1327 |
0 |
0 |
0 |
| T4 |
420 |
0 |
0 |
0 |
| T5 |
790 |
0 |
0 |
0 |
| T6 |
0 |
1 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
522 |
0 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T12 |
527 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
452 |
0 |
0 |
0 |
| T15 |
502 |
0 |
0 |
0 |
| T16 |
1432 |
2 |
0 |
0 |
| T17 |
982 |
0 |
0 |
0 |
| T18 |
3572 |
0 |
0 |
0 |
| T23 |
710 |
0 |
0 |
0 |
| T24 |
6838 |
6 |
0 |
0 |
| T25 |
496 |
0 |
0 |
0 |
| T29 |
471 |
0 |
0 |
0 |
| T31 |
0 |
4 |
0 |
0 |
| T37 |
0 |
15 |
0 |
0 |
| T38 |
0 |
8 |
0 |
0 |
| T53 |
0 |
1 |
0 |
0 |
| T54 |
0 |
1 |
0 |
0 |
| T56 |
0 |
2 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
404 |
0 |
0 |
0 |
| T63 |
725 |
0 |
0 |
0 |
| T64 |
897 |
0 |
0 |
0 |
| T65 |
540 |
0 |
0 |
0 |
| T87 |
0 |
1 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
| T132 |
0 |
2 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
17842893 |
2098916 |
0 |
0 |
| T3 |
3981 |
449 |
0 |
0 |
| T5 |
2370 |
0 |
0 |
0 |
| T6 |
1440 |
0 |
0 |
0 |
| T10 |
0 |
508 |
0 |
0 |
| T11 |
0 |
553 |
0 |
0 |
| T25 |
1488 |
0 |
0 |
0 |
| T27 |
1569 |
0 |
0 |
0 |
| T29 |
1413 |
0 |
0 |
0 |
| T62 |
1212 |
0 |
0 |
0 |
| T63 |
2175 |
0 |
0 |
0 |
| T66 |
0 |
329 |
0 |
0 |
| T67 |
0 |
1054 |
0 |
0 |
| T68 |
0 |
26 |
0 |
0 |
| T69 |
1269 |
0 |
0 |
0 |
| T70 |
1287 |
0 |
0 |
0 |
| T92 |
0 |
598 |
0 |
0 |
| T93 |
0 |
259 |
0 |
0 |
| T99 |
0 |
731 |
0 |
0 |
| T100 |
0 |
258 |
0 |
0 |
| T107 |
0 |
99 |
0 |
0 |
| T133 |
0 |
437 |
0 |
0 |
| T134 |
0 |
359 |
0 |
0 |
| T135 |
0 |
300 |
0 |
0 |
| T136 |
0 |
90 |
0 |
0 |
