Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_combo
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 92.31

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_combo 100.00 100.00 100.00



Module Instance : tb.dut.u_sysrst_ctrl_combo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.68 100.00 98.40 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_combo_trigger[0].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[1].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect 99.09 100.00 95.45 100.00 100.00 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[2].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[3].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect 99.09 100.00 95.45 100.00 100.00 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : sysrst_ctrl_combo
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15511100.00

42 logic [NumInputs-1:0] in; 43 1/1 assign in = { Tests: T4 T5 T6  44 pwrb_int_i, 45 key0_int_i, 46 key1_int_i, 47 key2_int_i, 48 ac_present_int_i 49 }; 50 51 for (genvar k = 0; k < NumCombo; k++) begin : gen_combo_trigger 52 // Generate the pre-condition 53 logic [NumInputs-1:0] cfg_in_pre; 54 4/4 assign cfg_in_pre = { Tests: T6 T31 T10  | T32 T33 T34  | T32 T33 T34  | T32 T33 T34  55 com_pre_sel_ctl_i[k].pwrb_in_sel.q, 56 com_pre_sel_ctl_i[k].key0_in_sel.q, 57 com_pre_sel_ctl_i[k].key1_in_sel.q, 58 com_pre_sel_ctl_i[k].key2_in_sel.q, 59 com_pre_sel_ctl_i[k].ac_present_sel.q 60 }; 61 62 // Combo pre-condition is enabled if any of the keys is selected for this 63 // pre-condition. Note that if no key is selected for this pre-condition, 64 // the precondition is automatically valid - see cfg_combo_en below. 65 logic cfg_combo_pre_en; 66 4/4 assign cfg_combo_pre_en = |cfg_in_pre; Tests: T6 T31 T10  | T32 T33 T34  | T32 T33 T34  | T32 T33 T34  67 68 // Config trigger is asserted if all configured keys are pressed (== 0) 69 logic precond; 70 4/4 assign precond = (in & cfg_in_pre) == '0; Tests: T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  71 72 logic precond_valid; 73 sysrst_ctrl_detect #( 74 .DebounceTimerWidth(TimerWidth), 75 .DetectTimerWidth(DetTimerWidth), 76 // This detects a high level. 77 .EventType(HighLevel), 78 .Sticky(0) 79 ) u_sysrst_ctrl_detect_pre ( 80 .clk_i, 81 .rst_ni, 82 .trigger_i (precond), 83 .cfg_debounce_timer_i (key_intr_debounce_ctl_i.q), 84 .cfg_detect_timer_i (com_pre_det_ctl_i[k].q), 85 .cfg_enable_i (cfg_combo_pre_en), 86 .event_detected_o (precond_valid), 87 .event_detected_pulse_o() 88 ); 89 90 // Generate the trigger for each combo 91 logic [NumInputs-1:0] cfg_in_sel; 92 4/4 assign cfg_in_sel = { Tests: T6 T1 T19  | T32 T33 T34  | T32 T33 T34  | T32 T33 T34  93 com_sel_ctl_i[k].pwrb_in_sel.q, 94 com_sel_ctl_i[k].key0_in_sel.q, 95 com_sel_ctl_i[k].key1_in_sel.q, 96 com_sel_ctl_i[k].key2_in_sel.q, 97 com_sel_ctl_i[k].ac_present_sel.q 98 }; 99 100 // Combo detection is enabled if 101 // - the pre-condition is valid and at least one of the keys is selected 102 // for this combo. 103 // - the pre-condition is disabled and at least one of the keys is 104 // selected for this combo. 105 logic cfg_combo_en; 106 4/4 assign cfg_combo_en = (|cfg_in_sel) && (precond_valid && cfg_combo_pre_en || Tests: T6 T1 T19  | T32 T33 T34  | T32 T33 T34  | T32 T33 T34  107 !cfg_combo_pre_en); 108 109 // Config trigger is asserted if all configured keys are pressed (== 0) 110 logic trigger; 111 4/4 assign trigger = (in & cfg_in_sel) == '0; Tests: T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  112 113 logic combo_det_pulse; 114 sysrst_ctrl_detect #( 115 .DebounceTimerWidth(TimerWidth), 116 .DetectTimerWidth(DetTimerWidth), 117 // This detects a positive edge 118 .EventType(EdgeToHigh), 119 .Sticky(0) 120 ) u_sysrst_ctrl_detect ( 121 .clk_i, 122 .rst_ni, 123 .trigger_i (trigger), 124 .cfg_debounce_timer_i (key_intr_debounce_ctl_i.q), 125 .cfg_detect_timer_i (com_det_ctl_i[k].q), 126 .cfg_enable_i (cfg_combo_en), 127 .event_detected_o (), 128 .event_detected_pulse_o(combo_det_pulse) 129 ); 130 131 //Instantiate the combo action module 132 sysrst_ctrl_comboact u_combo_act ( 133 .clk_i, 134 .rst_ni, 135 .cfg_intr_en_i(com_out_ctl_i[k].interrupt.q), 136 .cfg_bat_disable_en_i(com_out_ctl_i[k].bat_disable.q), 137 .cfg_ec_rst_en_i(com_out_ctl_i[k].ec_rst.q), 138 .cfg_rst_req_en_i(com_out_ctl_i[k].rst_req.q), 139 .combo_det_pulse_i(combo_det_pulse), 140 .ec_rst_l_i(ec_rst_l_int_i), 141 .ec_rst_ctl_i(ec_rst_ctl_i), 142 .combo_intr_pulse_o(combo_intr_o[k]), 143 .bat_disable_o(combo_bat_disable[k]), 144 .rst_req_o(combo_rst_req[k]), 145 .ec_rst_l_o(combo_ec_rst_l[k]) 146 ); 147 end 148 149 // bat_disable 150 // If any combo triggers bat_disable, assert the signal 151 1/1 assign bat_disable_hw_o = |(combo_bat_disable); Tests: T41 T59 T43  152 153 // If any combo triggers OT or EC RST(active low), assert the signal 154 1/1 assign rst_req_o = |(combo_rst_req); Tests: T35 T60 T41  155 1/1 assign ec_rst_l_hw_o = &(combo_ec_rst_l); Tests: T6 T1 T16 

Cond Coverage for Module : sysrst_ctrl_combo
TotalCoveredPercent
Conditions524892.31
Logical524892.31
Non-Logical00
Event00

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[0].cfg_in_sel)) && 
      2  ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T31,T10
11CoveredT6,T1,T19

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT6,T31,T10
01CoveredT4,T5,T6
10CoveredT6,T31,T10

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT6,T31,T10
10Not Covered
11CoveredT6,T31,T10

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[1].cfg_in_sel)) && 
      2  ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T33,T34
11CoveredT60,T41,T59

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT32,T33,T34
01CoveredT4,T5,T6
10CoveredT49,T61,T62

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT32,T33,T34
10Not Covered
11CoveredT49,T61,T62

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[2].cfg_in_sel)) && 
      2  ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T33,T34
11CoveredT35,T60,T41

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT32,T33,T34
01CoveredT4,T5,T6
10CoveredT49,T62,T63

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT32,T33,T34
10Not Covered
11CoveredT49,T62,T63

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[3].cfg_in_sel)) && 
      2  ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T33,T34
11CoveredT35,T60,T41

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT32,T33,T34
01CoveredT4,T5,T6
10CoveredT49,T62,T43

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT32,T33,T34
10Not Covered
11CoveredT49,T62,T43

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT6,T1,T19
1CoveredT4,T5,T6

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15511100.00

42 logic [NumInputs-1:0] in; 43 1/1 assign in = { Tests: T4 T5 T6  44 pwrb_int_i, 45 key0_int_i, 46 key1_int_i, 47 key2_int_i, 48 ac_present_int_i 49 }; 50 51 for (genvar k = 0; k < NumCombo; k++) begin : gen_combo_trigger 52 // Generate the pre-condition 53 logic [NumInputs-1:0] cfg_in_pre; 54 4/4 assign cfg_in_pre = { Tests: T6 T31 T10  | T32 T33 T34  | T32 T33 T34  | T32 T33 T34  55 com_pre_sel_ctl_i[k].pwrb_in_sel.q, 56 com_pre_sel_ctl_i[k].key0_in_sel.q, 57 com_pre_sel_ctl_i[k].key1_in_sel.q, 58 com_pre_sel_ctl_i[k].key2_in_sel.q, 59 com_pre_sel_ctl_i[k].ac_present_sel.q 60 }; 61 62 // Combo pre-condition is enabled if any of the keys is selected for this 63 // pre-condition. Note that if no key is selected for this pre-condition, 64 // the precondition is automatically valid - see cfg_combo_en below. 65 logic cfg_combo_pre_en; 66 4/4 assign cfg_combo_pre_en = |cfg_in_pre; Tests: T6 T31 T10  | T32 T33 T34  | T32 T33 T34  | T32 T33 T34  67 68 // Config trigger is asserted if all configured keys are pressed (== 0) 69 logic precond; 70 4/4 assign precond = (in & cfg_in_pre) == '0; Tests: T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  71 72 logic precond_valid; 73 sysrst_ctrl_detect #( 74 .DebounceTimerWidth(TimerWidth), 75 .DetectTimerWidth(DetTimerWidth), 76 // This detects a high level. 77 .EventType(HighLevel), 78 .Sticky(0) 79 ) u_sysrst_ctrl_detect_pre ( 80 .clk_i, 81 .rst_ni, 82 .trigger_i (precond), 83 .cfg_debounce_timer_i (key_intr_debounce_ctl_i.q), 84 .cfg_detect_timer_i (com_pre_det_ctl_i[k].q), 85 .cfg_enable_i (cfg_combo_pre_en), 86 .event_detected_o (precond_valid), 87 .event_detected_pulse_o() 88 ); 89 90 // Generate the trigger for each combo 91 logic [NumInputs-1:0] cfg_in_sel; 92 4/4 assign cfg_in_sel = { Tests: T6 T1 T19  | T32 T33 T34  | T32 T33 T34  | T32 T33 T34  93 com_sel_ctl_i[k].pwrb_in_sel.q, 94 com_sel_ctl_i[k].key0_in_sel.q, 95 com_sel_ctl_i[k].key1_in_sel.q, 96 com_sel_ctl_i[k].key2_in_sel.q, 97 com_sel_ctl_i[k].ac_present_sel.q 98 }; 99 100 // Combo detection is enabled if 101 // - the pre-condition is valid and at least one of the keys is selected 102 // for this combo. 103 // - the pre-condition is disabled and at least one of the keys is 104 // selected for this combo. 105 logic cfg_combo_en; 106 4/4 assign cfg_combo_en = (|cfg_in_sel) && (precond_valid && cfg_combo_pre_en || Tests: T6 T1 T19  | T32 T33 T34  | T32 T33 T34  | T32 T33 T34  107 !cfg_combo_pre_en); 108 109 // Config trigger is asserted if all configured keys are pressed (== 0) 110 logic trigger; 111 4/4 assign trigger = (in & cfg_in_sel) == '0; Tests: T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  112 113 logic combo_det_pulse; 114 sysrst_ctrl_detect #( 115 .DebounceTimerWidth(TimerWidth), 116 .DetectTimerWidth(DetTimerWidth), 117 // This detects a positive edge 118 .EventType(EdgeToHigh), 119 .Sticky(0) 120 ) u_sysrst_ctrl_detect ( 121 .clk_i, 122 .rst_ni, 123 .trigger_i (trigger), 124 .cfg_debounce_timer_i (key_intr_debounce_ctl_i.q), 125 .cfg_detect_timer_i (com_det_ctl_i[k].q), 126 .cfg_enable_i (cfg_combo_en), 127 .event_detected_o (), 128 .event_detected_pulse_o(combo_det_pulse) 129 ); 130 131 //Instantiate the combo action module 132 sysrst_ctrl_comboact u_combo_act ( 133 .clk_i, 134 .rst_ni, 135 .cfg_intr_en_i(com_out_ctl_i[k].interrupt.q), 136 .cfg_bat_disable_en_i(com_out_ctl_i[k].bat_disable.q), 137 .cfg_ec_rst_en_i(com_out_ctl_i[k].ec_rst.q), 138 .cfg_rst_req_en_i(com_out_ctl_i[k].rst_req.q), 139 .combo_det_pulse_i(combo_det_pulse), 140 .ec_rst_l_i(ec_rst_l_int_i), 141 .ec_rst_ctl_i(ec_rst_ctl_i), 142 .combo_intr_pulse_o(combo_intr_o[k]), 143 .bat_disable_o(combo_bat_disable[k]), 144 .rst_req_o(combo_rst_req[k]), 145 .ec_rst_l_o(combo_ec_rst_l[k]) 146 ); 147 end 148 149 // bat_disable 150 // If any combo triggers bat_disable, assert the signal 151 1/1 assign bat_disable_hw_o = |(combo_bat_disable); Tests: T41 T59 T43  152 153 // If any combo triggers OT or EC RST(active low), assert the signal 154 1/1 assign rst_req_o = |(combo_rst_req); Tests: T35 T60 T41  155 1/1 assign ec_rst_l_hw_o = &(combo_ec_rst_l); Tests: T6 T1 T16 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo
TotalCoveredPercent
Conditions4848100.00
Logical4848100.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[0].cfg_in_sel)) && 
      2  ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T31,T10
11CoveredT6,T1,T19

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT6,T31,T10
01CoveredT4,T5,T6
10CoveredT6,T31,T10

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTestsExclude Annotation
01CoveredT6,T31,T10
10Excluded vcs_gen_start:k=0:vcs_gen_end:VC_COV_UNR
11CoveredT6,T31,T10

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[1].cfg_in_sel)) && 
      2  ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T33,T34
11CoveredT60,T41,T59

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT32,T33,T34
01CoveredT4,T5,T6
10CoveredT49,T61,T62

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTestsExclude Annotation
01CoveredT32,T33,T34
10Excluded vcs_gen_start:k=1:vcs_gen_end:VC_COV_UNR
11CoveredT49,T61,T62

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[2].cfg_in_sel)) && 
      2  ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T33,T34
11CoveredT35,T60,T41

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT32,T33,T34
01CoveredT4,T5,T6
10CoveredT49,T62,T63

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTestsExclude Annotation
01CoveredT32,T33,T34
10Excluded vcs_gen_start:k=2:vcs_gen_end:VC_COV_UNR
11CoveredT49,T62,T63

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[3].cfg_in_sel)) && 
      2  ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T33,T34
11CoveredT35,T60,T41

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT32,T33,T34
01CoveredT4,T5,T6
10CoveredT49,T62,T43

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTestsExclude Annotation
01CoveredT32,T33,T34
10Excluded vcs_gen_start:k=3:vcs_gen_end:VC_COV_UNR
11CoveredT49,T62,T43

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT6,T1,T19
1CoveredT4,T5,T6

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT4,T5,T6