Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T32 T33 T34 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T31 T10 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T6 T31 T10 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T6 T31 T10 
129        1/1              cnt_en = 1'b0;
           Tests:       T6 T31 T10 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T6 T31 T10 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T6 T31 T10 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T6 T31 T10 
139                     
140        1/1              unique case (state_q)
           Tests:       T6 T31 T10 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T6 T31 T10 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T31 T10 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T31 T10 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T31 T10 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T31 T10 
163        1/1                    state_d = IdleSt;
           Tests:       T49 T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T31 T10 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T31 T10 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T31 T10 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T31 T10 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T49 T62 T110 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T31 T10 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T31 T10 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T31 T10 
186        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T34 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T31 T10 
191        1/1                      state_d = StableSt;
           Tests:       T6 T31 T10 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T31 T10 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T31 T10 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T31 T10 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T31 T10 
206        1/1                    state_d = IdleSt;
           Tests:       T49 T61 T62 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T31 T10 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T31,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T31,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T31,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T49,T61,T62
1	1	Covered	T6,T31,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T31,T10
0	1	Covered	T32,T33,T34
1	0	Covered	T49,T62,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T31,T10
0	1	Covered	T49,T61,T62
1	0	Covered	T239

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T31,T10
1	-	Covered	T49,T61,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T31,T10
DetectSt	168	Covered	T6,T31,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T31,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T31,T10
DebounceSt->IdleSt	163	Covered	T49,T62,T110
DetectSt->IdleSt	186	Covered	T32,T33,T34
DetectSt->StableSt	191	Covered	T6,T31,T10
IdleSt->DebounceSt	148	Covered	T6,T31,T10
StableSt->IdleSt	206	Covered	T49,T61,T62

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T31,T10
0	1	Covered	T6,T31,T10
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T31,T10
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T31,T10
IdleSt	0	-	-	-	-	-	-	Covered	T32,T33,T34
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T62
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T31,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T62,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T31,T10
DetectSt	-	-	-	-	1	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	0	1	-	Covered	T6,T31,T10
DetectSt	-	-	-	-	0	0	-	Covered	T6,T31,T10
StableSt	-	-	-	-	-	-	1	Covered	T49,T61,T62
StableSt	-	-	-	-	-	-	0	Covered	T6,T31,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	2895	0	0
CntIncr_A	6803201	99850	0	0
CntNoWrap_A	6803201	6335191	0	0
DetectStDropOut_A	6803201	313	0	0
DetectedOut_A	6803201	72116	0	0
DetectedPulseOut_A	6803201	960	0	0
DisabledIdleSt_A	6803201	5876716	0	0
DisabledNoDetection_A	6803201	5878475	0	0
EnterDebounceSt_A	6803201	1465	0	0
EnterDetectSt_A	6803201	1430	0	0
EnterStableSt_A	6803201	960	0	0
PulseIsPulse_A	6803201	960	0	0
StayInStableSt	6803201	71059	0	0
gen_high_event_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	862	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	2895	0	0
T1	486	0	0	0
T6	460	2	0	0
T10	0	2	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	2	0	0
T32	0	12	0	0
T33	0	30	0	0
T34	0	54	0	0
T40	0	2	0	0
T49	0	16	0	0
T66	0	2	0	0
T97	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	99850	0	0
T1	486	0	0	0
T6	460	21	0	0
T10	0	21	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	21	0	0
T32	0	313	0	0
T33	0	790	0	0
T34	0	1670	0	0
T40	0	21	0	0
T49	0	659	0	0
T66	0	21	0	0
T97	0	1402	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6335191	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	57	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	313	0	0
T32	5271	6	0	0
T33	0	15	0	0
T34	0	27	0	0
T44	0	9	0	0
T49	0	1	0	0
T62	0	1	0	0
T77	496	0	0	0
T97	0	26	0	0
T98	0	6	0	0
T99	0	13	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0
T119	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	72116	0	0
T1	486	0	0	0
T6	460	34	0	0
T10	0	81	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	37	0	0
T40	0	106	0	0
T43	0	827	0	0
T49	0	379	0	0
T61	0	779	0	0
T62	0	430	0	0
T63	0	888	0	0
T66	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	960	0	0
T1	486	0	0	0
T6	460	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	1	0	0
T40	0	1	0	0
T43	0	13	0	0
T49	0	5	0	0
T61	0	29	0	0
T62	0	5	0	0
T63	0	6	0	0
T66	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5876716	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	4	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5878475	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	4	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1465	0	0
T1	486	0	0	0
T6	460	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	1	0	0
T32	0	6	0	0
T33	0	15	0	0
T34	0	27	0	0
T40	0	1	0	0
T49	0	9	0	0
T66	0	1	0	0
T97	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1430	0	0
T1	486	0	0	0
T6	460	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	1	0	0
T32	0	6	0	0
T33	0	15	0	0
T34	0	27	0	0
T40	0	1	0	0
T49	0	7	0	0
T66	0	1	0	0
T97	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	960	0	0
T1	486	0	0	0
T6	460	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	1	0	0
T40	0	1	0	0
T43	0	13	0	0
T49	0	5	0	0
T61	0	29	0	0
T62	0	5	0	0
T63	0	6	0	0
T66	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	960	0	0
T1	486	0	0	0
T6	460	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	1	0	0
T40	0	1	0	0
T43	0	13	0	0
T49	0	5	0	0
T61	0	29	0	0
T62	0	5	0	0
T63	0	6	0	0
T66	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	71059	0	0
T1	486	0	0	0
T6	460	32	0	0
T10	0	79	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	35	0	0
T40	0	104	0	0
T43	0	814	0	0
T49	0	374	0	0
T61	0	749	0	0
T62	0	425	0	0
T63	0	881	0	0
T66	0	49	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	862	0	0
T42	10852	0	0	0
T43	0	13	0	0
T47	0	12	0	0
T49	7896	5	0	0
T54	759	0	0	0
T61	0	28	0	0
T62	0	5	0	0
T63	0	5	0	0
T110	0	10	0	0
T112	0	16	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	14	0	0
T241	0	11	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T6 T1 T19 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T1 T19 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T1 T19 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T1 T19 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T1 T19 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T1 T19 
163        1/1                    state_d = IdleSt;
           Tests:       T49 T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T1 T19 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T1 T19 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T1 T19 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T10 T40 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T6 T19 T64 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T10 T40 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T10 T40 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T10 T40 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T49 T62 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T49 T62 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T10 T40 
191        1/1                      state_d = StableSt;
           Tests:       T1 T10 T40 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T10 T40 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T10 T40 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T10 T40 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T10 T40 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T10 T40 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T10 T40 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T19

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T19
1	0	Covered	T7,T64,T111
1	1	Covered	T6,T1,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T40
0	1	Covered	T35,T49,T45
1	0	Covered	T49,T62

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T40
0	1	Covered	T1,T10,T40
1	0	Covered	T62

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T40
1	-	Covered	T1,T10,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T1,T19
DetectSt	168	Covered	T1,T10,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T10,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T40
DebounceSt->IdleSt	163	Covered	T6,T19,T64
DetectSt->IdleSt	186	Covered	T140,T35,T49
DetectSt->StableSt	191	Covered	T1,T10,T40
IdleSt->DebounceSt	148	Covered	T6,T1,T19
StableSt->IdleSt	206	Covered	T1,T10,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T1,T19
0	1	Covered	T6,T1,T19
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T40
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T1,T19
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T62
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T19,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T1,T19
DetectSt	-	-	-	-	1	-	-	Covered	T35,T49,T62
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T40
DetectSt	-	-	-	-	0	0	-	Covered	T1,T10,T40
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	869	0	0
CntIncr_A	6803201	45787	0	0
CntNoWrap_A	6803201	6337217	0	0
DetectStDropOut_A	6803201	27	0	0
DetectedOut_A	6803201	16772	0	0
DetectedPulseOut_A	6803201	378	0	0
DisabledIdleSt_A	6803201	6005982	0	0
DisabledNoDetection_A	6803201	6007229	0	0
EnterDebounceSt_A	6803201	461	0	0
EnterDetectSt_A	6803201	409	0	0
EnterStableSt_A	6803201	378	0	0
PulseIsPulse_A	6803201	378	0	0
StayInStableSt	6803201	16370	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	351	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	869	0	0
T1	486	2	0	0
T6	460	1	0	0
T10	0	2	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	1	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	1	0	0
T40	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	45787	0	0
T1	486	25	0	0
T6	460	20	0	0
T10	0	25	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	20	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	20	0	0
T40	0	25	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	0	20	0	0
T68	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6337217	0	0
T1	486	83	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	58	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	27	0	0
T35	11234	3	0	0
T45	0	1	0	0
T49	0	1	0	0
T120	0	2	0	0
T122	0	10	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	8	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	16772	0	0
T1	486	4	0	0
T10	0	4	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T21	524	0	0	0
T22	404	0	0	0
T40	0	4	0	0
T41	0	82	0	0
T60	0	41	0	0
T69	0	4	0	0
T72	0	4	0	0
T108	0	9	0	0
T140	0	3	0	0
T141	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	378	0	0
T1	486	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T21	524	0	0	0
T22	404	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T60	0	8	0	0
T69	0	1	0	0
T72	0	1	0	0
T108	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6005982	0	0
T1	486	3	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	26	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6007229	0	0
T1	486	3	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	26	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	461	0	0
T1	486	1	0	0
T6	460	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	1	0	0
T20	734	0	0	0
T23	421	0	0	0
T31	0	1	0	0
T40	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	409	0	0
T1	486	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T21	524	0	0	0
T22	404	0	0	0
T35	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0
T60	0	8	0	0
T69	0	1	0	0
T72	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	378	0	0
T1	486	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T21	524	0	0	0
T22	404	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T60	0	8	0	0
T69	0	1	0	0
T72	0	1	0	0
T108	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	378	0	0
T1	486	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T21	524	0	0	0
T22	404	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T60	0	8	0	0
T69	0	1	0	0
T72	0	1	0	0
T108	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	16370	0	0
T1	486	3	0	0
T10	0	3	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T21	524	0	0	0
T22	404	0	0	0
T40	0	3	0	0
T41	0	81	0	0
T60	0	33	0	0
T69	0	3	0	0
T72	0	3	0	0
T108	0	8	0	0
T140	0	2	0	0
T141	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	351	0	0
T1	486	1	0	0
T10	0	1	0	0
T14	493	0	0	0
T15	445	0	0	0
T16	891	0	0	0
T17	527	0	0	0
T18	423	0	0	0
T19	447	0	0	0
T20	734	0	0	0
T21	524	0	0	0
T22	404	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T60	0	8	0	0
T69	0	1	0	0
T72	0	1	0	0
T108	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T32 T33 T34 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T32 T33 T34 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T32 T33 T34 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T32 T33 T34 
129        1/1              cnt_en = 1'b0;
           Tests:       T32 T33 T34 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T32 T33 T34 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T32 T33 T34 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T32 T33 T34 
139                     
140        1/1              unique case (state_q)
           Tests:       T32 T33 T34 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T32 T33 T34 
148        1/1                    state_d = DebounceSt;
           Tests:       T32 T33 T34 
149        1/1                    cnt_en = 1'b1;
           Tests:       T32 T33 T34 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T34 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T32 T33 T34 
163        1/1                    state_d = IdleSt;
           Tests:       T49 T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T32 T33 T34 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
167        1/1                    if (trigger_active) begin
           Tests:       T32 T33 T34 
168        1/1                      state_d = DetectSt;
           Tests:       T32 T33 T34 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T49 T62 T110 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T32 T33 T34 
182        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T34 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T32 T33 T34 
186        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T34 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T32 T33 T34 
191        1/1                      state_d = StableSt;
           Tests:       T49 T61 T62 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T49 T61 T62 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T49 T61 T62 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T49 T61 T62 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T49 T61 T62 
206        1/1                    state_d = IdleSt;
           Tests:       T49 T61 T62 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T49 T61 T62 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T49,T61,T62
1	1	Covered	T32,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
1	0	Covered	T49,T62,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T61,T62
0	1	Covered	T49,T61,T62
1	0	Covered	T49,T62

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T61,T62
1	-	Covered	T49,T61,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T33,T34
DetectSt	168	Covered	T32,T33,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T49,T61,T62

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T33,T34
DebounceSt->IdleSt	163	Covered	T49,T62,T110
DetectSt->IdleSt	186	Covered	T32,T33,T34
DetectSt->StableSt	191	Covered	T49,T61,T62
IdleSt->DebounceSt	148	Covered	T32,T33,T34
StableSt->IdleSt	206	Covered	T49,T61,T62

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T34
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T32,T33,T34
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T62
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T33,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T62,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	0	1	-	Covered	T49,T61,T62
DetectSt	-	-	-	-	0	0	-	Covered	T32,T33,T34
StableSt	-	-	-	-	-	-	1	Covered	T49,T61,T62
StableSt	-	-	-	-	-	-	0	Covered	T49,T61,T62
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	2876	0	0
CntIncr_A	6803201	102548	0	0
CntNoWrap_A	6803201	6335210	0	0
DetectStDropOut_A	6803201	327	0	0
DetectedOut_A	6803201	53187	0	0
DetectedPulseOut_A	6803201	836	0	0
DisabledIdleSt_A	6803201	5889624	0	0
DisabledNoDetection_A	6803201	5891399	0	0
EnterDebounceSt_A	6803201	1462	0	0
EnterDetectSt_A	6803201	1414	0	0
EnterStableSt_A	6803201	836	0	0
PulseIsPulse_A	6803201	836	0	0
StayInStableSt	6803201	52270	0	0
gen_high_event_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	753	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	2876	0	0
T32	5271	20	0	0
T33	0	26	0	0
T34	0	54	0	0
T43	0	32	0	0
T49	0	16	0	0
T61	0	50	0	0
T62	0	16	0	0
T77	496	0	0	0
T97	0	2	0	0
T98	0	52	0	0
T99	0	20	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	102548	0	0
T32	5271	526	0	0
T33	0	682	0	0
T34	0	1670	0	0
T43	0	1216	0	0
T49	0	660	0	0
T61	0	1525	0	0
T62	0	536	0	0
T77	496	0	0	0
T97	0	54	0	0
T98	0	990	0	0
T99	0	435	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6335210	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	327	0	0
T32	5271	10	0	0
T33	0	13	0	0
T34	0	27	0	0
T44	0	1	0	0
T49	0	1	0	0
T62	0	1	0	0
T77	496	0	0	0
T97	0	1	0	0
T98	0	26	0	0
T99	0	10	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0
T245	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	53187	0	0
T42	10852	0	0	0
T43	0	2024	0	0
T49	7896	457	0	0
T54	759	0	0	0
T61	0	1979	0	0
T62	0	413	0	0
T63	0	878	0	0
T110	0	130	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	98	0	0
T241	0	299	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	506	0	0
T247	0	250	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	836	0	0
T42	10852	0	0	0
T43	0	16	0	0
T49	7896	5	0	0
T54	759	0	0	0
T61	0	25	0	0
T62	0	5	0	0
T63	0	26	0	0
T110	0	10	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	3	0	0
T241	0	9	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	9	0	0
T247	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5889624	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5891399	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1462	0	0
T32	5271	10	0	0
T33	0	13	0	0
T34	0	27	0	0
T43	0	16	0	0
T49	0	9	0	0
T61	0	25	0	0
T62	0	9	0	0
T77	496	0	0	0
T97	0	1	0	0
T98	0	26	0	0
T99	0	10	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1414	0	0
T32	5271	10	0	0
T33	0	13	0	0
T34	0	27	0	0
T43	0	16	0	0
T49	0	7	0	0
T61	0	25	0	0
T62	0	7	0	0
T77	496	0	0	0
T97	0	1	0	0
T98	0	26	0	0
T99	0	10	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	836	0	0
T42	10852	0	0	0
T43	0	16	0	0
T49	7896	5	0	0
T54	759	0	0	0
T61	0	25	0	0
T62	0	5	0	0
T63	0	26	0	0
T110	0	10	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	3	0	0
T241	0	9	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	9	0	0
T247	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	836	0	0
T42	10852	0	0	0
T43	0	16	0	0
T49	7896	5	0	0
T54	759	0	0	0
T61	0	25	0	0
T62	0	5	0	0
T63	0	26	0	0
T110	0	10	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	3	0	0
T241	0	9	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	9	0	0
T247	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	52270	0	0
T42	10852	0	0	0
T43	0	2005	0	0
T49	7896	452	0	0
T54	759	0	0	0
T61	0	1952	0	0
T62	0	408	0	0
T63	0	851	0	0
T110	0	120	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	95	0	0
T241	0	289	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	497	0	0
T247	0	242	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	753	0	0
T42	10852	0	0	0
T43	0	13	0	0
T49	7896	4	0	0
T54	759	0	0	0
T61	0	23	0	0
T62	0	4	0	0
T63	0	25	0	0
T110	0	10	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	3	0	0
T241	0	8	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	9	0	0
T247	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T60 T41 T59 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T60 T41 T59 
149        1/1                    cnt_en = 1'b1;
           Tests:       T60 T41 T59 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T60 T41 T59 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T60 T41 T59 
163        1/1                    state_d = IdleSt;
           Tests:       T49 T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T60 T41 T59 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T60 T41 T59 
167        1/1                    if (trigger_active) begin
           Tests:       T60 T41 T59 
168        1/1                      state_d = DetectSt;
           Tests:       T60 T41 T59 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T41 T46 T248 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T60 T41 T59 
182        1/1                  cnt_en = 1'b1;
           Tests:       T60 T41 T59 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T60 T41 T59 
186        1/1                    state_d = IdleSt;
           Tests:       T108 T49 T62 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T108 T49 T62 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T60 T41 T59 
191        1/1                      state_d = StableSt;
           Tests:       T60 T41 T59 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T60 T41 T59 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T60 T41 T59 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T60 T41 T59 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T60 T41 T59 
206        1/1                    state_d = IdleSt;
           Tests:       T60 T41 T59 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T60 T41 T59 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T60,T41,T59

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T60,T41,T59

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T60,T41,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T60,T41,T59
1	0	Covered	T7,T64,T111
1	1	Covered	T60,T41,T59

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T60,T41,T59
0	1	Covered	T108,T49,T249
1	0	Covered	T49,T62

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T60,T41,T59
0	1	Covered	T60,T41,T59
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T60,T41,T59
1	-	Covered	T60,T41,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T60,T41,T59
DetectSt	168	Covered	T60,T41,T59
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T60,T41,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T60,T41,T59
DebounceSt->IdleSt	163	Covered	T41,T49,T62
DetectSt->IdleSt	186	Covered	T108,T49,T62
DetectSt->StableSt	191	Covered	T60,T41,T59
IdleSt->DebounceSt	148	Covered	T60,T41,T59
StableSt->IdleSt	206	Covered	T60,T41,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T60,T41,T59
0	1	Covered	T60,T41,T59
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T60,T41,T59
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T60,T41,T59
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T62
DebounceSt	-	0	1	1	-	-	-	Covered	T60,T41,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T46,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T60,T41,T59
DetectSt	-	-	-	-	1	-	-	Covered	T108,T49,T62
DetectSt	-	-	-	-	0	1	-	Covered	T60,T41,T59
DetectSt	-	-	-	-	0	0	-	Covered	T60,T41,T59
StableSt	-	-	-	-	-	-	1	Covered	T60,T41,T59
StableSt	-	-	-	-	-	-	0	Covered	T60,T41,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	746	0	0
CntIncr_A	6803201	42201	0	0
CntNoWrap_A	6803201	6337340	0	0
DetectStDropOut_A	6803201	26	0	0
DetectedOut_A	6803201	12103	0	0
DetectedPulseOut_A	6803201	328	0	0
DisabledIdleSt_A	6803201	6023503	0	0
DisabledNoDetection_A	6803201	6024783	0	0
EnterDebounceSt_A	6803201	389	0	0
EnterDetectSt_A	6803201	357	0	0
EnterStableSt_A	6803201	328	0	0
PulseIsPulse_A	6803201	328	0	0
StayInStableSt	6803201	11744	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	297	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	746	0	0
T41	31522	10	0	0
T42	0	6	0	0
T43	0	2	0	0
T45	0	6	0	0
T49	0	8	0	0
T52	578	0	0	0
T59	10758	4	0	0
T60	28172	8	0	0
T61	0	4	0	0
T62	0	8	0	0
T97	5318	0	0	0
T108	9101	10	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	42201	0	0
T41	31522	902	0	0
T42	0	330	0	0
T43	0	77	0	0
T45	0	177	0	0
T49	0	280	0	0
T52	578	0	0	0
T59	10758	328	0	0
T60	28172	592	0	0
T61	0	146	0	0
T62	0	245	0	0
T97	5318	0	0	0
T108	9101	641	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6337340	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	26	0	0
T42	10852	0	0	0
T49	7896	1	0	0
T54	759	0	0	0
T108	9101	5	0	0
T220	429	0	0	0
T221	405	0	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T249	0	1	0	0
T254	0	3	0	0
T255	0	2	0	0
T256	0	1	0	0
T257	0	2	0	0
T258	0	2	0	0
T259	0	9	0	0
T260	2544	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	12103	0	0
T41	31522	18	0	0
T42	0	100	0	0
T43	0	70	0	0
T45	0	108	0	0
T46	0	38	0	0
T49	0	107	0	0
T52	578	0	0	0
T59	10758	11	0	0
T60	28172	162	0	0
T61	0	164	0	0
T62	0	96	0	0
T97	5318	0	0	0
T108	9101	0	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	328	0	0
T41	31522	4	0	0
T42	0	3	0	0
T43	0	1	0	0
T45	0	3	0	0
T46	0	6	0	0
T49	0	1	0	0
T52	578	0	0	0
T59	10758	2	0	0
T60	28172	4	0	0
T61	0	2	0	0
T62	0	1	0	0
T97	5318	0	0	0
T108	9101	0	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6023503	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6024783	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	389	0	0
T41	31522	6	0	0
T42	0	3	0	0
T43	0	1	0	0
T45	0	3	0	0
T49	0	5	0	0
T52	578	0	0	0
T59	10758	2	0	0
T60	28172	4	0	0
T61	0	2	0	0
T62	0	5	0	0
T97	5318	0	0	0
T108	9101	5	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	357	0	0
T41	31522	4	0	0
T42	0	3	0	0
T43	0	1	0	0
T45	0	3	0	0
T49	0	3	0	0
T52	578	0	0	0
T59	10758	2	0	0
T60	28172	4	0	0
T61	0	2	0	0
T62	0	3	0	0
T97	5318	0	0	0
T108	9101	5	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	328	0	0
T41	31522	4	0	0
T42	0	3	0	0
T43	0	1	0	0
T45	0	3	0	0
T46	0	6	0	0
T49	0	1	0	0
T52	578	0	0	0
T59	10758	2	0	0
T60	28172	4	0	0
T61	0	2	0	0
T62	0	1	0	0
T97	5318	0	0	0
T108	9101	0	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	328	0	0
T41	31522	4	0	0
T42	0	3	0	0
T43	0	1	0	0
T45	0	3	0	0
T46	0	6	0	0
T49	0	1	0	0
T52	578	0	0	0
T59	10758	2	0	0
T60	28172	4	0	0
T61	0	2	0	0
T62	0	1	0	0
T97	5318	0	0	0
T108	9101	0	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	11744	0	0
T41	31522	14	0	0
T42	0	97	0	0
T43	0	69	0	0
T45	0	105	0	0
T46	0	32	0	0
T49	0	106	0	0
T52	578	0	0	0
T59	10758	9	0	0
T60	28172	158	0	0
T61	0	160	0	0
T62	0	95	0	0
T97	5318	0	0	0
T108	9101	0	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	297	0	0
T41	31522	4	0	0
T42	0	3	0	0
T43	0	1	0	0
T45	0	3	0	0
T46	0	6	0	0
T49	0	1	0	0
T52	578	0	0	0
T59	10758	2	0	0
T60	28172	4	0	0
T62	0	1	0	0
T97	5318	0	0	0
T108	9101	0	0	0
T250	524	0	0	0
T251	402	0	0	0
T252	672	0	0	0
T253	8404	0	0	0
T261	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T32 T33 T34 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T32 T33 T34 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T32 T33 T34 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T32 T33 T34 
129        1/1              cnt_en = 1'b0;
           Tests:       T32 T33 T34 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T32 T33 T34 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T32 T33 T34 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T32 T33 T34 
139                     
140        1/1              unique case (state_q)
           Tests:       T32 T33 T34 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T32 T33 T34 
148        1/1                    state_d = DebounceSt;
           Tests:       T32 T33 T34 
149        1/1                    cnt_en = 1'b1;
           Tests:       T32 T33 T34 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T34 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T32 T33 T34 
163        1/1                    state_d = IdleSt;
           Tests:       T49 T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T32 T33 T34 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
167        1/1                    if (trigger_active) begin
           Tests:       T32 T33 T34 
168        1/1                      state_d = DetectSt;
           Tests:       T32 T33 T34 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T49 T62 T110 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T32 T33 T34 
182        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T34 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T32 T33 T34 
186        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T34 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T32 T33 T34 
191        1/1                      state_d = StableSt;
           Tests:       T49 T62 T63 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T49 T62 T63 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T49 T62 T63 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T49 T62 T63 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T49 T62 T63 
206        1/1                    state_d = IdleSt;
           Tests:       T49 T62 T63 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T49 T62 T63 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T49,T61,T62
1	1	Covered	T32,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
1	0	Covered	T49,T61,T62

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T62,T63
0	1	Covered	T49,T62,T63
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T62,T63
1	-	Covered	T49,T62,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T33,T34
DetectSt	168	Covered	T32,T33,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T49,T62,T63

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T33,T34
DebounceSt->IdleSt	163	Covered	T49,T62,T110
DetectSt->IdleSt	186	Covered	T32,T33,T34
DetectSt->StableSt	191	Covered	T49,T62,T63
IdleSt->DebounceSt	148	Covered	T32,T33,T34
StableSt->IdleSt	206	Covered	T49,T62,T63

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T34
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T32,T33,T34
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T62
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T33,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T62,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	0	1	-	Covered	T49,T62,T63
DetectSt	-	-	-	-	0	0	-	Covered	T32,T33,T34
StableSt	-	-	-	-	-	-	1	Covered	T49,T62,T63
StableSt	-	-	-	-	-	-	0	Covered	T49,T62,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	2963	0	0
CntIncr_A	6803201	101705	0	0
CntNoWrap_A	6803201	6335123	0	0
DetectStDropOut_A	6803201	338	0	0
DetectedOut_A	6803201	79160	0	0
DetectedPulseOut_A	6803201	994	0	0
DisabledIdleSt_A	6803201	5872252	0	0
DisabledNoDetection_A	6803201	5874017	0	0
EnterDebounceSt_A	6803201	1499	0	0
EnterDetectSt_A	6803201	1464	0	0
EnterStableSt_A	6803201	994	0	0
PulseIsPulse_A	6803201	994	0	0
StayInStableSt	6803201	78075	0	0
gen_high_event_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	902	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	2963	0	0
T32	5271	44	0	0
T33	0	30	0	0
T34	0	30	0	0
T43	0	24	0	0
T49	0	16	0	0
T61	0	24	0	0
T62	0	16	0	0
T77	496	0	0	0
T97	0	10	0	0
T98	0	54	0	0
T99	0	54	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	101705	0	0
T32	5271	1167	0	0
T33	0	790	0	0
T34	0	920	0	0
T43	0	1497	0	0
T49	0	639	0	0
T61	0	815	0	0
T62	0	590	0	0
T77	496	0	0	0
T97	0	266	0	0
T98	0	1021	0	0
T99	0	1193	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6335123	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	338	0	0
T32	5271	22	0	0
T33	0	15	0	0
T34	0	15	0	0
T49	0	1	0	0
T62	0	1	0	0
T77	496	0	0	0
T97	0	5	0	0
T98	0	27	0	0
T99	0	27	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0
T119	0	14	0	0
T245	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	79160	0	0
T42	10852	0	0	0
T44	0	1887	0	0
T47	0	130	0	0
T49	7896	378	0	0
T54	759	0	0	0
T62	0	466	0	0
T63	0	123	0	0
T110	0	1758	0	0
T112	0	2162	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	122	0	0
T241	0	2216	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	3344	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	994	0	0
T42	10852	0	0	0
T44	0	31	0	0
T47	0	8	0	0
T49	7896	5	0	0
T54	759	0	0	0
T62	0	5	0	0
T63	0	6	0	0
T110	0	8	0	0
T112	0	21	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	3	0	0
T241	0	28	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5872252	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5874017	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1499	0	0
T32	5271	22	0	0
T33	0	15	0	0
T34	0	15	0	0
T43	0	12	0	0
T49	0	9	0	0
T61	0	12	0	0
T62	0	9	0	0
T77	496	0	0	0
T97	0	5	0	0
T98	0	27	0	0
T99	0	27	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1464	0	0
T32	5271	22	0	0
T33	0	15	0	0
T34	0	15	0	0
T43	0	12	0	0
T49	0	7	0	0
T61	0	12	0	0
T62	0	7	0	0
T77	496	0	0	0
T97	0	5	0	0
T98	0	27	0	0
T99	0	27	0	0
T100	403	0	0	0
T101	422	0	0	0
T102	715	0	0	0
T103	442	0	0	0
T104	438	0	0	0
T105	423	0	0	0
T106	1828	0	0	0
T107	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	994	0	0
T42	10852	0	0	0
T44	0	31	0	0
T47	0	8	0	0
T49	7896	5	0	0
T54	759	0	0	0
T62	0	5	0	0
T63	0	6	0	0
T110	0	8	0	0
T112	0	21	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	3	0	0
T241	0	28	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	994	0	0
T42	10852	0	0	0
T44	0	31	0	0
T47	0	8	0	0
T49	7896	5	0	0
T54	759	0	0	0
T62	0	5	0	0
T63	0	6	0	0
T110	0	8	0	0
T112	0	21	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	3	0	0
T241	0	28	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	78075	0	0
T42	10852	0	0	0
T44	0	1856	0	0
T47	0	122	0	0
T49	7896	373	0	0
T54	759	0	0	0
T62	0	461	0	0
T63	0	117	0	0
T110	0	1750	0	0
T112	0	2140	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	119	0	0
T241	0	2184	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	3312	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	902	0	0
T42	10852	0	0	0
T44	0	31	0	0
T47	0	8	0	0
T49	7896	4	0	0
T54	759	0	0	0
T62	0	5	0	0
T63	0	6	0	0
T110	0	8	0	0
T112	0	20	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T240	0	3	0	0
T241	0	24	0	0
T242	820	0	0	0
T243	779	0	0	0
T244	960	0	0	0
T246	0	28	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T35 T60 T41 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T35 T41 T108 
149        1/1                    cnt_en = 1'b1;
           Tests:       T35 T41 T108 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T35 T41 T108 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T35 T41 T108 
163        1/1                    state_d = IdleSt;
           Tests:       T49 T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T35 T41 T108 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T41 T108 
167        1/1                    if (trigger_active) begin
           Tests:       T35 T41 T108 
168        1/1                      state_d = DetectSt;
           Tests:       T35 T41 T108 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T41 T108 T42 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T35 T41 T108 
182        1/1                  cnt_en = 1'b1;
           Tests:       T35 T41 T108 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T35 T41 T108 
186        1/1                    state_d = IdleSt;
           Tests:       T49 T62 T262 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 T262 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T35 T41 T108 
191        1/1                      state_d = StableSt;
           Tests:       T35 T41 T108 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T41 T108 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T41 T108 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T41 T108 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T41 T108 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T41 T108 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T41 T108 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T41,T108

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T41,T108

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T41,T108

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T60,T41
1	0	Covered	T7,T64,T111
1	1	Covered	T35,T41,T108

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T41,T108
0	1	Covered	T262,T263,T264
1	0	Covered	T49,T62

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T41,T108
0	1	Covered	T35,T41,T108
1	0	Covered	T62

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T41,T108
1	-	Covered	T35,T41,T108

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T41,T108
DetectSt	168	Covered	T35,T41,T108
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T41,T108

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T41,T108
DebounceSt->IdleSt	163	Covered	T41,T108,T49
DetectSt->IdleSt	186	Covered	T49,T62,T262
DetectSt->StableSt	191	Covered	T35,T41,T108
IdleSt->DebounceSt	148	Covered	T35,T41,T108
StableSt->IdleSt	206	Covered	T35,T41,T108

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T41,T108
0	1	Covered	T35,T41,T108
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T41,T108
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T41,T108
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T62
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T41,T108
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T108,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T41,T108
DetectSt	-	-	-	-	1	-	-	Covered	T49,T62,T262
DetectSt	-	-	-	-	0	1	-	Covered	T35,T41,T108
DetectSt	-	-	-	-	0	0	-	Covered	T35,T41,T108
StableSt	-	-	-	-	-	-	1	Covered	T35,T41,T108
StableSt	-	-	-	-	-	-	0	Covered	T35,T41,T108
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	790	0	0
CntIncr_A	6803201	43848	0	0
CntNoWrap_A	6803201	6337296	0	0
DetectStDropOut_A	6803201	40	0	0
DetectedOut_A	6803201	13688	0	0
DetectedPulseOut_A	6803201	331	0	0
DisabledIdleSt_A	6803201	5997033	0	0
DisabledNoDetection_A	6803201	5998316	0	0
EnterDebounceSt_A	6803201	415	0	0
EnterDetectSt_A	6803201	375	0	0
EnterStableSt_A	6803201	331	0	0
PulseIsPulse_A	6803201	331	0	0
StayInStableSt	6803201	13326	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	790	0	0
T35	11234	4	0	0
T41	0	10	0	0
T42	0	15	0	0
T44	0	2	0	0
T45	0	13	0	0
T46	0	21	0	0
T49	0	8	0	0
T62	0	8	0	0
T108	0	17	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	43848	0	0
T35	11234	244	0	0
T41	0	898	0	0
T42	0	1038	0	0
T44	0	48	0	0
T45	0	552	0	0
T46	0	741	0	0
T49	0	200	0	0
T62	0	303	0	0
T108	0	582	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	288	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6337296	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	40	0	0
T123	0	7	0	0
T262	63974	3	0	0
T263	0	6	0	0
T264	0	8	0	0
T265	0	1	0	0
T266	0	3	0	0
T267	0	12	0	0
T268	501	0	0	0
T269	720	0	0	0
T270	23716	0	0	0
T271	408	0	0	0
T272	521	0	0	0
T273	667	0	0	0
T274	501	0	0	0
T275	424	0	0	0
T276	448	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	13688	0	0
T35	11234	110	0	0
T41	0	22	0	0
T42	0	38	0	0
T44	0	55	0	0
T45	0	46	0	0
T46	0	460	0	0
T49	0	106	0	0
T62	0	96	0	0
T108	0	502	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	331	0	0
T35	11234	2	0	0
T41	0	4	0	0
T42	0	7	0	0
T44	0	1	0	0
T45	0	6	0	0
T46	0	10	0	0
T49	0	1	0	0
T62	0	1	0	0
T108	0	8	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5997033	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5998316	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	415	0	0
T35	11234	2	0	0
T41	0	6	0	0
T42	0	8	0	0
T44	0	1	0	0
T45	0	7	0	0
T46	0	11	0	0
T49	0	5	0	0
T62	0	5	0	0
T108	0	9	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	375	0	0
T35	11234	2	0	0
T41	0	4	0	0
T42	0	7	0	0
T44	0	1	0	0
T45	0	6	0	0
T46	0	10	0	0
T49	0	3	0	0
T62	0	3	0	0
T108	0	8	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	331	0	0
T35	11234	2	0	0
T41	0	4	0	0
T42	0	7	0	0
T44	0	1	0	0
T45	0	6	0	0
T46	0	10	0	0
T49	0	1	0	0
T62	0	1	0	0
T108	0	8	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	331	0	0
T35	11234	2	0	0
T41	0	4	0	0
T42	0	7	0	0
T44	0	1	0	0
T45	0	6	0	0
T46	0	10	0	0
T49	0	1	0	0
T62	0	1	0	0
T108	0	8	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	13326	0	0
T35	11234	108	0	0
T41	0	18	0	0
T42	0	31	0	0
T44	0	54	0	0
T45	0	40	0	0
T46	0	450	0	0
T49	0	105	0	0
T62	0	95	0	0
T108	0	494	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	299	0	0
T35	11234	2	0	0
T41	0	4	0	0
T42	0	7	0	0
T44	0	1	0	0
T45	0	6	0	0
T46	0	10	0	0
T49	0	1	0	0
T108	0	8	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T134	403	0	0	0
T249	0	4	0	0
T261	0	11	0	0