Unified Coverage Report :: Module :: sysrst_ctrl_keyintr

Module : sysrst_ctrl_keyintr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr	100.00	100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_keyintr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.69	98.30	94.16		95.24	97.62	98.16

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.09	100.00	95.45		100.00	100.00	100.00
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	91.69	95.65	90.91		83.33	95.24	93.33
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	99.09	100.00	95.45		100.00	100.00	100.00
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	99.09	100.00	95.45		100.00	100.00	100.00
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	90.39	93.48	90.91		83.33	90.48	93.75
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	99.09	100.00	95.45		100.00	100.00	100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	90.39	93.48	90.91		83.33	90.48	93.75
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	91.69	95.65	90.91		83.33	95.24	93.33
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	97.70	97.83	95.45		100.00	95.24	100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.09	100.00	95.45		100.00	100.00	100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	99.09	100.00	95.45		100.00	100.00	100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.09	100.00	95.45		100.00	100.00	100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	99.09	100.00	95.45		100.00	100.00	100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.09	100.00	95.45		100.00	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_keyintr

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	48	1	1	100.00

29                        logic [NumKeyIntr-1:0] triggers, l2h_en, h2l_en;
30         1/1            assign triggers = {
           Tests:       T4 T5 T6 
31                          pwrb_int_i,
32                          key0_int_i,
33                          key1_int_i,
34                          key2_int_i,
35                          ac_present_int_i,
36                          ec_rst_l_int_i,
37                          flash_wp_l_int_i
38                        };
39         1/1            assign l2h_en = {
           Tests:       T2 T7 T9 
40                          key_intr_ctl_i.pwrb_in_l2h.q,
41                          key_intr_ctl_i.key0_in_l2h.q,
42                          key_intr_ctl_i.key1_in_l2h.q,
43                          key_intr_ctl_i.key2_in_l2h.q,
44                          key_intr_ctl_i.ac_present_l2h.q,
45                          key_intr_ctl_i.ec_rst_l_l2h.q,
46                          key_intr_ctl_i.flash_wp_l_l2h.q
47                        };
48         1/1            assign h2l_en = {
           Tests:       T2 T7 T9