Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T4 T5 T6
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T3 T8 T29
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T6 T1 T20
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T6 T1 T20
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T3 T8 T29
149 1/1 cnt_en = 1'b1;
Tests: T3 T8 T29
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T3 T8 T29
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T3 T8 T29
163 1/1 state_d = IdleSt;
Tests: T49 T62
164 1/1 cnt_clr = 1'b1;
Tests: T49 T62
165 1/1 end else if (cnt_done) begin
Tests: T3 T8 T29
166 1/1 cnt_clr = 1'b1;
Tests: T3 T8 T29
167 1/1 if (trigger_active) begin
Tests: T3 T8 T29
168 1/1 state_d = DetectSt;
Tests: T3 T8 T29
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T12 T79 T69
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T3 T8 T29
182 1/1 cnt_en = 1'b1;
Tests: T3 T8 T29
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T3 T8 T29
186 1/1 state_d = IdleSt;
Tests: T7 T12 T80
187 1/1 cnt_clr = 1'b1;
Tests: T7 T12 T80
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T3 T8 T29
191 1/1 state_d = StableSt;
Tests: T3 T8 T29
192 1/1 cnt_clr = 1'b1;
Tests: T3 T8 T29
193 1/1 event_detected_o = 1'b1;
Tests: T3 T8 T29
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T3 T8 T29
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T3 T8 T29
206 1/1 state_d = IdleSt;
Tests: T3 T8 T29
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T3 T8 T29
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T6
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T3 T8
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T6 T1 T19
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T6 T1 T19
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T2 T3 T8
149 1/1 cnt_en = 1'b1;
Tests: T2 T3 T8
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T3 T8
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T3 T8
163 1/1 state_d = IdleSt;
Tests: T49 T62
164 1/1 cnt_clr = 1'b1;
Tests: T49 T62
165 1/1 end else if (cnt_done) begin
Tests: T2 T3 T8
166 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T8
167 1/1 if (trigger_active) begin
Tests: T2 T3 T8
168 1/1 state_d = DetectSt;
Tests: T2 T3 T12
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T8 T12 T55
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T3 T12
182 1/1 cnt_en = 1'b1;
Tests: T2 T3 T12
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T3 T12
186 1/1 state_d = IdleSt;
Tests: T7 T9 T12
187 1/1 cnt_clr = 1'b1;
Tests: T7 T9 T12
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T3 T12
191 1/1 state_d = StableSt;
Tests: T2 T3 T12
192 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T12
193 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T12
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T3 T12
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T3 T12
206 1/1 state_d = IdleSt;
Tests: T2 T3 T12
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T12
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T23
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T4 T5 T23
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T3 T8 T12
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T3 T7 T8
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T3 T7 T8
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T23
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T23
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T23
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T23
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T23
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T23
139
140 1/1 unique case (state_q)
Tests: T4 T5 T23
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T23
148 1/1 state_d = DebounceSt;
Tests: T3 T8 T12
149 1/1 cnt_en = 1'b1;
Tests: T3 T8 T12
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T3 T8 T12
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T3 T8 T12
163 1/1 state_d = IdleSt;
Tests: T49 T62
164 1/1 cnt_clr = 1'b1;
Tests: T49 T62
165 1/1 end else if (cnt_done) begin
Tests: T3 T8 T12
166 1/1 cnt_clr = 1'b1;
Tests: T3 T8 T12
167 1/1 if (trigger_active) begin
Tests: T3 T8 T12
168 1/1 state_d = DetectSt;
Tests: T3 T8 T12
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T78 T79 T82
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T3 T8 T12
182 1/1 cnt_en = 1'b1;
Tests: T3 T8 T12
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T3 T8 T12
186 1/1 state_d = IdleSt;
Tests: T82 T83 T109
187 1/1 cnt_clr = 1'b1;
Tests: T82 T83 T109
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T3 T8 T12
191 1/1 state_d = StableSt;
Tests: T3 T8 T12
192 1/1 cnt_clr = 1'b1;
Tests: T3 T8 T12
193 1/1 event_detected_o = 1'b1;
Tests: T3 T8 T12
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T3 T8 T12
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T3 T8 T12
206 1/1 state_d = IdleSt;
Tests: T3 T8 T12
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T3 T8 T12
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T32 T33 T34
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T32 T33 T34
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T6 T31 T10
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T6 T1 T19
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T6 T1 T19
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T6 T31 T10
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T6 T31 T10
129 1/1 cnt_en = 1'b0;
Tests: T6 T31 T10
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T6 T31 T10
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T6 T31 T10
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T6 T31 T10
139
140 1/1 unique case (state_q)
Tests: T6 T31 T10
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T6 T31 T10
148 1/1 state_d = DebounceSt;
Tests: T6 T31 T10
149 1/1 cnt_en = 1'b1;
Tests: T6 T31 T10
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T6 T31 T10
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T6 T31 T10
163 1/1 state_d = IdleSt;
Tests: T49 T62
164 1/1 cnt_clr = 1'b1;
Tests: T49 T62
165 1/1 end else if (cnt_done) begin
Tests: T6 T31 T10
166 1/1 cnt_clr = 1'b1;
Tests: T6 T31 T10
167 1/1 if (trigger_active) begin
Tests: T6 T31 T10
168 1/1 state_d = DetectSt;
Tests: T6 T31 T10
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T49 T62 T110
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T6 T31 T10
182 1/1 cnt_en = 1'b1;
Tests: T6 T31 T10
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T6 T31 T10
186 1/1 state_d = IdleSt;
Tests: T32 T33 T34
187 1/1 cnt_clr = 1'b1;
Tests: T32 T33 T34
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T6 T31 T10
191 1/1 state_d = StableSt;
Tests: T6 T31 T10
192 1/1 cnt_clr = 1'b1;
Tests: T6 T31 T10
193 1/1 event_detected_o = 1'b1;
Tests: T6 T31 T10
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T6 T31 T10
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T6 T31 T10
206 1/1 state_d = IdleSt;
Tests: T49 T61 T62
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T6 T31 T10
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T6 T1 T19
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T6 T1 T19
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T6 T1 T19
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T6 T1 T19
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T6 T1 T19
149 1/1 cnt_en = 1'b1;
Tests: T6 T1 T19
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T6 T1 T19
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T6 T1 T19
163 1/1 state_d = IdleSt;
Tests: T49 T62
164 1/1 cnt_clr = 1'b1;
Tests: T49 T62
165 1/1 end else if (cnt_done) begin
Tests: T6 T1 T19
166 1/1 cnt_clr = 1'b1;
Tests: T6 T1 T19
167 1/1 if (trigger_active) begin
Tests: T6 T1 T19
168 1/1 state_d = DetectSt;
Tests: T1 T10 T40
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T6 T19 T64
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T10 T40
182 1/1 cnt_en = 1'b1;
Tests: T1 T10 T40
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T10 T40
186 1/1 state_d = IdleSt;
Tests: T35 T108 T49
187 1/1 cnt_clr = 1'b1;
Tests: T35 T108 T49
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T10 T40
191 1/1 state_d = StableSt;
Tests: T1 T10 T40
192 1/1 cnt_clr = 1'b1;
Tests: T1 T10 T40
193 1/1 event_detected_o = 1'b1;
Tests: T1 T10 T40
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T10 T40
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T10 T40
206 1/1 state_d = IdleSt;
Tests: T1 T10 T40
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T10 T40
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T1,T19 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T6,T1,T19 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T6,T1,T19 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T6,T1,T19 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T10,T40 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T6,T1,T19 |
| 1 | 0 | Covered | T7,T64,T111 |
| 1 | 1 | Covered | T6,T1,T19 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T10,T40 |
| 0 | 1 | Covered | T35,T108,T49 |
| 1 | 0 | Covered | T49,T62 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T10,T40 |
| 0 | 1 | Covered | T1,T10,T40 |
| 1 | 0 | Covered | T62 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T10,T40 |
| 1 | - | Covered | T1,T10,T40 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T7,T29,T9 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T7,T29,T9 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T7,T29,T9 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T29,T9 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T7,T29,T9 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T29,T9 |
| 0 | 1 | Covered | T7,T55,T48 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T29,T9 |
| 0 | 1 | Covered | T29,T30,T67 |
| 1 | 0 | Covered | T49 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T7,T29,T9 |
| 1 | - | Covered | T29,T30,T67 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T32,T33,T34 |
| 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T6,T31,T10 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T6,T31,T10 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T6,T31,T10 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T32,T33,T34 |
| 1 | 0 | Covered | T49,T61,T62 |
| 1 | 1 | Covered | T6,T31,T10 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T31,T10 |
| 0 | 1 | Covered | T32,T33,T34 |
| 1 | 0 | Covered | T49,T61,T62 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T31,T10 |
| 0 | 1 | Covered | T49,T61,T62 |
| 1 | 0 | Covered | T49,T62,T112 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T6,T31,T10 |
| 1 | - | Covered | T49,T61,T62 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T23 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T12 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T12 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T12 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T8,T12 |
| 1 | 0 | Covered | T4,T5,T23 |
| 1 | 1 | Covered | T3,T8,T12 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T8,T12 |
| 0 | 1 | Covered | T82,T83,T109 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T8,T12 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T8,T12 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T7,T9 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T7,T9 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T7,T9 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T7,T9 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T2,T7,T9 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T7,T11 |
| 0 | 1 | Covered | T7,T9,T58 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T7,T11 |
| 0 | 1 | Covered | T2,T13,T48 |
| 1 | 0 | Covered | T49 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T2,T7,T11 |
| 1 | - | Covered | T2,T13,T48 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T23 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T23 |
| 1 | 1 | Covered | T4,T5,T23 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T12 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T12 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T12,T78 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T8,T12 |
| 1 | 0 | Covered | T4,T5,T23 |
| 1 | 1 | Covered | T3,T8,T12 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T12,T78 |
| 0 | 1 | Covered | T12,T82,T113 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T12,T78 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T12,T78 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T23 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T23 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T12 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T12 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T12 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T8,T12 |
| 1 | 0 | Covered | T4,T5,T23 |
| 1 | 1 | Covered | T3,T8,T12 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T8,T78 |
| 0 | 1 | Covered | T12,T80,T109 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T8,T78 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T8,T78 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T7,T29,T9 |
| DetectSt |
168 |
Covered |
T7,T29,T9 |
| IdleSt |
163 |
Covered |
T4,T5,T6 |
| StableSt |
191 |
Covered |
T7,T29,T9 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T7,T29,T9 |
| DebounceSt->IdleSt |
163 |
Covered |
T11,T12,T79 |
| DetectSt->IdleSt |
186 |
Covered |
T7,T12,T80 |
| DetectSt->StableSt |
191 |
Covered |
T7,T29,T9 |
| IdleSt->DebounceSt |
148 |
Covered |
T7,T29,T9 |
| StableSt->IdleSt |
206 |
Covered |
T7,T29,T30 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T7,T29,T9 |
| 0 |
1 |
Covered |
T7,T29,T9 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T29,T9 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T7,T29,T9 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T49,T62 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T7,T29,T9 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T11,T12,T79 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T7,T29,T9 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T7,T9,T12 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T7,T29,T9 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T10,T40 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T29,T30,T67 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T7,T29,T9 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T6,T3,T8 |
| 0 |
1 |
Covered |
T6,T3,T8 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T3,T8 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T3,T8 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T23 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T49,T62 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T6,T3,T8 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T78,T79,T82 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T6,T3,T8 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T32,T33,T34 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T6,T3,T8 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T6,T31,T10 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T3,T8,T12 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T6,T3,T8 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
17022 |
0 |
0 |
| T1 |
972 |
2 |
0 |
0 |
| T6 |
920 |
3 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
4 |
0 |
0 |
| T14 |
986 |
0 |
0 |
0 |
| T15 |
890 |
0 |
0 |
0 |
| T16 |
1782 |
0 |
0 |
0 |
| T17 |
1054 |
0 |
0 |
0 |
| T18 |
846 |
0 |
0 |
0 |
| T19 |
894 |
1 |
0 |
0 |
| T20 |
1468 |
0 |
0 |
0 |
| T23 |
842 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
2 |
0 |
0 |
| T30 |
650 |
2 |
0 |
0 |
| T31 |
463 |
3 |
0 |
0 |
| T32 |
0 |
12 |
0 |
0 |
| T40 |
0 |
4 |
0 |
0 |
| T60 |
28172 |
0 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T65 |
445 |
1 |
0 |
0 |
| T66 |
0 |
3 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
7 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
| T71 |
0 |
4 |
0 |
0 |
| T72 |
0 |
1 |
0 |
0 |
| T73 |
0 |
2 |
0 |
0 |
| T74 |
0 |
4 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T114 |
0 |
3 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
2778243 |
0 |
0 |
| T1 |
972 |
25 |
0 |
0 |
| T6 |
920 |
41 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
46 |
0 |
0 |
| T14 |
986 |
0 |
0 |
0 |
| T15 |
890 |
0 |
0 |
0 |
| T16 |
1782 |
0 |
0 |
0 |
| T17 |
1054 |
0 |
0 |
0 |
| T18 |
846 |
0 |
0 |
0 |
| T19 |
894 |
20 |
0 |
0 |
| T20 |
1468 |
0 |
0 |
0 |
| T23 |
842 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
41 |
0 |
0 |
| T30 |
650 |
36 |
0 |
0 |
| T31 |
463 |
41 |
0 |
0 |
| T32 |
0 |
313 |
0 |
0 |
| T40 |
0 |
46 |
0 |
0 |
| T60 |
28172 |
0 |
0 |
0 |
| T64 |
0 |
20 |
0 |
0 |
| T65 |
445 |
20 |
0 |
0 |
| T66 |
0 |
41 |
0 |
0 |
| T67 |
0 |
10 |
0 |
0 |
| T68 |
0 |
20 |
0 |
0 |
| T69 |
0 |
153 |
0 |
0 |
| T70 |
0 |
174 |
0 |
0 |
| T71 |
0 |
102 |
0 |
0 |
| T72 |
0 |
12 |
0 |
0 |
| T73 |
0 |
47 |
0 |
0 |
| T74 |
0 |
86 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T114 |
0 |
111 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
164773214 |
0 |
0 |
| T1 |
12636 |
2208 |
0 |
0 |
| T4 |
13130 |
2704 |
0 |
0 |
| T5 |
10946 |
520 |
0 |
0 |
| T6 |
11960 |
1531 |
0 |
0 |
| T14 |
12818 |
2392 |
0 |
0 |
| T15 |
11570 |
1144 |
0 |
0 |
| T16 |
23166 |
12740 |
0 |
0 |
| T17 |
13702 |
3276 |
0 |
0 |
| T18 |
10998 |
572 |
0 |
0 |
| T23 |
10946 |
520 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
1617 |
0 |
0 |
| T32 |
5271 |
6 |
0 |
0 |
| T33 |
0 |
15 |
0 |
0 |
| T34 |
0 |
27 |
0 |
0 |
| T35 |
11234 |
3 |
0 |
0 |
| T43 |
25643 |
0 |
0 |
0 |
| T44 |
7393 |
9 |
0 |
0 |
| T45 |
0 |
1 |
0 |
0 |
| T49 |
0 |
3 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
11190 |
0 |
0 |
0 |
| T97 |
0 |
26 |
0 |
0 |
| T98 |
0 |
6 |
0 |
0 |
| T99 |
4816 |
13 |
0 |
0 |
| T108 |
0 |
5 |
0 |
0 |
| T117 |
2468 |
1 |
0 |
0 |
| T118 |
0 |
1 |
0 |
0 |
| T119 |
0 |
5 |
0 |
0 |
| T120 |
0 |
2 |
0 |
0 |
| T121 |
0 |
1 |
0 |
0 |
| T122 |
0 |
10 |
0 |
0 |
| T123 |
0 |
1 |
0 |
0 |
| T124 |
0 |
1 |
0 |
0 |
| T125 |
0 |
8 |
0 |
0 |
| T126 |
529 |
0 |
0 |
0 |
| T127 |
755 |
0 |
0 |
0 |
| T128 |
660 |
0 |
0 |
0 |
| T129 |
522 |
0 |
0 |
0 |
| T130 |
424 |
0 |
0 |
0 |
| T131 |
672 |
0 |
0 |
0 |
| T132 |
490 |
0 |
0 |
0 |
| T133 |
790 |
0 |
0 |
0 |
| T134 |
403 |
0 |
0 |
0 |
| T135 |
1588 |
0 |
0 |
0 |
| T136 |
503 |
0 |
0 |
0 |
| T137 |
577 |
0 |
0 |
0 |
| T138 |
402 |
0 |
0 |
0 |
| T139 |
2404 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
1493968 |
0 |
0 |
| T1 |
972 |
4 |
0 |
0 |
| T6 |
460 |
34 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
85 |
0 |
0 |
| T14 |
986 |
0 |
0 |
0 |
| T15 |
890 |
0 |
0 |
0 |
| T16 |
1782 |
0 |
0 |
0 |
| T17 |
1054 |
0 |
0 |
0 |
| T18 |
846 |
0 |
0 |
0 |
| T19 |
894 |
0 |
0 |
0 |
| T20 |
1468 |
0 |
0 |
0 |
| T21 |
524 |
0 |
0 |
0 |
| T22 |
404 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
11 |
0 |
0 |
| T30 |
650 |
8 |
0 |
0 |
| T31 |
463 |
37 |
0 |
0 |
| T40 |
0 |
110 |
0 |
0 |
| T41 |
0 |
82 |
0 |
0 |
| T60 |
0 |
41 |
0 |
0 |
| T65 |
445 |
0 |
0 |
0 |
| T67 |
0 |
3 |
0 |
0 |
| T69 |
0 |
26 |
0 |
0 |
| T70 |
0 |
19 |
0 |
0 |
| T71 |
0 |
19 |
0 |
0 |
| T72 |
0 |
4 |
0 |
0 |
| T73 |
0 |
1 |
0 |
0 |
| T74 |
0 |
23 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T108 |
0 |
9 |
0 |
0 |
| T114 |
0 |
12 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
| T128 |
0 |
8 |
0 |
0 |
| T140 |
0 |
3 |
0 |
0 |
| T141 |
0 |
3 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
5850 |
0 |
0 |
| T1 |
972 |
1 |
0 |
0 |
| T6 |
460 |
1 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
2 |
0 |
0 |
| T14 |
986 |
0 |
0 |
0 |
| T15 |
890 |
0 |
0 |
0 |
| T16 |
1782 |
0 |
0 |
0 |
| T17 |
1054 |
0 |
0 |
0 |
| T18 |
846 |
0 |
0 |
0 |
| T19 |
894 |
0 |
0 |
0 |
| T20 |
1468 |
0 |
0 |
0 |
| T21 |
524 |
0 |
0 |
0 |
| T22 |
404 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
1 |
0 |
0 |
| T30 |
650 |
1 |
0 |
0 |
| T31 |
463 |
1 |
0 |
0 |
| T40 |
0 |
2 |
0 |
0 |
| T41 |
0 |
1 |
0 |
0 |
| T60 |
0 |
8 |
0 |
0 |
| T65 |
445 |
0 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T69 |
0 |
4 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T72 |
0 |
1 |
0 |
0 |
| T73 |
0 |
1 |
0 |
0 |
| T74 |
0 |
2 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T114 |
0 |
1 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
| T140 |
0 |
1 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
152581376 |
0 |
0 |
| T1 |
12636 |
2128 |
0 |
0 |
| T4 |
13130 |
2704 |
0 |
0 |
| T5 |
10946 |
520 |
0 |
0 |
| T6 |
11960 |
1446 |
0 |
0 |
| T14 |
12818 |
2392 |
0 |
0 |
| T15 |
11570 |
1144 |
0 |
0 |
| T16 |
23166 |
12740 |
0 |
0 |
| T17 |
13702 |
3276 |
0 |
0 |
| T18 |
10998 |
572 |
0 |
0 |
| T23 |
10946 |
520 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
152628140 |
0 |
0 |
| T1 |
12636 |
2153 |
0 |
0 |
| T4 |
13130 |
2730 |
0 |
0 |
| T5 |
10946 |
546 |
0 |
0 |
| T6 |
11960 |
1470 |
0 |
0 |
| T14 |
12818 |
2418 |
0 |
0 |
| T15 |
11570 |
1170 |
0 |
0 |
| T16 |
23166 |
12766 |
0 |
0 |
| T17 |
13702 |
3302 |
0 |
0 |
| T18 |
10998 |
598 |
0 |
0 |
| T23 |
10946 |
546 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
8801 |
0 |
0 |
| T1 |
972 |
1 |
0 |
0 |
| T6 |
920 |
2 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
2 |
0 |
0 |
| T14 |
986 |
0 |
0 |
0 |
| T15 |
890 |
0 |
0 |
0 |
| T16 |
1782 |
0 |
0 |
0 |
| T17 |
1054 |
0 |
0 |
0 |
| T18 |
846 |
0 |
0 |
0 |
| T19 |
894 |
1 |
0 |
0 |
| T20 |
1468 |
0 |
0 |
0 |
| T23 |
842 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
1 |
0 |
0 |
| T30 |
650 |
1 |
0 |
0 |
| T31 |
463 |
2 |
0 |
0 |
| T32 |
0 |
6 |
0 |
0 |
| T40 |
0 |
2 |
0 |
0 |
| T60 |
28172 |
0 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T65 |
445 |
1 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
4 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T72 |
0 |
1 |
0 |
0 |
| T73 |
0 |
1 |
0 |
0 |
| T74 |
0 |
2 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T114 |
0 |
2 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
8229 |
0 |
0 |
| T1 |
972 |
1 |
0 |
0 |
| T6 |
460 |
1 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
2 |
0 |
0 |
| T14 |
986 |
0 |
0 |
0 |
| T15 |
890 |
0 |
0 |
0 |
| T16 |
1782 |
0 |
0 |
0 |
| T17 |
1054 |
0 |
0 |
0 |
| T18 |
846 |
0 |
0 |
0 |
| T19 |
894 |
0 |
0 |
0 |
| T20 |
1468 |
0 |
0 |
0 |
| T21 |
524 |
0 |
0 |
0 |
| T22 |
404 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
1 |
0 |
0 |
| T30 |
650 |
1 |
0 |
0 |
| T31 |
463 |
1 |
0 |
0 |
| T35 |
0 |
3 |
0 |
0 |
| T40 |
0 |
2 |
0 |
0 |
| T41 |
0 |
1 |
0 |
0 |
| T60 |
0 |
8 |
0 |
0 |
| T65 |
445 |
0 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T69 |
0 |
4 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T72 |
0 |
1 |
0 |
0 |
| T73 |
0 |
1 |
0 |
0 |
| T74 |
0 |
2 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T114 |
0 |
1 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
| T140 |
0 |
2 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
5850 |
0 |
0 |
| T1 |
972 |
1 |
0 |
0 |
| T6 |
460 |
1 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
2 |
0 |
0 |
| T14 |
986 |
0 |
0 |
0 |
| T15 |
890 |
0 |
0 |
0 |
| T16 |
1782 |
0 |
0 |
0 |
| T17 |
1054 |
0 |
0 |
0 |
| T18 |
846 |
0 |
0 |
0 |
| T19 |
894 |
0 |
0 |
0 |
| T20 |
1468 |
0 |
0 |
0 |
| T21 |
524 |
0 |
0 |
0 |
| T22 |
404 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
1 |
0 |
0 |
| T30 |
650 |
1 |
0 |
0 |
| T31 |
463 |
1 |
0 |
0 |
| T40 |
0 |
2 |
0 |
0 |
| T41 |
0 |
1 |
0 |
0 |
| T60 |
0 |
8 |
0 |
0 |
| T65 |
445 |
0 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T69 |
0 |
4 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T72 |
0 |
1 |
0 |
0 |
| T73 |
0 |
1 |
0 |
0 |
| T74 |
0 |
2 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T114 |
0 |
1 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
| T140 |
0 |
1 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
5850 |
0 |
0 |
| T1 |
972 |
1 |
0 |
0 |
| T6 |
460 |
1 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
2 |
0 |
0 |
| T14 |
986 |
0 |
0 |
0 |
| T15 |
890 |
0 |
0 |
0 |
| T16 |
1782 |
0 |
0 |
0 |
| T17 |
1054 |
0 |
0 |
0 |
| T18 |
846 |
0 |
0 |
0 |
| T19 |
894 |
0 |
0 |
0 |
| T20 |
1468 |
0 |
0 |
0 |
| T21 |
524 |
0 |
0 |
0 |
| T22 |
404 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
1 |
0 |
0 |
| T30 |
650 |
1 |
0 |
0 |
| T31 |
463 |
1 |
0 |
0 |
| T40 |
0 |
2 |
0 |
0 |
| T41 |
0 |
1 |
0 |
0 |
| T60 |
0 |
8 |
0 |
0 |
| T65 |
445 |
0 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T69 |
0 |
4 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T72 |
0 |
1 |
0 |
0 |
| T73 |
0 |
1 |
0 |
0 |
| T74 |
0 |
2 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T114 |
0 |
1 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
| T140 |
0 |
1 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
176883226 |
1487416 |
0 |
0 |
| T1 |
972 |
3 |
0 |
0 |
| T6 |
460 |
32 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
82 |
0 |
0 |
| T14 |
986 |
0 |
0 |
0 |
| T15 |
890 |
0 |
0 |
0 |
| T16 |
1782 |
0 |
0 |
0 |
| T17 |
1054 |
0 |
0 |
0 |
| T18 |
846 |
0 |
0 |
0 |
| T19 |
894 |
0 |
0 |
0 |
| T20 |
1468 |
0 |
0 |
0 |
| T21 |
524 |
0 |
0 |
0 |
| T22 |
404 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
10 |
0 |
0 |
| T30 |
650 |
7 |
0 |
0 |
| T31 |
463 |
35 |
0 |
0 |
| T40 |
0 |
107 |
0 |
0 |
| T41 |
0 |
81 |
0 |
0 |
| T60 |
0 |
33 |
0 |
0 |
| T65 |
445 |
0 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T69 |
0 |
22 |
0 |
0 |
| T70 |
0 |
17 |
0 |
0 |
| T71 |
0 |
17 |
0 |
0 |
| T72 |
0 |
3 |
0 |
0 |
| T74 |
0 |
21 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T108 |
0 |
8 |
0 |
0 |
| T114 |
0 |
11 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
| T128 |
0 |
7 |
0 |
0 |
| T140 |
0 |
2 |
0 |
0 |
| T141 |
0 |
2 |
0 |
0 |
| T142 |
0 |
15 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
61228809 |
41127 |
0 |
0 |
| T1 |
4374 |
3 |
0 |
0 |
| T2 |
0 |
5 |
0 |
0 |
| T3 |
0 |
24 |
0 |
0 |
| T4 |
4545 |
46 |
0 |
0 |
| T5 |
3789 |
26 |
0 |
0 |
| T6 |
4140 |
3 |
0 |
0 |
| T14 |
4437 |
61 |
0 |
0 |
| T15 |
4005 |
22 |
0 |
0 |
| T16 |
8019 |
5 |
0 |
0 |
| T17 |
4743 |
45 |
0 |
0 |
| T18 |
3807 |
12 |
0 |
0 |
| T19 |
0 |
3 |
0 |
0 |
| T20 |
0 |
9 |
0 |
0 |
| T21 |
0 |
35 |
0 |
0 |
| T23 |
3789 |
19 |
0 |
0 |
| T75 |
0 |
3 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
34016005 |
31700185 |
0 |
0 |
| T1 |
2430 |
430 |
0 |
0 |
| T4 |
2525 |
525 |
0 |
0 |
| T5 |
2105 |
105 |
0 |
0 |
| T6 |
2300 |
300 |
0 |
0 |
| T14 |
2465 |
465 |
0 |
0 |
| T15 |
2225 |
225 |
0 |
0 |
| T16 |
4455 |
2455 |
0 |
0 |
| T17 |
2635 |
635 |
0 |
0 |
| T18 |
2115 |
115 |
0 |
0 |
| T23 |
2105 |
105 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
115654417 |
107780629 |
0 |
0 |
| T1 |
8262 |
1462 |
0 |
0 |
| T4 |
8585 |
1785 |
0 |
0 |
| T5 |
7157 |
357 |
0 |
0 |
| T6 |
7820 |
1020 |
0 |
0 |
| T14 |
8381 |
1581 |
0 |
0 |
| T15 |
7565 |
765 |
0 |
0 |
| T16 |
15147 |
8347 |
0 |
0 |
| T17 |
8959 |
2159 |
0 |
0 |
| T18 |
7191 |
391 |
0 |
0 |
| T23 |
7157 |
357 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
61228809 |
57060333 |
0 |
0 |
| T1 |
4374 |
774 |
0 |
0 |
| T4 |
4545 |
945 |
0 |
0 |
| T5 |
3789 |
189 |
0 |
0 |
| T6 |
4140 |
540 |
0 |
0 |
| T14 |
4437 |
837 |
0 |
0 |
| T15 |
4005 |
405 |
0 |
0 |
| T16 |
8019 |
4419 |
0 |
0 |
| T17 |
4743 |
1143 |
0 |
0 |
| T18 |
3807 |
207 |
0 |
0 |
| T23 |
3789 |
189 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
156473623 |
4997 |
0 |
0 |
| T1 |
486 |
1 |
0 |
0 |
| T9 |
494 |
0 |
0 |
0 |
| T10 |
506 |
1 |
0 |
0 |
| T14 |
493 |
0 |
0 |
0 |
| T15 |
445 |
0 |
0 |
0 |
| T16 |
891 |
0 |
0 |
0 |
| T17 |
527 |
0 |
0 |
0 |
| T18 |
423 |
0 |
0 |
0 |
| T19 |
447 |
0 |
0 |
0 |
| T20 |
734 |
0 |
0 |
0 |
| T21 |
524 |
0 |
0 |
0 |
| T22 |
404 |
0 |
0 |
0 |
| T28 |
495 |
0 |
0 |
0 |
| T29 |
656 |
1 |
0 |
0 |
| T30 |
650 |
1 |
0 |
0 |
| T31 |
463 |
0 |
0 |
0 |
| T40 |
0 |
1 |
0 |
0 |
| T41 |
0 |
1 |
0 |
0 |
| T49 |
7896 |
5 |
0 |
0 |
| T60 |
0 |
8 |
0 |
0 |
| T61 |
0 |
28 |
0 |
0 |
| T65 |
445 |
0 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T69 |
0 |
4 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T72 |
0 |
1 |
0 |
0 |
| T73 |
0 |
1 |
0 |
0 |
| T74 |
0 |
2 |
0 |
0 |
| T93 |
526 |
0 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T114 |
0 |
1 |
0 |
0 |
| T115 |
405 |
0 |
0 |
0 |
| T116 |
427 |
0 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
| T140 |
0 |
1 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
20409603 |
1743870 |
0 |
0 |
| T3 |
3153 |
478 |
0 |
0 |
| T7 |
8649 |
0 |
0 |
0 |
| T8 |
3174 |
325 |
0 |
0 |
| T12 |
0 |
429 |
0 |
0 |
| T27 |
1479 |
0 |
0 |
0 |
| T29 |
1968 |
0 |
0 |
0 |
| T64 |
8940 |
0 |
0 |
0 |
| T69 |
0 |
577 |
0 |
0 |
| T75 |
1269 |
0 |
0 |
0 |
| T76 |
1209 |
0 |
0 |
0 |
| T78 |
0 |
359 |
0 |
0 |
| T79 |
0 |
248 |
0 |
0 |
| T80 |
0 |
1079 |
0 |
0 |
| T81 |
0 |
578 |
0 |
0 |
| T82 |
0 |
39 |
0 |
0 |
| T83 |
0 |
617 |
0 |
0 |
| T84 |
1347 |
0 |
0 |
0 |
| T85 |
1506 |
0 |
0 |
0 |
| T113 |
0 |
610 |
0 |
0 |
| T143 |
0 |
75 |
0 |
0 |
| T144 |
0 |
301 |
0 |
0 |
| T145 |
0 |
456 |
0 |
0 |
| T146 |
0 |
312 |
0 |
0 |
