| T161 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2277354409 |
|
|
Oct 12 12:58:15 AM UTC 24 |
Oct 12 12:58:20 AM UTC 24 |
3811423407 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.360077544 |
|
|
Oct 12 12:58:17 AM UTC 24 |
Oct 12 12:58:20 AM UTC 24 |
2545004138 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.1990834388 |
|
|
Oct 12 12:58:17 AM UTC 24 |
Oct 12 12:58:20 AM UTC 24 |
2056883718 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.3437963898 |
|
|
Oct 12 12:56:35 AM UTC 24 |
Oct 12 12:58:21 AM UTC 24 |
39001051853 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1645485152 |
|
|
Oct 12 12:58:17 AM UTC 24 |
Oct 12 12:58:22 AM UTC 24 |
2120942018 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.313675047 |
|
|
Oct 12 12:58:07 AM UTC 24 |
Oct 12 12:58:22 AM UTC 24 |
15619177865 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3014654473 |
|
|
Oct 12 12:58:02 AM UTC 24 |
Oct 12 12:58:22 AM UTC 24 |
19355595724 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2416113416 |
|
|
Oct 12 12:58:19 AM UTC 24 |
Oct 12 12:58:23 AM UTC 24 |
2659445871 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.4219035223 |
|
|
Oct 12 12:58:21 AM UTC 24 |
Oct 12 12:58:26 AM UTC 24 |
4078900645 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3848964375 |
|
|
Oct 12 12:58:12 AM UTC 24 |
Oct 12 12:58:27 AM UTC 24 |
3611598015 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3067700334 |
|
|
Oct 12 12:58:15 AM UTC 24 |
Oct 12 12:58:29 AM UTC 24 |
3264164308 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.1851172855 |
|
|
Oct 12 12:58:23 AM UTC 24 |
Oct 12 12:58:29 AM UTC 24 |
4251658340 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4054946253 |
|
|
Oct 12 12:58:22 AM UTC 24 |
Oct 12 12:58:29 AM UTC 24 |
3578863019 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3262218776 |
|
|
Oct 12 12:58:19 AM UTC 24 |
Oct 12 12:58:30 AM UTC 24 |
2111989051 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.2014662435 |
|
|
Oct 12 12:58:29 AM UTC 24 |
Oct 12 12:58:33 AM UTC 24 |
2074138576 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.2282635226 |
|
|
Oct 12 12:58:19 AM UTC 24 |
Oct 12 12:58:33 AM UTC 24 |
2512805713 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.1861040445 |
|
|
Oct 12 12:58:28 AM UTC 24 |
Oct 12 12:58:33 AM UTC 24 |
2459320819 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.1774027166 |
|
|
Oct 12 12:58:28 AM UTC 24 |
Oct 12 12:58:34 AM UTC 24 |
2116050013 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.3654854472 |
|
|
Oct 12 12:58:02 AM UTC 24 |
Oct 12 12:58:35 AM UTC 24 |
12343728730 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1558833624 |
|
|
Oct 12 12:57:10 AM UTC 24 |
Oct 12 12:58:36 AM UTC 24 |
128216010046 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2094558350 |
|
|
Oct 12 12:57:54 AM UTC 24 |
Oct 12 12:58:36 AM UTC 24 |
24084588261 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1613617793 |
|
|
Oct 12 12:58:34 AM UTC 24 |
Oct 12 12:58:36 AM UTC 24 |
7942840672 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3501097266 |
|
|
Oct 12 12:57:43 AM UTC 24 |
Oct 12 12:58:37 AM UTC 24 |
55952349242 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1625476485 |
|
|
Oct 12 12:56:44 AM UTC 24 |
Oct 12 12:58:37 AM UTC 24 |
36968023366 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.3396938542 |
|
|
Oct 12 12:58:30 AM UTC 24 |
Oct 12 12:58:38 AM UTC 24 |
2519739731 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.423411023 |
|
|
Oct 12 12:58:40 AM UTC 24 |
Oct 12 12:58:50 AM UTC 24 |
2885223263 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.3404775571 |
|
|
Oct 12 12:58:27 AM UTC 24 |
Oct 12 12:58:39 AM UTC 24 |
2010435652 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1307393775 |
|
|
Oct 12 12:58:25 AM UTC 24 |
Oct 12 12:58:39 AM UTC 24 |
12024531454 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2121009620 |
|
|
Oct 12 12:58:38 AM UTC 24 |
Oct 12 12:58:42 AM UTC 24 |
2134364387 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3856686647 |
|
|
Oct 12 12:58:38 AM UTC 24 |
Oct 12 12:58:52 AM UTC 24 |
2450368568 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1664918964 |
|
|
Oct 12 12:58:34 AM UTC 24 |
Oct 12 12:58:44 AM UTC 24 |
3230329122 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.4128004186 |
|
|
Oct 12 12:58:30 AM UTC 24 |
Oct 12 12:58:45 AM UTC 24 |
2612062182 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.246467224 |
|
|
Oct 12 12:58:31 AM UTC 24 |
Oct 12 12:58:46 AM UTC 24 |
3898498881 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.1600941726 |
|
|
Oct 12 12:58:17 AM UTC 24 |
Oct 12 12:58:46 AM UTC 24 |
6643721196 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.412293844 |
|
|
Oct 12 12:58:39 AM UTC 24 |
Oct 12 12:58:48 AM UTC 24 |
2192436748 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2745847210 |
|
|
Oct 12 12:58:40 AM UTC 24 |
Oct 12 12:58:48 AM UTC 24 |
2614669153 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1624860382 |
|
|
Oct 12 12:58:37 AM UTC 24 |
Oct 12 12:58:49 AM UTC 24 |
2010514631 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.2906094415 |
|
|
Oct 12 12:58:46 AM UTC 24 |
Oct 12 12:58:49 AM UTC 24 |
2930597501 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.638367773 |
|
|
Oct 12 12:58:37 AM UTC 24 |
Oct 12 12:58:49 AM UTC 24 |
7942188157 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3311954706 |
|
|
Oct 12 12:58:45 AM UTC 24 |
Oct 12 12:58:50 AM UTC 24 |
9958574581 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.58164251 |
|
|
Oct 12 12:58:40 AM UTC 24 |
Oct 12 12:58:53 AM UTC 24 |
2514461245 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3675688356 |
|
|
Oct 12 12:58:51 AM UTC 24 |
Oct 12 12:58:56 AM UTC 24 |
2531600993 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1442718281 |
|
|
Oct 12 12:58:51 AM UTC 24 |
Oct 12 12:58:56 AM UTC 24 |
2627390908 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1066622721 |
|
|
Oct 12 12:58:43 AM UTC 24 |
Oct 12 12:58:57 AM UTC 24 |
3340710020 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2418197082 |
|
|
Oct 12 12:58:50 AM UTC 24 |
Oct 12 12:58:57 AM UTC 24 |
2207336544 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1852388169 |
|
|
Oct 12 12:57:48 AM UTC 24 |
Oct 12 12:58:58 AM UTC 24 |
47999696372 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2077031135 |
|
|
Oct 12 12:58:37 AM UTC 24 |
Oct 12 12:58:59 AM UTC 24 |
4394584188 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3725619898 |
|
|
Oct 12 12:58:53 AM UTC 24 |
Oct 12 12:59:00 AM UTC 24 |
3640328755 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1408763009 |
|
|
Oct 12 12:58:54 AM UTC 24 |
Oct 12 12:59:01 AM UTC 24 |
5684217676 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3403796282 |
|
|
Oct 12 12:58:53 AM UTC 24 |
Oct 12 12:59:02 AM UTC 24 |
2856453240 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.2625293578 |
|
|
Oct 12 12:58:50 AM UTC 24 |
Oct 12 12:59:03 AM UTC 24 |
2444281363 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.2538152091 |
|
|
Oct 12 12:59:00 AM UTC 24 |
Oct 12 12:59:04 AM UTC 24 |
2128970555 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.233781651 |
|
|
Oct 12 12:58:47 AM UTC 24 |
Oct 12 12:59:05 AM UTC 24 |
12546875266 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.1547762548 |
|
|
Oct 12 12:58:59 AM UTC 24 |
Oct 12 12:59:05 AM UTC 24 |
2020176259 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3399689113 |
|
|
Oct 12 12:59:02 AM UTC 24 |
Oct 12 12:59:06 AM UTC 24 |
2262733616 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3879561041 |
|
|
Oct 12 12:58:57 AM UTC 24 |
Oct 12 12:59:07 AM UTC 24 |
5898007612 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1421022692 |
|
|
Oct 12 12:58:57 AM UTC 24 |
Oct 12 12:59:08 AM UTC 24 |
2754533865 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.1188175333 |
|
|
Oct 12 12:59:03 AM UTC 24 |
Oct 12 12:59:08 AM UTC 24 |
2525184605 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1361447330 |
|
|
Oct 12 12:59:04 AM UTC 24 |
Oct 12 12:59:09 AM UTC 24 |
2633983289 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.312129809 |
|
|
Oct 12 12:59:06 AM UTC 24 |
Oct 12 12:59:10 AM UTC 24 |
3394768573 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.2143341702 |
|
|
Oct 12 12:59:11 AM UTC 24 |
Oct 12 12:59:14 AM UTC 24 |
2053744464 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2191403187 |
|
|
Oct 12 12:59:10 AM UTC 24 |
Oct 12 12:59:15 AM UTC 24 |
13999649908 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2486007998 |
|
|
Oct 12 12:56:53 AM UTC 24 |
Oct 12 12:59:15 AM UTC 24 |
71831670328 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.828514496 |
|
|
Oct 12 12:59:01 AM UTC 24 |
Oct 12 12:59:15 AM UTC 24 |
2466705601 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1917070823 |
|
|
Oct 12 12:59:06 AM UTC 24 |
Oct 12 12:59:17 AM UTC 24 |
203287624394 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2418067445 |
|
|
Oct 12 12:59:15 AM UTC 24 |
Oct 12 12:59:19 AM UTC 24 |
2126371788 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.2813809750 |
|
|
Oct 12 12:58:35 AM UTC 24 |
Oct 12 12:59:20 AM UTC 24 |
598610224377 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.1005629048 |
|
|
Oct 12 12:59:16 AM UTC 24 |
Oct 12 12:59:21 AM UTC 24 |
2525603285 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2680126506 |
|
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Oct 12 12:58:48 AM UTC 24 |
Oct 12 12:59:24 AM UTC 24 |
15344771101 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3252452328 |
|
|
Oct 12 12:59:17 AM UTC 24 |
Oct 12 12:59:24 AM UTC 24 |
2614239589 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1303994987 |
|
|
Oct 12 12:59:09 AM UTC 24 |
Oct 12 12:59:24 AM UTC 24 |
3961620358 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.617275222 |
|
|
Oct 12 12:59:20 AM UTC 24 |
Oct 12 12:59:25 AM UTC 24 |
2656289437 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3240507498 |
|
|
Oct 12 12:59:16 AM UTC 24 |
Oct 12 12:59:26 AM UTC 24 |
2205030316 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3040188144 |
|
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Oct 12 12:57:38 AM UTC 24 |
Oct 12 12:59:27 AM UTC 24 |
76684515411 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.4054800275 |
|
|
Oct 12 12:59:05 AM UTC 24 |
Oct 12 12:59:27 AM UTC 24 |
4458656276 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.3766995960 |
|
|
Oct 12 12:59:16 AM UTC 24 |
Oct 12 12:59:29 AM UTC 24 |
2469012427 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.609926623 |
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|
Oct 12 12:59:26 AM UTC 24 |
Oct 12 12:59:30 AM UTC 24 |
2825053962 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.960603042 |
|
|
Oct 12 12:59:28 AM UTC 24 |
Oct 12 12:59:33 AM UTC 24 |
2026665899 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.1905499642 |
|
|
Oct 12 12:56:54 AM UTC 24 |
Oct 12 12:59:36 AM UTC 24 |
156917757286 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3837411510 |
|
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Oct 12 12:59:20 AM UTC 24 |
Oct 12 12:59:36 AM UTC 24 |
3414061421 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2565547119 |
|
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Oct 12 12:59:07 AM UTC 24 |
Oct 12 12:59:37 AM UTC 24 |
5924834166 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1553755975 |
|
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Oct 12 12:59:30 AM UTC 24 |
Oct 12 12:59:38 AM UTC 24 |
2482869801 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.1884746134 |
|
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Oct 12 12:59:28 AM UTC 24 |
Oct 12 12:59:39 AM UTC 24 |
2110956715 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1495498486 |
|
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Oct 12 12:59:37 AM UTC 24 |
Oct 12 12:59:41 AM UTC 24 |
2637407441 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3032677857 |
|
|
Oct 12 12:59:27 AM UTC 24 |
Oct 12 12:59:41 AM UTC 24 |
12565299445 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.280241892 |
|
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Oct 12 12:59:30 AM UTC 24 |
Oct 12 12:59:43 AM UTC 24 |
2234314759 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4282999933 |
|
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Oct 12 12:59:21 AM UTC 24 |
Oct 12 12:59:44 AM UTC 24 |
1400865424485 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2675064014 |
|
|
Oct 12 12:59:26 AM UTC 24 |
Oct 12 12:59:47 AM UTC 24 |
4562590673 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.289581823 |
|
|
Oct 12 12:59:33 AM UTC 24 |
Oct 12 12:59:48 AM UTC 24 |
2510190354 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2654774526 |
|
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Oct 12 12:57:13 AM UTC 24 |
Oct 12 12:59:50 AM UTC 24 |
56049574127 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3832732502 |
|
|
Oct 12 12:59:48 AM UTC 24 |
Oct 12 12:59:51 AM UTC 24 |
2265956652 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2434957171 |
|
|
Oct 12 12:57:38 AM UTC 24 |
Oct 12 12:59:51 AM UTC 24 |
93962379996 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3662451819 |
|
|
Oct 12 12:59:38 AM UTC 24 |
Oct 12 12:59:52 AM UTC 24 |
3659206083 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1289066365 |
|
|
Oct 12 12:58:10 AM UTC 24 |
Oct 12 12:59:53 AM UTC 24 |
71220071316 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1155848896 |
|
|
Oct 12 12:59:42 AM UTC 24 |
Oct 12 12:59:53 AM UTC 24 |
4446007074 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.1281623942 |
|
|
Oct 12 12:59:47 AM UTC 24 |
Oct 12 12:59:53 AM UTC 24 |
2021388435 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.187023530 |
|
|
Oct 12 12:58:23 AM UTC 24 |
Oct 12 12:59:54 AM UTC 24 |
162055045369 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.203411946 |
|
|
Oct 12 12:58:45 AM UTC 24 |
Oct 12 12:59:55 AM UTC 24 |
91112736888 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.241237326 |
|
|
Oct 12 12:59:51 AM UTC 24 |
Oct 12 12:59:56 AM UTC 24 |
2489590769 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.2954365998 |
|
|
Oct 12 12:59:45 AM UTC 24 |
Oct 12 12:59:57 AM UTC 24 |
7795011023 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.502631758 |
|
|
Oct 12 12:59:54 AM UTC 24 |
Oct 12 12:59:57 AM UTC 24 |
2783356905 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3687407152 |
|
|
Oct 12 12:58:34 AM UTC 24 |
Oct 12 12:59:58 AM UTC 24 |
113104537685 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.4253480327 |
|
|
Oct 12 12:59:53 AM UTC 24 |
Oct 12 12:59:59 AM UTC 24 |
2518506228 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.927694852 |
|
|
Oct 12 12:56:52 AM UTC 24 |
Oct 12 01:00:00 AM UTC 24 |
119910847009 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1660431651 |
|
|
Oct 12 12:58:23 AM UTC 24 |
Oct 12 01:00:00 AM UTC 24 |
97690897329 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1675451435 |
|
|
Oct 12 12:59:54 AM UTC 24 |
Oct 12 01:00:00 AM UTC 24 |
14149547070 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.607523379 |
|
|
Oct 12 12:59:54 AM UTC 24 |
Oct 12 01:00:00 AM UTC 24 |
3489703517 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1548858346 |
|
|
Oct 12 12:59:55 AM UTC 24 |
Oct 12 01:00:00 AM UTC 24 |
3344977766 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3217868044 |
|
|
Oct 12 12:59:43 AM UTC 24 |
Oct 12 01:00:01 AM UTC 24 |
3534634498 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.4085215298 |
|
|
Oct 12 12:59:52 AM UTC 24 |
Oct 12 01:00:01 AM UTC 24 |
2065104858 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3250577744 |
|
|
Oct 12 12:58:47 AM UTC 24 |
Oct 12 01:00:02 AM UTC 24 |
76117021855 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3490706593 |
|
|
Oct 12 12:59:59 AM UTC 24 |
Oct 12 01:00:06 AM UTC 24 |
2114403707 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.895921088 |
|
|
Oct 12 12:58:23 AM UTC 24 |
Oct 12 01:00:02 AM UTC 24 |
937442765745 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.1219780822 |
|
|
Oct 12 12:58:07 AM UTC 24 |
Oct 12 01:00:04 AM UTC 24 |
165789558583 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.352239435 |
|
|
Oct 12 12:59:53 AM UTC 24 |
Oct 12 01:00:05 AM UTC 24 |
2614678134 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.50265405 |
|
|
Oct 12 01:00:00 AM UTC 24 |
Oct 12 01:00:07 AM UTC 24 |
2475157858 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1784030973 |
|
|
Oct 12 01:00:01 AM UTC 24 |
Oct 12 01:00:07 AM UTC 24 |
2618302358 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.1996164035 |
|
|
Oct 12 12:59:58 AM UTC 24 |
Oct 12 01:00:08 AM UTC 24 |
2015163106 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2383233829 |
|
|
Oct 12 01:00:02 AM UTC 24 |
Oct 12 01:00:09 AM UTC 24 |
11593162581 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2390294581 |
|
|
Oct 12 01:00:01 AM UTC 24 |
Oct 12 01:00:09 AM UTC 24 |
2087013103 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2321864 |
|
|
Oct 12 12:59:38 AM UTC 24 |
Oct 12 01:00:10 AM UTC 24 |
5305542735 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1412771247 |
|
|
Oct 12 12:59:57 AM UTC 24 |
Oct 12 01:00:11 AM UTC 24 |
17870246348 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1900343419 |
|
|
Oct 12 01:00:01 AM UTC 24 |
Oct 12 01:00:14 AM UTC 24 |
2611108315 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3747436722 |
|
|
Oct 12 12:56:36 AM UTC 24 |
Oct 12 01:00:14 AM UTC 24 |
71093980747 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2205715545 |
|
|
Oct 12 12:58:25 AM UTC 24 |
Oct 12 01:00:17 AM UTC 24 |
181560786579 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3351449195 |
|
|
Oct 12 01:00:01 AM UTC 24 |
Oct 12 01:00:17 AM UTC 24 |
2557384644 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2937251933 |
|
|
Oct 12 01:00:14 AM UTC 24 |
Oct 12 01:00:17 AM UTC 24 |
2133019876 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3902106145 |
|
|
Oct 12 01:00:01 AM UTC 24 |
Oct 12 01:00:18 AM UTC 24 |
3813626225 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3984180345 |
|
|
Oct 12 01:00:15 AM UTC 24 |
Oct 12 01:00:18 AM UTC 24 |
3356086291 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.2991536880 |
|
|
Oct 12 01:00:14 AM UTC 24 |
Oct 12 01:00:20 AM UTC 24 |
3272564849 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2869729568 |
|
|
Oct 12 01:00:15 AM UTC 24 |
Oct 12 01:00:21 AM UTC 24 |
4086516788 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.11384368 |
|
|
Oct 12 01:00:19 AM UTC 24 |
Oct 12 01:00:22 AM UTC 24 |
2147096907 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.4197116318 |
|
|
Oct 12 01:00:15 AM UTC 24 |
Oct 12 01:00:22 AM UTC 24 |
2259696908 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.1501208618 |
|
|
Oct 12 01:00:19 AM UTC 24 |
Oct 12 01:00:23 AM UTC 24 |
2027729710 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1428478600 |
|
|
Oct 12 12:58:58 AM UTC 24 |
Oct 12 01:00:24 AM UTC 24 |
104467636216 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1660470294 |
|
|
Oct 12 01:00:14 AM UTC 24 |
Oct 12 01:00:24 AM UTC 24 |
5106290558 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2426477775 |
|
|
Oct 12 01:00:14 AM UTC 24 |
Oct 12 01:00:24 AM UTC 24 |
2008520337 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2480395597 |
|
|
Oct 12 01:00:15 AM UTC 24 |
Oct 12 01:00:25 AM UTC 24 |
2511263783 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3309041974 |
|
|
Oct 12 12:56:49 AM UTC 24 |
Oct 12 01:00:25 AM UTC 24 |
124309101448 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.4215790333 |
|
|
Oct 12 01:00:22 AM UTC 24 |
Oct 12 01:00:25 AM UTC 24 |
2109213598 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.1038323839 |
|
|
Oct 12 01:00:23 AM UTC 24 |
Oct 12 01:00:26 AM UTC 24 |
2548102383 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.266114315 |
|
|
Oct 12 01:00:15 AM UTC 24 |
Oct 12 01:00:27 AM UTC 24 |
2613420663 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.3984164897 |
|
|
Oct 12 01:00:21 AM UTC 24 |
Oct 12 01:00:29 AM UTC 24 |
2455534623 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.268261492 |
|
|
Oct 12 01:00:15 AM UTC 24 |
Oct 12 01:00:30 AM UTC 24 |
4133156981 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.3499061687 |
|
|
Oct 12 01:00:15 AM UTC 24 |
Oct 12 01:00:30 AM UTC 24 |
2464824741 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1941925150 |
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Oct 12 01:00:25 AM UTC 24 |
Oct 12 01:00:32 AM UTC 24 |
3713919422 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.2220454813 |
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Oct 12 01:00:28 AM UTC 24 |
Oct 12 01:00:33 AM UTC 24 |
2019544028 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1115383601 |
|
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Oct 12 01:00:31 AM UTC 24 |
Oct 12 01:00:34 AM UTC 24 |
2489813661 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.496779628 |
|
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Oct 12 01:00:23 AM UTC 24 |
Oct 12 01:00:35 AM UTC 24 |
2613816307 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.3194048102 |
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|
Oct 12 01:00:31 AM UTC 24 |
Oct 12 01:00:35 AM UTC 24 |
2158510282 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1466919003 |
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Oct 12 01:00:27 AM UTC 24 |
Oct 12 01:00:36 AM UTC 24 |
7600250042 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.746090838 |
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Oct 12 01:00:25 AM UTC 24 |
Oct 12 01:00:36 AM UTC 24 |
4370286045 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.998650779 |
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|
Oct 12 01:00:50 AM UTC 24 |
Oct 12 01:00:59 AM UTC 24 |
2110597973 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.1416544616 |
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Oct 12 01:00:32 AM UTC 24 |
Oct 12 01:00:37 AM UTC 24 |
2522434858 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.169573361 |
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Oct 12 01:00:14 AM UTC 24 |
Oct 12 01:00:38 AM UTC 24 |
426937105171 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.1631832144 |
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Oct 12 01:00:30 AM UTC 24 |
Oct 12 01:00:39 AM UTC 24 |
2114586075 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3059737337 |
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Oct 12 01:00:24 AM UTC 24 |
Oct 12 01:00:39 AM UTC 24 |
5209671832 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3136788575 |
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|
Oct 12 01:00:17 AM UTC 24 |
Oct 12 01:00:41 AM UTC 24 |
33494577775 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2664886131 |
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Oct 12 01:00:15 AM UTC 24 |
Oct 12 01:00:41 AM UTC 24 |
412726960988 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1820272835 |
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Oct 12 01:00:25 AM UTC 24 |
Oct 12 01:00:41 AM UTC 24 |
8273286387 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.602597253 |
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Oct 12 01:00:35 AM UTC 24 |
Oct 12 01:00:41 AM UTC 24 |
3329585867 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2898580751 |
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Oct 12 01:00:34 AM UTC 24 |
Oct 12 01:00:43 AM UTC 24 |
2611813020 ps |
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/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2152314392 |
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Oct 12 01:00:38 AM UTC 24 |
Oct 12 01:00:43 AM UTC 24 |
2811905267 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1382864695 |
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Oct 12 01:00:18 AM UTC 24 |
Oct 12 01:00:43 AM UTC 24 |
6129330675 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.1357397996 |
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Oct 12 01:00:19 AM UTC 24 |
Oct 12 01:00:44 AM UTC 24 |
15786673461 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.1860279619 |
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Oct 12 01:00:41 AM UTC 24 |
Oct 12 01:00:45 AM UTC 24 |
2143182998 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.4135285683 |
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Oct 12 01:00:44 AM UTC 24 |
Oct 12 01:00:48 AM UTC 24 |
4958596755 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3193597710 |
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Oct 12 01:00:55 AM UTC 24 |
Oct 12 01:01:01 AM UTC 24 |
3704651119 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.455359736 |
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Oct 12 01:00:46 AM UTC 24 |
Oct 12 01:00:48 AM UTC 24 |
7448770677 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.1982264005 |
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Oct 12 01:00:40 AM UTC 24 |
Oct 12 01:00:48 AM UTC 24 |
11162820843 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1444782868 |
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Oct 12 01:00:40 AM UTC 24 |
Oct 12 01:00:49 AM UTC 24 |
2013100528 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3690494034 |
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Oct 12 01:00:35 AM UTC 24 |
Oct 12 01:00:50 AM UTC 24 |
3283672115 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.1425062365 |
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Oct 12 01:00:42 AM UTC 24 |
Oct 12 01:00:50 AM UTC 24 |
2454408892 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2300394676 |
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Oct 12 01:00:36 AM UTC 24 |
Oct 12 01:00:51 AM UTC 24 |
6939181376 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3410806937 |
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Oct 12 01:00:44 AM UTC 24 |
Oct 12 01:00:51 AM UTC 24 |
3680278706 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3634422996 |
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Oct 12 01:00:44 AM UTC 24 |
Oct 12 01:00:52 AM UTC 24 |
2620940763 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.931514091 |
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Oct 12 01:00:42 AM UTC 24 |
Oct 12 01:00:53 AM UTC 24 |
2512688267 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.1679793892 |
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Oct 12 01:00:42 AM UTC 24 |
Oct 12 01:00:54 AM UTC 24 |
2254071002 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.631280134 |
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Oct 12 01:00:50 AM UTC 24 |
Oct 12 01:00:55 AM UTC 24 |
2033830775 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2043771048 |
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Oct 12 12:58:07 AM UTC 24 |
Oct 12 01:00:55 AM UTC 24 |
99767950671 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.3984538135 |
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Oct 12 01:00:51 AM UTC 24 |
Oct 12 01:00:56 AM UTC 24 |
2501070211 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2891979280 |
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Oct 12 01:00:51 AM UTC 24 |
Oct 12 01:00:57 AM UTC 24 |
2270792391 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2401786742 |
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Oct 12 01:00:39 AM UTC 24 |
Oct 12 01:00:57 AM UTC 24 |
11162551725 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.505197444 |
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Oct 12 12:57:04 AM UTC 24 |
Oct 12 01:00:59 AM UTC 24 |
319871515612 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.2447354881 |
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Oct 12 01:00:51 AM UTC 24 |
Oct 12 01:01:01 AM UTC 24 |
2508349118 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1650580754 |
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Oct 12 01:00:49 AM UTC 24 |
Oct 12 01:01:03 AM UTC 24 |
3599739605 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3829320994 |
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Oct 12 12:59:40 AM UTC 24 |
Oct 12 01:01:03 AM UTC 24 |
118583100395 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.996807621 |
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Oct 12 01:01:00 AM UTC 24 |
Oct 12 01:01:03 AM UTC 24 |
2039413945 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.4262850606 |
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Oct 12 01:00:53 AM UTC 24 |
Oct 12 01:01:04 AM UTC 24 |
2609830683 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3905867398 |
|
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Oct 12 01:00:58 AM UTC 24 |
Oct 12 01:01:06 AM UTC 24 |
3337185041 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.1312377978 |
|
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Oct 12 01:01:02 AM UTC 24 |
Oct 12 01:01:07 AM UTC 24 |
2507535860 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3971652547 |
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Oct 12 01:01:01 AM UTC 24 |
Oct 12 01:01:07 AM UTC 24 |
2119257243 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.4085915825 |
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Oct 12 01:01:04 AM UTC 24 |
Oct 12 01:01:07 AM UTC 24 |
2241609486 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.451500288 |
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Oct 12 01:01:04 AM UTC 24 |
Oct 12 01:01:08 AM UTC 24 |
2522627829 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.375571646 |
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Oct 12 01:00:49 AM UTC 24 |
Oct 12 01:01:08 AM UTC 24 |
3978704850 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1978307176 |
|
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Oct 12 01:01:06 AM UTC 24 |
Oct 12 01:01:09 AM UTC 24 |
4470993641 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3835692866 |
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Oct 12 01:01:00 AM UTC 24 |
Oct 12 01:01:10 AM UTC 24 |
11163184618 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.519405958 |
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Oct 12 01:01:07 AM UTC 24 |
Oct 12 01:01:11 AM UTC 24 |
3498180186 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3709870175 |
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Oct 12 01:00:54 AM UTC 24 |
Oct 12 01:01:13 AM UTC 24 |
4584364617 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1219155510 |
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Oct 12 01:00:39 AM UTC 24 |
Oct 12 01:01:14 AM UTC 24 |
54807210043 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.4204879855 |
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Oct 12 01:00:57 AM UTC 24 |
Oct 12 01:01:14 AM UTC 24 |
3516778062 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.826686412 |
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Oct 12 01:01:05 AM UTC 24 |
Oct 12 01:01:15 AM UTC 24 |
2613147998 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.827170528 |
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Oct 12 01:01:09 AM UTC 24 |
Oct 12 01:01:16 AM UTC 24 |
6973170957 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.1483706410 |
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Oct 12 12:57:31 AM UTC 24 |
Oct 12 01:01:17 AM UTC 24 |
87956042615 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.3989018581 |
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Oct 12 01:00:27 AM UTC 24 |
Oct 12 01:01:18 AM UTC 24 |
14482463340 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2337143457 |
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Oct 12 01:01:12 AM UTC 24 |
Oct 12 01:01:18 AM UTC 24 |
2019438937 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.43141907 |
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Oct 12 01:01:08 AM UTC 24 |
Oct 12 01:01:18 AM UTC 24 |
4039079153 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.1622780231 |
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Oct 12 01:01:15 AM UTC 24 |
Oct 12 01:01:19 AM UTC 24 |
2129961703 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.1126885780 |
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Oct 12 01:01:15 AM UTC 24 |
Oct 12 01:01:20 AM UTC 24 |
2528049051 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.4169695122 |
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Oct 12 01:01:12 AM UTC 24 |
Oct 12 01:01:20 AM UTC 24 |
2112846389 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2044164809 |
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Oct 12 01:01:08 AM UTC 24 |
Oct 12 01:01:20 AM UTC 24 |
5457271484 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1206571768 |
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Oct 12 01:01:17 AM UTC 24 |
Oct 12 01:01:23 AM UTC 24 |
4200985829 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1238469145 |
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Oct 12 01:01:16 AM UTC 24 |
Oct 12 01:01:24 AM UTC 24 |
2617073547 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.5886012 |
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Oct 12 01:01:19 AM UTC 24 |
Oct 12 01:01:24 AM UTC 24 |
2711890345 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2867653854 |
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Oct 12 12:59:42 AM UTC 24 |
Oct 12 01:01:25 AM UTC 24 |
27583314739 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.107667525 |
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Oct 12 01:01:22 AM UTC 24 |
Oct 12 01:01:26 AM UTC 24 |
2028476747 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.4010860357 |
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Oct 12 01:01:18 AM UTC 24 |
Oct 12 01:01:27 AM UTC 24 |
3437122943 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.2573679010 |
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Oct 12 01:01:14 AM UTC 24 |
Oct 12 01:01:27 AM UTC 24 |
2449293463 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.3549526872 |
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Oct 12 01:01:26 AM UTC 24 |
Oct 12 01:01:30 AM UTC 24 |
2554982053 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3208099505 |
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Oct 12 01:01:25 AM UTC 24 |
Oct 12 01:01:30 AM UTC 24 |
2475064424 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.560990305 |
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Oct 12 12:59:26 AM UTC 24 |
Oct 12 01:01:30 AM UTC 24 |
68224760224 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1393378000 |
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Oct 12 01:01:20 AM UTC 24 |
Oct 12 01:01:31 AM UTC 24 |
4420767274 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.642126624 |
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Oct 12 01:01:18 AM UTC 24 |
Oct 12 01:01:32 AM UTC 24 |
5415672691 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3116559939 |
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Oct 12 01:01:28 AM UTC 24 |
Oct 12 01:01:32 AM UTC 24 |
3982926593 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.115521796 |
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Oct 12 01:01:22 AM UTC 24 |
Oct 12 01:01:33 AM UTC 24 |
8592169527 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.1159618520 |
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Oct 12 01:01:31 AM UTC 24 |
Oct 12 01:01:36 AM UTC 24 |
4421798532 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.1490679019 |
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Oct 12 01:01:25 AM UTC 24 |
Oct 12 01:01:36 AM UTC 24 |
2067364657 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.3002179530 |
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Oct 12 01:01:25 AM UTC 24 |
Oct 12 01:01:36 AM UTC 24 |
2109301864 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.1486915918 |
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Oct 12 01:01:34 AM UTC 24 |
Oct 12 01:01:38 AM UTC 24 |
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| T360 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.2523334666 |
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Oct 12 12:56:35 AM UTC 24 |
Oct 12 01:01:40 AM UTC 24 |
99285089460 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1151373750 |
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Oct 12 01:01:27 AM UTC 24 |
Oct 12 01:01:41 AM UTC 24 |
2613521794 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3967960759 |
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Oct 12 12:58:57 AM UTC 24 |
Oct 12 01:01:43 AM UTC 24 |
54378176558 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.4027012489 |
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Oct 12 01:01:37 AM UTC 24 |
Oct 12 01:01:44 AM UTC 24 |
2244574496 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.281989910 |
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Oct 12 01:01:28 AM UTC 24 |
Oct 12 01:01:44 AM UTC 24 |
4586198897 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.1851574601 |
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Oct 12 12:57:02 AM UTC 24 |
Oct 12 01:01:45 AM UTC 24 |
98647856247 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.62256279 |
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Oct 12 01:01:39 AM UTC 24 |
Oct 12 01:01:45 AM UTC 24 |
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| T643 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.850715242 |
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Oct 12 01:01:33 AM UTC 24 |
Oct 12 01:01:46 AM UTC 24 |
3416762736 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3795400469 |
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Oct 12 01:01:41 AM UTC 24 |
Oct 12 01:01:46 AM UTC 24 |
2629366153 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.2300741770 |
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Oct 12 01:01:37 AM UTC 24 |
Oct 12 01:01:47 AM UTC 24 |
2115562845 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.3019243492 |
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Oct 12 01:01:48 AM UTC 24 |
Oct 12 01:01:51 AM UTC 24 |
2083439060 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4173910725 |
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Oct 12 01:01:44 AM UTC 24 |
Oct 12 01:01:51 AM UTC 24 |
6013131124 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1765407822 |
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Oct 12 01:01:37 AM UTC 24 |
Oct 12 01:01:51 AM UTC 24 |
2461002145 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.4091014581 |
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Oct 12 01:00:49 AM UTC 24 |
Oct 12 01:01:52 AM UTC 24 |
65049709023 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4055916320 |
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Oct 12 01:00:49 AM UTC 24 |
Oct 12 01:01:54 AM UTC 24 |
91629629428 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1313649952 |
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Oct 12 01:01:42 AM UTC 24 |
Oct 12 01:01:55 AM UTC 24 |
3093099959 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2278601328 |
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Oct 12 01:01:47 AM UTC 24 |
Oct 12 01:01:56 AM UTC 24 |
9082026419 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.3878224990 |
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Oct 12 01:01:52 AM UTC 24 |
Oct 12 01:01:56 AM UTC 24 |
2132359912 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3541419784 |
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Oct 12 01:01:52 AM UTC 24 |
Oct 12 01:01:56 AM UTC 24 |
2167585217 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1383038149 |
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Oct 12 01:01:43 AM UTC 24 |
Oct 12 01:01:57 AM UTC 24 |
3401826145 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.2769241945 |
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Oct 12 01:01:46 AM UTC 24 |
Oct 12 01:01:57 AM UTC 24 |
2639921142 ps |