| T367 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2759573596 |
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Oct 12 12:59:09 AM UTC 24 |
Oct 12 01:01:57 AM UTC 24 |
42950870777 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.1957093305 |
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Oct 12 01:01:53 AM UTC 24 |
Oct 12 01:01:58 AM UTC 24 |
2518559464 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.2707895290 |
|
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Oct 12 01:01:52 AM UTC 24 |
Oct 12 01:02:01 AM UTC 24 |
2458005408 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1124632853 |
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Oct 12 01:01:54 AM UTC 24 |
Oct 12 01:02:03 AM UTC 24 |
2610347204 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2233663230 |
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Oct 12 01:01:46 AM UTC 24 |
Oct 12 01:02:07 AM UTC 24 |
23362448763 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1530500521 |
|
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Oct 12 01:01:47 AM UTC 24 |
Oct 12 01:02:07 AM UTC 24 |
4136515098 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.2575558966 |
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Oct 12 01:01:56 AM UTC 24 |
Oct 12 01:02:08 AM UTC 24 |
4228287473 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.2472535051 |
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Oct 12 01:01:34 AM UTC 24 |
Oct 12 01:02:09 AM UTC 24 |
14759871310 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2128303855 |
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Oct 12 01:02:03 AM UTC 24 |
Oct 12 01:02:10 AM UTC 24 |
2119418882 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.4103021735 |
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Oct 12 01:01:58 AM UTC 24 |
Oct 12 01:02:10 AM UTC 24 |
7422100435 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3854928054 |
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Oct 12 12:57:43 AM UTC 24 |
Oct 12 01:02:11 AM UTC 24 |
79458403599 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.537564961 |
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Oct 12 01:02:07 AM UTC 24 |
Oct 12 01:02:13 AM UTC 24 |
2489938022 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2104070541 |
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Oct 12 01:01:57 AM UTC 24 |
Oct 12 01:02:13 AM UTC 24 |
3532350921 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3153878793 |
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Oct 12 01:02:02 AM UTC 24 |
Oct 12 01:02:13 AM UTC 24 |
2014357537 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.2352327037 |
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Oct 12 12:59:54 AM UTC 24 |
Oct 12 01:02:13 AM UTC 24 |
176111015648 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3589504192 |
|
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Oct 12 01:02:10 AM UTC 24 |
Oct 12 01:02:14 AM UTC 24 |
2641861335 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2289832329 |
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Oct 12 01:01:58 AM UTC 24 |
Oct 12 01:02:15 AM UTC 24 |
14867065436 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.223526155 |
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Oct 12 01:02:14 AM UTC 24 |
Oct 12 01:02:18 AM UTC 24 |
5418146384 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1684225974 |
|
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Oct 12 01:02:11 AM UTC 24 |
Oct 12 01:02:19 AM UTC 24 |
3480713939 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.2408996309 |
|
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Oct 12 12:58:57 AM UTC 24 |
Oct 12 01:02:19 AM UTC 24 |
121905003954 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2968991695 |
|
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Oct 12 01:01:30 AM UTC 24 |
Oct 12 01:02:20 AM UTC 24 |
1071353253739 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2061437348 |
|
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Oct 12 01:02:08 AM UTC 24 |
Oct 12 01:02:21 AM UTC 24 |
2234032436 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1147686739 |
|
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Oct 12 12:57:53 AM UTC 24 |
Oct 12 01:02:22 AM UTC 24 |
94032465616 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.3226425916 |
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Oct 12 01:02:10 AM UTC 24 |
Oct 12 01:02:23 AM UTC 24 |
2513340520 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3252874908 |
|
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Oct 12 12:56:47 AM UTC 24 |
Oct 12 01:02:23 AM UTC 24 |
120281190265 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2845928989 |
|
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Oct 12 01:02:16 AM UTC 24 |
Oct 12 01:02:25 AM UTC 24 |
2010371728 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.248626127 |
|
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Oct 12 01:02:11 AM UTC 24 |
Oct 12 01:02:25 AM UTC 24 |
3001471010 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1817737706 |
|
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Oct 12 01:02:22 AM UTC 24 |
Oct 12 01:02:26 AM UTC 24 |
2645893545 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.2116136729 |
|
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Oct 12 01:02:19 AM UTC 24 |
Oct 12 01:02:26 AM UTC 24 |
2111901225 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.558510981 |
|
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Oct 12 01:02:21 AM UTC 24 |
Oct 12 01:02:27 AM UTC 24 |
2076314787 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1130445676 |
|
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Oct 12 12:56:44 AM UTC 24 |
Oct 12 01:02:28 AM UTC 24 |
110257803031 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.1539590055 |
|
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Oct 12 12:56:36 AM UTC 24 |
Oct 12 01:02:29 AM UTC 24 |
115866172406 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2823540278 |
|
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Oct 12 01:02:24 AM UTC 24 |
Oct 12 01:02:30 AM UTC 24 |
2894391784 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.206427533 |
|
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Oct 12 01:02:24 AM UTC 24 |
Oct 12 01:02:30 AM UTC 24 |
3345123492 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2828259206 |
|
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Oct 12 01:02:21 AM UTC 24 |
Oct 12 01:02:30 AM UTC 24 |
2508791419 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.2407416873 |
|
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Oct 12 01:02:29 AM UTC 24 |
Oct 12 01:02:32 AM UTC 24 |
2048229040 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.3454732751 |
|
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Oct 12 01:02:21 AM UTC 24 |
Oct 12 01:02:33 AM UTC 24 |
2449115917 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1506836802 |
|
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Oct 12 01:02:26 AM UTC 24 |
Oct 12 01:02:34 AM UTC 24 |
3239628741 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1139709938 |
|
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Oct 12 01:02:31 AM UTC 24 |
Oct 12 01:02:35 AM UTC 24 |
2050568780 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2166489103 |
|
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Oct 12 01:02:24 AM UTC 24 |
Oct 12 01:02:36 AM UTC 24 |
4435804514 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.866314543 |
|
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Oct 12 01:02:14 AM UTC 24 |
Oct 12 01:02:37 AM UTC 24 |
8967913526 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2017420675 |
|
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Oct 12 01:02:32 AM UTC 24 |
Oct 12 01:02:37 AM UTC 24 |
2626244911 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.252052943 |
|
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Oct 12 12:56:57 AM UTC 24 |
Oct 12 01:02:37 AM UTC 24 |
2064776300498 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.303957449 |
|
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Oct 12 01:01:08 AM UTC 24 |
Oct 12 01:02:38 AM UTC 24 |
117601950083 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.764985040 |
|
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Oct 12 01:02:31 AM UTC 24 |
Oct 12 01:02:38 AM UTC 24 |
2115824228 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1490670132 |
|
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Oct 12 01:02:35 AM UTC 24 |
Oct 12 01:02:38 AM UTC 24 |
3342147527 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.314025286 |
|
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Oct 12 01:01:20 AM UTC 24 |
Oct 12 01:02:40 AM UTC 24 |
147671290556 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.3428505207 |
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Oct 12 12:56:58 AM UTC 24 |
Oct 12 01:02:42 AM UTC 24 |
132564205505 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2774988057 |
|
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Oct 12 12:59:25 AM UTC 24 |
Oct 12 01:02:43 AM UTC 24 |
73557118972 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.2797906005 |
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Oct 12 01:02:31 AM UTC 24 |
Oct 12 01:02:44 AM UTC 24 |
2510801352 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2582652685 |
|
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Oct 12 01:02:31 AM UTC 24 |
Oct 12 01:02:44 AM UTC 24 |
2449998826 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.4007701315 |
|
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Oct 12 01:02:39 AM UTC 24 |
Oct 12 01:02:44 AM UTC 24 |
14998415561 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1247929094 |
|
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Oct 12 01:02:41 AM UTC 24 |
Oct 12 01:02:46 AM UTC 24 |
2475640250 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1423450801 |
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Oct 12 01:02:42 AM UTC 24 |
Oct 12 01:02:46 AM UTC 24 |
2163380927 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.1613576062 |
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Oct 12 01:02:14 AM UTC 24 |
Oct 12 01:02:47 AM UTC 24 |
66216684026 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3398427355 |
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Oct 12 01:00:57 AM UTC 24 |
Oct 12 01:02:47 AM UTC 24 |
74568761086 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2924308296 |
|
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Oct 12 01:02:35 AM UTC 24 |
Oct 12 01:02:47 AM UTC 24 |
3473216372 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1422810553 |
|
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Oct 12 01:02:45 AM UTC 24 |
Oct 12 01:02:48 AM UTC 24 |
2663293481 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.573328215 |
|
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Oct 12 01:02:27 AM UTC 24 |
Oct 12 01:02:48 AM UTC 24 |
5123789608 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.3328547709 |
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Oct 12 01:02:29 AM UTC 24 |
Oct 12 01:02:48 AM UTC 24 |
16060158492 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.2046543656 |
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Oct 12 01:02:44 AM UTC 24 |
Oct 12 01:02:49 AM UTC 24 |
2538743845 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3257532765 |
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Oct 12 01:02:39 AM UTC 24 |
Oct 12 01:02:49 AM UTC 24 |
30716967835 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2317203949 |
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Oct 12 01:02:14 AM UTC 24 |
Oct 12 01:02:50 AM UTC 24 |
56184514524 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.984676658 |
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Oct 12 01:02:39 AM UTC 24 |
Oct 12 01:02:50 AM UTC 24 |
2111283320 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4065067035 |
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Oct 12 01:02:45 AM UTC 24 |
Oct 12 01:02:50 AM UTC 24 |
5660479602 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.3511101988 |
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Oct 12 01:02:15 AM UTC 24 |
Oct 12 01:02:51 AM UTC 24 |
12267216923 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1305615595 |
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Oct 12 01:02:46 AM UTC 24 |
Oct 12 01:02:51 AM UTC 24 |
5830227806 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.876738304 |
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Oct 12 01:02:39 AM UTC 24 |
Oct 12 01:02:52 AM UTC 24 |
2014237371 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.347178665 |
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Oct 12 01:02:49 AM UTC 24 |
Oct 12 01:02:52 AM UTC 24 |
2139893685 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2194321310 |
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Oct 12 01:02:34 AM UTC 24 |
Oct 12 01:02:53 AM UTC 24 |
3974813848 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.1826126516 |
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Oct 12 01:02:50 AM UTC 24 |
Oct 12 01:02:54 AM UTC 24 |
2473828604 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.3883475038 |
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Oct 12 01:02:50 AM UTC 24 |
Oct 12 01:02:55 AM UTC 24 |
2117236568 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3463758729 |
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Oct 12 01:02:51 AM UTC 24 |
Oct 12 01:02:55 AM UTC 24 |
2565173036 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.605735248 |
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Oct 12 01:01:30 AM UTC 24 |
Oct 12 01:02:55 AM UTC 24 |
77465137252 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4047159374 |
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Oct 12 01:02:53 AM UTC 24 |
Oct 12 01:02:55 AM UTC 24 |
5222501503 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.2021122941 |
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Oct 12 01:02:49 AM UTC 24 |
Oct 12 01:02:56 AM UTC 24 |
12399681225 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1707631288 |
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Oct 12 01:02:51 AM UTC 24 |
Oct 12 01:02:56 AM UTC 24 |
2638886665 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2947578693 |
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Oct 12 01:02:45 AM UTC 24 |
Oct 12 01:02:57 AM UTC 24 |
3289969279 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3866283208 |
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Oct 12 01:02:53 AM UTC 24 |
Oct 12 01:02:57 AM UTC 24 |
2461122660 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2991338033 |
|
|
Oct 12 01:00:14 AM UTC 24 |
Oct 12 01:02:58 AM UTC 24 |
40438213980 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.2685486959 |
|
|
Oct 12 01:02:49 AM UTC 24 |
Oct 12 01:02:58 AM UTC 24 |
2014504863 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.3664153918 |
|
|
Oct 12 01:02:48 AM UTC 24 |
Oct 12 01:02:59 AM UTC 24 |
5603047390 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.775494067 |
|
|
Oct 12 01:02:49 AM UTC 24 |
Oct 12 01:02:59 AM UTC 24 |
4878916565 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.3887477228 |
|
|
Oct 12 01:02:56 AM UTC 24 |
Oct 12 01:03:00 AM UTC 24 |
2121424122 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.3784490132 |
|
|
Oct 12 01:02:56 AM UTC 24 |
Oct 12 01:03:00 AM UTC 24 |
2060732336 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.2679909389 |
|
|
Oct 12 01:02:56 AM UTC 24 |
Oct 12 01:03:01 AM UTC 24 |
2238912142 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.149383217 |
|
|
Oct 12 01:02:58 AM UTC 24 |
Oct 12 01:03:01 AM UTC 24 |
2537999466 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.1433067500 |
|
|
Oct 12 01:02:56 AM UTC 24 |
Oct 12 01:03:02 AM UTC 24 |
2454346532 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1434119658 |
|
|
Oct 12 01:02:58 AM UTC 24 |
Oct 12 01:03:03 AM UTC 24 |
2630660392 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2284821827 |
|
|
Oct 12 01:02:55 AM UTC 24 |
Oct 12 01:03:03 AM UTC 24 |
10932373606 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1607298714 |
|
|
Oct 12 01:02:52 AM UTC 24 |
Oct 12 01:03:04 AM UTC 24 |
4283331355 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.909376819 |
|
|
Oct 12 01:03:02 AM UTC 24 |
Oct 12 01:03:05 AM UTC 24 |
2068143394 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.981627701 |
|
|
Oct 12 01:02:53 AM UTC 24 |
Oct 12 01:03:05 AM UTC 24 |
3440396624 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.2823709412 |
|
|
Oct 12 01:03:04 AM UTC 24 |
Oct 12 01:03:06 AM UTC 24 |
2574840578 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2946313359 |
|
|
Oct 12 01:02:59 AM UTC 24 |
Oct 12 01:03:07 AM UTC 24 |
3520325181 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.2009521052 |
|
|
Oct 12 01:02:55 AM UTC 24 |
Oct 12 01:03:08 AM UTC 24 |
12286917984 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.3841255560 |
|
|
Oct 12 01:03:04 AM UTC 24 |
Oct 12 01:03:08 AM UTC 24 |
2056643086 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3646148542 |
|
|
Oct 12 01:02:59 AM UTC 24 |
Oct 12 01:03:08 AM UTC 24 |
3173503555 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.3875081232 |
|
|
Oct 12 01:03:05 AM UTC 24 |
Oct 12 01:03:09 AM UTC 24 |
2527343597 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.899873444 |
|
|
Oct 12 01:03:06 AM UTC 24 |
Oct 12 01:03:09 AM UTC 24 |
2538318184 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3734346382 |
|
|
Oct 12 01:02:26 AM UTC 24 |
Oct 12 01:03:10 AM UTC 24 |
27084154299 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.864999286 |
|
|
Oct 12 01:03:06 AM UTC 24 |
Oct 12 01:03:11 AM UTC 24 |
2631623160 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.3783135222 |
|
|
Oct 12 01:03:00 AM UTC 24 |
Oct 12 01:03:11 AM UTC 24 |
4127938567 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1283238886 |
|
|
Oct 12 01:03:07 AM UTC 24 |
Oct 12 01:03:13 AM UTC 24 |
99487980982 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.481582323 |
|
|
Oct 12 01:03:09 AM UTC 24 |
Oct 12 01:03:13 AM UTC 24 |
3285428007 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.2819977482 |
|
|
Oct 12 01:03:02 AM UTC 24 |
Oct 12 01:03:14 AM UTC 24 |
2110673915 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.531060001 |
|
|
Oct 12 01:03:12 AM UTC 24 |
Oct 12 01:03:15 AM UTC 24 |
2159459314 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2056306052 |
|
|
Oct 12 01:03:11 AM UTC 24 |
Oct 12 01:03:15 AM UTC 24 |
2040737317 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.3226434036 |
|
|
Oct 12 01:02:37 AM UTC 24 |
Oct 12 01:03:16 AM UTC 24 |
299316466288 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.450286965 |
|
|
Oct 12 12:58:36 AM UTC 24 |
Oct 12 01:03:16 AM UTC 24 |
81318530938 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3757013206 |
|
|
Oct 12 01:01:58 AM UTC 24 |
Oct 12 01:03:16 AM UTC 24 |
97804808637 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4060302728 |
|
|
Oct 12 01:02:59 AM UTC 24 |
Oct 12 01:03:16 AM UTC 24 |
5234991581 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3941330817 |
|
|
Oct 12 01:01:58 AM UTC 24 |
Oct 12 01:03:18 AM UTC 24 |
75601526020 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.919802391 |
|
|
Oct 12 01:03:14 AM UTC 24 |
Oct 12 01:03:18 AM UTC 24 |
2163856587 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1158161060 |
|
|
Oct 12 01:03:09 AM UTC 24 |
Oct 12 01:03:19 AM UTC 24 |
7998803309 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3100020060 |
|
|
Oct 12 01:03:01 AM UTC 24 |
Oct 12 01:03:19 AM UTC 24 |
6547916702 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1189417913 |
|
|
Oct 12 01:03:16 AM UTC 24 |
Oct 12 01:03:20 AM UTC 24 |
2620640571 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3129211224 |
|
|
Oct 12 01:03:15 AM UTC 24 |
Oct 12 01:03:21 AM UTC 24 |
2839450172 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1821498660 |
|
|
Oct 12 01:03:16 AM UTC 24 |
Oct 12 01:03:21 AM UTC 24 |
3533131221 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.698910225 |
|
|
Oct 12 01:00:27 AM UTC 24 |
Oct 12 01:03:22 AM UTC 24 |
58697437284 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1666068668 |
|
|
Oct 12 01:03:15 AM UTC 24 |
Oct 12 01:03:22 AM UTC 24 |
2613788342 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3226465152 |
|
|
Oct 12 01:03:17 AM UTC 24 |
Oct 12 01:03:22 AM UTC 24 |
4129757277 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.2203617552 |
|
|
Oct 12 01:03:20 AM UTC 24 |
Oct 12 01:03:23 AM UTC 24 |
2144365586 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2070289960 |
|
|
Oct 12 01:03:01 AM UTC 24 |
Oct 12 01:03:23 AM UTC 24 |
40612072244 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.912825178 |
|
|
Oct 12 01:03:07 AM UTC 24 |
Oct 12 01:03:23 AM UTC 24 |
3476562236 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.2325602617 |
|
|
Oct 12 01:03:20 AM UTC 24 |
Oct 12 01:03:24 AM UTC 24 |
2026342895 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1517448154 |
|
|
Oct 12 01:03:12 AM UTC 24 |
Oct 12 01:03:25 AM UTC 24 |
2461545911 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.108658837 |
|
|
Oct 12 01:03:14 AM UTC 24 |
Oct 12 01:03:27 AM UTC 24 |
2514327425 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1566602886 |
|
|
Oct 12 01:01:08 AM UTC 24 |
Oct 12 01:03:27 AM UTC 24 |
151668875777 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.3544281857 |
|
|
Oct 12 01:03:22 AM UTC 24 |
Oct 12 01:03:27 AM UTC 24 |
2528298183 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.431004408 |
|
|
Oct 12 01:03:01 AM UTC 24 |
Oct 12 01:03:27 AM UTC 24 |
18000549628 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.492513206 |
|
|
Oct 12 01:03:23 AM UTC 24 |
Oct 12 01:03:28 AM UTC 24 |
2623621762 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.1231777601 |
|
|
Oct 12 01:03:25 AM UTC 24 |
Oct 12 01:03:29 AM UTC 24 |
4030810173 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1995319994 |
|
|
Oct 12 01:03:23 AM UTC 24 |
Oct 12 01:03:31 AM UTC 24 |
3063755044 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.1487452316 |
|
|
Oct 12 01:03:28 AM UTC 24 |
Oct 12 01:03:31 AM UTC 24 |
2097034834 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.4284383632 |
|
|
Oct 12 01:03:22 AM UTC 24 |
Oct 12 01:03:31 AM UTC 24 |
2164867758 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.1341025918 |
|
|
Oct 12 01:03:28 AM UTC 24 |
Oct 12 01:03:32 AM UTC 24 |
2506515908 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.333598659 |
|
|
Oct 12 01:03:21 AM UTC 24 |
Oct 12 01:03:32 AM UTC 24 |
2452528214 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1462135870 |
|
|
Oct 12 01:03:30 AM UTC 24 |
Oct 12 01:03:34 AM UTC 24 |
2631287355 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1913728310 |
|
|
Oct 12 01:03:33 AM UTC 24 |
Oct 12 01:03:36 AM UTC 24 |
4705515394 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2280963253 |
|
|
Oct 12 01:02:12 AM UTC 24 |
Oct 12 01:03:36 AM UTC 24 |
662835078684 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.1370817682 |
|
|
Oct 12 01:03:29 AM UTC 24 |
Oct 12 01:03:37 AM UTC 24 |
2514609036 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.1995639552 |
|
|
Oct 12 01:01:33 AM UTC 24 |
Oct 12 01:03:37 AM UTC 24 |
53509148397 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3343159972 |
|
|
Oct 12 01:03:32 AM UTC 24 |
Oct 12 01:03:38 AM UTC 24 |
3433675016 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4279627877 |
|
|
Oct 12 01:03:26 AM UTC 24 |
Oct 12 01:03:38 AM UTC 24 |
2974535617 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3052995830 |
|
|
Oct 12 01:03:28 AM UTC 24 |
Oct 12 01:03:39 AM UTC 24 |
2110508147 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3461728674 |
|
|
Oct 12 01:03:08 AM UTC 24 |
Oct 12 01:03:39 AM UTC 24 |
159386548400 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2199437882 |
|
|
Oct 12 01:03:19 AM UTC 24 |
Oct 12 01:03:40 AM UTC 24 |
5899859911 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.1783358159 |
|
|
Oct 12 01:03:29 AM UTC 24 |
Oct 12 01:03:40 AM UTC 24 |
2165027431 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3665682321 |
|
|
Oct 12 01:03:37 AM UTC 24 |
Oct 12 01:03:40 AM UTC 24 |
2065152461 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.4173254477 |
|
|
Oct 12 01:03:40 AM UTC 24 |
Oct 12 01:03:44 AM UTC 24 |
2229666683 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.2464628018 |
|
|
Oct 12 01:01:58 AM UTC 24 |
Oct 12 01:03:44 AM UTC 24 |
229976575249 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.3302301432 |
|
|
Oct 12 01:03:33 AM UTC 24 |
Oct 12 01:03:44 AM UTC 24 |
3020702172 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2738448560 |
|
|
Oct 12 01:03:32 AM UTC 24 |
Oct 12 01:03:45 AM UTC 24 |
3288519710 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.2387211825 |
|
|
Oct 12 01:03:38 AM UTC 24 |
Oct 12 01:03:46 AM UTC 24 |
2109880708 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.1986668884 |
|
|
Oct 12 01:03:38 AM UTC 24 |
Oct 12 01:03:46 AM UTC 24 |
2463601373 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.81638670 |
|
|
Oct 12 01:03:40 AM UTC 24 |
Oct 12 01:03:50 AM UTC 24 |
2613196718 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2421538804 |
|
|
Oct 12 01:03:45 AM UTC 24 |
Oct 12 01:03:50 AM UTC 24 |
3953976432 ps |
| T756 |
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Oct 12 01:03:37 AM UTC 24 |
Oct 12 01:03:50 AM UTC 24 |
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| T397 |
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Oct 12 12:57:24 AM UTC 24 |
Oct 12 01:03:51 AM UTC 24 |
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Oct 12 01:03:41 AM UTC 24 |
Oct 12 01:03:52 AM UTC 24 |
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Oct 12 01:03:47 AM UTC 24 |
Oct 12 01:03:52 AM UTC 24 |
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Oct 12 01:03:40 AM UTC 24 |
Oct 12 01:03:54 AM UTC 24 |
2507961820 ps |
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Oct 12 01:03:41 AM UTC 24 |
Oct 12 01:03:56 AM UTC 24 |
3342286839 ps |
| T761 |
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Oct 12 01:03:46 AM UTC 24 |
Oct 12 01:03:59 AM UTC 24 |
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Oct 12 01:03:27 AM UTC 24 |
Oct 12 01:04:00 AM UTC 24 |
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Oct 12 01:03:37 AM UTC 24 |
Oct 12 01:04:02 AM UTC 24 |
8632248650 ps |
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Oct 12 01:03:25 AM UTC 24 |
Oct 12 01:04:04 AM UTC 24 |
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Oct 12 01:02:39 AM UTC 24 |
Oct 12 01:04:14 AM UTC 24 |
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Oct 12 01:00:15 AM UTC 24 |
Oct 12 01:04:17 AM UTC 24 |
75020578222 ps |
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Oct 12 01:03:53 AM UTC 24 |
Oct 12 01:04:18 AM UTC 24 |
49119885128 ps |
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Oct 12 01:02:48 AM UTC 24 |
Oct 12 01:04:20 AM UTC 24 |
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Oct 12 01:03:54 AM UTC 24 |
Oct 12 01:04:26 AM UTC 24 |
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Oct 12 01:01:59 AM UTC 24 |
Oct 12 01:04:29 AM UTC 24 |
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Oct 12 01:04:06 AM UTC 24 |
Oct 12 01:04:32 AM UTC 24 |
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Oct 12 01:03:51 AM UTC 24 |
Oct 12 01:04:33 AM UTC 24 |
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Oct 12 01:03:52 AM UTC 24 |
Oct 12 01:04:34 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3038632970 |
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Oct 12 01:02:54 AM UTC 24 |
Oct 12 01:04:36 AM UTC 24 |
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Oct 12 01:00:46 AM UTC 24 |
Oct 12 01:04:39 AM UTC 24 |
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Oct 12 01:03:00 AM UTC 24 |
Oct 12 01:04:41 AM UTC 24 |
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Oct 12 01:03:57 AM UTC 24 |
Oct 12 01:04:46 AM UTC 24 |
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Oct 12 01:04:19 AM UTC 24 |
Oct 12 01:04:47 AM UTC 24 |
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Oct 12 12:59:07 AM UTC 24 |
Oct 12 01:04:47 AM UTC 24 |
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Oct 12 01:02:48 AM UTC 24 |
Oct 12 01:04:48 AM UTC 24 |
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Oct 12 01:03:53 AM UTC 24 |
Oct 12 01:04:50 AM UTC 24 |
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Oct 12 01:00:25 AM UTC 24 |
Oct 12 01:04:52 AM UTC 24 |
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Oct 12 01:00:36 AM UTC 24 |
Oct 12 01:04:57 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.1452955502 |
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Oct 12 12:58:01 AM UTC 24 |
Oct 12 01:05:04 AM UTC 24 |
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Oct 12 01:04:00 AM UTC 24 |
Oct 12 01:05:08 AM UTC 24 |
61911128427 ps |
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Oct 12 01:05:25 AM UTC 24 |
Oct 12 01:06:09 AM UTC 24 |
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Oct 12 01:03:47 AM UTC 24 |
Oct 12 01:05:14 AM UTC 24 |
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Oct 12 01:04:40 AM UTC 24 |
Oct 12 01:05:14 AM UTC 24 |
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Oct 12 01:03:16 AM UTC 24 |
Oct 12 01:05:15 AM UTC 24 |
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Oct 12 01:04:41 AM UTC 24 |
Oct 12 01:05:17 AM UTC 24 |
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Oct 12 01:03:23 AM UTC 24 |
Oct 12 01:05:21 AM UTC 24 |
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Oct 12 01:04:02 AM UTC 24 |
Oct 12 01:05:23 AM UTC 24 |
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Oct 12 01:03:51 AM UTC 24 |
Oct 12 01:05:24 AM UTC 24 |
102295744452 ps |
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Oct 12 01:04:46 AM UTC 24 |
Oct 12 01:05:24 AM UTC 24 |
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Oct 12 01:01:45 AM UTC 24 |
Oct 12 01:05:24 AM UTC 24 |
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Oct 12 01:04:53 AM UTC 24 |
Oct 12 01:05:25 AM UTC 24 |
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Oct 12 01:04:58 AM UTC 24 |
Oct 12 01:05:26 AM UTC 24 |
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Oct 12 01:05:15 AM UTC 24 |
Oct 12 01:05:31 AM UTC 24 |
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Oct 12 01:03:52 AM UTC 24 |
Oct 12 01:05:35 AM UTC 24 |
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Oct 12 01:04:01 AM UTC 24 |
Oct 12 01:05:44 AM UTC 24 |
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Oct 12 01:04:40 AM UTC 24 |
Oct 12 01:05:47 AM UTC 24 |
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Oct 12 12:58:12 AM UTC 24 |
Oct 12 01:05:51 AM UTC 24 |
156651710916 ps |
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Oct 12 01:05:14 AM UTC 24 |
Oct 12 01:05:51 AM UTC 24 |
49361277721 ps |
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Oct 12 01:00:56 AM UTC 24 |
Oct 12 01:05:57 AM UTC 24 |
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Oct 12 12:57:10 AM UTC 24 |
Oct 12 01:05:58 AM UTC 24 |
187776318812 ps |
| T781 |
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Oct 12 01:03:45 AM UTC 24 |
Oct 12 01:05:59 AM UTC 24 |
45980545014 ps |
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Oct 12 12:59:56 AM UTC 24 |
Oct 12 01:06:00 AM UTC 24 |
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Oct 12 01:05:25 AM UTC 24 |
Oct 12 01:06:01 AM UTC 24 |
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Oct 12 01:01:10 AM UTC 24 |
Oct 12 01:06:03 AM UTC 24 |
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Oct 12 01:05:14 AM UTC 24 |
Oct 12 01:06:03 AM UTC 24 |
51250392718 ps |
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Oct 12 01:05:22 AM UTC 24 |
Oct 12 01:06:06 AM UTC 24 |
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Oct 12 01:05:25 AM UTC 24 |
Oct 12 01:06:12 AM UTC 24 |
39416985210 ps |
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Oct 12 01:05:24 AM UTC 24 |
Oct 12 01:06:17 AM UTC 24 |
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Oct 12 01:03:09 AM UTC 24 |
Oct 12 01:06:24 AM UTC 24 |
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Oct 12 12:57:40 AM UTC 24 |
Oct 12 01:06:31 AM UTC 24 |
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Oct 12 01:03:45 AM UTC 24 |
Oct 12 01:06:36 AM UTC 24 |
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Oct 12 01:03:18 AM UTC 24 |
Oct 12 01:06:36 AM UTC 24 |
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Oct 12 01:02:53 AM UTC 24 |
Oct 12 01:06:38 AM UTC 24 |
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Oct 12 01:03:41 AM UTC 24 |
Oct 12 01:06:39 AM UTC 24 |
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Oct 12 01:05:27 AM UTC 24 |
Oct 12 01:06:40 AM UTC 24 |
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Oct 12 01:05:25 AM UTC 24 |
Oct 12 01:06:45 AM UTC 24 |
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Oct 12 01:04:49 AM UTC 24 |
Oct 12 01:06:47 AM UTC 24 |
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Oct 12 01:04:40 AM UTC 24 |
Oct 12 01:06:59 AM UTC 24 |
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Oct 12 01:05:18 AM UTC 24 |
Oct 12 01:06:59 AM UTC 24 |
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Oct 12 01:04:40 AM UTC 24 |
Oct 12 01:07:02 AM UTC 24 |
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Oct 12 01:05:05 AM UTC 24 |
Oct 12 01:07:11 AM UTC 24 |
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Oct 12 01:00:14 AM UTC 24 |
Oct 12 01:07:12 AM UTC 24 |
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Oct 12 01:00:56 AM UTC 24 |
Oct 12 01:07:20 AM UTC 24 |
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Oct 12 01:04:18 AM UTC 24 |
Oct 12 01:07:22 AM UTC 24 |
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Oct 12 01:05:31 AM UTC 24 |
Oct 12 01:07:24 AM UTC 24 |
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Oct 12 01:01:18 AM UTC 24 |
Oct 12 01:07:27 AM UTC 24 |
121973308587 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1327666375 |
|
|
Oct 12 01:03:10 AM UTC 24 |
Oct 12 01:07:33 AM UTC 24 |
157760279072 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4109059121 |
|
|
Oct 12 01:04:38 AM UTC 24 |
Oct 12 01:07:33 AM UTC 24 |
57848820887 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1064206215 |
|
|
Oct 12 01:04:21 AM UTC 24 |
Oct 12 01:07:37 AM UTC 24 |
243788781086 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.486251140 |
|
|
Oct 12 01:04:40 AM UTC 24 |
Oct 12 01:07:44 AM UTC 24 |
54160285611 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2730022121 |
|
|
Oct 12 01:04:48 AM UTC 24 |
Oct 12 01:07:49 AM UTC 24 |
51731971822 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.3977456319 |
|
|
Oct 12 01:03:25 AM UTC 24 |
Oct 12 01:07:50 AM UTC 24 |
79092468213 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.2737378281 |
|
|
Oct 12 01:02:25 AM UTC 24 |
Oct 12 01:07:54 AM UTC 24 |
208323756345 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1759801033 |
|
|
Oct 12 01:05:37 AM UTC 24 |
Oct 12 01:07:59 AM UTC 24 |
78278142781 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.220576836 |
|
|
Oct 12 01:05:09 AM UTC 24 |
Oct 12 01:08:03 AM UTC 24 |
86704158349 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1061688149 |
|
|
Oct 12 01:05:16 AM UTC 24 |
Oct 12 01:08:12 AM UTC 24 |
62404032189 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.697420576 |
|
|
Oct 12 01:04:40 AM UTC 24 |
Oct 12 01:08:17 AM UTC 24 |
77819777418 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.557508448 |
|
|
Oct 12 12:57:47 AM UTC 24 |
Oct 12 01:08:24 AM UTC 24 |
221174847898 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1949185193 |
|
|
Oct 12 01:04:38 AM UTC 24 |
Oct 12 01:08:29 AM UTC 24 |
71115555569 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.939104900 |
|
|
Oct 12 12:56:49 AM UTC 24 |
Oct 12 01:08:39 AM UTC 24 |
340063481788 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2009568321 |
|
|
Oct 12 01:04:48 AM UTC 24 |
Oct 12 01:09:17 AM UTC 24 |
198489214924 ps |