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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.35 99.35 98.00 100.00 97.44 99.59 99.61 80.48


Total test records in report: 923
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T804 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1022820939 Oct 12 01:04:41 AM UTC 24 Oct 12 01:09:21 AM UTC 24 119197327180 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.3963725704 Oct 12 01:03:33 AM UTC 24 Oct 12 01:11:43 AM UTC 24 116430724772 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.1174273940 Oct 12 01:03:20 AM UTC 24 Oct 12 01:11:52 AM UTC 24 199881041446 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.2196730582 Oct 12 01:02:37 AM UTC 24 Oct 12 01:12:07 AM UTC 24 142067481903 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2779149877 Oct 12 01:04:16 AM UTC 24 Oct 12 01:12:40 AM UTC 24 159682981036 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2507705720 Oct 12 01:04:51 AM UTC 24 Oct 12 01:12:59 AM UTC 24 128713959871 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.3129285066 Oct 12 12:59:58 AM UTC 24 Oct 12 01:16:28 AM UTC 24 1103690422380 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.4101776258 Oct 12 12:57:47 AM UTC 24 Oct 12 01:17:56 AM UTC 24 330519515475 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.598236663 Oct 12 01:05:46 AM UTC 24 Oct 12 01:05:51 AM UTC 24 2472099496 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2807853386 Oct 12 01:05:52 AM UTC 24 Oct 12 01:05:56 AM UTC 24 2065246917 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2665105932 Oct 12 01:05:52 AM UTC 24 Oct 12 01:06:00 AM UTC 24 2059117582 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2117272204 Oct 12 01:05:52 AM UTC 24 Oct 12 01:06:02 AM UTC 24 4031699753 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4157764378 Oct 12 01:05:59 AM UTC 24 Oct 12 01:06:03 AM UTC 24 2069150772 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.805772538 Oct 12 01:05:58 AM UTC 24 Oct 12 01:06:05 AM UTC 24 4630727399 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3553950310 Oct 12 01:06:02 AM UTC 24 Oct 12 01:06:06 AM UTC 24 2033820926 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1627175904 Oct 12 01:05:57 AM UTC 24 Oct 12 01:06:07 AM UTC 24 3467073077 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1368852994 Oct 12 01:06:00 AM UTC 24 Oct 12 01:06:07 AM UTC 24 2373955838 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.776539320 Oct 12 01:06:04 AM UTC 24 Oct 12 01:06:08 AM UTC 24 2044431502 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.522234684 Oct 12 01:06:07 AM UTC 24 Oct 12 01:06:10 AM UTC 24 2145743320 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2965205957 Oct 12 01:06:07 AM UTC 24 Oct 12 01:06:13 AM UTC 24 2099064433 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1406552765 Oct 12 01:06:03 AM UTC 24 Oct 12 01:06:14 AM UTC 24 6053684676 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.4047705006 Oct 12 01:06:08 AM UTC 24 Oct 12 01:06:15 AM UTC 24 2015245523 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1040512001 Oct 12 01:06:11 AM UTC 24 Oct 12 01:06:15 AM UTC 24 2039782613 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3345392640 Oct 12 01:06:15 AM UTC 24 Oct 12 01:06:20 AM UTC 24 2092203556 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2306755332 Oct 12 01:06:13 AM UTC 24 Oct 12 01:06:20 AM UTC 24 2694421958 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.284793859 Oct 12 01:05:48 AM UTC 24 Oct 12 01:06:21 AM UTC 24 42911005077 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1737515998 Oct 12 01:06:16 AM UTC 24 Oct 12 01:06:22 AM UTC 24 2084147741 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3652987784 Oct 12 01:06:06 AM UTC 24 Oct 12 01:06:23 AM UTC 24 10899978180 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1489292039 Oct 12 01:06:04 AM UTC 24 Oct 12 01:06:25 AM UTC 24 2672269702 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4265370217 Oct 12 01:06:21 AM UTC 24 Oct 12 01:06:27 AM UTC 24 4046156571 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.467426916 Oct 12 01:06:14 AM UTC 24 Oct 12 01:06:30 AM UTC 24 8018813965 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.47359918 Oct 12 01:06:18 AM UTC 24 Oct 12 01:06:30 AM UTC 24 2011682011 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3895705542 Oct 12 01:06:25 AM UTC 24 Oct 12 01:06:31 AM UTC 24 2077010470 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1850888327 Oct 12 01:06:21 AM UTC 24 Oct 12 01:06:33 AM UTC 24 2030187871 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2796747278 Oct 12 01:06:32 AM UTC 24 Oct 12 01:06:37 AM UTC 24 2119511322 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3245426538 Oct 12 01:06:26 AM UTC 24 Oct 12 01:06:39 AM UTC 24 2062644907 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.603566398 Oct 12 01:06:23 AM UTC 24 Oct 12 01:06:39 AM UTC 24 2512096845 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2372170232 Oct 12 01:06:31 AM UTC 24 Oct 12 01:06:43 AM UTC 24 4028441138 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.782914472 Oct 12 01:06:31 AM UTC 24 Oct 12 01:06:43 AM UTC 24 2010495926 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1900719762 Oct 12 01:06:10 AM UTC 24 Oct 12 01:06:43 AM UTC 24 6016088738 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1326373762 Oct 12 01:06:35 AM UTC 24 Oct 12 01:06:47 AM UTC 24 2676899553 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1270831918 Oct 12 01:06:43 AM UTC 24 Oct 12 01:06:47 AM UTC 24 2031153265 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3711951204 Oct 12 01:06:37 AM UTC 24 Oct 12 01:06:47 AM UTC 24 10072132610 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2283199805 Oct 12 01:06:24 AM UTC 24 Oct 12 01:06:48 AM UTC 24 9598193326 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2929313935 Oct 12 01:06:43 AM UTC 24 Oct 12 01:06:48 AM UTC 24 2117007501 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1962114263 Oct 12 01:06:43 AM UTC 24 Oct 12 01:06:49 AM UTC 24 2047325785 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.984978401 Oct 12 01:06:42 AM UTC 24 Oct 12 01:06:50 AM UTC 24 2048038285 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1879914175 Oct 12 01:06:42 AM UTC 24 Oct 12 01:06:50 AM UTC 24 2089872015 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1244310872 Oct 12 01:06:48 AM UTC 24 Oct 12 01:06:52 AM UTC 24 2036640387 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.859722343 Oct 12 01:06:47 AM UTC 24 Oct 12 01:06:53 AM UTC 24 2060371436 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2428596624 Oct 12 01:06:48 AM UTC 24 Oct 12 01:06:54 AM UTC 24 2042816995 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2064396066 Oct 12 01:06:50 AM UTC 24 Oct 12 01:06:55 AM UTC 24 2129131123 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1707846768 Oct 12 01:06:45 AM UTC 24 Oct 12 01:06:55 AM UTC 24 2039811597 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1107422408 Oct 12 01:06:45 AM UTC 24 Oct 12 01:06:56 AM UTC 24 2015298779 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1904736375 Oct 12 01:06:51 AM UTC 24 Oct 12 01:06:56 AM UTC 24 2575906809 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3643307749 Oct 12 01:06:54 AM UTC 24 Oct 12 01:06:56 AM UTC 24 2196956672 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1736970721 Oct 12 01:06:44 AM UTC 24 Oct 12 01:06:57 AM UTC 24 2035067294 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2937502711 Oct 12 01:06:57 AM UTC 24 Oct 12 01:07:10 AM UTC 24 2064229633 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1290050551 Oct 12 01:06:54 AM UTC 24 Oct 12 01:06:58 AM UTC 24 2046566236 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.557481678 Oct 12 01:06:57 AM UTC 24 Oct 12 01:07:03 AM UTC 24 2026043496 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2495814344 Oct 12 01:06:56 AM UTC 24 Oct 12 01:07:03 AM UTC 24 2053117432 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2597356153 Oct 12 01:06:48 AM UTC 24 Oct 12 01:07:04 AM UTC 24 2151741843 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.811795563 Oct 12 01:06:42 AM UTC 24 Oct 12 01:07:05 AM UTC 24 22416403013 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2765989027 Oct 12 01:06:58 AM UTC 24 Oct 12 01:07:05 AM UTC 24 5048200135 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2750570999 Oct 12 01:06:43 AM UTC 24 Oct 12 01:07:06 AM UTC 24 10581312378 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4007809279 Oct 12 01:07:03 AM UTC 24 Oct 12 01:07:07 AM UTC 24 2026500424 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2635872487 Oct 12 01:06:49 AM UTC 24 Oct 12 01:07:08 AM UTC 24 7759489841 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.990431385 Oct 12 01:06:56 AM UTC 24 Oct 12 01:07:08 AM UTC 24 2043492928 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.586420420 Oct 12 01:06:59 AM UTC 24 Oct 12 01:07:08 AM UTC 24 2064161475 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.913670771 Oct 12 01:07:04 AM UTC 24 Oct 12 01:07:09 AM UTC 24 2100131310 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.522427512 Oct 12 01:06:11 AM UTC 24 Oct 12 01:07:09 AM UTC 24 56369786549 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.593141377 Oct 12 01:07:06 AM UTC 24 Oct 12 01:07:10 AM UTC 24 2029854130 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3355793538 Oct 12 01:07:00 AM UTC 24 Oct 12 01:07:11 AM UTC 24 2170484542 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1083870911 Oct 12 01:07:04 AM UTC 24 Oct 12 01:07:13 AM UTC 24 2034695359 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3691160699 Oct 12 01:05:56 AM UTC 24 Oct 12 01:07:13 AM UTC 24 38496928267 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1256811184 Oct 12 01:06:48 AM UTC 24 Oct 12 01:07:13 AM UTC 24 22255198288 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1645882837 Oct 12 01:07:10 AM UTC 24 Oct 12 01:07:13 AM UTC 24 2040618940 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2950750378 Oct 12 01:07:11 AM UTC 24 Oct 12 01:07:15 AM UTC 24 2076922712 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2498411948 Oct 12 01:07:12 AM UTC 24 Oct 12 01:07:16 AM UTC 24 2101916245 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3972430213 Oct 12 01:07:09 AM UTC 24 Oct 12 01:07:16 AM UTC 24 2037114327 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.959223168 Oct 12 01:07:09 AM UTC 24 Oct 12 01:07:16 AM UTC 24 2118449750 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.697336569 Oct 12 01:06:46 AM UTC 24 Oct 12 01:07:16 AM UTC 24 9025478757 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3949082393 Oct 12 01:07:10 AM UTC 24 Oct 12 01:07:16 AM UTC 24 2216648135 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2218454956 Oct 12 01:07:14 AM UTC 24 Oct 12 01:07:18 AM UTC 24 2078437386 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3677941544 Oct 12 01:07:05 AM UTC 24 Oct 12 01:07:19 AM UTC 24 2040775385 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3257972469 Oct 12 01:07:14 AM UTC 24 Oct 12 01:07:20 AM UTC 24 2015031707 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1533393506 Oct 12 01:07:04 AM UTC 24 Oct 12 01:07:20 AM UTC 24 6893040136 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.691589593 Oct 12 01:07:12 AM UTC 24 Oct 12 01:07:21 AM UTC 24 2068103566 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.676827517 Oct 12 01:07:17 AM UTC 24 Oct 12 01:07:21 AM UTC 24 2043319066 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.4095692947 Oct 12 01:07:16 AM UTC 24 Oct 12 01:07:22 AM UTC 24 4368426070 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.573322486 Oct 12 01:07:11 AM UTC 24 Oct 12 01:07:23 AM UTC 24 10179414474 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1678143913 Oct 12 01:07:17 AM UTC 24 Oct 12 01:07:25 AM UTC 24 4822426486 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1809852622 Oct 12 01:07:10 AM UTC 24 Oct 12 01:07:25 AM UTC 24 22589576122 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3591256445 Oct 12 01:07:14 AM UTC 24 Oct 12 01:07:25 AM UTC 24 2047506858 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1954667859 Oct 12 01:07:23 AM UTC 24 Oct 12 01:07:26 AM UTC 24 2204824427 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3037681910 Oct 12 01:07:22 AM UTC 24 Oct 12 01:07:26 AM UTC 24 2067374241 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1687285075 Oct 12 01:07:14 AM UTC 24 Oct 12 01:07:26 AM UTC 24 7930752730 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.564158034 Oct 12 01:07:21 AM UTC 24 Oct 12 01:07:27 AM UTC 24 2051435984 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.570698903 Oct 12 01:06:55 AM UTC 24 Oct 12 01:07:29 AM UTC 24 5140932759 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3614184820 Oct 12 01:07:22 AM UTC 24 Oct 12 01:07:29 AM UTC 24 2441465572 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2908656006 Oct 12 01:07:24 AM UTC 24 Oct 12 01:07:29 AM UTC 24 2073563258 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1803527349 Oct 12 01:07:18 AM UTC 24 Oct 12 01:07:29 AM UTC 24 2071923679 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.290368120 Oct 12 01:07:17 AM UTC 24 Oct 12 01:07:29 AM UTC 24 2059487121 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3122845323 Oct 12 01:06:27 AM UTC 24 Oct 12 01:07:29 AM UTC 24 42626207032 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.321870038 Oct 12 01:07:17 AM UTC 24 Oct 12 01:07:30 AM UTC 24 2043074868 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.19117108 Oct 12 01:07:09 AM UTC 24 Oct 12 01:07:30 AM UTC 24 4652816384 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2109253425 Oct 12 01:07:27 AM UTC 24 Oct 12 01:07:30 AM UTC 24 2140508677 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3634361126 Oct 12 01:07:27 AM UTC 24 Oct 12 01:07:31 AM UTC 24 2139249503 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2966843137 Oct 12 01:07:26 AM UTC 24 Oct 12 01:07:31 AM UTC 24 2061515072 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3894918157 Oct 12 01:07:21 AM UTC 24 Oct 12 01:07:31 AM UTC 24 2013621474 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.630203958 Oct 12 01:07:21 AM UTC 24 Oct 12 01:07:32 AM UTC 24 7744595962 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2312843052 Oct 12 01:07:26 AM UTC 24 Oct 12 01:07:32 AM UTC 24 2298500669 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3563152319 Oct 12 01:06:16 AM UTC 24 Oct 12 01:07:34 AM UTC 24 22183835143 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2614074593 Oct 12 01:07:30 AM UTC 24 Oct 12 01:07:34 AM UTC 24 2075513418 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2813525162 Oct 12 01:07:31 AM UTC 24 Oct 12 01:07:34 AM UTC 24 2161566371 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3342931340 Oct 12 01:07:31 AM UTC 24 Oct 12 01:07:35 AM UTC 24 2035417121 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1768139898 Oct 12 01:07:33 AM UTC 24 Oct 12 01:07:37 AM UTC 24 2039531937 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2374982476 Oct 12 01:07:28 AM UTC 24 Oct 12 01:07:37 AM UTC 24 2108890844 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4188252624 Oct 12 01:07:32 AM UTC 24 Oct 12 01:07:37 AM UTC 24 2151805985 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.640545764 Oct 12 01:07:28 AM UTC 24 Oct 12 01:07:37 AM UTC 24 2044839821 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3102158840 Oct 12 01:07:34 AM UTC 24 Oct 12 01:07:37 AM UTC 24 2044681070 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3304850574 Oct 12 01:07:30 AM UTC 24 Oct 12 01:07:38 AM UTC 24 2009642491 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3982537911 Oct 12 01:07:34 AM UTC 24 Oct 12 01:07:38 AM UTC 24 2034460980 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2718547657 Oct 12 01:07:21 AM UTC 24 Oct 12 01:07:38 AM UTC 24 22243797663 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.439853096 Oct 12 01:07:06 AM UTC 24 Oct 12 01:07:38 AM UTC 24 42538592371 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1837004949 Oct 12 01:07:26 AM UTC 24 Oct 12 01:07:39 AM UTC 24 4716653314 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2112189544 Oct 12 01:07:14 AM UTC 24 Oct 12 01:07:39 AM UTC 24 22427316973 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.919275295 Oct 12 01:07:34 AM UTC 24 Oct 12 01:07:39 AM UTC 24 2019173993 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3398528938 Oct 12 01:07:31 AM UTC 24 Oct 12 01:07:39 AM UTC 24 2213653447 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1345080133 Oct 12 01:07:30 AM UTC 24 Oct 12 01:07:40 AM UTC 24 7013164320 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1716463872 Oct 12 01:07:35 AM UTC 24 Oct 12 01:07:40 AM UTC 24 2016813996 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.803532764 Oct 12 01:07:37 AM UTC 24 Oct 12 01:07:41 AM UTC 24 2052103114 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.4210735270 Oct 12 01:07:38 AM UTC 24 Oct 12 01:07:41 AM UTC 24 2090463185 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1897139818 Oct 12 01:07:31 AM UTC 24 Oct 12 01:07:41 AM UTC 24 2079003918 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1554280468 Oct 12 01:07:37 AM UTC 24 Oct 12 01:07:41 AM UTC 24 2033908652 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.4269620434 Oct 12 01:07:32 AM UTC 24 Oct 12 01:07:42 AM UTC 24 2013149302 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.381954447 Oct 12 01:07:39 AM UTC 24 Oct 12 01:07:42 AM UTC 24 2044231217 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1778164225 Oct 12 01:07:35 AM UTC 24 Oct 12 01:07:43 AM UTC 24 2011934128 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3491331997 Oct 12 01:07:36 AM UTC 24 Oct 12 01:07:43 AM UTC 24 2011958415 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2864425460 Oct 12 01:07:35 AM UTC 24 Oct 12 01:07:44 AM UTC 24 2014833484 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3938411177 Oct 12 01:07:41 AM UTC 24 Oct 12 01:07:44 AM UTC 24 2036828925 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3978221873 Oct 12 01:07:32 AM UTC 24 Oct 12 01:07:44 AM UTC 24 4423109460 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1939351004 Oct 12 01:07:38 AM UTC 24 Oct 12 01:07:44 AM UTC 24 2019276244 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.297999782 Oct 12 01:07:39 AM UTC 24 Oct 12 01:07:45 AM UTC 24 2019785320 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2104515426 Oct 12 01:07:41 AM UTC 24 Oct 12 01:07:45 AM UTC 24 2052169096 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.4289808275 Oct 12 01:07:42 AM UTC 24 Oct 12 01:07:45 AM UTC 24 2027598703 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3663093201 Oct 12 01:07:39 AM UTC 24 Oct 12 01:07:46 AM UTC 24 2009062260 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2843930721 Oct 12 01:07:39 AM UTC 24 Oct 12 01:07:47 AM UTC 24 2020296337 ps
T902 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2882514704 Oct 12 01:07:41 AM UTC 24 Oct 12 01:07:47 AM UTC 24 2020186536 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1746031813 Oct 12 01:07:39 AM UTC 24 Oct 12 01:07:47 AM UTC 24 2015889291 ps
T904 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2888545379 Oct 12 01:07:42 AM UTC 24 Oct 12 01:07:47 AM UTC 24 2016790592 ps
T905 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3645546984 Oct 12 01:07:39 AM UTC 24 Oct 12 01:07:47 AM UTC 24 2013689241 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2763515686 Oct 12 01:07:42 AM UTC 24 Oct 12 01:07:47 AM UTC 24 2016286560 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3510812198 Oct 12 01:07:43 AM UTC 24 Oct 12 01:07:48 AM UTC 24 2021902737 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2709741768 Oct 12 01:07:40 AM UTC 24 Oct 12 01:07:48 AM UTC 24 2010411647 ps
T909 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2165309904 Oct 12 01:07:40 AM UTC 24 Oct 12 01:07:49 AM UTC 24 2010706920 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1029984849 Oct 12 01:07:42 AM UTC 24 Oct 12 01:07:51 AM UTC 24 2012153155 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.869290905 Oct 12 01:07:42 AM UTC 24 Oct 12 01:07:51 AM UTC 24 2016065521 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4118363501 Oct 12 01:07:17 AM UTC 24 Oct 12 01:07:54 AM UTC 24 42481012050 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2760348809 Oct 12 01:06:02 AM UTC 24 Oct 12 01:07:57 AM UTC 24 42448385361 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3828033596 Oct 12 01:07:27 AM UTC 24 Oct 12 01:08:01 AM UTC 24 5596620018 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.209312906 Oct 12 01:07:30 AM UTC 24 Oct 12 01:08:05 AM UTC 24 42992906173 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3835147551 Oct 12 01:06:07 AM UTC 24 Oct 12 01:08:12 AM UTC 24 42378921090 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.156599197 Oct 12 01:06:57 AM UTC 24 Oct 12 01:08:19 AM UTC 24 42528637295 ps
T915 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.211532563 Oct 12 01:06:32 AM UTC 24 Oct 12 01:08:21 AM UTC 24 38806754967 ps
T916 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3077462471 Oct 12 01:06:22 AM UTC 24 Oct 12 01:08:22 AM UTC 24 39647086647 ps
T917 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.543094848 Oct 12 01:07:31 AM UTC 24 Oct 12 01:08:37 AM UTC 24 42725028182 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.392578800 Oct 12 01:06:04 AM UTC 24 Oct 12 01:08:49 AM UTC 24 76032712060 ps
T919 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.4183541624 Oct 12 01:06:44 AM UTC 24 Oct 12 01:09:13 AM UTC 24 42407594256 ps
T920 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.21845252 Oct 12 01:06:52 AM UTC 24 Oct 12 01:09:15 AM UTC 24 42403029534 ps
T921 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3935965892 Oct 12 01:07:27 AM UTC 24 Oct 12 01:09:22 AM UTC 24 42465790797 ps
T922 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1112369871 Oct 12 01:07:00 AM UTC 24 Oct 12 01:09:24 AM UTC 24 42442887096 ps
T923 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.4131869355 Oct 12 01:07:23 AM UTC 24 Oct 12 01:09:28 AM UTC 24 42489843588 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.1478952179
Short name T4
Test name
Test status
Simulation time 2525212601 ps
CPU time 2.65 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:31 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478952179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.1478952179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.480078308
Short name T49
Test name
Test status
Simulation time 39482461017 ps
CPU time 64.47 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:57:42 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480078308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.480078308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1219423197
Short name T69
Test name
Test status
Simulation time 47401043052 ps
CPU time 13.23 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:59 AM UTC 24
Peak memory 226068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1219423197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.1219423197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1136660738
Short name T1
Test name
Test status
Simulation time 2432582282 ps
CPU time 6.29 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:35 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136660738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.1136660738
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3841303271
Short name T60
Test name
Test status
Simulation time 140858882350 ps
CPU time 24.8 seconds
Started Oct 12 12:57:13 AM UTC 24
Finished Oct 12 12:57:39 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841303271 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.3841303271
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.151292222
Short name T7
Test name
Test status
Simulation time 14421168373 ps
CPU time 4.73 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:41 AM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=151292222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.151292222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.3437963898
Short name T62
Test name
Test status
Simulation time 39001051853 ps
CPU time 103.74 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:58:21 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437963898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.3437963898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.284793859
Short name T285
Test name
Test status
Simulation time 42911005077 ps
CPU time 31.71 seconds
Started Oct 12 01:05:48 AM UTC 24
Finished Oct 12 01:06:21 AM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284793859 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.284793859
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.3369215913
Short name T41
Test name
Test status
Simulation time 157612650862 ps
CPU time 46.18 seconds
Started Oct 12 12:56:53 AM UTC 24
Finished Oct 12 12:57:41 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369215913 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.3369215913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.505197444
Short name T262
Test name
Test status
Simulation time 319871515612 ps
CPU time 231.93 seconds
Started Oct 12 12:57:04 AM UTC 24
Finished Oct 12 01:00:59 AM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505197444 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.505197444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3309041974
Short name T247
Test name
Test status
Simulation time 124309101448 ps
CPU time 213.46 seconds
Started Oct 12 12:56:49 AM UTC 24
Finished Oct 12 01:00:25 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309041974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.3309041974
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.1324266284
Short name T48
Test name
Test status
Simulation time 15645049764 ps
CPU time 37.74 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:57:20 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324266284 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.1324266284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.4239844393
Short name T111
Test name
Test status
Simulation time 22041982941 ps
CPU time 15.4 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:52 AM UTC 24
Peak memory 240924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239844393 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.4239844393
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3203650586
Short name T82
Test name
Test status
Simulation time 7153854409 ps
CPU time 11.35 seconds
Started Oct 12 12:57:10 AM UTC 24
Finished Oct 12 12:57:22 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203650586 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.3203650586
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.598236663
Short name T36
Test name
Test status
Simulation time 2472099496 ps
CPU time 4.18 seconds
Started Oct 12 01:05:46 AM UTC 24
Finished Oct 12 01:05:51 AM UTC 24
Peak memory 220048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598236663 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.598236663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.2421014867
Short name T58
Test name
Test status
Simulation time 5154578839 ps
CPU time 10.39 seconds
Started Oct 12 12:56:49 AM UTC 24
Finished Oct 12 12:57:00 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421014867 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.2421014867
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3250577744
Short name T112
Test name
Test status
Simulation time 76117021855 ps
CPU time 72.68 seconds
Started Oct 12 12:58:47 AM UTC 24
Finished Oct 12 01:00:02 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250577744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_with_pre_cond.3250577744
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.4047719599
Short name T67
Test name
Test status
Simulation time 3037273054 ps
CPU time 5.45 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:47 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047719599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.4047719599
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.4126262125
Short name T42
Test name
Test status
Simulation time 54264707379 ps
CPU time 30.67 seconds
Started Oct 12 12:57:10 AM UTC 24
Finished Oct 12 12:57:42 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126262125 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.4126262125
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.3989018581
Short name T180
Test name
Test status
Simulation time 14482463340 ps
CPU time 49.2 seconds
Started Oct 12 01:00:27 AM UTC 24
Finished Oct 12 01:01:18 AM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989018581 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.3989018581
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1421022692
Short name T187
Test name
Test status
Simulation time 2754533865 ps
CPU time 9.2 seconds
Started Oct 12 12:58:57 AM UTC 24
Finished Oct 12 12:59:08 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421022692 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.1421022692
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1489292039
Short name T295
Test name
Test status
Simulation time 2672269702 ps
CPU time 19.5 seconds
Started Oct 12 01:06:04 AM UTC 24
Finished Oct 12 01:06:25 AM UTC 24
Peak memory 209796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489292039 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.1489292039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4282999933
Short name T109
Test name
Test status
Simulation time 1400865424485 ps
CPU time 21.53 seconds
Started Oct 12 12:59:21 AM UTC 24
Finished Oct 12 12:59:44 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282999933 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.4282999933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.993252289
Short name T23
Test name
Test status
Simulation time 2105038341 ps
CPU time 6.07 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:34 AM UTC 24
Peak memory 209220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993252289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.993252289
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1660431651
Short name T241
Test name
Test status
Simulation time 97690897329 ps
CPU time 94.94 seconds
Started Oct 12 12:58:23 AM UTC 24
Finished Oct 12 01:00:00 AM UTC 24
Peak memory 209552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660431651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.1660431651
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.223526155
Short name T174
Test name
Test status
Simulation time 5418146384 ps
CPU time 3.06 seconds
Started Oct 12 01:02:14 AM UTC 24
Finished Oct 12 01:02:18 AM UTC 24
Peak memory 209292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223526155 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.223526155
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3226465152
Short name T189
Test name
Test status
Simulation time 4129757277 ps
CPU time 3.9 seconds
Started Oct 12 01:03:17 AM UTC 24
Finished Oct 12 01:03:22 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226465152 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.3226465152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.3654854472
Short name T117
Test name
Test status
Simulation time 12343728730 ps
CPU time 31.44 seconds
Started Oct 12 12:58:02 AM UTC 24
Finished Oct 12 12:58:35 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654854472 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.3654854472
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.640764652
Short name T61
Test name
Test status
Simulation time 71293608855 ps
CPU time 49.41 seconds
Started Oct 12 12:56:58 AM UTC 24
Finished Oct 12 12:57:49 AM UTC 24
Peak memory 209484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640764652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.640764652
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.2670808582
Short name T363
Test name
Test status
Simulation time 114165001374 ps
CPU time 147.65 seconds
Started Oct 12 01:01:59 AM UTC 24
Finished Oct 12 01:04:29 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670808582 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.2670808582
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2991338033
Short name T423
Test name
Test status
Simulation time 40438213980 ps
CPU time 161.39 seconds
Started Oct 12 01:00:14 AM UTC 24
Finished Oct 12 01:02:58 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991338033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.2991338033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.564737094
Short name T72
Test name
Test status
Simulation time 22268949945 ps
CPU time 20.17 seconds
Started Oct 12 12:56:49 AM UTC 24
Finished Oct 12 12:57:10 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=564737094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.564737094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.805772538
Short name T24
Test name
Test status
Simulation time 4630727399 ps
CPU time 5.64 seconds
Started Oct 12 01:05:58 AM UTC 24
Finished Oct 12 01:06:05 AM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805772538 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.805772538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3217868044
Short name T290
Test name
Test status
Simulation time 3534634498 ps
CPU time 16.76 seconds
Started Oct 12 12:59:43 AM UTC 24
Finished Oct 12 01:00:01 AM UTC 24
Peak memory 217816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3217868044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.3217868044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2429312857
Short name T422
Test name
Test status
Simulation time 7852366127 ps
CPU time 10.62 seconds
Started Oct 12 12:57:48 AM UTC 24
Finished Oct 12 12:58:00 AM UTC 24
Peak memory 209556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2429312857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2429312857
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.2296220934
Short name T373
Test name
Test status
Simulation time 154730427922 ps
CPU time 116.27 seconds
Started Oct 12 01:03:16 AM UTC 24
Finished Oct 12 01:05:15 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296220934 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.2296220934
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3461728674
Short name T371
Test name
Test status
Simulation time 159386548400 ps
CPU time 29.57 seconds
Started Oct 12 01:03:08 AM UTC 24
Finished Oct 12 01:03:39 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461728674 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.3461728674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.314025286
Short name T385
Test name
Test status
Simulation time 147671290556 ps
CPU time 78.27 seconds
Started Oct 12 01:01:20 AM UTC 24
Finished Oct 12 01:02:40 AM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314025286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.314025286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.43502276
Short name T76
Test name
Test status
Simulation time 2013110013 ps
CPU time 5.68 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:42 AM UTC 24
Peak memory 209076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43502276 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.43502276
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2817375871
Short name T379
Test name
Test status
Simulation time 47184630797 ps
CPU time 38.04 seconds
Started Oct 12 01:03:25 AM UTC 24
Finished Oct 12 01:04:04 AM UTC 24
Peak memory 209416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817375871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_with_pre_cond.2817375871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1904736375
Short name T301
Test name
Test status
Simulation time 2575906809 ps
CPU time 4.61 seconds
Started Oct 12 01:06:51 AM UTC 24
Finished Oct 12 01:06:56 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904736375 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.1904736375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.4091014581
Short name T179
Test name
Test status
Simulation time 65049709023 ps
CPU time 61.56 seconds
Started Oct 12 01:00:49 AM UTC 24
Finished Oct 12 01:01:52 AM UTC 24
Peak memory 209744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091014581 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.4091014581
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.811795563
Short name T286
Test name
Test status
Simulation time 22416403013 ps
CPU time 21.3 seconds
Started Oct 12 01:06:42 AM UTC 24
Finished Oct 12 01:07:05 AM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811795563 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.811795563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3870862177
Short name T380
Test name
Test status
Simulation time 109020496096 ps
CPU time 359.87 seconds
Started Oct 12 12:59:56 AM UTC 24
Finished Oct 12 01:06:00 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870862177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.3870862177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.303957449
Short name T372
Test name
Test status
Simulation time 117601950083 ps
CPU time 87.44 seconds
Started Oct 12 01:01:08 AM UTC 24
Finished Oct 12 01:02:38 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303957449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_with_pre_cond.303957449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.3785407664
Short name T322
Test name
Test status
Simulation time 2536237610 ps
CPU time 4.06 seconds
Started Oct 12 12:57:05 AM UTC 24
Finished Oct 12 12:57:10 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785407664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.3785407664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2191403187
Short name T198
Test name
Test status
Simulation time 13999649908 ps
CPU time 4.57 seconds
Started Oct 12 12:59:10 AM UTC 24
Finished Oct 12 12:59:15 AM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191403187 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.2191403187
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1428478600
Short name T312
Test name
Test status
Simulation time 104467636216 ps
CPU time 83.69 seconds
Started Oct 12 12:58:58 AM UTC 24
Finished Oct 12 01:00:24 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428478600 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.1428478600
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.944999464
Short name T226
Test name
Test status
Simulation time 15187599139 ps
CPU time 12.04 seconds
Started Oct 12 12:57:33 AM UTC 24
Finished Oct 12 12:57:46 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944999464 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.944999464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3040188144
Short name T45
Test name
Test status
Simulation time 76684515411 ps
CPU time 106.95 seconds
Started Oct 12 12:57:38 AM UTC 24
Finished Oct 12 12:59:27 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040188144 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.3040188144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3252874908
Short name T236
Test name
Test status
Simulation time 120281190265 ps
CPU time 331.51 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 01:02:23 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252874908 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.3252874908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2923190717
Short name T396
Test name
Test status
Simulation time 61911128427 ps
CPU time 66 seconds
Started Oct 12 01:04:00 AM UTC 24
Finished Oct 12 01:05:08 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923190717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_with_pre_cond.2923190717
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1277594334
Short name T378
Test name
Test status
Simulation time 130964845898 ps
CPU time 99.68 seconds
Started Oct 12 01:05:18 AM UTC 24
Finished Oct 12 01:06:59 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277594334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_with_pre_cond.1277594334
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.481582323
Short name T175
Test name
Test status
Simulation time 3285428007 ps
CPU time 2.96 seconds
Started Oct 12 01:03:09 AM UTC 24
Finished Oct 12 01:03:13 AM UTC 24
Peak memory 209556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481582323 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.481582323
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.572492074
Short name T64
Test name
Test status
Simulation time 14903641205 ps
CPU time 6.33 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:43 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572492074 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.572492074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.169573361
Short name T429
Test name
Test status
Simulation time 426937105171 ps
CPU time 23.18 seconds
Started Oct 12 01:00:14 AM UTC 24
Finished Oct 12 01:00:38 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169573361 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.169573361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1627175904
Short name T291
Test name
Test status
Simulation time 3467073077 ps
CPU time 8.25 seconds
Started Oct 12 01:05:57 AM UTC 24
Finished Oct 12 01:06:07 AM UTC 24
Peak memory 210240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627175904 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.1627175904
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.439853096
Short name T405
Test name
Test status
Simulation time 42538592371 ps
CPU time 30.58 seconds
Started Oct 12 01:07:06 AM UTC 24
Finished Oct 12 01:07:38 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439853096 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.439853096
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.2523334666
Short name T360
Test name
Test status
Simulation time 99285089460 ps
CPU time 301.28 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 01:01:40 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523334666 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.2523334666
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3747436722
Short name T246
Test name
Test status
Simulation time 71093980747 ps
CPU time 215.19 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 01:00:14 AM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747436722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.3747436722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3693053509
Short name T397
Test name
Test status
Simulation time 137695286085 ps
CPU time 382.36 seconds
Started Oct 12 12:57:24 AM UTC 24
Finished Oct 12 01:03:51 AM UTC 24
Peak memory 209388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693053509 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.3693053509
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1917070823
Short name T216
Test name
Test status
Simulation time 203287624394 ps
CPU time 9.53 seconds
Started Oct 12 12:59:06 AM UTC 24
Finished Oct 12 12:59:17 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917070823 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.1917070823
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1625476485
Short name T44
Test name
Test status
Simulation time 36968023366 ps
CPU time 111.28 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:58:37 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625476485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with_pre_cond.1625476485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3941330817
Short name T418
Test name
Test status
Simulation time 75601526020 ps
CPU time 77.89 seconds
Started Oct 12 01:01:58 AM UTC 24
Finished Oct 12 01:03:18 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941330817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_with_pre_cond.3941330817
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.896678763
Short name T392
Test name
Test status
Simulation time 60660729598 ps
CPU time 93.39 seconds
Started Oct 12 01:02:39 AM UTC 24
Finished Oct 12 01:04:14 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896678763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.896678763
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2723855172
Short name T377
Test name
Test status
Simulation time 61712740147 ps
CPU time 192.08 seconds
Started Oct 12 01:03:09 AM UTC 24
Finished Oct 12 01:06:24 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723855172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.2723855172
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.4015809697
Short name T421
Test name
Test status
Simulation time 89820840223 ps
CPU time 196.07 seconds
Started Oct 12 01:03:18 AM UTC 24
Finished Oct 12 01:06:36 AM UTC 24
Peak memory 209820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015809697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_with_pre_cond.4015809697
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1384680515
Short name T420
Test name
Test status
Simulation time 49119885128 ps
CPU time 23.57 seconds
Started Oct 12 01:03:53 AM UTC 24
Finished Oct 12 01:04:18 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384680515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_with_pre_cond.1384680515
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.4087083863
Short name T417
Test name
Test status
Simulation time 77840654340 ps
CPU time 100.9 seconds
Started Oct 12 01:04:01 AM UTC 24
Finished Oct 12 01:05:44 AM UTC 24
Peak memory 209416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087083863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_with_pre_cond.4087083863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1157332983
Short name T389
Test name
Test status
Simulation time 69749128617 ps
CPU time 26.64 seconds
Started Oct 12 01:04:19 AM UTC 24
Finished Oct 12 01:04:47 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157332983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.1157332983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.268261492
Short name T171
Test name
Test status
Simulation time 4133156981 ps
CPU time 12.94 seconds
Started Oct 12 01:00:15 AM UTC 24
Finished Oct 12 01:00:30 AM UTC 24
Peak memory 209288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268261492 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.268261492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.2769241945
Short name T159
Test name
Test status
Simulation time 2639921142 ps
CPU time 9.97 seconds
Started Oct 12 01:01:46 AM UTC 24
Finished Oct 12 01:01:57 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769241945 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.2769241945
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.661158870
Short name T239
Test name
Test status
Simulation time 56841835462 ps
CPU time 123.9 seconds
Started Oct 12 01:05:05 AM UTC 24
Finished Oct 12 01:07:11 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661158870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_with_pre_cond.661158870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3706073508
Short name T33
Test name
Test status
Simulation time 26338507988 ps
CPU time 35.89 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:57:12 AM UTC 24
Peak memory 209416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706073508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.3706073508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3691160699
Short name T836
Test name
Test status
Simulation time 38496928267 ps
CPU time 74.75 seconds
Started Oct 12 01:05:56 AM UTC 24
Finished Oct 12 01:07:13 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691160699 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.3691160699
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2117272204
Short name T38
Test name
Test status
Simulation time 4031699753 ps
CPU time 9.3 seconds
Started Oct 12 01:05:52 AM UTC 24
Finished Oct 12 01:06:02 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117272204 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.2117272204
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4157764378
Short name T39
Test name
Test status
Simulation time 2069150772 ps
CPU time 3.05 seconds
Started Oct 12 01:05:59 AM UTC 24
Finished Oct 12 01:06:03 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4157764378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_csr_mem_rw_with_rand_reset.4157764378
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2665105932
Short name T37
Test name
Test status
Simulation time 2059117582 ps
CPU time 6.88 seconds
Started Oct 12 01:05:52 AM UTC 24
Finished Oct 12 01:06:00 AM UTC 24
Peak memory 209452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665105932 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.2665105932
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2807853386
Short name T809
Test name
Test status
Simulation time 2065246917 ps
CPU time 2.71 seconds
Started Oct 12 01:05:52 AM UTC 24
Finished Oct 12 01:05:56 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807853386 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.2807853386
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.392578800
Short name T918
Test name
Test status
Simulation time 76032712060 ps
CPU time 162.11 seconds
Started Oct 12 01:06:04 AM UTC 24
Finished Oct 12 01:08:49 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392578800 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.392578800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1406552765
Short name T293
Test name
Test status
Simulation time 6053684676 ps
CPU time 9.92 seconds
Started Oct 12 01:06:03 AM UTC 24
Finished Oct 12 01:06:14 AM UTC 24
Peak memory 209580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406552765 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.1406552765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.522234684
Short name T292
Test name
Test status
Simulation time 2145743320 ps
CPU time 1.89 seconds
Started Oct 12 01:06:07 AM UTC 24
Finished Oct 12 01:06:10 AM UTC 24
Peak memory 208224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=522234684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
sysrst_ctrl_csr_mem_rw_with_rand_reset.522234684
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.776539320
Short name T357
Test name
Test status
Simulation time 2044431502 ps
CPU time 3.42 seconds
Started Oct 12 01:06:04 AM UTC 24
Finished Oct 12 01:06:08 AM UTC 24
Peak memory 209724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776539320 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.776539320
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3553950310
Short name T810
Test name
Test status
Simulation time 2033820926 ps
CPU time 3.31 seconds
Started Oct 12 01:06:02 AM UTC 24
Finished Oct 12 01:06:06 AM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553950310 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.3553950310
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3652987784
Short name T25
Test name
Test status
Simulation time 10899978180 ps
CPU time 15.57 seconds
Started Oct 12 01:06:06 AM UTC 24
Finished Oct 12 01:06:23 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652987784 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.3652987784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1368852994
Short name T283
Test name
Test status
Simulation time 2373955838 ps
CPU time 5.69 seconds
Started Oct 12 01:06:00 AM UTC 24
Finished Oct 12 01:06:07 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368852994 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.1368852994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2760348809
Short name T408
Test name
Test status
Simulation time 42448385361 ps
CPU time 113.56 seconds
Started Oct 12 01:06:02 AM UTC 24
Finished Oct 12 01:07:57 AM UTC 24
Peak memory 209724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760348809 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.2760348809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.913670771
Short name T833
Test name
Test status
Simulation time 2100131310 ps
CPU time 3.91 seconds
Started Oct 12 01:07:04 AM UTC 24
Finished Oct 12 01:07:09 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=913670771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_csr_mem_rw_with_rand_reset.913670771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1083870911
Short name T353
Test name
Test status
Simulation time 2034695359 ps
CPU time 7.46 seconds
Started Oct 12 01:07:04 AM UTC 24
Finished Oct 12 01:07:13 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083870911 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.1083870911
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4007809279
Short name T829
Test name
Test status
Simulation time 2026500424 ps
CPU time 3.53 seconds
Started Oct 12 01:07:03 AM UTC 24
Finished Oct 12 01:07:07 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007809279 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.4007809279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1533393506
Short name T847
Test name
Test status
Simulation time 6893040136 ps
CPU time 14.78 seconds
Started Oct 12 01:07:04 AM UTC 24
Finished Oct 12 01:07:20 AM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533393506 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.1533393506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3355793538
Short name T835
Test name
Test status
Simulation time 2170484542 ps
CPU time 10.61 seconds
Started Oct 12 01:07:00 AM UTC 24
Finished Oct 12 01:07:11 AM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355793538 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.3355793538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1112369871
Short name T922
Test name
Test status
Simulation time 42442887096 ps
CPU time 141.84 seconds
Started Oct 12 01:07:00 AM UTC 24
Finished Oct 12 01:09:24 AM UTC 24
Peak memory 209956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112369871 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.1112369871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.959223168
Short name T841
Test name
Test status
Simulation time 2118449750 ps
CPU time 6.57 seconds
Started Oct 12 01:07:09 AM UTC 24
Finished Oct 12 01:07:16 AM UTC 24
Peak memory 209584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=959223168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_csr_mem_rw_with_rand_reset.959223168
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3972430213
Short name T840
Test name
Test status
Simulation time 2037114327 ps
CPU time 6.66 seconds
Started Oct 12 01:07:09 AM UTC 24
Finished Oct 12 01:07:16 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972430213 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.3972430213
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.593141377
Short name T834
Test name
Test status
Simulation time 2029854130 ps
CPU time 2.32 seconds
Started Oct 12 01:07:06 AM UTC 24
Finished Oct 12 01:07:10 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593141377 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.593141377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.19117108
Short name T862
Test name
Test status
Simulation time 4652816384 ps
CPU time 19.99 seconds
Started Oct 12 01:07:09 AM UTC 24
Finished Oct 12 01:07:30 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19117108 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.19117108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3677941544
Short name T845
Test name
Test status
Simulation time 2040775385 ps
CPU time 13.01 seconds
Started Oct 12 01:07:05 AM UTC 24
Finished Oct 12 01:07:19 AM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677941544 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.3677941544
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2498411948
Short name T839
Test name
Test status
Simulation time 2101916245 ps
CPU time 3 seconds
Started Oct 12 01:07:12 AM UTC 24
Finished Oct 12 01:07:16 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2498411948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2498411948
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2950750378
Short name T838
Test name
Test status
Simulation time 2076922712 ps
CPU time 3.35 seconds
Started Oct 12 01:07:11 AM UTC 24
Finished Oct 12 01:07:15 AM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950750378 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.2950750378
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1645882837
Short name T837
Test name
Test status
Simulation time 2040618940 ps
CPU time 2.13 seconds
Started Oct 12 01:07:10 AM UTC 24
Finished Oct 12 01:07:13 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645882837 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.1645882837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.573322486
Short name T851
Test name
Test status
Simulation time 10179414474 ps
CPU time 10.76 seconds
Started Oct 12 01:07:11 AM UTC 24
Finished Oct 12 01:07:23 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573322486 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.573322486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3949082393
Short name T843
Test name
Test status
Simulation time 2216648135 ps
CPU time 5.49 seconds
Started Oct 12 01:07:10 AM UTC 24
Finished Oct 12 01:07:16 AM UTC 24
Peak memory 209888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949082393 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.3949082393
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1809852622
Short name T403
Test name
Test status
Simulation time 22589576122 ps
CPU time 13.5 seconds
Started Oct 12 01:07:10 AM UTC 24
Finished Oct 12 01:07:25 AM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809852622 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.1809852622
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2218454956
Short name T844
Test name
Test status
Simulation time 2078437386 ps
CPU time 2.77 seconds
Started Oct 12 01:07:14 AM UTC 24
Finished Oct 12 01:07:18 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2218454956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2218454956
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3591256445
Short name T354
Test name
Test status
Simulation time 2047506858 ps
CPU time 10.67 seconds
Started Oct 12 01:07:14 AM UTC 24
Finished Oct 12 01:07:25 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591256445 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.3591256445
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3257972469
Short name T846
Test name
Test status
Simulation time 2015031707 ps
CPU time 5.16 seconds
Started Oct 12 01:07:14 AM UTC 24
Finished Oct 12 01:07:20 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257972469 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.3257972469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1687285075
Short name T855
Test name
Test status
Simulation time 7930752730 ps
CPU time 11.5 seconds
Started Oct 12 01:07:14 AM UTC 24
Finished Oct 12 01:07:26 AM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687285075 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.1687285075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.691589593
Short name T848
Test name
Test status
Simulation time 2068103566 ps
CPU time 7.38 seconds
Started Oct 12 01:07:12 AM UTC 24
Finished Oct 12 01:07:21 AM UTC 24
Peak memory 210052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691589593 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.691589593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2112189544
Short name T406
Test name
Test status
Simulation time 22427316973 ps
CPU time 24.06 seconds
Started Oct 12 01:07:14 AM UTC 24
Finished Oct 12 01:07:39 AM UTC 24
Peak memory 209928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112189544 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.2112189544
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.290368120
Short name T861
Test name
Test status
Simulation time 2059487121 ps
CPU time 10.6 seconds
Started Oct 12 01:07:17 AM UTC 24
Finished Oct 12 01:07:29 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=290368120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_csr_mem_rw_with_rand_reset.290368120
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.321870038
Short name T355
Test name
Test status
Simulation time 2043074868 ps
CPU time 11.19 seconds
Started Oct 12 01:07:17 AM UTC 24
Finished Oct 12 01:07:30 AM UTC 24
Peak memory 209392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321870038 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.321870038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.676827517
Short name T849
Test name
Test status
Simulation time 2043319066 ps
CPU time 2.68 seconds
Started Oct 12 01:07:17 AM UTC 24
Finished Oct 12 01:07:21 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676827517 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.676827517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1678143913
Short name T852
Test name
Test status
Simulation time 4822426486 ps
CPU time 6.11 seconds
Started Oct 12 01:07:17 AM UTC 24
Finished Oct 12 01:07:25 AM UTC 24
Peak memory 209888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678143913 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.1678143913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.4095692947
Short name T850
Test name
Test status
Simulation time 4368426070 ps
CPU time 4.43 seconds
Started Oct 12 01:07:16 AM UTC 24
Finished Oct 12 01:07:22 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095692947 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.4095692947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4118363501
Short name T912
Test name
Test status
Simulation time 42481012050 ps
CPU time 35.21 seconds
Started Oct 12 01:07:17 AM UTC 24
Finished Oct 12 01:07:54 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118363501 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.4118363501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3037681910
Short name T854
Test name
Test status
Simulation time 2067374241 ps
CPU time 2.67 seconds
Started Oct 12 01:07:22 AM UTC 24
Finished Oct 12 01:07:26 AM UTC 24
Peak memory 209444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3037681910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3037681910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.564158034
Short name T856
Test name
Test status
Simulation time 2051435984 ps
CPU time 5.19 seconds
Started Oct 12 01:07:21 AM UTC 24
Finished Oct 12 01:07:27 AM UTC 24
Peak memory 209452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564158034 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.564158034
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3894918157
Short name T865
Test name
Test status
Simulation time 2013621474 ps
CPU time 9.27 seconds
Started Oct 12 01:07:21 AM UTC 24
Finished Oct 12 01:07:31 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894918157 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.3894918157
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.630203958
Short name T866
Test name
Test status
Simulation time 7744595962 ps
CPU time 9.32 seconds
Started Oct 12 01:07:21 AM UTC 24
Finished Oct 12 01:07:32 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630203958 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.630203958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1803527349
Short name T860
Test name
Test status
Simulation time 2071923679 ps
CPU time 9.09 seconds
Started Oct 12 01:07:18 AM UTC 24
Finished Oct 12 01:07:29 AM UTC 24
Peak memory 219920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803527349 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.1803527349
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2718547657
Short name T879
Test name
Test status
Simulation time 22243797663 ps
CPU time 15.9 seconds
Started Oct 12 01:07:21 AM UTC 24
Finished Oct 12 01:07:38 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718547657 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.2718547657
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2966843137
Short name T864
Test name
Test status
Simulation time 2061515072 ps
CPU time 3.88 seconds
Started Oct 12 01:07:26 AM UTC 24
Finished Oct 12 01:07:31 AM UTC 24
Peak memory 209516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2966843137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2966843137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2908656006
Short name T859
Test name
Test status
Simulation time 2073563258 ps
CPU time 2.74 seconds
Started Oct 12 01:07:24 AM UTC 24
Finished Oct 12 01:07:29 AM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908656006 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.2908656006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1954667859
Short name T853
Test name
Test status
Simulation time 2204824427 ps
CPU time 1.03 seconds
Started Oct 12 01:07:23 AM UTC 24
Finished Oct 12 01:07:26 AM UTC 24
Peak memory 207980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954667859 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.1954667859
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1837004949
Short name T880
Test name
Test status
Simulation time 4716653314 ps
CPU time 11.33 seconds
Started Oct 12 01:07:26 AM UTC 24
Finished Oct 12 01:07:39 AM UTC 24
Peak memory 209656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837004949 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.1837004949
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3614184820
Short name T858
Test name
Test status
Simulation time 2441465572 ps
CPU time 5.05 seconds
Started Oct 12 01:07:22 AM UTC 24
Finished Oct 12 01:07:29 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614184820 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.3614184820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.4131869355
Short name T923
Test name
Test status
Simulation time 42489843588 ps
CPU time 122.58 seconds
Started Oct 12 01:07:23 AM UTC 24
Finished Oct 12 01:09:28 AM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131869355 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.4131869355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.640545764
Short name T875
Test name
Test status
Simulation time 2044839821 ps
CPU time 7.25 seconds
Started Oct 12 01:07:28 AM UTC 24
Finished Oct 12 01:07:37 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=640545764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_csr_mem_rw_with_rand_reset.640545764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3634361126
Short name T356
Test name
Test status
Simulation time 2139249503 ps
CPU time 2.39 seconds
Started Oct 12 01:07:27 AM UTC 24
Finished Oct 12 01:07:31 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634361126 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.3634361126
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2109253425
Short name T863
Test name
Test status
Simulation time 2140508677 ps
CPU time 1.61 seconds
Started Oct 12 01:07:27 AM UTC 24
Finished Oct 12 01:07:30 AM UTC 24
Peak memory 208576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109253425 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.2109253425
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3828033596
Short name T913
Test name
Test status
Simulation time 5596620018 ps
CPU time 31.72 seconds
Started Oct 12 01:07:27 AM UTC 24
Finished Oct 12 01:08:01 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828033596 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.3828033596
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2312843052
Short name T867
Test name
Test status
Simulation time 2298500669 ps
CPU time 4.97 seconds
Started Oct 12 01:07:26 AM UTC 24
Finished Oct 12 01:07:32 AM UTC 24
Peak memory 209928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312843052 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.2312843052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3935965892
Short name T921
Test name
Test status
Simulation time 42465790797 ps
CPU time 112.66 seconds
Started Oct 12 01:07:27 AM UTC 24
Finished Oct 12 01:09:22 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935965892 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.3935965892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1897139818
Short name T887
Test name
Test status
Simulation time 2079003918 ps
CPU time 8.65 seconds
Started Oct 12 01:07:31 AM UTC 24
Finished Oct 12 01:07:41 AM UTC 24
Peak memory 209584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1897139818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1897139818
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2614074593
Short name T869
Test name
Test status
Simulation time 2075513418 ps
CPU time 3 seconds
Started Oct 12 01:07:30 AM UTC 24
Finished Oct 12 01:07:34 AM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614074593 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.2614074593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3304850574
Short name T877
Test name
Test status
Simulation time 2009642491 ps
CPU time 6.66 seconds
Started Oct 12 01:07:30 AM UTC 24
Finished Oct 12 01:07:38 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304850574 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.3304850574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1345080133
Short name T883
Test name
Test status
Simulation time 7013164320 ps
CPU time 8.61 seconds
Started Oct 12 01:07:30 AM UTC 24
Finished Oct 12 01:07:40 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345080133 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.1345080133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2374982476
Short name T873
Test name
Test status
Simulation time 2108890844 ps
CPU time 7.25 seconds
Started Oct 12 01:07:28 AM UTC 24
Finished Oct 12 01:07:37 AM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374982476 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.2374982476
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.209312906
Short name T409
Test name
Test status
Simulation time 42992906173 ps
CPU time 33.61 seconds
Started Oct 12 01:07:30 AM UTC 24
Finished Oct 12 01:08:05 AM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209312906 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.209312906
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4188252624
Short name T874
Test name
Test status
Simulation time 2151805985 ps
CPU time 2.94 seconds
Started Oct 12 01:07:32 AM UTC 24
Finished Oct 12 01:07:37 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4188252624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_csr_mem_rw_with_rand_reset.4188252624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2813525162
Short name T870
Test name
Test status
Simulation time 2161566371 ps
CPU time 1.83 seconds
Started Oct 12 01:07:31 AM UTC 24
Finished Oct 12 01:07:34 AM UTC 24
Peak memory 208048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813525162 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.2813525162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3342931340
Short name T871
Test name
Test status
Simulation time 2035417121 ps
CPU time 3.31 seconds
Started Oct 12 01:07:31 AM UTC 24
Finished Oct 12 01:07:35 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342931340 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.3342931340
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3978221873
Short name T895
Test name
Test status
Simulation time 4423109460 ps
CPU time 10.64 seconds
Started Oct 12 01:07:32 AM UTC 24
Finished Oct 12 01:07:44 AM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978221873 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.3978221873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3398528938
Short name T882
Test name
Test status
Simulation time 2213653447 ps
CPU time 7.07 seconds
Started Oct 12 01:07:31 AM UTC 24
Finished Oct 12 01:07:39 AM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398528938 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.3398528938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.543094848
Short name T917
Test name
Test status
Simulation time 42725028182 ps
CPU time 64.14 seconds
Started Oct 12 01:07:31 AM UTC 24
Finished Oct 12 01:08:37 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543094848 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.543094848
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2306755332
Short name T297
Test name
Test status
Simulation time 2694421958 ps
CPU time 6.64 seconds
Started Oct 12 01:06:13 AM UTC 24
Finished Oct 12 01:06:20 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306755332 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.2306755332
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.522427512
Short name T352
Test name
Test status
Simulation time 56369786549 ps
CPU time 56.83 seconds
Started Oct 12 01:06:11 AM UTC 24
Finished Oct 12 01:07:09 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522427512 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.522427512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1900719762
Short name T349
Test name
Test status
Simulation time 6016088738 ps
CPU time 32.48 seconds
Started Oct 12 01:06:10 AM UTC 24
Finished Oct 12 01:06:43 AM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900719762 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.1900719762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3345392640
Short name T294
Test name
Test status
Simulation time 2092203556 ps
CPU time 4.22 seconds
Started Oct 12 01:06:15 AM UTC 24
Finished Oct 12 01:06:20 AM UTC 24
Peak memory 209512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3345392640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3345392640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1040512001
Short name T296
Test name
Test status
Simulation time 2039782613 ps
CPU time 3.65 seconds
Started Oct 12 01:06:11 AM UTC 24
Finished Oct 12 01:06:15 AM UTC 24
Peak memory 209456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040512001 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.1040512001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.4047705006
Short name T811
Test name
Test status
Simulation time 2015245523 ps
CPU time 5.48 seconds
Started Oct 12 01:06:08 AM UTC 24
Finished Oct 12 01:06:15 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047705006 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.4047705006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.467426916
Short name T26
Test name
Test status
Simulation time 8018813965 ps
CPU time 15.23 seconds
Started Oct 12 01:06:14 AM UTC 24
Finished Oct 12 01:06:30 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467426916 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.467426916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2965205957
Short name T284
Test name
Test status
Simulation time 2099064433 ps
CPU time 4.47 seconds
Started Oct 12 01:06:07 AM UTC 24
Finished Oct 12 01:06:13 AM UTC 24
Peak memory 209676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965205957 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.2965205957
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3835147551
Short name T914
Test name
Test status
Simulation time 42378921090 ps
CPU time 122.36 seconds
Started Oct 12 01:06:07 AM UTC 24
Finished Oct 12 01:08:12 AM UTC 24
Peak memory 209804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835147551 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.3835147551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.4269620434
Short name T889
Test name
Test status
Simulation time 2013149302 ps
CPU time 7.78 seconds
Started Oct 12 01:07:32 AM UTC 24
Finished Oct 12 01:07:42 AM UTC 24
Peak memory 209604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269620434 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.4269620434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1768139898
Short name T872
Test name
Test status
Simulation time 2039531937 ps
CPU time 2.77 seconds
Started Oct 12 01:07:33 AM UTC 24
Finished Oct 12 01:07:37 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768139898 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.1768139898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3102158840
Short name T876
Test name
Test status
Simulation time 2044681070 ps
CPU time 2.61 seconds
Started Oct 12 01:07:34 AM UTC 24
Finished Oct 12 01:07:37 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102158840 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.3102158840
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.919275295
Short name T881
Test name
Test status
Simulation time 2019173993 ps
CPU time 4.34 seconds
Started Oct 12 01:07:34 AM UTC 24
Finished Oct 12 01:07:39 AM UTC 24
Peak memory 209284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919275295 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.919275295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3982537911
Short name T878
Test name
Test status
Simulation time 2034460980 ps
CPU time 3.03 seconds
Started Oct 12 01:07:34 AM UTC 24
Finished Oct 12 01:07:38 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982537911 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.3982537911
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1778164225
Short name T891
Test name
Test status
Simulation time 2011934128 ps
CPU time 6.41 seconds
Started Oct 12 01:07:35 AM UTC 24
Finished Oct 12 01:07:43 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778164225 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.1778164225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1716463872
Short name T884
Test name
Test status
Simulation time 2016813996 ps
CPU time 3.95 seconds
Started Oct 12 01:07:35 AM UTC 24
Finished Oct 12 01:07:40 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716463872 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.1716463872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2864425460
Short name T893
Test name
Test status
Simulation time 2014833484 ps
CPU time 7.36 seconds
Started Oct 12 01:07:35 AM UTC 24
Finished Oct 12 01:07:44 AM UTC 24
Peak memory 209672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864425460 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.2864425460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3491331997
Short name T892
Test name
Test status
Simulation time 2011958415 ps
CPU time 5.83 seconds
Started Oct 12 01:07:36 AM UTC 24
Finished Oct 12 01:07:43 AM UTC 24
Peak memory 209668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491331997 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.3491331997
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1554280468
Short name T888
Test name
Test status
Simulation time 2033908652 ps
CPU time 2.3 seconds
Started Oct 12 01:07:37 AM UTC 24
Finished Oct 12 01:07:41 AM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554280468 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.1554280468
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.603566398
Short name T411
Test name
Test status
Simulation time 2512096845 ps
CPU time 15.59 seconds
Started Oct 12 01:06:23 AM UTC 24
Finished Oct 12 01:06:39 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603566398 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.603566398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3077462471
Short name T916
Test name
Test status
Simulation time 39647086647 ps
CPU time 118.35 seconds
Started Oct 12 01:06:22 AM UTC 24
Finished Oct 12 01:08:22 AM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077462471 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.3077462471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4265370217
Short name T812
Test name
Test status
Simulation time 4046156571 ps
CPU time 4.19 seconds
Started Oct 12 01:06:21 AM UTC 24
Finished Oct 12 01:06:27 AM UTC 24
Peak memory 209580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265370217 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.4265370217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3895705542
Short name T410
Test name
Test status
Simulation time 2077010470 ps
CPU time 5.01 seconds
Started Oct 12 01:06:25 AM UTC 24
Finished Oct 12 01:06:31 AM UTC 24
Peak memory 209444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3895705542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3895705542
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1850888327
Short name T346
Test name
Test status
Simulation time 2030187871 ps
CPU time 10.67 seconds
Started Oct 12 01:06:21 AM UTC 24
Finished Oct 12 01:06:33 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850888327 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.1850888327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.47359918
Short name T813
Test name
Test status
Simulation time 2011682011 ps
CPU time 10.93 seconds
Started Oct 12 01:06:18 AM UTC 24
Finished Oct 12 01:06:30 AM UTC 24
Peak memory 209612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47359918 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.47359918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2283199805
Short name T359
Test name
Test status
Simulation time 9598193326 ps
CPU time 22.58 seconds
Started Oct 12 01:06:24 AM UTC 24
Finished Oct 12 01:06:48 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283199805 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.2283199805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1737515998
Short name T300
Test name
Test status
Simulation time 2084147741 ps
CPU time 4.46 seconds
Started Oct 12 01:06:16 AM UTC 24
Finished Oct 12 01:06:22 AM UTC 24
Peak memory 209724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737515998 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.1737515998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3563152319
Short name T868
Test name
Test status
Simulation time 22183835143 ps
CPU time 75.79 seconds
Started Oct 12 01:06:16 AM UTC 24
Finished Oct 12 01:07:34 AM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563152319 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.3563152319
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.803532764
Short name T885
Test name
Test status
Simulation time 2052103114 ps
CPU time 1.83 seconds
Started Oct 12 01:07:37 AM UTC 24
Finished Oct 12 01:07:41 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803532764 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.803532764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1939351004
Short name T896
Test name
Test status
Simulation time 2019276244 ps
CPU time 5.77 seconds
Started Oct 12 01:07:38 AM UTC 24
Finished Oct 12 01:07:44 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939351004 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.1939351004
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.4210735270
Short name T886
Test name
Test status
Simulation time 2090463185 ps
CPU time 1.77 seconds
Started Oct 12 01:07:38 AM UTC 24
Finished Oct 12 01:07:41 AM UTC 24
Peak memory 208576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210735270 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.4210735270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.381954447
Short name T890
Test name
Test status
Simulation time 2044231217 ps
CPU time 2.36 seconds
Started Oct 12 01:07:39 AM UTC 24
Finished Oct 12 01:07:42 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381954447 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.381954447
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3645546984
Short name T905
Test name
Test status
Simulation time 2013689241 ps
CPU time 7.1 seconds
Started Oct 12 01:07:39 AM UTC 24
Finished Oct 12 01:07:47 AM UTC 24
Peak memory 209320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645546984 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.3645546984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1746031813
Short name T903
Test name
Test status
Simulation time 2015889291 ps
CPU time 6.26 seconds
Started Oct 12 01:07:39 AM UTC 24
Finished Oct 12 01:07:47 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746031813 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.1746031813
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.297999782
Short name T897
Test name
Test status
Simulation time 2019785320 ps
CPU time 4.24 seconds
Started Oct 12 01:07:39 AM UTC 24
Finished Oct 12 01:07:45 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297999782 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.297999782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3663093201
Short name T900
Test name
Test status
Simulation time 2009062260 ps
CPU time 5.8 seconds
Started Oct 12 01:07:39 AM UTC 24
Finished Oct 12 01:07:46 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663093201 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.3663093201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2843930721
Short name T901
Test name
Test status
Simulation time 2020296337 ps
CPU time 6.09 seconds
Started Oct 12 01:07:39 AM UTC 24
Finished Oct 12 01:07:47 AM UTC 24
Peak memory 209608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843930721 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.2843930721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2709741768
Short name T908
Test name
Test status
Simulation time 2010411647 ps
CPU time 6.73 seconds
Started Oct 12 01:07:40 AM UTC 24
Finished Oct 12 01:07:48 AM UTC 24
Peak memory 209316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709741768 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.2709741768
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1326373762
Short name T815
Test name
Test status
Simulation time 2676899553 ps
CPU time 11.19 seconds
Started Oct 12 01:06:35 AM UTC 24
Finished Oct 12 01:06:47 AM UTC 24
Peak memory 210112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326373762 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.1326373762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.211532563
Short name T915
Test name
Test status
Simulation time 38806754967 ps
CPU time 106.98 seconds
Started Oct 12 01:06:32 AM UTC 24
Finished Oct 12 01:08:21 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211532563 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.211532563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2372170232
Short name T348
Test name
Test status
Simulation time 4028441138 ps
CPU time 10.34 seconds
Started Oct 12 01:06:31 AM UTC 24
Finished Oct 12 01:06:43 AM UTC 24
Peak memory 209516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372170232 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.2372170232
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1879914175
Short name T413
Test name
Test status
Simulation time 2089872015 ps
CPU time 7.19 seconds
Started Oct 12 01:06:42 AM UTC 24
Finished Oct 12 01:06:50 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1879914175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_csr_mem_rw_with_rand_reset.1879914175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2796747278
Short name T347
Test name
Test status
Simulation time 2119511322 ps
CPU time 3.32 seconds
Started Oct 12 01:06:32 AM UTC 24
Finished Oct 12 01:06:37 AM UTC 24
Peak memory 209452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796747278 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.2796747278
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.782914472
Short name T814
Test name
Test status
Simulation time 2010495926 ps
CPU time 10.56 seconds
Started Oct 12 01:06:31 AM UTC 24
Finished Oct 12 01:06:43 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782914472 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.782914472
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3711951204
Short name T358
Test name
Test status
Simulation time 10072132610 ps
CPU time 9.44 seconds
Started Oct 12 01:06:37 AM UTC 24
Finished Oct 12 01:06:47 AM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711951204 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.3711951204
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3245426538
Short name T303
Test name
Test status
Simulation time 2062644907 ps
CPU time 11.67 seconds
Started Oct 12 01:06:26 AM UTC 24
Finished Oct 12 01:06:39 AM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245426538 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.3245426538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3122845323
Short name T404
Test name
Test status
Simulation time 42626207032 ps
CPU time 60.73 seconds
Started Oct 12 01:06:27 AM UTC 24
Finished Oct 12 01:07:29 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122845323 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.3122845323
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2165309904
Short name T909
Test name
Test status
Simulation time 2010706920 ps
CPU time 7.06 seconds
Started Oct 12 01:07:40 AM UTC 24
Finished Oct 12 01:07:49 AM UTC 24
Peak memory 209320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165309904 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.2165309904
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3938411177
Short name T894
Test name
Test status
Simulation time 2036828925 ps
CPU time 2.18 seconds
Started Oct 12 01:07:41 AM UTC 24
Finished Oct 12 01:07:44 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938411177 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.3938411177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2104515426
Short name T898
Test name
Test status
Simulation time 2052169096 ps
CPU time 3.33 seconds
Started Oct 12 01:07:41 AM UTC 24
Finished Oct 12 01:07:45 AM UTC 24
Peak memory 209288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104515426 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.2104515426
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2882514704
Short name T902
Test name
Test status
Simulation time 2020186536 ps
CPU time 4.58 seconds
Started Oct 12 01:07:41 AM UTC 24
Finished Oct 12 01:07:47 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882514704 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.2882514704
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2763515686
Short name T906
Test name
Test status
Simulation time 2016286560 ps
CPU time 4.28 seconds
Started Oct 12 01:07:42 AM UTC 24
Finished Oct 12 01:07:47 AM UTC 24
Peak memory 209324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763515686 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.2763515686
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.869290905
Short name T911
Test name
Test status
Simulation time 2016065521 ps
CPU time 8.22 seconds
Started Oct 12 01:07:42 AM UTC 24
Finished Oct 12 01:07:51 AM UTC 24
Peak memory 209396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869290905 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.869290905
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2888545379
Short name T904
Test name
Test status
Simulation time 2016790592 ps
CPU time 3.49 seconds
Started Oct 12 01:07:42 AM UTC 24
Finished Oct 12 01:07:47 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888545379 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.2888545379
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.4289808275
Short name T899
Test name
Test status
Simulation time 2027598703 ps
CPU time 2.3 seconds
Started Oct 12 01:07:42 AM UTC 24
Finished Oct 12 01:07:45 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289808275 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.4289808275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1029984849
Short name T910
Test name
Test status
Simulation time 2012153155 ps
CPU time 7.88 seconds
Started Oct 12 01:07:42 AM UTC 24
Finished Oct 12 01:07:51 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029984849 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.1029984849
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3510812198
Short name T907
Test name
Test status
Simulation time 2021902737 ps
CPU time 3.99 seconds
Started Oct 12 01:07:43 AM UTC 24
Finished Oct 12 01:07:48 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510812198 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.3510812198
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2929313935
Short name T412
Test name
Test status
Simulation time 2117007501 ps
CPU time 3.78 seconds
Started Oct 12 01:06:43 AM UTC 24
Finished Oct 12 01:06:48 AM UTC 24
Peak memory 209780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2929313935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2929313935
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1962114263
Short name T817
Test name
Test status
Simulation time 2047325785 ps
CPU time 4.62 seconds
Started Oct 12 01:06:43 AM UTC 24
Finished Oct 12 01:06:49 AM UTC 24
Peak memory 209452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962114263 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.1962114263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1270831918
Short name T816
Test name
Test status
Simulation time 2031153265 ps
CPU time 2.83 seconds
Started Oct 12 01:06:43 AM UTC 24
Finished Oct 12 01:06:47 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270831918 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.1270831918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2750570999
Short name T828
Test name
Test status
Simulation time 10581312378 ps
CPU time 21.02 seconds
Started Oct 12 01:06:43 AM UTC 24
Finished Oct 12 01:07:06 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750570999 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.2750570999
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.984978401
Short name T304
Test name
Test status
Simulation time 2048038285 ps
CPU time 6.64 seconds
Started Oct 12 01:06:42 AM UTC 24
Finished Oct 12 01:06:50 AM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984978401 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.984978401
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.859722343
Short name T819
Test name
Test status
Simulation time 2060371436 ps
CPU time 5.2 seconds
Started Oct 12 01:06:47 AM UTC 24
Finished Oct 12 01:06:53 AM UTC 24
Peak memory 209580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=859722343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
sysrst_ctrl_csr_mem_rw_with_rand_reset.859722343
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1707846768
Short name T821
Test name
Test status
Simulation time 2039811597 ps
CPU time 9.06 seconds
Started Oct 12 01:06:45 AM UTC 24
Finished Oct 12 01:06:55 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707846768 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.1707846768
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1107422408
Short name T822
Test name
Test status
Simulation time 2015298779 ps
CPU time 9.84 seconds
Started Oct 12 01:06:45 AM UTC 24
Finished Oct 12 01:06:56 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107422408 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.1107422408
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.697336569
Short name T842
Test name
Test status
Simulation time 9025478757 ps
CPU time 29.32 seconds
Started Oct 12 01:06:46 AM UTC 24
Finished Oct 12 01:07:16 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697336569 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.697336569
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1736970721
Short name T302
Test name
Test status
Simulation time 2035067294 ps
CPU time 12.18 seconds
Started Oct 12 01:06:44 AM UTC 24
Finished Oct 12 01:06:57 AM UTC 24
Peak memory 209728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736970721 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.1736970721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.4183541624
Short name T919
Test name
Test status
Simulation time 42407594256 ps
CPU time 147.11 seconds
Started Oct 12 01:06:44 AM UTC 24
Finished Oct 12 01:09:13 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183541624 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.4183541624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2064396066
Short name T414
Test name
Test status
Simulation time 2129131123 ps
CPU time 3.53 seconds
Started Oct 12 01:06:50 AM UTC 24
Finished Oct 12 01:06:55 AM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2064396066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2064396066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2428596624
Short name T820
Test name
Test status
Simulation time 2042816995 ps
CPU time 4.74 seconds
Started Oct 12 01:06:48 AM UTC 24
Finished Oct 12 01:06:54 AM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428596624 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.2428596624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1244310872
Short name T818
Test name
Test status
Simulation time 2036640387 ps
CPU time 3.25 seconds
Started Oct 12 01:06:48 AM UTC 24
Finished Oct 12 01:06:52 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244310872 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.1244310872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2635872487
Short name T830
Test name
Test status
Simulation time 7759489841 ps
CPU time 17.36 seconds
Started Oct 12 01:06:49 AM UTC 24
Finished Oct 12 01:07:08 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635872487 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.2635872487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2597356153
Short name T826
Test name
Test status
Simulation time 2151741843 ps
CPU time 14.28 seconds
Started Oct 12 01:06:48 AM UTC 24
Finished Oct 12 01:07:04 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597356153 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.2597356153
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1256811184
Short name T287
Test name
Test status
Simulation time 22255198288 ps
CPU time 23.42 seconds
Started Oct 12 01:06:48 AM UTC 24
Finished Oct 12 01:07:13 AM UTC 24
Peak memory 209828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256811184 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.1256811184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2495814344
Short name T825
Test name
Test status
Simulation time 2053117432 ps
CPU time 6.24 seconds
Started Oct 12 01:06:56 AM UTC 24
Finished Oct 12 01:07:03 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2495814344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2495814344
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3643307749
Short name T350
Test name
Test status
Simulation time 2196956672 ps
CPU time 1.54 seconds
Started Oct 12 01:06:54 AM UTC 24
Finished Oct 12 01:06:56 AM UTC 24
Peak memory 208044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643307749 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.3643307749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1290050551
Short name T823
Test name
Test status
Simulation time 2046566236 ps
CPU time 2.93 seconds
Started Oct 12 01:06:54 AM UTC 24
Finished Oct 12 01:06:58 AM UTC 24
Peak memory 209396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290050551 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.1290050551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.570698903
Short name T857
Test name
Test status
Simulation time 5140932759 ps
CPU time 32.33 seconds
Started Oct 12 01:06:55 AM UTC 24
Finished Oct 12 01:07:29 AM UTC 24
Peak memory 210040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570698903 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.570698903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.21845252
Short name T920
Test name
Test status
Simulation time 42403029534 ps
CPU time 141.48 seconds
Started Oct 12 01:06:52 AM UTC 24
Finished Oct 12 01:09:15 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21845252 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.21845252
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.586420420
Short name T832
Test name
Test status
Simulation time 2064161475 ps
CPU time 8.77 seconds
Started Oct 12 01:06:59 AM UTC 24
Finished Oct 12 01:07:08 AM UTC 24
Peak memory 209584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=586420420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
sysrst_ctrl_csr_mem_rw_with_rand_reset.586420420
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2937502711
Short name T351
Test name
Test status
Simulation time 2064229633 ps
CPU time 11.2 seconds
Started Oct 12 01:06:57 AM UTC 24
Finished Oct 12 01:07:10 AM UTC 24
Peak memory 209452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937502711 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.2937502711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.557481678
Short name T824
Test name
Test status
Simulation time 2026043496 ps
CPU time 4.8 seconds
Started Oct 12 01:06:57 AM UTC 24
Finished Oct 12 01:07:03 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557481678 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.557481678
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2765989027
Short name T827
Test name
Test status
Simulation time 5048200135 ps
CPU time 5.84 seconds
Started Oct 12 01:06:58 AM UTC 24
Finished Oct 12 01:07:05 AM UTC 24
Peak memory 209828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765989027 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.2765989027
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.990431385
Short name T831
Test name
Test status
Simulation time 2043492928 ps
CPU time 10.88 seconds
Started Oct 12 01:06:56 AM UTC 24
Finished Oct 12 01:07:08 AM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990431385 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.990431385
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.156599197
Short name T407
Test name
Test status
Simulation time 42528637295 ps
CPU time 79.58 seconds
Started Oct 12 01:06:57 AM UTC 24
Finished Oct 12 01:08:19 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156599197 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.156599197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1400772691
Short name T29
Test name
Test status
Simulation time 3281144369 ps
CPU time 6.87 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:43 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400772691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1400772691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1651890407
Short name T6
Test name
Test status
Simulation time 2298833762 ps
CPU time 5.92 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:34 AM UTC 24
Peak memory 209556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651890407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1651890407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.3689207873
Short name T16
Test name
Test status
Simulation time 4458001601 ps
CPU time 2.35 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:38 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689207873 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.3689207873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.3863814473
Short name T2
Test name
Test status
Simulation time 3506796788 ps
CPU time 4.03 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:40 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863814473 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.3863814473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.496073939
Short name T17
Test name
Test status
Simulation time 2636619376 ps
CPU time 2.27 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:38 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496073939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.496073939
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3979492393
Short name T14
Test name
Test status
Simulation time 2471443553 ps
CPU time 6.62 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:35 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979492393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.3979492393
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.4208000125
Short name T5
Test name
Test status
Simulation time 2108047853 ps
CPU time 5.84 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:34 AM UTC 24
Peak memory 209316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208000125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.4208000125
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1476280835
Short name T8
Test name
Test status
Simulation time 5291511180 ps
CPU time 6.63 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:43 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476280835 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.1476280835
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.371316167
Short name T22
Test name
Test status
Simulation time 2022078784 ps
CPU time 2.94 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:40 AM UTC 24
Peak memory 209224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371316167 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.371316167
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1936116936
Short name T20
Test name
Test status
Simulation time 3672773996 ps
CPU time 2.48 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:39 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936116936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1936116936
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.1539590055
Short name T256
Test name
Test status
Simulation time 115866172406 ps
CPU time 349.34 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 01:02:29 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539590055 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.1539590055
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3133642789
Short name T19
Test name
Test status
Simulation time 2237549220 ps
CPU time 2.45 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:39 AM UTC 24
Peak memory 209444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133642789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.3133642789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1547191073
Short name T10
Test name
Test status
Simulation time 2531607755 ps
CPU time 7.58 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:44 AM UTC 24
Peak memory 209292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547191073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1547191073
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.4029988258
Short name T307
Test name
Test status
Simulation time 5369075277 ps
CPU time 15.89 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:53 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029988258 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.4029988258
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.644936471
Short name T9
Test name
Test status
Simulation time 2474634970 ps
CPU time 6.49 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:43 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644936471 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.644936471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2769523429
Short name T21
Test name
Test status
Simulation time 2622888570 ps
CPU time 2.72 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:39 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769523429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.2769523429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1732291265
Short name T27
Test name
Test status
Simulation time 2463709715 ps
CPU time 4.66 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:41 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732291265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.1732291265
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.2473550373
Short name T18
Test name
Test status
Simulation time 2117553577 ps
CPU time 2.08 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:39 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473550373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.2473550373
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.945816324
Short name T85
Test name
Test status
Simulation time 2512174679 ps
CPU time 6.31 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:43 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945816324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.945816324
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.2689413926
Short name T281
Test name
Test status
Simulation time 22077763750 ps
CPU time 15.95 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:53 AM UTC 24
Peak memory 241008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689413926 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2689413926
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.3137998270
Short name T15
Test name
Test status
Simulation time 2230837132 ps
CPU time 0.94 seconds
Started Oct 12 12:56:35 AM UTC 24
Finished Oct 12 12:56:37 AM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137998270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.3137998270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.3281549715
Short name T91
Test name
Test status
Simulation time 6471542032 ps
CPU time 20.13 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:57 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281549715 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.3281549715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2470478289
Short name T299
Test name
Test status
Simulation time 7060648790 ps
CPU time 19.29 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:56 AM UTC 24
Peak memory 221912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2470478289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.2470478289
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.327517206
Short name T3
Test name
Test status
Simulation time 5261303408 ps
CPU time 4.18 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:41 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327517206 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.327517206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2192997872
Short name T134
Test name
Test status
Simulation time 2015051273 ps
CPU time 7.01 seconds
Started Oct 12 12:57:21 AM UTC 24
Finished Oct 12 12:57:29 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192997872 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.2192997872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.796468928
Short name T114
Test name
Test status
Simulation time 3394395382 ps
CPU time 2.3 seconds
Started Oct 12 12:57:18 AM UTC 24
Finished Oct 12 12:57:22 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796468928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.796468928
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.4257051412
Short name T59
Test name
Test status
Simulation time 53791125030 ps
CPU time 20.97 seconds
Started Oct 12 12:57:19 AM UTC 24
Finished Oct 12 12:57:42 AM UTC 24
Peak memory 209604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257051412 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.4257051412
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1698386295
Short name T97
Test name
Test status
Simulation time 26594388002 ps
CPU time 19.1 seconds
Started Oct 12 12:57:20 AM UTC 24
Finished Oct 12 12:57:40 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698386295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_with_pre_cond.1698386295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.400103572
Short name T133
Test name
Test status
Simulation time 3950170691 ps
CPU time 9.68 seconds
Started Oct 12 12:57:18 AM UTC 24
Finished Oct 12 12:57:29 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400103572 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.400103572
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.2491643459
Short name T57
Test name
Test status
Simulation time 3109908635 ps
CPU time 9.33 seconds
Started Oct 12 12:57:20 AM UTC 24
Finished Oct 12 12:57:30 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491643459 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.2491643459
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.413513624
Short name T129
Test name
Test status
Simulation time 2609175071 ps
CPU time 8.14 seconds
Started Oct 12 12:57:18 AM UTC 24
Finished Oct 12 12:57:27 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413513624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.413513624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.176511702
Short name T132
Test name
Test status
Simulation time 2451806444 ps
CPU time 11.21 seconds
Started Oct 12 12:57:16 AM UTC 24
Finished Oct 12 12:57:29 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176511702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.176511702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.1280409955
Short name T183
Test name
Test status
Simulation time 2284099717 ps
CPU time 2.04 seconds
Started Oct 12 12:57:16 AM UTC 24
Finished Oct 12 12:57:19 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280409955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.1280409955
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.237962738
Short name T177
Test name
Test status
Simulation time 2531778329 ps
CPU time 2.95 seconds
Started Oct 12 12:57:18 AM UTC 24
Finished Oct 12 12:57:22 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237962738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.237962738
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.1442999466
Short name T182
Test name
Test status
Simulation time 2132470680 ps
CPU time 3.12 seconds
Started Oct 12 12:57:15 AM UTC 24
Finished Oct 12 12:57:19 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442999466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.1442999466
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2975913264
Short name T108
Test name
Test status
Simulation time 45508496473 ps
CPU time 40.1 seconds
Started Oct 12 12:57:21 AM UTC 24
Finished Oct 12 12:58:02 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975913264 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.2975913264
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3490126308
Short name T127
Test name
Test status
Simulation time 3777860886 ps
CPU time 5.72 seconds
Started Oct 12 12:57:20 AM UTC 24
Finished Oct 12 12:57:26 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3490126308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.3490126308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2287385588
Short name T83
Test name
Test status
Simulation time 6227974498 ps
CPU time 12.66 seconds
Started Oct 12 12:57:18 AM UTC 24
Finished Oct 12 12:57:32 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287385588 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.2287385588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1674042750
Short name T439
Test name
Test status
Simulation time 2055029980 ps
CPU time 1.57 seconds
Started Oct 12 12:57:29 AM UTC 24
Finished Oct 12 12:57:31 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674042750 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.1674042750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.235605342
Short name T445
Test name
Test status
Simulation time 3631157231 ps
CPU time 5.51 seconds
Started Oct 12 12:57:24 AM UTC 24
Finished Oct 12 12:57:31 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235605342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.235605342
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3644448630
Short name T98
Test name
Test status
Simulation time 22592067539 ps
CPU time 30.6 seconds
Started Oct 12 12:57:27 AM UTC 24
Finished Oct 12 12:57:59 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644448630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_with_pre_cond.3644448630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1694452551
Short name T244
Test name
Test status
Simulation time 4804566770 ps
CPU time 17.57 seconds
Started Oct 12 12:57:24 AM UTC 24
Finished Oct 12 12:57:43 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694452551 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.1694452551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.1318248955
Short name T52
Test name
Test status
Simulation time 2896958836 ps
CPU time 13.37 seconds
Started Oct 12 12:57:25 AM UTC 24
Finished Oct 12 12:57:40 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318248955 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.1318248955
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.4057098532
Short name T126
Test name
Test status
Simulation time 2646754224 ps
CPU time 2.92 seconds
Started Oct 12 12:57:22 AM UTC 24
Finished Oct 12 12:57:26 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057098532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.4057098532
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3567008116
Short name T450
Test name
Test status
Simulation time 2464828408 ps
CPU time 12.5 seconds
Started Oct 12 12:57:21 AM UTC 24
Finished Oct 12 12:57:35 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567008116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3567008116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.2270846856
Short name T444
Test name
Test status
Simulation time 2087713933 ps
CPU time 8.04 seconds
Started Oct 12 12:57:21 AM UTC 24
Finished Oct 12 12:57:30 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270846856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.2270846856
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2112810946
Short name T443
Test name
Test status
Simulation time 2508938286 ps
CPU time 6.9 seconds
Started Oct 12 12:57:21 AM UTC 24
Finished Oct 12 12:57:29 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112810946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2112810946
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2957518292
Short name T130
Test name
Test status
Simulation time 2122411541 ps
CPU time 5.31 seconds
Started Oct 12 12:57:21 AM UTC 24
Finished Oct 12 12:57:27 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957518292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2957518292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2772457210
Short name T260
Test name
Test status
Simulation time 12722922574 ps
CPU time 13.26 seconds
Started Oct 12 12:57:27 AM UTC 24
Finished Oct 12 12:57:42 AM UTC 24
Peak memory 209360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772457210 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.2772457210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2670853216
Short name T324
Test name
Test status
Simulation time 9118600487 ps
CPU time 10.63 seconds
Started Oct 12 12:57:27 AM UTC 24
Finished Oct 12 12:57:39 AM UTC 24
Peak memory 217908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2670853216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2670853216
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.578697086
Short name T323
Test name
Test status
Simulation time 6059950391 ps
CPU time 4.33 seconds
Started Oct 12 12:57:24 AM UTC 24
Finished Oct 12 12:57:29 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578697086 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.578697086
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.2922294242
Short name T251
Test name
Test status
Simulation time 2012294321 ps
CPU time 6.86 seconds
Started Oct 12 12:57:33 AM UTC 24
Finished Oct 12 12:57:41 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922294242 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.2922294242
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3984450554
Short name T252
Test name
Test status
Simulation time 3362506826 ps
CPU time 10.05 seconds
Started Oct 12 12:57:30 AM UTC 24
Finished Oct 12 12:57:42 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984450554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3984450554
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.1483706410
Short name T255
Test name
Test status
Simulation time 87956042615 ps
CPU time 222.21 seconds
Started Oct 12 12:57:31 AM UTC 24
Finished Oct 12 01:01:17 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483706410 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.1483706410
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.772712581
Short name T456
Test name
Test status
Simulation time 4236922439 ps
CPU time 17.46 seconds
Started Oct 12 12:57:30 AM UTC 24
Finished Oct 12 12:57:49 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772712581 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.772712581
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.2553950074
Short name T201
Test name
Test status
Simulation time 2586391269 ps
CPU time 4.85 seconds
Started Oct 12 12:57:31 AM UTC 24
Finished Oct 12 12:57:37 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553950074 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.2553950074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.415608815
Short name T451
Test name
Test status
Simulation time 2619735741 ps
CPU time 4.21 seconds
Started Oct 12 12:57:30 AM UTC 24
Finished Oct 12 12:57:35 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415608815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.415608815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2770683346
Short name T448
Test name
Test status
Simulation time 2470175748 ps
CPU time 4.99 seconds
Started Oct 12 12:57:29 AM UTC 24
Finished Oct 12 12:57:35 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770683346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2770683346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.498112035
Short name T449
Test name
Test status
Simulation time 2144336220 ps
CPU time 3.73 seconds
Started Oct 12 12:57:30 AM UTC 24
Finished Oct 12 12:57:35 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498112035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.498112035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.804807675
Short name T447
Test name
Test status
Simulation time 2545559967 ps
CPU time 1.97 seconds
Started Oct 12 12:57:30 AM UTC 24
Finished Oct 12 12:57:33 AM UTC 24
Peak memory 207028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804807675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.804807675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.241612215
Short name T446
Test name
Test status
Simulation time 2128844457 ps
CPU time 1.99 seconds
Started Oct 12 12:57:29 AM UTC 24
Finished Oct 12 12:57:32 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241612215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.241612215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3786449125
Short name T224
Test name
Test status
Simulation time 16395478954 ps
CPU time 11.84 seconds
Started Oct 12 12:57:33 AM UTC 24
Finished Oct 12 12:57:46 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3786449125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3786449125
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4278539375
Short name T143
Test name
Test status
Simulation time 2664365060 ps
CPU time 4.8 seconds
Started Oct 12 12:57:31 AM UTC 24
Finished Oct 12 12:57:37 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278539375 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.4278539375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1207871186
Short name T221
Test name
Test status
Simulation time 2032051982 ps
CPU time 2.01 seconds
Started Oct 12 12:57:40 AM UTC 24
Finished Oct 12 12:57:43 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207871186 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.1207871186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2661604473
Short name T242
Test name
Test status
Simulation time 4102220651 ps
CPU time 4.38 seconds
Started Oct 12 12:57:37 AM UTC 24
Finished Oct 12 12:57:42 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661604473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2661604473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2434957171
Short name T47
Test name
Test status
Simulation time 93962379996 ps
CPU time 131.09 seconds
Started Oct 12 12:57:38 AM UTC 24
Finished Oct 12 12:59:51 AM UTC 24
Peak memory 209820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434957171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_with_pre_cond.2434957171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.2227622381
Short name T243
Test name
Test status
Simulation time 3898472620 ps
CPU time 5.5 seconds
Started Oct 12 12:57:36 AM UTC 24
Finished Oct 12 12:57:42 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227622381 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.2227622381
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.3530820676
Short name T54
Test name
Test status
Simulation time 3800147666 ps
CPU time 3.83 seconds
Started Oct 12 12:57:38 AM UTC 24
Finished Oct 12 12:57:43 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530820676 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.3530820676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.448969733
Short name T250
Test name
Test status
Simulation time 2624734979 ps
CPU time 3.05 seconds
Started Oct 12 12:57:35 AM UTC 24
Finished Oct 12 12:57:40 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448969733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.448969733
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.222446984
Short name T453
Test name
Test status
Simulation time 2487377399 ps
CPU time 2.69 seconds
Started Oct 12 12:57:34 AM UTC 24
Finished Oct 12 12:57:38 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222446984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.222446984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.3748521574
Short name T454
Test name
Test status
Simulation time 2066432438 ps
CPU time 2.74 seconds
Started Oct 12 12:57:35 AM UTC 24
Finished Oct 12 12:57:39 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748521574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.3748521574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.2705248674
Short name T228
Test name
Test status
Simulation time 2514747150 ps
CPU time 10.54 seconds
Started Oct 12 12:57:35 AM UTC 24
Finished Oct 12 12:57:47 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705248674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.2705248674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.3372063428
Short name T452
Test name
Test status
Simulation time 2136977922 ps
CPU time 3.04 seconds
Started Oct 12 12:57:33 AM UTC 24
Finished Oct 12 12:57:37 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372063428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.3372063428
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.1395942918
Short name T154
Test name
Test status
Simulation time 311405935313 ps
CPU time 525.6 seconds
Started Oct 12 12:57:40 AM UTC 24
Finished Oct 12 01:06:31 AM UTC 24
Peak memory 209360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395942918 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.1395942918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3527636590
Short name T457
Test name
Test status
Simulation time 7752827966 ps
CPU time 8.64 seconds
Started Oct 12 12:57:39 AM UTC 24
Finished Oct 12 12:57:49 AM UTC 24
Peak memory 217816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3527636590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3527636590
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3644839890
Short name T113
Test name
Test status
Simulation time 6182931540 ps
CPU time 9.26 seconds
Started Oct 12 12:57:37 AM UTC 24
Finished Oct 12 12:57:47 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644839890 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.3644839890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.399321632
Short name T227
Test name
Test status
Simulation time 2054287147 ps
CPU time 2.38 seconds
Started Oct 12 12:57:43 AM UTC 24
Finished Oct 12 12:57:47 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399321632 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.399321632
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2355402917
Short name T468
Test name
Test status
Simulation time 3572447015 ps
CPU time 10.22 seconds
Started Oct 12 12:57:43 AM UTC 24
Finished Oct 12 12:57:54 AM UTC 24
Peak memory 209584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355402917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.2355402917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3854928054
Short name T361
Test name
Test status
Simulation time 79458403599 ps
CPU time 264.48 seconds
Started Oct 12 12:57:43 AM UTC 24
Finished Oct 12 01:02:11 AM UTC 24
Peak memory 209408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854928054 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.3854928054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3501097266
Short name T63
Test name
Test status
Simulation time 55952349242 ps
CPU time 52.67 seconds
Started Oct 12 12:57:43 AM UTC 24
Finished Oct 12 12:58:37 AM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501097266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.3501097266
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1943821560
Short name T225
Test name
Test status
Simulation time 4653255119 ps
CPU time 3.38 seconds
Started Oct 12 12:57:42 AM UTC 24
Finished Oct 12 12:57:46 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943821560 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.1943821560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2913599650
Short name T184
Test name
Test status
Simulation time 3419560880 ps
CPU time 7.23 seconds
Started Oct 12 12:57:43 AM UTC 24
Finished Oct 12 12:57:51 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913599650 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.2913599650
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1266844639
Short name T462
Test name
Test status
Simulation time 2611468551 ps
CPU time 9.2 seconds
Started Oct 12 12:57:42 AM UTC 24
Finished Oct 12 12:57:52 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266844639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1266844639
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.2813604290
Short name T223
Test name
Test status
Simulation time 2475184382 ps
CPU time 3.98 seconds
Started Oct 12 12:57:40 AM UTC 24
Finished Oct 12 12:57:45 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813604290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.2813604290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.4159540036
Short name T222
Test name
Test status
Simulation time 2233414965 ps
CPU time 2.22 seconds
Started Oct 12 12:57:40 AM UTC 24
Finished Oct 12 12:57:44 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159540036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.4159540036
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.700145884
Short name T466
Test name
Test status
Simulation time 2508440609 ps
CPU time 11.29 seconds
Started Oct 12 12:57:42 AM UTC 24
Finished Oct 12 12:57:54 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700145884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.700145884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.3443747468
Short name T220
Test name
Test status
Simulation time 2148971260 ps
CPU time 1.7 seconds
Started Oct 12 12:57:40 AM UTC 24
Finished Oct 12 12:57:43 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443747468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3443747468
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.242644505
Short name T480
Test name
Test status
Simulation time 7026900981 ps
CPU time 20.09 seconds
Started Oct 12 12:57:43 AM UTC 24
Finished Oct 12 12:58:05 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242644505 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.242644505
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.25997739
Short name T455
Test name
Test status
Simulation time 6733081707 ps
CPU time 3.62 seconds
Started Oct 12 12:57:43 AM UTC 24
Finished Oct 12 12:57:48 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25997739 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.25997739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1319503391
Short name T475
Test name
Test status
Simulation time 2013615127 ps
CPU time 10.24 seconds
Started Oct 12 12:57:49 AM UTC 24
Finished Oct 12 12:58:01 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319503391 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.1319503391
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.4101776258
Short name T808
Test name
Test status
Simulation time 330519515475 ps
CPU time 1196.95 seconds
Started Oct 12 12:57:47 AM UTC 24
Finished Oct 12 01:17:56 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101776258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.4101776258
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.557508448
Short name T803
Test name
Test status
Simulation time 221174847898 ps
CPU time 630.21 seconds
Started Oct 12 12:57:47 AM UTC 24
Finished Oct 12 01:08:24 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557508448 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.557508448
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1852388169
Short name T240
Test name
Test status
Simulation time 47999696372 ps
CPU time 68.11 seconds
Started Oct 12 12:57:48 AM UTC 24
Finished Oct 12 12:58:58 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852388169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_with_pre_cond.1852388169
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3224915441
Short name T459
Test name
Test status
Simulation time 2712573519 ps
CPU time 3.26 seconds
Started Oct 12 12:57:46 AM UTC 24
Finished Oct 12 12:57:50 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224915441 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.3224915441
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.241319742
Short name T209
Test name
Test status
Simulation time 4476241945 ps
CPU time 8.44 seconds
Started Oct 12 12:57:48 AM UTC 24
Finished Oct 12 12:57:58 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241319742 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.241319742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2575877852
Short name T463
Test name
Test status
Simulation time 2611260298 ps
CPU time 6.72 seconds
Started Oct 12 12:57:45 AM UTC 24
Finished Oct 12 12:57:52 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575877852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.2575877852
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1559989775
Short name T464
Test name
Test status
Simulation time 2463039639 ps
CPU time 8.11 seconds
Started Oct 12 12:57:44 AM UTC 24
Finished Oct 12 12:57:54 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559989775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1559989775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.323731395
Short name T460
Test name
Test status
Simulation time 2180966725 ps
CPU time 4.6 seconds
Started Oct 12 12:57:44 AM UTC 24
Finished Oct 12 12:57:50 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323731395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.323731395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.3562993996
Short name T471
Test name
Test status
Simulation time 2512994974 ps
CPU time 11.19 seconds
Started Oct 12 12:57:45 AM UTC 24
Finished Oct 12 12:57:57 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562993996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.3562993996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.3786594742
Short name T461
Test name
Test status
Simulation time 2118067455 ps
CPU time 6.29 seconds
Started Oct 12 12:57:44 AM UTC 24
Finished Oct 12 12:57:52 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786594742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3786594742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.1453179633
Short name T319
Test name
Test status
Simulation time 11653255963 ps
CPU time 7.8 seconds
Started Oct 12 12:57:48 AM UTC 24
Finished Oct 12 12:57:57 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453179633 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.1453179633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2617239959
Short name T144
Test name
Test status
Simulation time 3607441144 ps
CPU time 7.15 seconds
Started Oct 12 12:57:47 AM UTC 24
Finished Oct 12 12:57:55 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617239959 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.2617239959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.611740963
Short name T476
Test name
Test status
Simulation time 2013767581 ps
CPU time 6.71 seconds
Started Oct 12 12:57:56 AM UTC 24
Finished Oct 12 12:58:03 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611740963 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.611740963
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.2011129761
Short name T469
Test name
Test status
Simulation time 3543739062 ps
CPU time 7.1 seconds
Started Oct 12 12:57:53 AM UTC 24
Finished Oct 12 12:58:01 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011129761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.2011129761
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1147686739
Short name T234
Test name
Test status
Simulation time 94032465616 ps
CPU time 265.98 seconds
Started Oct 12 12:57:53 AM UTC 24
Finished Oct 12 01:02:22 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147686739 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.1147686739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2094558350
Short name T99
Test name
Test status
Simulation time 24084588261 ps
CPU time 40.22 seconds
Started Oct 12 12:57:54 AM UTC 24
Finished Oct 12 12:58:36 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094558350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.2094558350
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3668590172
Short name T472
Test name
Test status
Simulation time 3025705484 ps
CPU time 4.16 seconds
Started Oct 12 12:57:52 AM UTC 24
Finished Oct 12 12:57:57 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668590172 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.3668590172
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.1824631011
Short name T162
Test name
Test status
Simulation time 3619271178 ps
CPU time 4.82 seconds
Started Oct 12 12:57:54 AM UTC 24
Finished Oct 12 12:58:00 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824631011 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.1824631011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3622761241
Short name T479
Test name
Test status
Simulation time 2610290208 ps
CPU time 11.78 seconds
Started Oct 12 12:57:51 AM UTC 24
Finished Oct 12 12:58:04 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622761241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3622761241
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.2441266355
Short name T465
Test name
Test status
Simulation time 2494812893 ps
CPU time 3.27 seconds
Started Oct 12 12:57:50 AM UTC 24
Finished Oct 12 12:57:54 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441266355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2441266355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.3606885540
Short name T477
Test name
Test status
Simulation time 2140713281 ps
CPU time 10 seconds
Started Oct 12 12:57:51 AM UTC 24
Finished Oct 12 12:58:02 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606885540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3606885540
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3638106304
Short name T467
Test name
Test status
Simulation time 2528839927 ps
CPU time 2.5 seconds
Started Oct 12 12:57:51 AM UTC 24
Finished Oct 12 12:57:54 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638106304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.3638106304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1733765491
Short name T470
Test name
Test status
Simulation time 2118908973 ps
CPU time 5.59 seconds
Started Oct 12 12:57:49 AM UTC 24
Finished Oct 12 12:57:56 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733765491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1733765491
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1064613141
Short name T146
Test name
Test status
Simulation time 8616775322 ps
CPU time 7.04 seconds
Started Oct 12 12:57:55 AM UTC 24
Finished Oct 12 12:58:04 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064613141 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.1064613141
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4100601355
Short name T314
Test name
Test status
Simulation time 9880781852 ps
CPU time 8.67 seconds
Started Oct 12 12:57:55 AM UTC 24
Finished Oct 12 12:58:05 AM UTC 24
Peak memory 226212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4100601355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.4100601355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3012739698
Short name T145
Test name
Test status
Simulation time 8249232538 ps
CPU time 5.15 seconds
Started Oct 12 12:57:53 AM UTC 24
Finished Oct 12 12:57:59 AM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012739698 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.3012739698
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.2045949183
Short name T493
Test name
Test status
Simulation time 2012338617 ps
CPU time 7.95 seconds
Started Oct 12 12:58:02 AM UTC 24
Finished Oct 12 12:58:11 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045949183 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.2045949183
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2724404024
Short name T482
Test name
Test status
Simulation time 3515064524 ps
CPU time 4.91 seconds
Started Oct 12 12:58:01 AM UTC 24
Finished Oct 12 12:58:07 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724404024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.2724404024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.1452955502
Short name T400
Test name
Test status
Simulation time 143314349773 ps
CPU time 418.05 seconds
Started Oct 12 12:58:01 AM UTC 24
Finished Oct 12 01:05:04 AM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452955502 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.1452955502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2305106633
Short name T486
Test name
Test status
Simulation time 3875192505 ps
CPU time 9.07 seconds
Started Oct 12 12:57:58 AM UTC 24
Finished Oct 12 12:58:08 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305106633 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.2305106633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.494924039
Short name T50
Test name
Test status
Simulation time 4251222931 ps
CPU time 1.64 seconds
Started Oct 12 12:58:01 AM UTC 24
Finished Oct 12 12:58:04 AM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494924039 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.494924039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3729028584
Short name T478
Test name
Test status
Simulation time 2633794721 ps
CPU time 4.05 seconds
Started Oct 12 12:57:58 AM UTC 24
Finished Oct 12 12:58:03 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729028584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.3729028584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.4257320171
Short name T485
Test name
Test status
Simulation time 2461848308 ps
CPU time 9.72 seconds
Started Oct 12 12:57:57 AM UTC 24
Finished Oct 12 12:58:07 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257320171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.4257320171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.3963910210
Short name T474
Test name
Test status
Simulation time 2171330843 ps
CPU time 2.51 seconds
Started Oct 12 12:57:57 AM UTC 24
Finished Oct 12 12:58:00 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963910210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3963910210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.187658333
Short name T483
Test name
Test status
Simulation time 2511038180 ps
CPU time 7.86 seconds
Started Oct 12 12:57:58 AM UTC 24
Finished Oct 12 12:58:07 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187658333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.187658333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.1281295511
Short name T473
Test name
Test status
Simulation time 2130339325 ps
CPU time 2.71 seconds
Started Oct 12 12:57:56 AM UTC 24
Finished Oct 12 12:57:59 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281295511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.1281295511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3014654473
Short name T325
Test name
Test status
Simulation time 19355595724 ps
CPU time 18.8 seconds
Started Oct 12 12:58:02 AM UTC 24
Finished Oct 12 12:58:22 AM UTC 24
Peak memory 217908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3014654473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.3014654473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3125048681
Short name T481
Test name
Test status
Simulation time 5334354780 ps
CPU time 3.3 seconds
Started Oct 12 12:58:01 AM UTC 24
Finished Oct 12 12:58:05 AM UTC 24
Peak memory 209320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125048681 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.3125048681
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.1939264389
Short name T497
Test name
Test status
Simulation time 2045131180 ps
CPU time 3.21 seconds
Started Oct 12 12:58:10 AM UTC 24
Finished Oct 12 12:58:14 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939264389 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.1939264389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1226782620
Short name T504
Test name
Test status
Simulation time 3842123678 ps
CPU time 11.9 seconds
Started Oct 12 12:58:05 AM UTC 24
Finished Oct 12 12:58:18 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226782620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1226782620
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.1219780822
Short name T248
Test name
Test status
Simulation time 165789558583 ps
CPU time 114.51 seconds
Started Oct 12 12:58:07 AM UTC 24
Finished Oct 12 01:00:04 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219780822 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.1219780822
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2043771048
Short name T368
Test name
Test status
Simulation time 99767950671 ps
CPU time 165.52 seconds
Started Oct 12 12:58:07 AM UTC 24
Finished Oct 12 01:00:55 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043771048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.2043771048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1745637435
Short name T487
Test name
Test status
Simulation time 4333155700 ps
CPU time 2.74 seconds
Started Oct 12 12:58:05 AM UTC 24
Finished Oct 12 12:58:09 AM UTC 24
Peak memory 209624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745637435 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.1745637435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.4018565603
Short name T200
Test name
Test status
Simulation time 2470484132 ps
CPU time 2.94 seconds
Started Oct 12 12:58:07 AM UTC 24
Finished Oct 12 12:58:11 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018565603 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.4018565603
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3842876593
Short name T489
Test name
Test status
Simulation time 2624685717 ps
CPU time 2.74 seconds
Started Oct 12 12:58:05 AM UTC 24
Finished Oct 12 12:58:09 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842876593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.3842876593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1210095492
Short name T484
Test name
Test status
Simulation time 2489027542 ps
CPU time 3.66 seconds
Started Oct 12 12:58:03 AM UTC 24
Finished Oct 12 12:58:07 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210095492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1210095492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1243383670
Short name T495
Test name
Test status
Simulation time 2243325607 ps
CPU time 7.54 seconds
Started Oct 12 12:58:05 AM UTC 24
Finished Oct 12 12:58:13 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243383670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.1243383670
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.3822377502
Short name T492
Test name
Test status
Simulation time 2512369283 ps
CPU time 5.35 seconds
Started Oct 12 12:58:05 AM UTC 24
Finished Oct 12 12:58:11 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822377502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3822377502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.1148871429
Short name T490
Test name
Test status
Simulation time 2115313484 ps
CPU time 5.81 seconds
Started Oct 12 12:58:03 AM UTC 24
Finished Oct 12 12:58:09 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148871429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.1148871429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1289066365
Short name T249
Test name
Test status
Simulation time 71220071316 ps
CPU time 100.86 seconds
Started Oct 12 12:58:10 AM UTC 24
Finished Oct 12 12:59:53 AM UTC 24
Peak memory 209792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289066365 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.1289066365
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.313675047
Short name T152
Test name
Test status
Simulation time 15619177865 ps
CPU time 13 seconds
Started Oct 12 12:58:07 AM UTC 24
Finished Oct 12 12:58:22 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=313675047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.313675047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3040962323
Short name T488
Test name
Test status
Simulation time 6603186213 ps
CPU time 2.6 seconds
Started Oct 12 12:58:05 AM UTC 24
Finished Oct 12 12:58:09 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040962323 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.3040962323
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.1990834388
Short name T506
Test name
Test status
Simulation time 2056883718 ps
CPU time 2.42 seconds
Started Oct 12 12:58:17 AM UTC 24
Finished Oct 12 12:58:20 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990834388 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.1990834388
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3848964375
Short name T341
Test name
Test status
Simulation time 3611598015 ps
CPU time 13.46 seconds
Started Oct 12 12:58:12 AM UTC 24
Finished Oct 12 12:58:27 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848964375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3848964375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.740640065
Short name T265
Test name
Test status
Simulation time 156651710916 ps
CPU time 452.94 seconds
Started Oct 12 12:58:12 AM UTC 24
Finished Oct 12 01:05:51 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740640065 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.740640065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1128820231
Short name T503
Test name
Test status
Simulation time 3609104076 ps
CPU time 4.76 seconds
Started Oct 12 12:58:12 AM UTC 24
Finished Oct 12 12:58:18 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128820231 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.1128820231
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2277354409
Short name T161
Test name
Test status
Simulation time 3811423407 ps
CPU time 4.04 seconds
Started Oct 12 12:58:15 AM UTC 24
Finished Oct 12 12:58:20 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277354409 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.2277354409
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1651357292
Short name T499
Test name
Test status
Simulation time 2624163574 ps
CPU time 3.4 seconds
Started Oct 12 12:58:10 AM UTC 24
Finished Oct 12 12:58:15 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651357292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.1651357292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.1513927577
Short name T500
Test name
Test status
Simulation time 2467315224 ps
CPU time 3.82 seconds
Started Oct 12 12:58:10 AM UTC 24
Finished Oct 12 12:58:15 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513927577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1513927577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.2723917146
Short name T502
Test name
Test status
Simulation time 2125360813 ps
CPU time 5.66 seconds
Started Oct 12 12:58:10 AM UTC 24
Finished Oct 12 12:58:17 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723917146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.2723917146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2052081583
Short name T494
Test name
Test status
Simulation time 2768046907 ps
CPU time 1.75 seconds
Started Oct 12 12:58:10 AM UTC 24
Finished Oct 12 12:58:13 AM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052081583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.2052081583
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.222301656
Short name T498
Test name
Test status
Simulation time 2116748599 ps
CPU time 3.64 seconds
Started Oct 12 12:58:10 AM UTC 24
Finished Oct 12 12:58:14 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222301656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.222301656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.1600941726
Short name T515
Test name
Test status
Simulation time 6643721196 ps
CPU time 28.35 seconds
Started Oct 12 12:58:17 AM UTC 24
Finished Oct 12 12:58:46 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600941726 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.1600941726
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3067700334
Short name T288
Test name
Test status
Simulation time 3264164308 ps
CPU time 12.94 seconds
Started Oct 12 12:58:15 AM UTC 24
Finished Oct 12 12:58:29 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3067700334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.3067700334
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2774863467
Short name T501
Test name
Test status
Simulation time 5782022364 ps
CPU time 2.8 seconds
Started Oct 12 12:58:12 AM UTC 24
Finished Oct 12 12:58:16 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774863467 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.2774863467
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.33585159
Short name T115
Test name
Test status
Simulation time 2028052827 ps
CPU time 1.79 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:44 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33585159 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.33585159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.2561529174
Short name T35
Test name
Test status
Simulation time 56173982481 ps
CPU time 42.27 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:57:25 AM UTC 24
Peak memory 209724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561529174 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.2561529174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2718555700
Short name T65
Test name
Test status
Simulation time 2225998174 ps
CPU time 3.95 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:46 AM UTC 24
Peak memory 209444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718555700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.2718555700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.873355841
Short name T31
Test name
Test status
Simulation time 2317932597 ps
CPU time 2.44 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:44 AM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873355841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.873355841
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1882419853
Short name T32
Test name
Test status
Simulation time 26353438665 ps
CPU time 21.67 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:57:04 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882419853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.1882419853
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.324049001
Short name T150
Test name
Test status
Simulation time 2765707066 ps
CPU time 8.27 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:50 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324049001 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.324049001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.2633186249
Short name T13
Test name
Test status
Simulation time 2987803517 ps
CPU time 7.33 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:49 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633186249 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.2633186249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2835435899
Short name T93
Test name
Test status
Simulation time 2635637300 ps
CPU time 2.54 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:44 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835435899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.2835435899
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2062366870
Short name T28
Test name
Test status
Simulation time 2475899053 ps
CPU time 3.75 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:45 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062366870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2062366870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.37201351
Short name T84
Test name
Test status
Simulation time 2246650761 ps
CPU time 1.11 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:43 AM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37201351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysr
st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.37201351
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2041650885
Short name T94
Test name
Test status
Simulation time 2522523337 ps
CPU time 4.38 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:46 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041650885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.2041650885
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2489822686
Short name T253
Test name
Test status
Simulation time 42019844535 ps
CPU time 58.9 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:57:42 AM UTC 24
Peak memory 241008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489822686 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.2489822686
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.1194963877
Short name T75
Test name
Test status
Simulation time 2117573794 ps
CPU time 3.91 seconds
Started Oct 12 12:56:36 AM UTC 24
Finished Oct 12 12:56:41 AM UTC 24
Peak memory 209244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194963877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1194963877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1824318783
Short name T298
Test name
Test status
Simulation time 3362897820 ps
CPU time 10.17 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:52 AM UTC 24
Peak memory 209748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1824318783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1824318783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.233859472
Short name T86
Test name
Test status
Simulation time 5685592589 ps
CPU time 5.99 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:48 AM UTC 24
Peak memory 209524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233859472 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.233859472
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.3404775571
Short name T138
Test name
Test status
Simulation time 2010435652 ps
CPU time 10.43 seconds
Started Oct 12 12:58:27 AM UTC 24
Finished Oct 12 12:58:39 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404775571 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.3404775571
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4054946253
Short name T342
Test name
Test status
Simulation time 3578863019 ps
CPU time 5.82 seconds
Started Oct 12 12:58:22 AM UTC 24
Finished Oct 12 12:58:29 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054946253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.4054946253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.187023530
Short name T261
Test name
Test status
Simulation time 162055045369 ps
CPU time 89.04 seconds
Started Oct 12 12:58:23 AM UTC 24
Finished Oct 12 12:59:54 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187023530 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.187023530
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.4219035223
Short name T340
Test name
Test status
Simulation time 4078900645 ps
CPU time 3.9 seconds
Started Oct 12 12:58:21 AM UTC 24
Finished Oct 12 12:58:26 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219035223 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.4219035223
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.1851172855
Short name T185
Test name
Test status
Simulation time 4251658340 ps
CPU time 5.3 seconds
Started Oct 12 12:58:23 AM UTC 24
Finished Oct 12 12:58:29 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851172855 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.1851172855
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2416113416
Short name T339
Test name
Test status
Simulation time 2659445871 ps
CPU time 2.31 seconds
Started Oct 12 12:58:19 AM UTC 24
Finished Oct 12 12:58:23 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416113416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.2416113416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.360077544
Short name T505
Test name
Test status
Simulation time 2545004138 ps
CPU time 1.84 seconds
Started Oct 12 12:58:17 AM UTC 24
Finished Oct 12 12:58:20 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360077544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.360077544
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3262218776
Short name T343
Test name
Test status
Simulation time 2111989051 ps
CPU time 10.23 seconds
Started Oct 12 12:58:19 AM UTC 24
Finished Oct 12 12:58:30 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262218776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3262218776
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.2282635226
Short name T345
Test name
Test status
Simulation time 2512805713 ps
CPU time 12.82 seconds
Started Oct 12 12:58:19 AM UTC 24
Finished Oct 12 12:58:33 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282635226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.2282635226
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1645485152
Short name T507
Test name
Test status
Simulation time 2120942018 ps
CPU time 3.45 seconds
Started Oct 12 12:58:17 AM UTC 24
Finished Oct 12 12:58:22 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645485152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1645485152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2205715545
Short name T277
Test name
Test status
Simulation time 181560786579 ps
CPU time 109.48 seconds
Started Oct 12 12:58:25 AM UTC 24
Finished Oct 12 01:00:17 AM UTC 24
Peak memory 209552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205715545 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.2205715545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1307393775
Short name T139
Test name
Test status
Simulation time 12024531454 ps
CPU time 12.64 seconds
Started Oct 12 12:58:25 AM UTC 24
Finished Oct 12 12:58:39 AM UTC 24
Peak memory 217800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1307393775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1307393775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.895921088
Short name T427
Test name
Test status
Simulation time 937442765745 ps
CPU time 97.32 seconds
Started Oct 12 12:58:23 AM UTC 24
Finished Oct 12 01:00:02 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895921088 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.895921088
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1624860382
Short name T518
Test name
Test status
Simulation time 2010514631 ps
CPU time 9.77 seconds
Started Oct 12 12:58:37 AM UTC 24
Finished Oct 12 12:58:49 AM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624860382 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.1624860382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1664918964
Short name T512
Test name
Test status
Simulation time 3230329122 ps
CPU time 9.08 seconds
Started Oct 12 12:58:34 AM UTC 24
Finished Oct 12 12:58:44 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664918964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1664918964
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3687407152
Short name T254
Test name
Test status
Simulation time 113104537685 ps
CPU time 82.63 seconds
Started Oct 12 12:58:34 AM UTC 24
Finished Oct 12 12:59:58 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687407152 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.3687407152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.450286965
Short name T382
Test name
Test status
Simulation time 81318530938 ps
CPU time 275.88 seconds
Started Oct 12 12:58:36 AM UTC 24
Finished Oct 12 01:03:16 AM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450286965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.450286965
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.246467224
Short name T514
Test name
Test status
Simulation time 3898498881 ps
CPU time 12.79 seconds
Started Oct 12 12:58:31 AM UTC 24
Finished Oct 12 12:58:46 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246467224 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.246467224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.2813809750
Short name T425
Test name
Test status
Simulation time 598610224377 ps
CPU time 43.61 seconds
Started Oct 12 12:58:35 AM UTC 24
Finished Oct 12 12:59:20 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813809750 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.2813809750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.4128004186
Short name T513
Test name
Test status
Simulation time 2612062182 ps
CPU time 13.19 seconds
Started Oct 12 12:58:30 AM UTC 24
Finished Oct 12 12:58:45 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128004186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.4128004186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.1861040445
Short name T508
Test name
Test status
Simulation time 2459320819 ps
CPU time 4.03 seconds
Started Oct 12 12:58:28 AM UTC 24
Finished Oct 12 12:58:33 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861040445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.1861040445
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.2014662435
Short name T344
Test name
Test status
Simulation time 2074138576 ps
CPU time 2.8 seconds
Started Oct 12 12:58:29 AM UTC 24
Finished Oct 12 12:58:33 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014662435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.2014662435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.3396938542
Short name T136
Test name
Test status
Simulation time 2519739731 ps
CPU time 6.77 seconds
Started Oct 12 12:58:30 AM UTC 24
Finished Oct 12 12:58:38 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396938542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.3396938542
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.1774027166
Short name T509
Test name
Test status
Simulation time 2116050013 ps
CPU time 4.97 seconds
Started Oct 12 12:58:28 AM UTC 24
Finished Oct 12 12:58:34 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774027166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1774027166
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.638367773
Short name T519
Test name
Test status
Simulation time 7942188157 ps
CPU time 9.81 seconds
Started Oct 12 12:58:37 AM UTC 24
Finished Oct 12 12:58:49 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638367773 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.638367773
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2077031135
Short name T526
Test name
Test status
Simulation time 4394584188 ps
CPU time 19.64 seconds
Started Oct 12 12:58:37 AM UTC 24
Finished Oct 12 12:58:59 AM UTC 24
Peak memory 217700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2077031135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2077031135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1613617793
Short name T135
Test name
Test status
Simulation time 7942840672 ps
CPU time 1.73 seconds
Started Oct 12 12:58:34 AM UTC 24
Finished Oct 12 12:58:36 AM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613617793 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.1613617793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.3475202971
Short name T496
Test name
Test status
Simulation time 2031710636 ps
CPU time 3.04 seconds
Started Oct 12 12:58:48 AM UTC 24
Finished Oct 12 12:58:52 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475202971 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.3475202971
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1066622721
Short name T524
Test name
Test status
Simulation time 3340710020 ps
CPU time 12.65 seconds
Started Oct 12 12:58:43 AM UTC 24
Finished Oct 12 12:58:57 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066622721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.1066622721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.203411946
Short name T280
Test name
Test status
Simulation time 91112736888 ps
CPU time 68.54 seconds
Started Oct 12 12:58:45 AM UTC 24
Finished Oct 12 12:59:55 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203411946 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.203411946
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.423411023
Short name T137
Test name
Test status
Simulation time 2885223263 ps
CPU time 9.07 seconds
Started Oct 12 12:58:40 AM UTC 24
Finished Oct 12 12:58:50 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423411023 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.423411023
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.2906094415
Short name T186
Test name
Test status
Simulation time 2930597501 ps
CPU time 1.67 seconds
Started Oct 12 12:58:46 AM UTC 24
Finished Oct 12 12:58:49 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906094415 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.2906094415
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2745847210
Short name T517
Test name
Test status
Simulation time 2614669153 ps
CPU time 6.99 seconds
Started Oct 12 12:58:40 AM UTC 24
Finished Oct 12 12:58:48 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745847210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.2745847210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3856686647
Short name T511
Test name
Test status
Simulation time 2450368568 ps
CPU time 12.12 seconds
Started Oct 12 12:58:38 AM UTC 24
Finished Oct 12 12:58:52 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856686647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3856686647
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.412293844
Short name T516
Test name
Test status
Simulation time 2192436748 ps
CPU time 7.02 seconds
Started Oct 12 12:58:39 AM UTC 24
Finished Oct 12 12:58:48 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412293844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.412293844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.58164251
Short name T521
Test name
Test status
Simulation time 2514461245 ps
CPU time 11.93 seconds
Started Oct 12 12:58:40 AM UTC 24
Finished Oct 12 12:58:53 AM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58164251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.58164251
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2121009620
Short name T510
Test name
Test status
Simulation time 2134364387 ps
CPU time 2.04 seconds
Started Oct 12 12:58:38 AM UTC 24
Finished Oct 12 12:58:42 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121009620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2121009620
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2680126506
Short name T535
Test name
Test status
Simulation time 15344771101 ps
CPU time 34.2 seconds
Started Oct 12 12:58:48 AM UTC 24
Finished Oct 12 12:59:24 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680126506 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.2680126506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.233781651
Short name T316
Test name
Test status
Simulation time 12546875266 ps
CPU time 16.32 seconds
Started Oct 12 12:58:47 AM UTC 24
Finished Oct 12 12:59:05 AM UTC 24
Peak memory 226212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=233781651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.233781651
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3311954706
Short name T520
Test name
Test status
Simulation time 9958574581 ps
CPU time 3.66 seconds
Started Oct 12 12:58:45 AM UTC 24
Finished Oct 12 12:58:50 AM UTC 24
Peak memory 209288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311954706 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.3311954706
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.1547762548
Short name T532
Test name
Test status
Simulation time 2020176259 ps
CPU time 5.33 seconds
Started Oct 12 12:58:59 AM UTC 24
Finished Oct 12 12:59:05 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547762548 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.1547762548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3725619898
Short name T527
Test name
Test status
Simulation time 3640328755 ps
CPU time 5.43 seconds
Started Oct 12 12:58:53 AM UTC 24
Finished Oct 12 12:59:00 AM UTC 24
Peak memory 209360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725619898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3725619898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.2408996309
Short name T231
Test name
Test status
Simulation time 121905003954 ps
CPU time 199.12 seconds
Started Oct 12 12:58:57 AM UTC 24
Finished Oct 12 01:02:19 AM UTC 24
Peak memory 209744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408996309 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.2408996309
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3967960759
Short name T381
Test name
Test status
Simulation time 54378176558 ps
CPU time 162.81 seconds
Started Oct 12 12:58:57 AM UTC 24
Finished Oct 12 01:01:43 AM UTC 24
Peak memory 209544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967960759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_with_pre_cond.3967960759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3403796282
Short name T529
Test name
Test status
Simulation time 2856453240 ps
CPU time 8.02 seconds
Started Oct 12 12:58:53 AM UTC 24
Finished Oct 12 12:59:02 AM UTC 24
Peak memory 209544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403796282 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.3403796282
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1442718281
Short name T523
Test name
Test status
Simulation time 2627390908 ps
CPU time 3.94 seconds
Started Oct 12 12:58:51 AM UTC 24
Finished Oct 12 12:58:56 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442718281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.1442718281
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.2625293578
Short name T530
Test name
Test status
Simulation time 2444281363 ps
CPU time 12.43 seconds
Started Oct 12 12:58:50 AM UTC 24
Finished Oct 12 12:59:03 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625293578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2625293578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2418197082
Short name T525
Test name
Test status
Simulation time 2207336544 ps
CPU time 6.41 seconds
Started Oct 12 12:58:50 AM UTC 24
Finished Oct 12 12:58:57 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418197082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.2418197082
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3675688356
Short name T522
Test name
Test status
Simulation time 2531600993 ps
CPU time 3.83 seconds
Started Oct 12 12:58:51 AM UTC 24
Finished Oct 12 12:58:56 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675688356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.3675688356
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3207225533
Short name T491
Test name
Test status
Simulation time 2114445934 ps
CPU time 5.9 seconds
Started Oct 12 12:58:50 AM UTC 24
Finished Oct 12 12:58:57 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207225533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3207225533
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3879561041
Short name T335
Test name
Test status
Simulation time 5898007612 ps
CPU time 8.23 seconds
Started Oct 12 12:58:57 AM UTC 24
Finished Oct 12 12:59:07 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3879561041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.3879561041
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1408763009
Short name T528
Test name
Test status
Simulation time 5684217676 ps
CPU time 5.4 seconds
Started Oct 12 12:58:54 AM UTC 24
Finished Oct 12 12:59:01 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408763009 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.1408763009
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.2143341702
Short name T214
Test name
Test status
Simulation time 2053744464 ps
CPU time 2.1 seconds
Started Oct 12 12:59:11 AM UTC 24
Finished Oct 12 12:59:14 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143341702 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.2143341702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.312129809
Short name T213
Test name
Test status
Simulation time 3394768573 ps
CPU time 2.7 seconds
Started Oct 12 12:59:06 AM UTC 24
Finished Oct 12 12:59:10 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312129809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.312129809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.2582050846
Short name T279
Test name
Test status
Simulation time 121757835366 ps
CPU time 335.75 seconds
Started Oct 12 12:59:07 AM UTC 24
Finished Oct 12 01:04:47 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582050846 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.2582050846
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2759573596
Short name T367
Test name
Test status
Simulation time 42950870777 ps
CPU time 165.79 seconds
Started Oct 12 12:59:09 AM UTC 24
Finished Oct 12 01:01:57 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759573596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_with_pre_cond.2759573596
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.4054800275
Short name T539
Test name
Test status
Simulation time 4458656276 ps
CPU time 20.45 seconds
Started Oct 12 12:59:05 AM UTC 24
Finished Oct 12 12:59:27 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054800275 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.4054800275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2565547119
Short name T163
Test name
Test status
Simulation time 5924834166 ps
CPU time 28.4 seconds
Started Oct 12 12:59:07 AM UTC 24
Finished Oct 12 12:59:37 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565547119 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.2565547119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1361447330
Short name T212
Test name
Test status
Simulation time 2633983289 ps
CPU time 3.78 seconds
Started Oct 12 12:59:04 AM UTC 24
Finished Oct 12 12:59:09 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361447330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.1361447330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.828514496
Short name T215
Test name
Test status
Simulation time 2466705601 ps
CPU time 13.59 seconds
Started Oct 12 12:59:01 AM UTC 24
Finished Oct 12 12:59:15 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828514496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.828514496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3399689113
Short name T533
Test name
Test status
Simulation time 2262733616 ps
CPU time 3.56 seconds
Started Oct 12 12:59:02 AM UTC 24
Finished Oct 12 12:59:06 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399689113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3399689113
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.1188175333
Short name T211
Test name
Test status
Simulation time 2525184605 ps
CPU time 4.04 seconds
Started Oct 12 12:59:03 AM UTC 24
Finished Oct 12 12:59:08 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188175333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.1188175333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.2538152091
Short name T531
Test name
Test status
Simulation time 2128970555 ps
CPU time 3.39 seconds
Started Oct 12 12:59:00 AM UTC 24
Finished Oct 12 12:59:04 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538152091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.2538152091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1303994987
Short name T289
Test name
Test status
Simulation time 3961620358 ps
CPU time 14.59 seconds
Started Oct 12 12:59:09 AM UTC 24
Finished Oct 12 12:59:24 AM UTC 24
Peak memory 209748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1303994987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1303994987
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.960603042
Short name T541
Test name
Test status
Simulation time 2026665899 ps
CPU time 3.88 seconds
Started Oct 12 12:59:28 AM UTC 24
Finished Oct 12 12:59:33 AM UTC 24
Peak memory 209224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960603042 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.960603042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3837411510
Short name T542
Test name
Test status
Simulation time 3414061421 ps
CPU time 15 seconds
Started Oct 12 12:59:20 AM UTC 24
Finished Oct 12 12:59:36 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837411510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.3837411510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2774988057
Short name T278
Test name
Test status
Simulation time 73557118972 ps
CPU time 195.89 seconds
Started Oct 12 12:59:25 AM UTC 24
Finished Oct 12 01:02:43 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774988057 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.2774988057
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.560990305
Short name T369
Test name
Test status
Simulation time 68224760224 ps
CPU time 122.47 seconds
Started Oct 12 12:59:26 AM UTC 24
Finished Oct 12 01:01:30 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560990305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_with_pre_cond.560990305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.617275222
Short name T537
Test name
Test status
Simulation time 2656289437 ps
CPU time 3.42 seconds
Started Oct 12 12:59:20 AM UTC 24
Finished Oct 12 12:59:25 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617275222 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.617275222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.609926623
Short name T229
Test name
Test status
Simulation time 2825053962 ps
CPU time 2.99 seconds
Started Oct 12 12:59:26 AM UTC 24
Finished Oct 12 12:59:30 AM UTC 24
Peak memory 209556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609926623 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.609926623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3252452328
Short name T536
Test name
Test status
Simulation time 2614239589 ps
CPU time 6.06 seconds
Started Oct 12 12:59:17 AM UTC 24
Finished Oct 12 12:59:24 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252452328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3252452328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.3766995960
Short name T540
Test name
Test status
Simulation time 2469012427 ps
CPU time 12.1 seconds
Started Oct 12 12:59:16 AM UTC 24
Finished Oct 12 12:59:29 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766995960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.3766995960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3240507498
Short name T538
Test name
Test status
Simulation time 2205030316 ps
CPU time 9 seconds
Started Oct 12 12:59:16 AM UTC 24
Finished Oct 12 12:59:26 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240507498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.3240507498
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.1005629048
Short name T534
Test name
Test status
Simulation time 2525603285 ps
CPU time 3.82 seconds
Started Oct 12 12:59:16 AM UTC 24
Finished Oct 12 12:59:21 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005629048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.1005629048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2418067445
Short name T217
Test name
Test status
Simulation time 2126371788 ps
CPU time 3.08 seconds
Started Oct 12 12:59:15 AM UTC 24
Finished Oct 12 12:59:19 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418067445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2418067445
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3032677857
Short name T546
Test name
Test status
Simulation time 12565299445 ps
CPU time 13.21 seconds
Started Oct 12 12:59:27 AM UTC 24
Finished Oct 12 12:59:41 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032677857 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.3032677857
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2675064014
Short name T548
Test name
Test status
Simulation time 4562590673 ps
CPU time 19.98 seconds
Started Oct 12 12:59:26 AM UTC 24
Finished Oct 12 12:59:47 AM UTC 24
Peak memory 217724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2675064014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2675064014
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.1281623942
Short name T552
Test name
Test status
Simulation time 2021388435 ps
CPU time 4.35 seconds
Started Oct 12 12:59:47 AM UTC 24
Finished Oct 12 12:59:53 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281623942 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.1281623942
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3662451819
Short name T551
Test name
Test status
Simulation time 3659206083 ps
CPU time 12.97 seconds
Started Oct 12 12:59:38 AM UTC 24
Finished Oct 12 12:59:52 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662451819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.3662451819
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3829320994
Short name T270
Test name
Test status
Simulation time 118583100395 ps
CPU time 81.27 seconds
Started Oct 12 12:59:40 AM UTC 24
Finished Oct 12 01:01:03 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829320994 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.3829320994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2867653854
Short name T119
Test name
Test status
Simulation time 27583314739 ps
CPU time 100.69 seconds
Started Oct 12 12:59:42 AM UTC 24
Finished Oct 12 01:01:25 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867653854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_with_pre_cond.2867653854
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2321864
Short name T568
Test name
Test status
Simulation time 5305542735 ps
CPU time 31.1 seconds
Started Oct 12 12:59:38 AM UTC 24
Finished Oct 12 01:00:10 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321864 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.2321864
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1155848896
Short name T202
Test name
Test status
Simulation time 4446007074 ps
CPU time 9.57 seconds
Started Oct 12 12:59:42 AM UTC 24
Finished Oct 12 12:59:53 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155848896 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.1155848896
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1495498486
Short name T545
Test name
Test status
Simulation time 2637407441 ps
CPU time 3.67 seconds
Started Oct 12 12:59:37 AM UTC 24
Finished Oct 12 12:59:41 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495498486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1495498486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1553755975
Short name T543
Test name
Test status
Simulation time 2482869801 ps
CPU time 6.92 seconds
Started Oct 12 12:59:30 AM UTC 24
Finished Oct 12 12:59:38 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553755975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1553755975
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.280241892
Short name T547
Test name
Test status
Simulation time 2234314759 ps
CPU time 11.27 seconds
Started Oct 12 12:59:30 AM UTC 24
Finished Oct 12 12:59:43 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280241892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.280241892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.289581823
Short name T549
Test name
Test status
Simulation time 2510190354 ps
CPU time 13.38 seconds
Started Oct 12 12:59:33 AM UTC 24
Finished Oct 12 12:59:48 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289581823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.289581823
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.1884746134
Short name T544
Test name
Test status
Simulation time 2110956715 ps
CPU time 9.46 seconds
Started Oct 12 12:59:28 AM UTC 24
Finished Oct 12 12:59:39 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884746134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.1884746134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.2954365998
Short name T554
Test name
Test status
Simulation time 7795011023 ps
CPU time 10.83 seconds
Started Oct 12 12:59:45 AM UTC 24
Finished Oct 12 12:59:57 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954365998 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.2954365998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.1996164035
Short name T565
Test name
Test status
Simulation time 2015163106 ps
CPU time 8.72 seconds
Started Oct 12 12:59:58 AM UTC 24
Finished Oct 12 01:00:08 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996164035 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.1996164035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.607523379
Short name T559
Test name
Test status
Simulation time 3489703517 ps
CPU time 5.05 seconds
Started Oct 12 12:59:54 AM UTC 24
Finished Oct 12 01:00:00 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607523379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.607523379
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.2352327037
Short name T366
Test name
Test status
Simulation time 176111015648 ps
CPU time 137.14 seconds
Started Oct 12 12:59:54 AM UTC 24
Finished Oct 12 01:02:13 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352327037 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.2352327037
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.502631758
Short name T555
Test name
Test status
Simulation time 2783356905 ps
CPU time 2.41 seconds
Started Oct 12 12:59:54 AM UTC 24
Finished Oct 12 12:59:57 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502631758 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.502631758
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1548858346
Short name T169
Test name
Test status
Simulation time 3344977766 ps
CPU time 3.94 seconds
Started Oct 12 12:59:55 AM UTC 24
Finished Oct 12 01:00:00 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548858346 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.1548858346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.352239435
Short name T562
Test name
Test status
Simulation time 2614678134 ps
CPU time 11.61 seconds
Started Oct 12 12:59:53 AM UTC 24
Finished Oct 12 01:00:05 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352239435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.352239435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.241237326
Short name T553
Test name
Test status
Simulation time 2489590769 ps
CPU time 3.88 seconds
Started Oct 12 12:59:51 AM UTC 24
Finished Oct 12 12:59:56 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241237326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.241237326
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.4085215298
Short name T560
Test name
Test status
Simulation time 2065104858 ps
CPU time 8.82 seconds
Started Oct 12 12:59:52 AM UTC 24
Finished Oct 12 01:00:01 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085215298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.4085215298
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.4253480327
Short name T556
Test name
Test status
Simulation time 2518506228 ps
CPU time 5.17 seconds
Started Oct 12 12:59:53 AM UTC 24
Finished Oct 12 12:59:59 AM UTC 24
Peak memory 207912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253480327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.4253480327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3832732502
Short name T550
Test name
Test status
Simulation time 2265956652 ps
CPU time 1.28 seconds
Started Oct 12 12:59:48 AM UTC 24
Finished Oct 12 12:59:51 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832732502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.3832732502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.3129285066
Short name T807
Test name
Test status
Simulation time 1103690422380 ps
CPU time 978.4 seconds
Started Oct 12 12:59:58 AM UTC 24
Finished Oct 12 01:16:28 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129285066 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.3129285066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1412771247
Short name T569
Test name
Test status
Simulation time 17870246348 ps
CPU time 12.79 seconds
Started Oct 12 12:59:57 AM UTC 24
Finished Oct 12 01:00:11 AM UTC 24
Peak memory 221876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1412771247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.1412771247
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1675451435
Short name T558
Test name
Test status
Simulation time 14149547070 ps
CPU time 4.93 seconds
Started Oct 12 12:59:54 AM UTC 24
Finished Oct 12 01:00:00 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675451435 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.1675451435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2426477775
Short name T579
Test name
Test status
Simulation time 2008520337 ps
CPU time 9.4 seconds
Started Oct 12 01:00:14 AM UTC 24
Finished Oct 12 01:00:24 AM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426477775 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.2426477775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3902106145
Short name T573
Test name
Test status
Simulation time 3813626225 ps
CPU time 11.82 seconds
Started Oct 12 01:00:01 AM UTC 24
Finished Oct 12 01:00:18 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902106145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3902106145
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.4137562138
Short name T791
Test name
Test status
Simulation time 142396065851 ps
CPU time 413.68 seconds
Started Oct 12 01:00:14 AM UTC 24
Finished Oct 12 01:07:12 AM UTC 24
Peak memory 209288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137562138 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.4137562138
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3351449195
Short name T571
Test name
Test status
Simulation time 2557384644 ps
CPU time 10.8 seconds
Started Oct 12 01:00:01 AM UTC 24
Finished Oct 12 01:00:17 AM UTC 24
Peak memory 208832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351449195 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.3351449195
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.2991536880
Short name T170
Test name
Test status
Simulation time 3272564849 ps
CPU time 5.09 seconds
Started Oct 12 01:00:14 AM UTC 24
Finished Oct 12 01:00:20 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991536880 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.2991536880
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1900343419
Short name T570
Test name
Test status
Simulation time 2611108315 ps
CPU time 7.52 seconds
Started Oct 12 01:00:01 AM UTC 24
Finished Oct 12 01:00:14 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900343419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.1900343419
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.50265405
Short name T563
Test name
Test status
Simulation time 2475157858 ps
CPU time 6.73 seconds
Started Oct 12 01:00:00 AM UTC 24
Finished Oct 12 01:00:07 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50265405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.50265405
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2390294581
Short name T567
Test name
Test status
Simulation time 2087013103 ps
CPU time 3.5 seconds
Started Oct 12 01:00:01 AM UTC 24
Finished Oct 12 01:00:09 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390294581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2390294581
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1784030973
Short name T564
Test name
Test status
Simulation time 2618302358 ps
CPU time 1.45 seconds
Started Oct 12 01:00:01 AM UTC 24
Finished Oct 12 01:00:07 AM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784030973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1784030973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3490706593
Short name T561
Test name
Test status
Simulation time 2114403707 ps
CPU time 4.94 seconds
Started Oct 12 12:59:59 AM UTC 24
Finished Oct 12 01:00:06 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490706593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3490706593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1660470294
Short name T317
Test name
Test status
Simulation time 5106290558 ps
CPU time 9.33 seconds
Started Oct 12 01:00:14 AM UTC 24
Finished Oct 12 01:00:24 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1660470294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.1660470294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2383233829
Short name T566
Test name
Test status
Simulation time 11593162581 ps
CPU time 2.39 seconds
Started Oct 12 01:00:02 AM UTC 24
Finished Oct 12 01:00:09 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383233829 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.2383233829
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.1501208618
Short name T578
Test name
Test status
Simulation time 2027729710 ps
CPU time 3.25 seconds
Started Oct 12 01:00:19 AM UTC 24
Finished Oct 12 01:00:23 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501208618 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.1501208618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3984180345
Short name T574
Test name
Test status
Simulation time 3356086291 ps
CPU time 1.46 seconds
Started Oct 12 01:00:15 AM UTC 24
Finished Oct 12 01:00:18 AM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984180345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3984180345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.478095707
Short name T264
Test name
Test status
Simulation time 75020578222 ps
CPU time 238.38 seconds
Started Oct 12 01:00:15 AM UTC 24
Finished Oct 12 01:04:17 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478095707 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.478095707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3136788575
Short name T365
Test name
Test status
Simulation time 33494577775 ps
CPU time 21.87 seconds
Started Oct 12 01:00:17 AM UTC 24
Finished Oct 12 01:00:41 AM UTC 24
Peak memory 209400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136788575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.3136788575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2869729568
Short name T575
Test name
Test status
Simulation time 4086516788 ps
CPU time 3.77 seconds
Started Oct 12 01:00:15 AM UTC 24
Finished Oct 12 01:00:21 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869729568 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.2869729568
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.266114315
Short name T583
Test name
Test status
Simulation time 2613420663 ps
CPU time 10.61 seconds
Started Oct 12 01:00:15 AM UTC 24
Finished Oct 12 01:00:27 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266114315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.266114315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.3499061687
Short name T585
Test name
Test status
Simulation time 2464824741 ps
CPU time 13.99 seconds
Started Oct 12 01:00:15 AM UTC 24
Finished Oct 12 01:00:30 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499061687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.3499061687
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.4197116318
Short name T577
Test name
Test status
Simulation time 2259696908 ps
CPU time 6.06 seconds
Started Oct 12 01:00:15 AM UTC 24
Finished Oct 12 01:00:22 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197116318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.4197116318
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2480395597
Short name T580
Test name
Test status
Simulation time 2511263783 ps
CPU time 8.34 seconds
Started Oct 12 01:00:15 AM UTC 24
Finished Oct 12 01:00:25 AM UTC 24
Peak memory 209444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480395597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.2480395597
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2937251933
Short name T572
Test name
Test status
Simulation time 2133019876 ps
CPU time 2.37 seconds
Started Oct 12 01:00:14 AM UTC 24
Finished Oct 12 01:00:17 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937251933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.2937251933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.1357397996
Short name T155
Test name
Test status
Simulation time 15786673461 ps
CPU time 24.56 seconds
Started Oct 12 01:00:19 AM UTC 24
Finished Oct 12 01:00:44 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357397996 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.1357397996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1382864695
Short name T305
Test name
Test status
Simulation time 6129330675 ps
CPU time 24.78 seconds
Started Oct 12 01:00:18 AM UTC 24
Finished Oct 12 01:00:43 AM UTC 24
Peak memory 225056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1382864695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.1382864695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2664886131
Short name T430
Test name
Test status
Simulation time 412726960988 ps
CPU time 24.3 seconds
Started Oct 12 01:00:15 AM UTC 24
Finished Oct 12 01:00:41 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664886131 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.2664886131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3776304311
Short name T149
Test name
Test status
Simulation time 2096111544 ps
CPU time 1.45 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:49 AM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776304311 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.3776304311
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2385614074
Short name T30
Test name
Test status
Simulation time 3252686948 ps
CPU time 9.78 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:55 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385614074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.2385614074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1130445676
Short name T398
Test name
Test status
Simulation time 110257803031 ps
CPU time 339.36 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 01:02:28 AM UTC 24
Peak memory 209404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130445676 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.1130445676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2186956295
Short name T68
Test name
Test status
Simulation time 2220020355 ps
CPU time 6.63 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:51 AM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186956295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.2186956295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.595779313
Short name T66
Test name
Test status
Simulation time 2389723003 ps
CPU time 1.75 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:47 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595779313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.595779313
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2618621954
Short name T308
Test name
Test status
Simulation time 3056360002 ps
CPU time 8.53 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:54 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618621954 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.2618621954
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2927804780
Short name T11
Test name
Test status
Simulation time 3200285389 ps
CPU time 2.09 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:47 AM UTC 24
Peak memory 209292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927804780 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.2927804780
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.830096313
Short name T309
Test name
Test status
Simulation time 2609233272 ps
CPU time 8.68 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:54 AM UTC 24
Peak memory 209292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830096313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.830096313
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.3387311128
Short name T88
Test name
Test status
Simulation time 2475798402 ps
CPU time 2.88 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:48 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387311128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.3387311128
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2912787548
Short name T148
Test name
Test status
Simulation time 2186419395 ps
CPU time 4.19 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:49 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912787548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2912787548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2401012406
Short name T96
Test name
Test status
Simulation time 2511359625 ps
CPU time 7.11 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:52 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401012406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2401012406
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1575388075
Short name T282
Test name
Test status
Simulation time 42192682616 ps
CPU time 29.12 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:57:17 AM UTC 24
Peak memory 241080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575388075 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.1575388075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.4092396380
Short name T116
Test name
Test status
Simulation time 2133256642 ps
CPU time 2.17 seconds
Started Oct 12 12:56:41 AM UTC 24
Finished Oct 12 12:56:45 AM UTC 24
Peak memory 209508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092396380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.4092396380
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1004709537
Short name T81
Test name
Test status
Simulation time 18654795184 ps
CPU time 36.26 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:57:22 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004709537 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.1004709537
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.3127314194
Short name T12
Test name
Test status
Simulation time 6139005133 ps
CPU time 2.54 seconds
Started Oct 12 12:56:44 AM UTC 24
Finished Oct 12 12:56:48 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127314194 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.3127314194
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.2220454813
Short name T586
Test name
Test status
Simulation time 2019544028 ps
CPU time 4.51 seconds
Started Oct 12 01:00:28 AM UTC 24
Finished Oct 12 01:00:33 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220454813 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.2220454813
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1941925150
Short name T118
Test name
Test status
Simulation time 3713919422 ps
CPU time 5.2 seconds
Started Oct 12 01:00:25 AM UTC 24
Finished Oct 12 01:00:32 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941925150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.1941925150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.278294984
Short name T123
Test name
Test status
Simulation time 86459599323 ps
CPU time 263 seconds
Started Oct 12 01:00:25 AM UTC 24
Finished Oct 12 01:04:52 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278294984 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.278294984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.698910225
Short name T733
Test name
Test status
Simulation time 58697437284 ps
CPU time 172.68 seconds
Started Oct 12 01:00:27 AM UTC 24
Finished Oct 12 01:03:22 AM UTC 24
Peak memory 209416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698910225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_with_pre_cond.698910225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3059737337
Short name T594
Test name
Test status
Simulation time 5209671832 ps
CPU time 13.86 seconds
Started Oct 12 01:00:24 AM UTC 24
Finished Oct 12 01:00:39 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059737337 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.3059737337
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.746090838
Short name T172
Test name
Test status
Simulation time 4370286045 ps
CPU time 9.64 seconds
Started Oct 12 01:00:25 AM UTC 24
Finished Oct 12 01:00:36 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746090838 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.746090838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.496779628
Short name T588
Test name
Test status
Simulation time 2613816307 ps
CPU time 10.55 seconds
Started Oct 12 01:00:23 AM UTC 24
Finished Oct 12 01:00:35 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496779628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.496779628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.3984164897
Short name T584
Test name
Test status
Simulation time 2455534623 ps
CPU time 6.24 seconds
Started Oct 12 01:00:21 AM UTC 24
Finished Oct 12 01:00:29 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984164897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3984164897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.4215790333
Short name T581
Test name
Test status
Simulation time 2109213598 ps
CPU time 1.85 seconds
Started Oct 12 01:00:22 AM UTC 24
Finished Oct 12 01:00:25 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215790333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.4215790333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.1038323839
Short name T582
Test name
Test status
Simulation time 2548102383 ps
CPU time 1.65 seconds
Started Oct 12 01:00:23 AM UTC 24
Finished Oct 12 01:00:26 AM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038323839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1038323839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.11384368
Short name T576
Test name
Test status
Simulation time 2147096907 ps
CPU time 2.31 seconds
Started Oct 12 01:00:19 AM UTC 24
Finished Oct 12 01:00:22 AM UTC 24
Peak memory 209312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11384368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.11384368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1466919003
Short name T590
Test name
Test status
Simulation time 7600250042 ps
CPU time 7.77 seconds
Started Oct 12 01:00:27 AM UTC 24
Finished Oct 12 01:00:36 AM UTC 24
Peak memory 221916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1466919003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1466919003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1820272835
Short name T595
Test name
Test status
Simulation time 8273286387 ps
CPU time 14.82 seconds
Started Oct 12 01:00:25 AM UTC 24
Finished Oct 12 01:00:41 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820272835 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.1820272835
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1444782868
Short name T603
Test name
Test status
Simulation time 2013100528 ps
CPU time 8.22 seconds
Started Oct 12 01:00:40 AM UTC 24
Finished Oct 12 01:00:49 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444782868 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.1444782868
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3690494034
Short name T604
Test name
Test status
Simulation time 3283672115 ps
CPU time 12.74 seconds
Started Oct 12 01:00:35 AM UTC 24
Finished Oct 12 01:00:50 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690494034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3690494034
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.2230643529
Short name T402
Test name
Test status
Simulation time 166640467200 ps
CPU time 256.66 seconds
Started Oct 12 01:00:36 AM UTC 24
Finished Oct 12 01:04:57 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230643529 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.2230643529
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1219155510
Short name T364
Test name
Test status
Simulation time 54807210043 ps
CPU time 33.05 seconds
Started Oct 12 01:00:39 AM UTC 24
Finished Oct 12 01:01:14 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219155510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.1219155510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.602597253
Short name T596
Test name
Test status
Simulation time 3329585867 ps
CPU time 4.58 seconds
Started Oct 12 01:00:35 AM UTC 24
Finished Oct 12 01:00:41 AM UTC 24
Peak memory 209312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602597253 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.602597253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2152314392
Short name T173
Test name
Test status
Simulation time 2811905267 ps
CPU time 3.99 seconds
Started Oct 12 01:00:38 AM UTC 24
Finished Oct 12 01:00:43 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152314392 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.2152314392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2898580751
Short name T597
Test name
Test status
Simulation time 2611813020 ps
CPU time 7.59 seconds
Started Oct 12 01:00:34 AM UTC 24
Finished Oct 12 01:00:43 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898580751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2898580751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1115383601
Short name T587
Test name
Test status
Simulation time 2489813661 ps
CPU time 2.49 seconds
Started Oct 12 01:00:31 AM UTC 24
Finished Oct 12 01:00:34 AM UTC 24
Peak memory 209516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115383601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1115383601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.3194048102
Short name T589
Test name
Test status
Simulation time 2158510282 ps
CPU time 3.43 seconds
Started Oct 12 01:00:31 AM UTC 24
Finished Oct 12 01:00:35 AM UTC 24
Peak memory 209292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194048102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3194048102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.1416544616
Short name T592
Test name
Test status
Simulation time 2522434858 ps
CPU time 4.11 seconds
Started Oct 12 01:00:32 AM UTC 24
Finished Oct 12 01:00:37 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416544616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.1416544616
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.1631832144
Short name T593
Test name
Test status
Simulation time 2114586075 ps
CPU time 7.86 seconds
Started Oct 12 01:00:30 AM UTC 24
Finished Oct 12 01:00:39 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631832144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.1631832144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.1982264005
Short name T602
Test name
Test status
Simulation time 11162820843 ps
CPU time 7.11 seconds
Started Oct 12 01:00:40 AM UTC 24
Finished Oct 12 01:00:48 AM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982264005 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.1982264005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2401786742
Short name T326
Test name
Test status
Simulation time 11162551725 ps
CPU time 16.4 seconds
Started Oct 12 01:00:39 AM UTC 24
Finished Oct 12 01:00:57 AM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2401786742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.2401786742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2300394676
Short name T606
Test name
Test status
Simulation time 6939181376 ps
CPU time 12.73 seconds
Started Oct 12 01:00:36 AM UTC 24
Finished Oct 12 01:00:51 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300394676 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.2300394676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.631280134
Short name T611
Test name
Test status
Simulation time 2033830775 ps
CPU time 3.31 seconds
Started Oct 12 01:00:50 AM UTC 24
Finished Oct 12 01:00:55 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631280134 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.631280134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3410806937
Short name T607
Test name
Test status
Simulation time 3680278706 ps
CPU time 5.43 seconds
Started Oct 12 01:00:44 AM UTC 24
Finished Oct 12 01:00:51 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410806937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.3410806937
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.1740340863
Short name T769
Test name
Test status
Simulation time 172935327774 ps
CPU time 230.52 seconds
Started Oct 12 01:00:46 AM UTC 24
Finished Oct 12 01:04:39 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740340863 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.1740340863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4055916320
Short name T384
Test name
Test status
Simulation time 91629629428 ps
CPU time 63.49 seconds
Started Oct 12 01:00:49 AM UTC 24
Finished Oct 12 01:01:54 AM UTC 24
Peak memory 209680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055916320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.4055916320
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.4135285683
Short name T599
Test name
Test status
Simulation time 4958596755 ps
CPU time 2.37 seconds
Started Oct 12 01:00:44 AM UTC 24
Finished Oct 12 01:00:48 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135285683 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.4135285683
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.375571646
Short name T206
Test name
Test status
Simulation time 3978704850 ps
CPU time 18.6 seconds
Started Oct 12 01:00:49 AM UTC 24
Finished Oct 12 01:01:08 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375571646 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.375571646
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3634422996
Short name T608
Test name
Test status
Simulation time 2620940763 ps
CPU time 6.13 seconds
Started Oct 12 01:00:44 AM UTC 24
Finished Oct 12 01:00:52 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634422996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3634422996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.1425062365
Short name T605
Test name
Test status
Simulation time 2454408892 ps
CPU time 6.92 seconds
Started Oct 12 01:00:42 AM UTC 24
Finished Oct 12 01:00:50 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425062365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1425062365
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.1679793892
Short name T610
Test name
Test status
Simulation time 2254071002 ps
CPU time 10.33 seconds
Started Oct 12 01:00:42 AM UTC 24
Finished Oct 12 01:00:54 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679793892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1679793892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.931514091
Short name T609
Test name
Test status
Simulation time 2512688267 ps
CPU time 9.24 seconds
Started Oct 12 01:00:42 AM UTC 24
Finished Oct 12 01:00:53 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931514091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.931514091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.1860279619
Short name T598
Test name
Test status
Simulation time 2143182998 ps
CPU time 2.52 seconds
Started Oct 12 01:00:41 AM UTC 24
Finished Oct 12 01:00:45 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860279619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.1860279619
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1650580754
Short name T269
Test name
Test status
Simulation time 3599739605 ps
CPU time 12.69 seconds
Started Oct 12 01:00:49 AM UTC 24
Finished Oct 12 01:01:03 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1650580754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1650580754
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.455359736
Short name T601
Test name
Test status
Simulation time 7448770677 ps
CPU time 1.32 seconds
Started Oct 12 01:00:46 AM UTC 24
Finished Oct 12 01:00:48 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455359736 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.455359736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.996807621
Short name T271
Test name
Test status
Simulation time 2039413945 ps
CPU time 2.12 seconds
Started Oct 12 01:01:00 AM UTC 24
Finished Oct 12 01:01:03 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996807621 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.996807621
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3193597710
Short name T600
Test name
Test status
Simulation time 3704651119 ps
CPU time 5.17 seconds
Started Oct 12 01:00:55 AM UTC 24
Finished Oct 12 01:01:01 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193597710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.3193597710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.1259874134
Short name T125
Test name
Test status
Simulation time 132213067578 ps
CPU time 379.12 seconds
Started Oct 12 01:00:56 AM UTC 24
Finished Oct 12 01:07:20 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259874134 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.1259874134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3398427355
Short name T374
Test name
Test status
Simulation time 74568761086 ps
CPU time 107.7 seconds
Started Oct 12 01:00:57 AM UTC 24
Finished Oct 12 01:02:47 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398427355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.3398427355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3709870175
Short name T618
Test name
Test status
Simulation time 4584364617 ps
CPU time 18.05 seconds
Started Oct 12 01:00:54 AM UTC 24
Finished Oct 12 01:01:13 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709870175 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.3709870175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.4204879855
Short name T188
Test name
Test status
Simulation time 3516778062 ps
CPU time 16.04 seconds
Started Oct 12 01:00:57 AM UTC 24
Finished Oct 12 01:01:14 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204879855 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.4204879855
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.4262850606
Short name T272
Test name
Test status
Simulation time 2609830683 ps
CPU time 10.81 seconds
Started Oct 12 01:00:53 AM UTC 24
Finished Oct 12 01:01:04 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262850606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.4262850606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.3984538135
Short name T612
Test name
Test status
Simulation time 2501070211 ps
CPU time 3.27 seconds
Started Oct 12 01:00:51 AM UTC 24
Finished Oct 12 01:00:56 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984538135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.3984538135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2891979280
Short name T613
Test name
Test status
Simulation time 2270792391 ps
CPU time 3.91 seconds
Started Oct 12 01:00:51 AM UTC 24
Finished Oct 12 01:00:57 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891979280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.2891979280
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.2447354881
Short name T268
Test name
Test status
Simulation time 2508349118 ps
CPU time 8.69 seconds
Started Oct 12 01:00:51 AM UTC 24
Finished Oct 12 01:01:01 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447354881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.2447354881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.998650779
Short name T591
Test name
Test status
Simulation time 2110597973 ps
CPU time 8.04 seconds
Started Oct 12 01:00:50 AM UTC 24
Finished Oct 12 01:00:59 AM UTC 24
Peak memory 209312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998650779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.998650779
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3835692866
Short name T616
Test name
Test status
Simulation time 11163184618 ps
CPU time 9.08 seconds
Started Oct 12 01:01:00 AM UTC 24
Finished Oct 12 01:01:10 AM UTC 24
Peak memory 209004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835692866 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.3835692866
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3905867398
Short name T273
Test name
Test status
Simulation time 3337185041 ps
CPU time 7 seconds
Started Oct 12 01:00:58 AM UTC 24
Finished Oct 12 01:01:06 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3905867398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3905867398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2503637872
Short name T153
Test name
Test status
Simulation time 2980661120198 ps
CPU time 297.15 seconds
Started Oct 12 01:00:56 AM UTC 24
Finished Oct 12 01:05:57 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503637872 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.2503637872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2337143457
Short name T620
Test name
Test status
Simulation time 2019438937 ps
CPU time 5.15 seconds
Started Oct 12 01:01:12 AM UTC 24
Finished Oct 12 01:01:18 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337143457 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.2337143457
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.519405958
Short name T617
Test name
Test status
Simulation time 3498180186 ps
CPU time 3.31 seconds
Started Oct 12 01:01:07 AM UTC 24
Finished Oct 12 01:01:11 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519405958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.519405958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1566602886
Short name T122
Test name
Test status
Simulation time 151668875777 ps
CPU time 136.8 seconds
Started Oct 12 01:01:08 AM UTC 24
Finished Oct 12 01:03:27 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566602886 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.1566602886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1978307176
Short name T615
Test name
Test status
Simulation time 4470993641 ps
CPU time 2.62 seconds
Started Oct 12 01:01:06 AM UTC 24
Finished Oct 12 01:01:09 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978307176 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.1978307176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.43141907
Short name T178
Test name
Test status
Simulation time 4039079153 ps
CPU time 8.54 seconds
Started Oct 12 01:01:08 AM UTC 24
Finished Oct 12 01:01:18 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43141907 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.43141907
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.826686412
Short name T619
Test name
Test status
Simulation time 2613147998 ps
CPU time 9.25 seconds
Started Oct 12 01:01:05 AM UTC 24
Finished Oct 12 01:01:15 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826686412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.826686412
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.1312377978
Short name T274
Test name
Test status
Simulation time 2507535860 ps
CPU time 3.24 seconds
Started Oct 12 01:01:02 AM UTC 24
Finished Oct 12 01:01:07 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312377978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.1312377978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.4085915825
Short name T276
Test name
Test status
Simulation time 2241609486 ps
CPU time 2.16 seconds
Started Oct 12 01:01:04 AM UTC 24
Finished Oct 12 01:01:07 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085915825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.4085915825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.451500288
Short name T614
Test name
Test status
Simulation time 2522627829 ps
CPU time 3.11 seconds
Started Oct 12 01:01:04 AM UTC 24
Finished Oct 12 01:01:08 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451500288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.451500288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3971652547
Short name T275
Test name
Test status
Simulation time 2119257243 ps
CPU time 4.29 seconds
Started Oct 12 01:01:01 AM UTC 24
Finished Oct 12 01:01:07 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971652547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3971652547
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.2145896116
Short name T783
Test name
Test status
Simulation time 1209402246296 ps
CPU time 288.7 seconds
Started Oct 12 01:01:10 AM UTC 24
Finished Oct 12 01:06:03 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145896116 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.2145896116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.827170528
Short name T318
Test name
Test status
Simulation time 6973170957 ps
CPU time 6.11 seconds
Started Oct 12 01:01:09 AM UTC 24
Finished Oct 12 01:01:16 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=827170528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.827170528
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2044164809
Short name T624
Test name
Test status
Simulation time 5457271484 ps
CPU time 10.92 seconds
Started Oct 12 01:01:08 AM UTC 24
Finished Oct 12 01:01:20 AM UTC 24
Peak memory 209620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044164809 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.2044164809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.107667525
Short name T628
Test name
Test status
Simulation time 2028476747 ps
CPU time 3.17 seconds
Started Oct 12 01:01:22 AM UTC 24
Finished Oct 12 01:01:26 AM UTC 24
Peak memory 209224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107667525 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.107667525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.4010860357
Short name T629
Test name
Test status
Simulation time 3437122943 ps
CPU time 8.17 seconds
Started Oct 12 01:01:18 AM UTC 24
Finished Oct 12 01:01:27 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010860357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.4010860357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2519848875
Short name T794
Test name
Test status
Simulation time 121973308587 ps
CPU time 364.62 seconds
Started Oct 12 01:01:18 AM UTC 24
Finished Oct 12 01:07:27 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519848875 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.2519848875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1206571768
Short name T625
Test name
Test status
Simulation time 4200985829 ps
CPU time 5.42 seconds
Started Oct 12 01:01:17 AM UTC 24
Finished Oct 12 01:01:23 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206571768 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.1206571768
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.5886012
Short name T627
Test name
Test status
Simulation time 2711890345 ps
CPU time 3.55 seconds
Started Oct 12 01:01:19 AM UTC 24
Finished Oct 12 01:01:24 AM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5886012 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.5886012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1238469145
Short name T626
Test name
Test status
Simulation time 2617073547 ps
CPU time 6.8 seconds
Started Oct 12 01:01:16 AM UTC 24
Finished Oct 12 01:01:24 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238469145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.1238469145
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.2573679010
Short name T630
Test name
Test status
Simulation time 2449293463 ps
CPU time 12.7 seconds
Started Oct 12 01:01:14 AM UTC 24
Finished Oct 12 01:01:27 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573679010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.2573679010
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.1622780231
Short name T621
Test name
Test status
Simulation time 2129961703 ps
CPU time 3.24 seconds
Started Oct 12 01:01:15 AM UTC 24
Finished Oct 12 01:01:19 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622780231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1622780231
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.1126885780
Short name T622
Test name
Test status
Simulation time 2528049051 ps
CPU time 3.81 seconds
Started Oct 12 01:01:15 AM UTC 24
Finished Oct 12 01:01:20 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126885780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1126885780
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.4169695122
Short name T623
Test name
Test status
Simulation time 2112846389 ps
CPU time 7.46 seconds
Started Oct 12 01:01:12 AM UTC 24
Finished Oct 12 01:01:20 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169695122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.4169695122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.115521796
Short name T635
Test name
Test status
Simulation time 8592169527 ps
CPU time 10.52 seconds
Started Oct 12 01:01:22 AM UTC 24
Finished Oct 12 01:01:33 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115521796 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.115521796
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1393378000
Short name T336
Test name
Test status
Simulation time 4420767274 ps
CPU time 9.86 seconds
Started Oct 12 01:01:20 AM UTC 24
Finished Oct 12 01:01:31 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1393378000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1393378000
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.642126624
Short name T633
Test name
Test status
Simulation time 5415672691 ps
CPU time 12.66 seconds
Started Oct 12 01:01:18 AM UTC 24
Finished Oct 12 01:01:32 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642126624 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.642126624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.1486915918
Short name T638
Test name
Test status
Simulation time 2044346539 ps
CPU time 3 seconds
Started Oct 12 01:01:34 AM UTC 24
Finished Oct 12 01:01:38 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486915918 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.1486915918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3116559939
Short name T634
Test name
Test status
Simulation time 3982926593 ps
CPU time 3.28 seconds
Started Oct 12 01:01:28 AM UTC 24
Finished Oct 12 01:01:32 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116559939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3116559939
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.605735248
Short name T257
Test name
Test status
Simulation time 77465137252 ps
CPU time 82.71 seconds
Started Oct 12 01:01:30 AM UTC 24
Finished Oct 12 01:02:55 AM UTC 24
Peak memory 209404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605735248 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.605735248
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.1995639552
Short name T424
Test name
Test status
Simulation time 53509148397 ps
CPU time 122.32 seconds
Started Oct 12 01:01:33 AM UTC 24
Finished Oct 12 01:03:37 AM UTC 24
Peak memory 209804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995639552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_with_pre_cond.1995639552
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.281989910
Short name T641
Test name
Test status
Simulation time 4586198897 ps
CPU time 14.43 seconds
Started Oct 12 01:01:28 AM UTC 24
Finished Oct 12 01:01:44 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281989910 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.281989910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.1159618520
Short name T203
Test name
Test status
Simulation time 4421798532 ps
CPU time 2.97 seconds
Started Oct 12 01:01:31 AM UTC 24
Finished Oct 12 01:01:36 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159618520 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.1159618520
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1151373750
Short name T639
Test name
Test status
Simulation time 2613521794 ps
CPU time 13.03 seconds
Started Oct 12 01:01:27 AM UTC 24
Finished Oct 12 01:01:41 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151373750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1151373750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3208099505
Short name T632
Test name
Test status
Simulation time 2475064424 ps
CPU time 3.69 seconds
Started Oct 12 01:01:25 AM UTC 24
Finished Oct 12 01:01:30 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208099505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3208099505
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.1490679019
Short name T636
Test name
Test status
Simulation time 2067364657 ps
CPU time 10.01 seconds
Started Oct 12 01:01:25 AM UTC 24
Finished Oct 12 01:01:36 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490679019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1490679019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.3549526872
Short name T631
Test name
Test status
Simulation time 2554982053 ps
CPU time 2.51 seconds
Started Oct 12 01:01:26 AM UTC 24
Finished Oct 12 01:01:30 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549526872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.3549526872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.3002179530
Short name T637
Test name
Test status
Simulation time 2109301864 ps
CPU time 10.41 seconds
Started Oct 12 01:01:25 AM UTC 24
Finished Oct 12 01:01:36 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002179530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.3002179530
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.2472535051
Short name T659
Test name
Test status
Simulation time 14759871310 ps
CPU time 33.32 seconds
Started Oct 12 01:01:34 AM UTC 24
Finished Oct 12 01:02:09 AM UTC 24
Peak memory 209356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472535051 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.2472535051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.850715242
Short name T643
Test name
Test status
Simulation time 3416762736 ps
CPU time 11.94 seconds
Started Oct 12 01:01:33 AM UTC 24
Finished Oct 12 01:01:46 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=850715242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.850715242
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2968991695
Short name T232
Test name
Test status
Simulation time 1071353253739 ps
CPU time 48.04 seconds
Started Oct 12 01:01:30 AM UTC 24
Finished Oct 12 01:02:20 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968991695 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.2968991695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.3019243492
Short name T646
Test name
Test status
Simulation time 2083439060 ps
CPU time 1.94 seconds
Started Oct 12 01:01:48 AM UTC 24
Finished Oct 12 01:01:51 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019243492 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.3019243492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1383038149
Short name T652
Test name
Test status
Simulation time 3401826145 ps
CPU time 12.17 seconds
Started Oct 12 01:01:43 AM UTC 24
Finished Oct 12 01:01:57 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383038149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.1383038149
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.3081618189
Short name T777
Test name
Test status
Simulation time 76665765604 ps
CPU time 216.2 seconds
Started Oct 12 01:01:45 AM UTC 24
Finished Oct 12 01:05:24 AM UTC 24
Peak memory 209552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081618189 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.3081618189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2233663230
Short name T656
Test name
Test status
Simulation time 23362448763 ps
CPU time 19.83 seconds
Started Oct 12 01:01:46 AM UTC 24
Finished Oct 12 01:02:07 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233663230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_with_pre_cond.2233663230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1313649952
Short name T649
Test name
Test status
Simulation time 3093099959 ps
CPU time 11.93 seconds
Started Oct 12 01:01:42 AM UTC 24
Finished Oct 12 01:01:55 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313649952 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.1313649952
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3795400469
Short name T644
Test name
Test status
Simulation time 2629366153 ps
CPU time 3.45 seconds
Started Oct 12 01:01:41 AM UTC 24
Finished Oct 12 01:01:46 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795400469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3795400469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1765407822
Short name T648
Test name
Test status
Simulation time 2461002145 ps
CPU time 13.3 seconds
Started Oct 12 01:01:37 AM UTC 24
Finished Oct 12 01:01:51 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765407822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.1765407822
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.4027012489
Short name T640
Test name
Test status
Simulation time 2244574496 ps
CPU time 5.39 seconds
Started Oct 12 01:01:37 AM UTC 24
Finished Oct 12 01:01:44 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027012489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.4027012489
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.62256279
Short name T642
Test name
Test status
Simulation time 2519624801 ps
CPU time 4.84 seconds
Started Oct 12 01:01:39 AM UTC 24
Finished Oct 12 01:01:45 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62256279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.62256279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.2300741770
Short name T645
Test name
Test status
Simulation time 2115562845 ps
CPU time 9.29 seconds
Started Oct 12 01:01:37 AM UTC 24
Finished Oct 12 01:01:47 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300741770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.2300741770
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2278601328
Short name T147
Test name
Test status
Simulation time 9082026419 ps
CPU time 8 seconds
Started Oct 12 01:01:47 AM UTC 24
Finished Oct 12 01:01:56 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278601328 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.2278601328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1530500521
Short name T657
Test name
Test status
Simulation time 4136515098 ps
CPU time 19.23 seconds
Started Oct 12 01:01:47 AM UTC 24
Finished Oct 12 01:02:07 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1530500521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.1530500521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4173910725
Short name T647
Test name
Test status
Simulation time 6013131124 ps
CPU time 5.52 seconds
Started Oct 12 01:01:44 AM UTC 24
Finished Oct 12 01:01:51 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173910725 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.4173910725
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3153878793
Short name T664
Test name
Test status
Simulation time 2014357537 ps
CPU time 9.8 seconds
Started Oct 12 01:02:02 AM UTC 24
Finished Oct 12 01:02:13 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153878793 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.3153878793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2104070541
Short name T663
Test name
Test status
Simulation time 3532350921 ps
CPU time 14.9 seconds
Started Oct 12 01:01:57 AM UTC 24
Finished Oct 12 01:02:13 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104070541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2104070541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3757013206
Short name T401
Test name
Test status
Simulation time 97804808637 ps
CPU time 76.48 seconds
Started Oct 12 01:01:58 AM UTC 24
Finished Oct 12 01:03:16 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757013206 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.3757013206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.2575558966
Short name T658
Test name
Test status
Simulation time 4228287473 ps
CPU time 10.64 seconds
Started Oct 12 01:01:56 AM UTC 24
Finished Oct 12 01:02:08 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575558966 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.2575558966
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.2464628018
Short name T210
Test name
Test status
Simulation time 229976575249 ps
CPU time 104.21 seconds
Started Oct 12 01:01:58 AM UTC 24
Finished Oct 12 01:03:44 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464628018 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.2464628018
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1124632853
Short name T655
Test name
Test status
Simulation time 2610347204 ps
CPU time 7.18 seconds
Started Oct 12 01:01:54 AM UTC 24
Finished Oct 12 01:02:03 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124632853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1124632853
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.2707895290
Short name T654
Test name
Test status
Simulation time 2458005408 ps
CPU time 7.91 seconds
Started Oct 12 01:01:52 AM UTC 24
Finished Oct 12 01:02:01 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707895290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.2707895290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3541419784
Short name T651
Test name
Test status
Simulation time 2167585217 ps
CPU time 3.23 seconds
Started Oct 12 01:01:52 AM UTC 24
Finished Oct 12 01:01:56 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541419784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3541419784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.1957093305
Short name T653
Test name
Test status
Simulation time 2518559464 ps
CPU time 3.33 seconds
Started Oct 12 01:01:53 AM UTC 24
Finished Oct 12 01:01:58 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957093305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1957093305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.3878224990
Short name T650
Test name
Test status
Simulation time 2132359912 ps
CPU time 3.39 seconds
Started Oct 12 01:01:52 AM UTC 24
Finished Oct 12 01:01:56 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878224990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.3878224990
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2289832329
Short name T327
Test name
Test status
Simulation time 14867065436 ps
CPU time 15.88 seconds
Started Oct 12 01:01:58 AM UTC 24
Finished Oct 12 01:02:15 AM UTC 24
Peak memory 217828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2289832329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.2289832329
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.4103021735
Short name T661
Test name
Test status
Simulation time 7422100435 ps
CPU time 11.18 seconds
Started Oct 12 01:01:58 AM UTC 24
Finished Oct 12 01:02:10 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103021735 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.4103021735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2845928989
Short name T237
Test name
Test status
Simulation time 2010371728 ps
CPU time 7.08 seconds
Started Oct 12 01:02:16 AM UTC 24
Finished Oct 12 01:02:25 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845928989 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.2845928989
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1684225974
Short name T230
Test name
Test status
Simulation time 3480713939 ps
CPU time 6.99 seconds
Started Oct 12 01:02:11 AM UTC 24
Finished Oct 12 01:02:19 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684225974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1684225974
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.1613576062
Short name T370
Test name
Test status
Simulation time 66216684026 ps
CPU time 31.18 seconds
Started Oct 12 01:02:14 AM UTC 24
Finished Oct 12 01:02:47 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613576062 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.1613576062
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2317203949
Short name T376
Test name
Test status
Simulation time 56184514524 ps
CPU time 34.56 seconds
Started Oct 12 01:02:14 AM UTC 24
Finished Oct 12 01:02:50 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317203949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.2317203949
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.248626127
Short name T238
Test name
Test status
Simulation time 3001471010 ps
CPU time 12.82 seconds
Started Oct 12 01:02:11 AM UTC 24
Finished Oct 12 01:02:25 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248626127 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.248626127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3589504192
Short name T665
Test name
Test status
Simulation time 2641861335 ps
CPU time 2.7 seconds
Started Oct 12 01:02:10 AM UTC 24
Finished Oct 12 01:02:14 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589504192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3589504192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.537564961
Short name T662
Test name
Test status
Simulation time 2489938022 ps
CPU time 3.63 seconds
Started Oct 12 01:02:07 AM UTC 24
Finished Oct 12 01:02:13 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537564961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.537564961
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2061437348
Short name T233
Test name
Test status
Simulation time 2234032436 ps
CPU time 10.63 seconds
Started Oct 12 01:02:08 AM UTC 24
Finished Oct 12 01:02:21 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061437348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2061437348
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.3226425916
Short name T235
Test name
Test status
Simulation time 2513340520 ps
CPU time 11.5 seconds
Started Oct 12 01:02:10 AM UTC 24
Finished Oct 12 01:02:23 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226425916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.3226425916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2128303855
Short name T660
Test name
Test status
Simulation time 2119418882 ps
CPU time 5.51 seconds
Started Oct 12 01:02:03 AM UTC 24
Finished Oct 12 01:02:10 AM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128303855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.2128303855
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.3511101988
Short name T691
Test name
Test status
Simulation time 12267216923 ps
CPU time 34.51 seconds
Started Oct 12 01:02:15 AM UTC 24
Finished Oct 12 01:02:51 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511101988 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.3511101988
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.866314543
Short name T337
Test name
Test status
Simulation time 8967913526 ps
CPU time 21.28 seconds
Started Oct 12 01:02:14 AM UTC 24
Finished Oct 12 01:02:37 AM UTC 24
Peak memory 225948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=866314543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.866314543
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2280963253
Short name T426
Test name
Test status
Simulation time 662835078684 ps
CPU time 82.34 seconds
Started Oct 12 01:02:12 AM UTC 24
Finished Oct 12 01:03:36 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280963253 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.2280963253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.434303522
Short name T311
Test name
Test status
Simulation time 2032135933 ps
CPU time 2.68 seconds
Started Oct 12 12:56:50 AM UTC 24
Finished Oct 12 12:56:54 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434303522 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.434303522
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1956630342
Short name T70
Test name
Test status
Simulation time 3828790610 ps
CPU time 12.87 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:57:01 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956630342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.1956630342
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1897161805
Short name T204
Test name
Test status
Simulation time 2198054688 ps
CPU time 3.73 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:52 AM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897161805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.1897161805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3036549224
Short name T40
Test name
Test status
Simulation time 2657404501 ps
CPU time 1.33 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:50 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036549224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3036549224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3138025342
Short name T151
Test name
Test status
Simulation time 2467526492 ps
CPU time 2.72 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:51 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138025342 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.3138025342
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1880344223
Short name T433
Test name
Test status
Simulation time 2610284233 ps
CPU time 8.18 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:56 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880344223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.1880344223
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.334599477
Short name T89
Test name
Test status
Simulation time 2481853918 ps
CPU time 2.48 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:51 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334599477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.334599477
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.215179605
Short name T315
Test name
Test status
Simulation time 2262028132 ps
CPU time 8.02 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:56 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215179605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.215179605
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.1451726534
Short name T95
Test name
Test status
Simulation time 2525072188 ps
CPU time 3.45 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:52 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451726534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1451726534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.1657165888
Short name T306
Test name
Test status
Simulation time 22015782530 ps
CPU time 43.39 seconds
Started Oct 12 12:56:49 AM UTC 24
Finished Oct 12 12:57:34 AM UTC 24
Peak memory 241080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657165888 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.1657165888
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.175146617
Short name T310
Test name
Test status
Simulation time 2117539672 ps
CPU time 5.6 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:54 AM UTC 24
Peak memory 209312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175146617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.175146617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.939104900
Short name T160
Test name
Test status
Simulation time 340063481788 ps
CPU time 702.23 seconds
Started Oct 12 12:56:49 AM UTC 24
Finished Oct 12 01:08:39 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939104900 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.939104900
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1486530643
Short name T78
Test name
Test status
Simulation time 6791975515 ps
CPU time 1.38 seconds
Started Oct 12 12:56:47 AM UTC 24
Finished Oct 12 12:56:50 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486530643 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.1486530643
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.2407416873
Short name T672
Test name
Test status
Simulation time 2048229040 ps
CPU time 1.8 seconds
Started Oct 12 01:02:29 AM UTC 24
Finished Oct 12 01:02:32 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407416873 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.2407416873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.206427533
Short name T670
Test name
Test status
Simulation time 3345123492 ps
CPU time 4.36 seconds
Started Oct 12 01:02:24 AM UTC 24
Finished Oct 12 01:02:30 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206427533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.206427533
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.2737378281
Short name T799
Test name
Test status
Simulation time 208323756345 ps
CPU time 325.16 seconds
Started Oct 12 01:02:25 AM UTC 24
Finished Oct 12 01:07:54 AM UTC 24
Peak memory 209552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737378281 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.2737378281
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3734346382
Short name T720
Test name
Test status
Simulation time 27084154299 ps
CPU time 42.21 seconds
Started Oct 12 01:02:26 AM UTC 24
Finished Oct 12 01:03:10 AM UTC 24
Peak memory 209616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734346382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_with_pre_cond.3734346382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2823540278
Short name T669
Test name
Test status
Simulation time 2894391784 ps
CPU time 4.36 seconds
Started Oct 12 01:02:24 AM UTC 24
Finished Oct 12 01:02:30 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823540278 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.2823540278
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1506836802
Short name T199
Test name
Test status
Simulation time 3239628741 ps
CPU time 6.56 seconds
Started Oct 12 01:02:26 AM UTC 24
Finished Oct 12 01:02:34 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506836802 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.1506836802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1817737706
Short name T666
Test name
Test status
Simulation time 2645893545 ps
CPU time 2.42 seconds
Started Oct 12 01:02:22 AM UTC 24
Finished Oct 12 01:02:26 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817737706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1817737706
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.3454732751
Short name T673
Test name
Test status
Simulation time 2449115917 ps
CPU time 11.73 seconds
Started Oct 12 01:02:21 AM UTC 24
Finished Oct 12 01:02:33 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454732751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3454732751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.558510981
Short name T668
Test name
Test status
Simulation time 2076314787 ps
CPU time 5.69 seconds
Started Oct 12 01:02:21 AM UTC 24
Finished Oct 12 01:02:27 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558510981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.558510981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2828259206
Short name T671
Test name
Test status
Simulation time 2508791419 ps
CPU time 8.16 seconds
Started Oct 12 01:02:21 AM UTC 24
Finished Oct 12 01:02:30 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828259206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2828259206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.2116136729
Short name T667
Test name
Test status
Simulation time 2111901225 ps
CPU time 5.23 seconds
Started Oct 12 01:02:19 AM UTC 24
Finished Oct 12 01:02:26 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116136729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.2116136729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.3328547709
Short name T207
Test name
Test status
Simulation time 16060158492 ps
CPU time 17.87 seconds
Started Oct 12 01:02:29 AM UTC 24
Finished Oct 12 01:02:48 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328547709 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.3328547709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.573328215
Short name T686
Test name
Test status
Simulation time 5123789608 ps
CPU time 19.13 seconds
Started Oct 12 01:02:27 AM UTC 24
Finished Oct 12 01:02:48 AM UTC 24
Peak memory 217836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=573328215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.573328215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2166489103
Short name T675
Test name
Test status
Simulation time 4435804514 ps
CPU time 10.95 seconds
Started Oct 12 01:02:24 AM UTC 24
Finished Oct 12 01:02:36 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166489103 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.2166489103
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.876738304
Short name T693
Test name
Test status
Simulation time 2014237371 ps
CPU time 11.77 seconds
Started Oct 12 01:02:39 AM UTC 24
Finished Oct 12 01:02:52 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876738304 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.876738304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1490670132
Short name T678
Test name
Test status
Simulation time 3342147527 ps
CPU time 1.72 seconds
Started Oct 12 01:02:35 AM UTC 24
Finished Oct 12 01:02:38 AM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490670132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.1490670132
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.2196730582
Short name T267
Test name
Test status
Simulation time 142067481903 ps
CPU time 562.89 seconds
Started Oct 12 01:02:37 AM UTC 24
Finished Oct 12 01:12:07 AM UTC 24
Peak memory 209668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196730582 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.2196730582
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2194321310
Short name T695
Test name
Test status
Simulation time 3974813848 ps
CPU time 18.22 seconds
Started Oct 12 01:02:34 AM UTC 24
Finished Oct 12 01:02:53 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194321310 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.2194321310
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.3226434036
Short name T727
Test name
Test status
Simulation time 299316466288 ps
CPU time 36.95 seconds
Started Oct 12 01:02:37 AM UTC 24
Finished Oct 12 01:03:16 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226434036 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.3226434036
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2017420675
Short name T676
Test name
Test status
Simulation time 2626244911 ps
CPU time 4.21 seconds
Started Oct 12 01:02:32 AM UTC 24
Finished Oct 12 01:02:37 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017420675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2017420675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2582652685
Short name T680
Test name
Test status
Simulation time 2449998826 ps
CPU time 12.37 seconds
Started Oct 12 01:02:31 AM UTC 24
Finished Oct 12 01:02:44 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582652685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.2582652685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1139709938
Short name T674
Test name
Test status
Simulation time 2050568780 ps
CPU time 2.61 seconds
Started Oct 12 01:02:31 AM UTC 24
Finished Oct 12 01:02:35 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139709938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1139709938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.2797906005
Short name T679
Test name
Test status
Simulation time 2510801352 ps
CPU time 12.17 seconds
Started Oct 12 01:02:31 AM UTC 24
Finished Oct 12 01:02:44 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797906005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.2797906005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.764985040
Short name T677
Test name
Test status
Simulation time 2115824228 ps
CPU time 6 seconds
Started Oct 12 01:02:31 AM UTC 24
Finished Oct 12 01:02:38 AM UTC 24
Peak memory 209248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764985040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.764985040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.4007701315
Short name T681
Test name
Test status
Simulation time 14998415561 ps
CPU time 4.63 seconds
Started Oct 12 01:02:39 AM UTC 24
Finished Oct 12 01:02:44 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007701315 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.4007701315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3257532765
Short name T688
Test name
Test status
Simulation time 30716967835 ps
CPU time 9.52 seconds
Started Oct 12 01:02:39 AM UTC 24
Finished Oct 12 01:02:49 AM UTC 24
Peak memory 217908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3257532765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.3257532765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2924308296
Short name T684
Test name
Test status
Simulation time 3473216372 ps
CPU time 11.12 seconds
Started Oct 12 01:02:35 AM UTC 24
Finished Oct 12 01:02:47 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924308296 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.2924308296
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.2685486959
Short name T703
Test name
Test status
Simulation time 2014504863 ps
CPU time 8.25 seconds
Started Oct 12 01:02:49 AM UTC 24
Finished Oct 12 01:02:58 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685486959 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.2685486959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2947578693
Short name T702
Test name
Test status
Simulation time 3289969279 ps
CPU time 10.38 seconds
Started Oct 12 01:02:45 AM UTC 24
Finished Oct 12 01:02:57 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947578693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.2947578693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.3352499069
Short name T399
Test name
Test status
Simulation time 80868848202 ps
CPU time 117.99 seconds
Started Oct 12 01:02:48 AM UTC 24
Finished Oct 12 01:04:48 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352499069 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.3352499069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2949191982
Short name T763
Test name
Test status
Simulation time 24328383022 ps
CPU time 90.4 seconds
Started Oct 12 01:02:48 AM UTC 24
Finished Oct 12 01:04:20 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949191982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_with_pre_cond.2949191982
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4065067035
Short name T690
Test name
Test status
Simulation time 5660479602 ps
CPU time 3.87 seconds
Started Oct 12 01:02:45 AM UTC 24
Finished Oct 12 01:02:50 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065067035 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.4065067035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.3664153918
Short name T208
Test name
Test status
Simulation time 5603047390 ps
CPU time 10.38 seconds
Started Oct 12 01:02:48 AM UTC 24
Finished Oct 12 01:02:59 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664153918 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.3664153918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1422810553
Short name T685
Test name
Test status
Simulation time 2663293481 ps
CPU time 1.45 seconds
Started Oct 12 01:02:45 AM UTC 24
Finished Oct 12 01:02:48 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422810553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1422810553
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1247929094
Short name T682
Test name
Test status
Simulation time 2475640250 ps
CPU time 3.77 seconds
Started Oct 12 01:02:41 AM UTC 24
Finished Oct 12 01:02:46 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247929094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.1247929094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1423450801
Short name T683
Test name
Test status
Simulation time 2163380927 ps
CPU time 3.1 seconds
Started Oct 12 01:02:42 AM UTC 24
Finished Oct 12 01:02:46 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423450801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1423450801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.2046543656
Short name T687
Test name
Test status
Simulation time 2538743845 ps
CPU time 3.87 seconds
Started Oct 12 01:02:44 AM UTC 24
Finished Oct 12 01:02:49 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046543656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.2046543656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.984676658
Short name T689
Test name
Test status
Simulation time 2111283320 ps
CPU time 10.07 seconds
Started Oct 12 01:02:39 AM UTC 24
Finished Oct 12 01:02:50 AM UTC 24
Peak memory 209312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984676658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.984676658
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.2021122941
Short name T700
Test name
Test status
Simulation time 12399681225 ps
CPU time 5.57 seconds
Started Oct 12 01:02:49 AM UTC 24
Finished Oct 12 01:02:56 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021122941 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.2021122941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.775494067
Short name T704
Test name
Test status
Simulation time 4878916565 ps
CPU time 9.08 seconds
Started Oct 12 01:02:49 AM UTC 24
Finished Oct 12 01:02:59 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=775494067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.775494067
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1305615595
Short name T692
Test name
Test status
Simulation time 5830227806 ps
CPU time 3.92 seconds
Started Oct 12 01:02:46 AM UTC 24
Finished Oct 12 01:02:51 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305615595 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.1305615595
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.3784490132
Short name T706
Test name
Test status
Simulation time 2060732336 ps
CPU time 2.92 seconds
Started Oct 12 01:02:56 AM UTC 24
Finished Oct 12 01:03:00 AM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784490132 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.3784490132
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.981627701
Short name T121
Test name
Test status
Simulation time 3440396624 ps
CPU time 11.66 seconds
Started Oct 12 01:02:53 AM UTC 24
Finished Oct 12 01:03:05 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981627701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.981627701
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.3301312105
Short name T124
Test name
Test status
Simulation time 72443258339 ps
CPU time 221.56 seconds
Started Oct 12 01:02:53 AM UTC 24
Finished Oct 12 01:06:38 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301312105 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.3301312105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3038632970
Short name T768
Test name
Test status
Simulation time 123030377663 ps
CPU time 100.13 seconds
Started Oct 12 01:02:54 AM UTC 24
Finished Oct 12 01:04:36 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038632970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_with_pre_cond.3038632970
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1607298714
Short name T712
Test name
Test status
Simulation time 4283331355 ps
CPU time 11.68 seconds
Started Oct 12 01:02:52 AM UTC 24
Finished Oct 12 01:03:04 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607298714 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.1607298714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3866283208
Short name T205
Test name
Test status
Simulation time 2461122660 ps
CPU time 3.61 seconds
Started Oct 12 01:02:53 AM UTC 24
Finished Oct 12 01:02:57 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866283208 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.3866283208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1707631288
Short name T701
Test name
Test status
Simulation time 2638886665 ps
CPU time 3.77 seconds
Started Oct 12 01:02:51 AM UTC 24
Finished Oct 12 01:02:56 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707631288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.1707631288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.1826126516
Short name T696
Test name
Test status
Simulation time 2473828604 ps
CPU time 2.68 seconds
Started Oct 12 01:02:50 AM UTC 24
Finished Oct 12 01:02:54 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826126516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.1826126516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.3883475038
Short name T697
Test name
Test status
Simulation time 2117236568 ps
CPU time 3.41 seconds
Started Oct 12 01:02:50 AM UTC 24
Finished Oct 12 01:02:55 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883475038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.3883475038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3463758729
Short name T698
Test name
Test status
Simulation time 2565173036 ps
CPU time 2.42 seconds
Started Oct 12 01:02:51 AM UTC 24
Finished Oct 12 01:02:55 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463758729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.3463758729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.347178665
Short name T694
Test name
Test status
Simulation time 2139893685 ps
CPU time 2.24 seconds
Started Oct 12 01:02:49 AM UTC 24
Finished Oct 12 01:02:52 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347178665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.347178665
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.2009521052
Short name T715
Test name
Test status
Simulation time 12286917984 ps
CPU time 11.58 seconds
Started Oct 12 01:02:55 AM UTC 24
Finished Oct 12 01:03:08 AM UTC 24
Peak memory 209292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009521052 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.2009521052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2284821827
Short name T711
Test name
Test status
Simulation time 10932373606 ps
CPU time 7.07 seconds
Started Oct 12 01:02:55 AM UTC 24
Finished Oct 12 01:03:03 AM UTC 24
Peak memory 218100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2284821827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2284821827
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4047159374
Short name T699
Test name
Test status
Simulation time 5222501503 ps
CPU time 1.66 seconds
Started Oct 12 01:02:53 AM UTC 24
Finished Oct 12 01:02:55 AM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047159374 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.4047159374
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.909376819
Short name T713
Test name
Test status
Simulation time 2068143394 ps
CPU time 2.01 seconds
Started Oct 12 01:03:02 AM UTC 24
Finished Oct 12 01:03:05 AM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909376819 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.909376819
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3646148542
Short name T717
Test name
Test status
Simulation time 3173503555 ps
CPU time 8.5 seconds
Started Oct 12 01:02:59 AM UTC 24
Finished Oct 12 01:03:08 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646148542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.3646148542
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.720211994
Short name T416
Test name
Test status
Simulation time 114705192109 ps
CPU time 98.85 seconds
Started Oct 12 01:03:00 AM UTC 24
Finished Oct 12 01:04:41 AM UTC 24
Peak memory 209424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720211994 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.720211994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2070289960
Short name T191
Test name
Test status
Simulation time 40612072244 ps
CPU time 20.64 seconds
Started Oct 12 01:03:01 AM UTC 24
Finished Oct 12 01:03:23 AM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070289960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_with_pre_cond.2070289960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4060302728
Short name T728
Test name
Test status
Simulation time 5234991581 ps
CPU time 16.5 seconds
Started Oct 12 01:02:59 AM UTC 24
Finished Oct 12 01:03:16 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060302728 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.4060302728
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.3783135222
Short name T722
Test name
Test status
Simulation time 4127938567 ps
CPU time 9.69 seconds
Started Oct 12 01:03:00 AM UTC 24
Finished Oct 12 01:03:11 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783135222 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.3783135222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1434119658
Short name T710
Test name
Test status
Simulation time 2630660392 ps
CPU time 3.77 seconds
Started Oct 12 01:02:58 AM UTC 24
Finished Oct 12 01:03:03 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434119658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1434119658
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.1433067500
Short name T709
Test name
Test status
Simulation time 2454346532 ps
CPU time 4.65 seconds
Started Oct 12 01:02:56 AM UTC 24
Finished Oct 12 01:03:02 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433067500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1433067500
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.2679909389
Short name T707
Test name
Test status
Simulation time 2238912142 ps
CPU time 3.18 seconds
Started Oct 12 01:02:56 AM UTC 24
Finished Oct 12 01:03:01 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679909389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.2679909389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.149383217
Short name T708
Test name
Test status
Simulation time 2537999466 ps
CPU time 2.52 seconds
Started Oct 12 01:02:58 AM UTC 24
Finished Oct 12 01:03:01 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149383217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.149383217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.3887477228
Short name T705
Test name
Test status
Simulation time 2121424122 ps
CPU time 2.93 seconds
Started Oct 12 01:02:56 AM UTC 24
Finished Oct 12 01:03:00 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887477228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3887477228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.431004408
Short name T197
Test name
Test status
Simulation time 18000549628 ps
CPU time 24.86 seconds
Started Oct 12 01:03:01 AM UTC 24
Finished Oct 12 01:03:27 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431004408 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.431004408
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3100020060
Short name T338
Test name
Test status
Simulation time 6547916702 ps
CPU time 16.34 seconds
Started Oct 12 01:03:01 AM UTC 24
Finished Oct 12 01:03:19 AM UTC 24
Peak memory 217652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3100020060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.3100020060
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2946313359
Short name T156
Test name
Test status
Simulation time 3520325181 ps
CPU time 6.76 seconds
Started Oct 12 01:02:59 AM UTC 24
Finished Oct 12 01:03:07 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946313359 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.2946313359
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2056306052
Short name T726
Test name
Test status
Simulation time 2040737317 ps
CPU time 3.29 seconds
Started Oct 12 01:03:11 AM UTC 24
Finished Oct 12 01:03:15 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056306052 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.2056306052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.912825178
Short name T192
Test name
Test status
Simulation time 3476562236 ps
CPU time 14.81 seconds
Started Oct 12 01:03:07 AM UTC 24
Finished Oct 12 01:03:23 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912825178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.912825178
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.899873444
Short name T719
Test name
Test status
Simulation time 2538318184 ps
CPU time 2.07 seconds
Started Oct 12 01:03:06 AM UTC 24
Finished Oct 12 01:03:09 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899873444 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.899873444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.864999286
Short name T721
Test name
Test status
Simulation time 2631623160 ps
CPU time 3.66 seconds
Started Oct 12 01:03:06 AM UTC 24
Finished Oct 12 01:03:11 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864999286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.864999286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.2823709412
Short name T714
Test name
Test status
Simulation time 2574840578 ps
CPU time 1.5 seconds
Started Oct 12 01:03:04 AM UTC 24
Finished Oct 12 01:03:06 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823709412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.2823709412
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.3841255560
Short name T716
Test name
Test status
Simulation time 2056643086 ps
CPU time 3.58 seconds
Started Oct 12 01:03:04 AM UTC 24
Finished Oct 12 01:03:08 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841255560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.3841255560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.3875081232
Short name T718
Test name
Test status
Simulation time 2527343597 ps
CPU time 2.91 seconds
Started Oct 12 01:03:05 AM UTC 24
Finished Oct 12 01:03:09 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875081232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.3875081232
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.2819977482
Short name T724
Test name
Test status
Simulation time 2110673915 ps
CPU time 10.29 seconds
Started Oct 12 01:03:02 AM UTC 24
Finished Oct 12 01:03:14 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819977482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2819977482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1327666375
Short name T158
Test name
Test status
Simulation time 157760279072 ps
CPU time 259.47 seconds
Started Oct 12 01:03:10 AM UTC 24
Finished Oct 12 01:07:33 AM UTC 24
Peak memory 209284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327666375 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.1327666375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1158161060
Short name T328
Test name
Test status
Simulation time 7998803309 ps
CPU time 8.21 seconds
Started Oct 12 01:03:09 AM UTC 24
Finished Oct 12 01:03:19 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1158161060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.1158161060
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1283238886
Short name T723
Test name
Test status
Simulation time 99487980982 ps
CPU time 4.82 seconds
Started Oct 12 01:03:07 AM UTC 24
Finished Oct 12 01:03:13 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283238886 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.1283238886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.2325602617
Short name T193
Test name
Test status
Simulation time 2026342895 ps
CPU time 3.3 seconds
Started Oct 12 01:03:20 AM UTC 24
Finished Oct 12 01:03:24 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325602617 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.2325602617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1821498660
Short name T732
Test name
Test status
Simulation time 3533131221 ps
CPU time 3.58 seconds
Started Oct 12 01:03:16 AM UTC 24
Finished Oct 12 01:03:21 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821498660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.1821498660
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3129211224
Short name T731
Test name
Test status
Simulation time 2839450172 ps
CPU time 4.51 seconds
Started Oct 12 01:03:15 AM UTC 24
Finished Oct 12 01:03:21 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129211224 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.3129211224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1666068668
Short name T734
Test name
Test status
Simulation time 2613788342 ps
CPU time 6.04 seconds
Started Oct 12 01:03:15 AM UTC 24
Finished Oct 12 01:03:22 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666068668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1666068668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1517448154
Short name T194
Test name
Test status
Simulation time 2461545911 ps
CPU time 12.28 seconds
Started Oct 12 01:03:12 AM UTC 24
Finished Oct 12 01:03:25 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517448154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1517448154
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.919802391
Short name T729
Test name
Test status
Simulation time 2163856587 ps
CPU time 3.45 seconds
Started Oct 12 01:03:14 AM UTC 24
Finished Oct 12 01:03:18 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919802391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.919802391
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.108658837
Short name T195
Test name
Test status
Simulation time 2514327425 ps
CPU time 11.53 seconds
Started Oct 12 01:03:14 AM UTC 24
Finished Oct 12 01:03:27 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108658837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.108658837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.531060001
Short name T725
Test name
Test status
Simulation time 2159459314 ps
CPU time 1.8 seconds
Started Oct 12 01:03:12 AM UTC 24
Finished Oct 12 01:03:15 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531060001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.531060001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.1174273940
Short name T266
Test name
Test status
Simulation time 199881041446 ps
CPU time 506.4 seconds
Started Oct 12 01:03:20 AM UTC 24
Finished Oct 12 01:11:52 AM UTC 24
Peak memory 209556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174273940 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.1174273940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2199437882
Short name T748
Test name
Test status
Simulation time 5899859911 ps
CPU time 20.09 seconds
Started Oct 12 01:03:19 AM UTC 24
Finished Oct 12 01:03:40 AM UTC 24
Peak memory 217908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2199437882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.2199437882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1189417913
Short name T730
Test name
Test status
Simulation time 2620640571 ps
CPU time 2.92 seconds
Started Oct 12 01:03:16 AM UTC 24
Finished Oct 12 01:03:20 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189417913 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.1189417913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.1487452316
Short name T738
Test name
Test status
Simulation time 2097034834 ps
CPU time 1.32 seconds
Started Oct 12 01:03:28 AM UTC 24
Finished Oct 12 01:03:31 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487452316 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.1487452316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3213977046
Short name T774
Test name
Test status
Simulation time 83338719132 ps
CPU time 115.88 seconds
Started Oct 12 01:03:23 AM UTC 24
Finished Oct 12 01:05:21 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213977046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3213977046
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.3977456319
Short name T362
Test name
Test status
Simulation time 79092468213 ps
CPU time 261.62 seconds
Started Oct 12 01:03:25 AM UTC 24
Finished Oct 12 01:07:50 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977456319 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.3977456319
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1995319994
Short name T737
Test name
Test status
Simulation time 3063755044 ps
CPU time 6.11 seconds
Started Oct 12 01:03:23 AM UTC 24
Finished Oct 12 01:03:31 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995319994 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.1995319994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.1231777601
Short name T736
Test name
Test status
Simulation time 4030810173 ps
CPU time 3.16 seconds
Started Oct 12 01:03:25 AM UTC 24
Finished Oct 12 01:03:29 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231777601 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.1231777601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.492513206
Short name T735
Test name
Test status
Simulation time 2623621762 ps
CPU time 3.6 seconds
Started Oct 12 01:03:23 AM UTC 24
Finished Oct 12 01:03:28 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492513206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.492513206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.333598659
Short name T741
Test name
Test status
Simulation time 2452528214 ps
CPU time 10.26 seconds
Started Oct 12 01:03:21 AM UTC 24
Finished Oct 12 01:03:32 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333598659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.333598659
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.4284383632
Short name T739
Test name
Test status
Simulation time 2164867758 ps
CPU time 8.19 seconds
Started Oct 12 01:03:22 AM UTC 24
Finished Oct 12 01:03:31 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284383632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.4284383632
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.3544281857
Short name T196
Test name
Test status
Simulation time 2528298183 ps
CPU time 4.18 seconds
Started Oct 12 01:03:22 AM UTC 24
Finished Oct 12 01:03:27 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544281857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.3544281857
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.2203617552
Short name T190
Test name
Test status
Simulation time 2144365586 ps
CPU time 2.04 seconds
Started Oct 12 01:03:20 AM UTC 24
Finished Oct 12 01:03:23 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203617552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2203617552
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.2467161205
Short name T431
Test name
Test status
Simulation time 803546004066 ps
CPU time 31.75 seconds
Started Oct 12 01:03:27 AM UTC 24
Finished Oct 12 01:04:00 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467161205 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.2467161205
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4279627877
Short name T746
Test name
Test status
Simulation time 2974535617 ps
CPU time 11.27 seconds
Started Oct 12 01:03:26 AM UTC 24
Finished Oct 12 01:03:38 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4279627877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.4279627877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3665682321
Short name T750
Test name
Test status
Simulation time 2065152461 ps
CPU time 2.25 seconds
Started Oct 12 01:03:37 AM UTC 24
Finished Oct 12 01:03:40 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665682321 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.3665682321
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2738448560
Short name T752
Test name
Test status
Simulation time 3288519710 ps
CPU time 12.62 seconds
Started Oct 12 01:03:32 AM UTC 24
Finished Oct 12 01:03:45 AM UTC 24
Peak memory 209200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738448560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.2738448560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.3963725704
Short name T805
Test name
Test status
Simulation time 116430724772 ps
CPU time 484.33 seconds
Started Oct 12 01:03:33 AM UTC 24
Finished Oct 12 01:11:43 AM UTC 24
Peak memory 209788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963725704 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.3963725704
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3343159972
Short name T745
Test name
Test status
Simulation time 3433675016 ps
CPU time 4.93 seconds
Started Oct 12 01:03:32 AM UTC 24
Finished Oct 12 01:03:38 AM UTC 24
Peak memory 209220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343159972 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.3343159972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.3302301432
Short name T218
Test name
Test status
Simulation time 3020702172 ps
CPU time 10.41 seconds
Started Oct 12 01:03:33 AM UTC 24
Finished Oct 12 01:03:44 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302301432 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.3302301432
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1462135870
Short name T742
Test name
Test status
Simulation time 2631287355 ps
CPU time 2.76 seconds
Started Oct 12 01:03:30 AM UTC 24
Finished Oct 12 01:03:34 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462135870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.1462135870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.1341025918
Short name T740
Test name
Test status
Simulation time 2506515908 ps
CPU time 2.66 seconds
Started Oct 12 01:03:28 AM UTC 24
Finished Oct 12 01:03:32 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341025918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1341025918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.1783358159
Short name T749
Test name
Test status
Simulation time 2165027431 ps
CPU time 9.48 seconds
Started Oct 12 01:03:29 AM UTC 24
Finished Oct 12 01:03:40 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783358159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.1783358159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.1370817682
Short name T744
Test name
Test status
Simulation time 2514609036 ps
CPU time 6.23 seconds
Started Oct 12 01:03:29 AM UTC 24
Finished Oct 12 01:03:37 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370817682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.1370817682
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3052995830
Short name T747
Test name
Test status
Simulation time 2110508147 ps
CPU time 9.17 seconds
Started Oct 12 01:03:28 AM UTC 24
Finished Oct 12 01:03:39 AM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052995830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3052995830
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.1733110265
Short name T762
Test name
Test status
Simulation time 8632248650 ps
CPU time 23.21 seconds
Started Oct 12 01:03:37 AM UTC 24
Finished Oct 12 01:04:02 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733110265 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.1733110265
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2346576414
Short name T756
Test name
Test status
Simulation time 4545674001 ps
CPU time 11.94 seconds
Started Oct 12 01:03:37 AM UTC 24
Finished Oct 12 01:03:50 AM UTC 24
Peak memory 217708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2346576414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.2346576414
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1913728310
Short name T743
Test name
Test status
Simulation time 4705515394 ps
CPU time 2.19 seconds
Started Oct 12 01:03:33 AM UTC 24
Finished Oct 12 01:03:36 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913728310 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.1913728310
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.2717614485
Short name T758
Test name
Test status
Simulation time 2044710568 ps
CPU time 3.04 seconds
Started Oct 12 01:03:47 AM UTC 24
Finished Oct 12 01:03:52 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717614485 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.2717614485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1313931785
Short name T760
Test name
Test status
Simulation time 3342286839 ps
CPU time 13.72 seconds
Started Oct 12 01:03:41 AM UTC 24
Finished Oct 12 01:03:56 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313931785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.1313931785
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.717191924
Short name T259
Test name
Test status
Simulation time 109268807832 ps
CPU time 167.47 seconds
Started Oct 12 01:03:45 AM UTC 24
Finished Oct 12 01:06:36 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717191924 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.717191924
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.119244820
Short name T781
Test name
Test status
Simulation time 45980545014 ps
CPU time 131.38 seconds
Started Oct 12 01:03:45 AM UTC 24
Finished Oct 12 01:05:59 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119244820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.119244820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.579879523
Short name T757
Test name
Test status
Simulation time 3666903676 ps
CPU time 9.33 seconds
Started Oct 12 01:03:41 AM UTC 24
Finished Oct 12 01:03:52 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579879523 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.579879523
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2421538804
Short name T219
Test name
Test status
Simulation time 3953976432 ps
CPU time 3.58 seconds
Started Oct 12 01:03:45 AM UTC 24
Finished Oct 12 01:03:50 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421538804 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.2421538804
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.81638670
Short name T755
Test name
Test status
Simulation time 2613196718 ps
CPU time 9.16 seconds
Started Oct 12 01:03:40 AM UTC 24
Finished Oct 12 01:03:50 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81638670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.81638670
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.1986668884
Short name T754
Test name
Test status
Simulation time 2463601373 ps
CPU time 7.05 seconds
Started Oct 12 01:03:38 AM UTC 24
Finished Oct 12 01:03:46 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986668884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.1986668884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.4173254477
Short name T751
Test name
Test status
Simulation time 2229666683 ps
CPU time 3.64 seconds
Started Oct 12 01:03:40 AM UTC 24
Finished Oct 12 01:03:44 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173254477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.4173254477
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.436207238
Short name T759
Test name
Test status
Simulation time 2507961820 ps
CPU time 12.82 seconds
Started Oct 12 01:03:40 AM UTC 24
Finished Oct 12 01:03:54 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436207238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.436207238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.2387211825
Short name T753
Test name
Test status
Simulation time 2109880708 ps
CPU time 6.62 seconds
Started Oct 12 01:03:38 AM UTC 24
Finished Oct 12 01:03:46 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387211825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.2387211825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.3415968702
Short name T415
Test name
Test status
Simulation time 138323098380 ps
CPU time 84.43 seconds
Started Oct 12 01:03:47 AM UTC 24
Finished Oct 12 01:05:14 AM UTC 24
Peak memory 209556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415968702 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.3415968702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3637848103
Short name T761
Test name
Test status
Simulation time 2679352862 ps
CPU time 11.5 seconds
Started Oct 12 01:03:46 AM UTC 24
Finished Oct 12 01:03:59 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3637848103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3637848103
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1435438959
Short name T157
Test name
Test status
Simulation time 1995322645998 ps
CPU time 174.97 seconds
Started Oct 12 01:03:41 AM UTC 24
Finished Oct 12 01:06:39 AM UTC 24
Peak memory 209624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435438959 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.1435438959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.1564730160
Short name T166
Test name
Test status
Simulation time 2010934123 ps
CPU time 6.56 seconds
Started Oct 12 12:56:54 AM UTC 24
Finished Oct 12 12:57:02 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564730160 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.1564730160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.927694852
Short name T557
Test name
Test status
Simulation time 119910847009 ps
CPU time 184.12 seconds
Started Oct 12 12:56:52 AM UTC 24
Finished Oct 12 01:00:00 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927694852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.927694852
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2486007998
Short name T110
Test name
Test status
Simulation time 71831670328 ps
CPU time 140.08 seconds
Started Oct 12 12:56:53 AM UTC 24
Finished Oct 12 12:59:15 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486007998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.2486007998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3638488194
Short name T333
Test name
Test status
Simulation time 2449066216 ps
CPU time 6.38 seconds
Started Oct 12 12:56:51 AM UTC 24
Finished Oct 12 12:56:59 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638488194 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.3638488194
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.1788315546
Short name T51
Test name
Test status
Simulation time 2496213649 ps
CPU time 7.04 seconds
Started Oct 12 12:56:53 AM UTC 24
Finished Oct 12 12:57:01 AM UTC 24
Peak memory 209360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788315546 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.1788315546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1996415217
Short name T167
Test name
Test status
Simulation time 2611603647 ps
CPU time 8.78 seconds
Started Oct 12 12:56:51 AM UTC 24
Finished Oct 12 12:57:02 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996415217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1996415217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3600449021
Short name T90
Test name
Test status
Simulation time 2493686025 ps
CPU time 2.66 seconds
Started Oct 12 12:56:50 AM UTC 24
Finished Oct 12 12:56:55 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600449021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.3600449021
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2980764345
Short name T332
Test name
Test status
Simulation time 2126654183 ps
CPU time 6.43 seconds
Started Oct 12 12:56:50 AM UTC 24
Finished Oct 12 12:56:58 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980764345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.2980764345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.1497517831
Short name T331
Test name
Test status
Simulation time 2516922676 ps
CPU time 4.57 seconds
Started Oct 12 12:56:51 AM UTC 24
Finished Oct 12 12:56:57 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497517831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1497517831
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.3912542696
Short name T330
Test name
Test status
Simulation time 2116839260 ps
CPU time 5.4 seconds
Started Oct 12 12:56:50 AM UTC 24
Finished Oct 12 12:56:57 AM UTC 24
Peak memory 209316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912542696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.3912542696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.1905499642
Short name T46
Test name
Test status
Simulation time 156917757286 ps
CPU time 159.24 seconds
Started Oct 12 12:56:54 AM UTC 24
Finished Oct 12 12:59:36 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905499642 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.1905499642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3218534116
Short name T140
Test name
Test status
Simulation time 21535012413 ps
CPU time 16.21 seconds
Started Oct 12 12:56:54 AM UTC 24
Finished Oct 12 12:57:11 AM UTC 24
Peak memory 221928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3218534116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.3218534116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2544572242
Short name T79
Test name
Test status
Simulation time 4272445034 ps
CPU time 2.51 seconds
Started Oct 12 12:56:52 AM UTC 24
Finished Oct 12 12:56:56 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544572242 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.2544572242
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2905819248
Short name T766
Test name
Test status
Simulation time 26337078700 ps
CPU time 40.85 seconds
Started Oct 12 01:03:51 AM UTC 24
Finished Oct 12 01:04:33 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905819248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_with_pre_cond.2905819248
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.764440686
Short name T383
Test name
Test status
Simulation time 102295744452 ps
CPU time 91.17 seconds
Started Oct 12 01:03:51 AM UTC 24
Finished Oct 12 01:05:24 AM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764440686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.764440686
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2550102634
Short name T395
Test name
Test status
Simulation time 47372414166 ps
CPU time 101.57 seconds
Started Oct 12 01:03:52 AM UTC 24
Finished Oct 12 01:05:35 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550102634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.2550102634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2158568941
Short name T767
Test name
Test status
Simulation time 26092338086 ps
CPU time 40.82 seconds
Started Oct 12 01:03:52 AM UTC 24
Finished Oct 12 01:04:34 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158568941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_with_pre_cond.2158568941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3448988484
Short name T770
Test name
Test status
Simulation time 25839454071 ps
CPU time 55.54 seconds
Started Oct 12 01:03:53 AM UTC 24
Finished Oct 12 01:04:50 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448988484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.3448988484
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3339932847
Short name T764
Test name
Test status
Simulation time 31022327915 ps
CPU time 30.48 seconds
Started Oct 12 01:03:54 AM UTC 24
Finished Oct 12 01:04:26 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339932847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.3339932847
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1461352383
Short name T394
Test name
Test status
Simulation time 67475737352 ps
CPU time 46.93 seconds
Started Oct 12 01:03:57 AM UTC 24
Finished Oct 12 01:04:46 AM UTC 24
Peak memory 209416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461352383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.1461352383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.2746584830
Short name T100
Test name
Test status
Simulation time 2019190553 ps
CPU time 5.41 seconds
Started Oct 12 12:56:59 AM UTC 24
Finished Oct 12 12:57:05 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746584830 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.2746584830
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.669098693
Short name T71
Test name
Test status
Simulation time 3232187575 ps
CPU time 4.67 seconds
Started Oct 12 12:56:56 AM UTC 24
Finished Oct 12 12:57:02 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669098693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.669098693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.3428505207
Short name T263
Test name
Test status
Simulation time 132564205505 ps
CPU time 339.85 seconds
Started Oct 12 12:56:58 AM UTC 24
Finished Oct 12 01:02:42 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428505207 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.3428505207
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2040145511
Short name T165
Test name
Test status
Simulation time 3621177535 ps
CPU time 4.77 seconds
Started Oct 12 12:56:55 AM UTC 24
Finished Oct 12 12:57:01 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040145511 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.2040145511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2720433331
Short name T56
Test name
Test status
Simulation time 2732277567 ps
CPU time 4.54 seconds
Started Oct 12 12:56:58 AM UTC 24
Finished Oct 12 12:57:03 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720433331 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.2720433331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3337168461
Short name T164
Test name
Test status
Simulation time 2634021541 ps
CPU time 4.18 seconds
Started Oct 12 12:56:55 AM UTC 24
Finished Oct 12 12:57:01 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337168461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3337168461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.871552257
Short name T77
Test name
Test status
Simulation time 2483600142 ps
CPU time 8.61 seconds
Started Oct 12 12:56:55 AM UTC 24
Finished Oct 12 12:57:05 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871552257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.871552257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.166783149
Short name T334
Test name
Test status
Simulation time 2144271165 ps
CPU time 3.42 seconds
Started Oct 12 12:56:55 AM UTC 24
Finished Oct 12 12:57:00 AM UTC 24
Peak memory 209312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166783149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.166783149
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.1613013122
Short name T321
Test name
Test status
Simulation time 2534491668 ps
CPU time 3.68 seconds
Started Oct 12 12:56:55 AM UTC 24
Finished Oct 12 12:57:00 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613013122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.1613013122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.288995149
Short name T329
Test name
Test status
Simulation time 2142640314 ps
CPU time 1.78 seconds
Started Oct 12 12:56:54 AM UTC 24
Finished Oct 12 12:56:57 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288995149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.288995149
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.2327183838
Short name T141
Test name
Test status
Simulation time 12176270666 ps
CPU time 30.88 seconds
Started Oct 12 12:56:59 AM UTC 24
Finished Oct 12 12:57:31 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327183838 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.2327183838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2138784105
Short name T106
Test name
Test status
Simulation time 9140112108 ps
CPU time 9.92 seconds
Started Oct 12 12:56:58 AM UTC 24
Finished Oct 12 12:57:09 AM UTC 24
Peak memory 217892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2138784105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.2138784105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.252052943
Short name T428
Test name
Test status
Simulation time 2064776300498 ps
CPU time 336.09 seconds
Started Oct 12 12:56:57 AM UTC 24
Finished Oct 12 01:02:37 AM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252052943 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.252052943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3916434832
Short name T775
Test name
Test status
Simulation time 42928523051 ps
CPU time 78.43 seconds
Started Oct 12 01:04:02 AM UTC 24
Finished Oct 12 01:05:23 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916434832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_with_pre_cond.3916434832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.4234919465
Short name T765
Test name
Test status
Simulation time 38251520207 ps
CPU time 25.19 seconds
Started Oct 12 01:04:06 AM UTC 24
Finished Oct 12 01:04:32 AM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234919465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with_pre_cond.4234919465
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2779149877
Short name T419
Test name
Test status
Simulation time 159682981036 ps
CPU time 499.17 seconds
Started Oct 12 01:04:16 AM UTC 24
Finished Oct 12 01:12:40 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779149877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.2779149877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4052383900
Short name T792
Test name
Test status
Simulation time 66039915030 ps
CPU time 181.94 seconds
Started Oct 12 01:04:18 AM UTC 24
Finished Oct 12 01:07:22 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052383900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_with_pre_cond.4052383900
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1064206215
Short name T796
Test name
Test status
Simulation time 243788781086 ps
CPU time 193.02 seconds
Started Oct 12 01:04:21 AM UTC 24
Finished Oct 12 01:07:37 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064206215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_with_pre_cond.1064206215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1949185193
Short name T393
Test name
Test status
Simulation time 71115555569 ps
CPU time 227.91 seconds
Started Oct 12 01:04:38 AM UTC 24
Finished Oct 12 01:08:29 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949185193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.1949185193
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4109059121
Short name T795
Test name
Test status
Simulation time 57848820887 ps
CPU time 172.15 seconds
Started Oct 12 01:04:38 AM UTC 24
Finished Oct 12 01:07:33 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109059121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.4109059121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.249498238
Short name T388
Test name
Test status
Simulation time 90489146696 ps
CPU time 136.31 seconds
Started Oct 12 01:04:40 AM UTC 24
Finished Oct 12 01:06:59 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249498238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.249498238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.877775011
Short name T437
Test name
Test status
Simulation time 2010259513 ps
CPU time 7.37 seconds
Started Oct 12 12:57:04 AM UTC 24
Finished Oct 12 12:57:12 AM UTC 24
Peak memory 209220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877775011 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.877775011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3157449805
Short name T73
Test name
Test status
Simulation time 12874925934 ps
CPU time 12.46 seconds
Started Oct 12 12:57:01 AM UTC 24
Finished Oct 12 12:57:15 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157449805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.3157449805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.1851574601
Short name T120
Test name
Test status
Simulation time 98647856247 ps
CPU time 279.55 seconds
Started Oct 12 12:57:02 AM UTC 24
Finished Oct 12 01:01:45 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851574601 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.1851574601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1105439624
Short name T34
Test name
Test status
Simulation time 28838568724 ps
CPU time 13.81 seconds
Started Oct 12 12:57:03 AM UTC 24
Finished Oct 12 12:57:19 AM UTC 24
Peak memory 209680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105439624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_with_pre_cond.1105439624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2617623291
Short name T102
Test name
Test status
Simulation time 3577602197 ps
CPU time 5.51 seconds
Started Oct 12 12:57:01 AM UTC 24
Finished Oct 12 12:57:08 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617623291 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.2617623291
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3628067942
Short name T107
Test name
Test status
Simulation time 2608957378 ps
CPU time 7.63 seconds
Started Oct 12 12:57:00 AM UTC 24
Finished Oct 12 12:57:09 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628067942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.3628067942
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.549271877
Short name T436
Test name
Test status
Simulation time 2486867981 ps
CPU time 11.98 seconds
Started Oct 12 12:56:59 AM UTC 24
Finished Oct 12 12:57:12 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549271877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.549271877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2753719675
Short name T104
Test name
Test status
Simulation time 2189797320 ps
CPU time 7.05 seconds
Started Oct 12 12:57:00 AM UTC 24
Finished Oct 12 12:57:08 AM UTC 24
Peak memory 209448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753719675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.2753719675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.3655797618
Short name T168
Test name
Test status
Simulation time 2541457776 ps
CPU time 2.13 seconds
Started Oct 12 12:57:00 AM UTC 24
Finished Oct 12 12:57:03 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655797618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.3655797618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.4120442004
Short name T101
Test name
Test status
Simulation time 2111036845 ps
CPU time 7.41 seconds
Started Oct 12 12:56:59 AM UTC 24
Finished Oct 12 12:57:08 AM UTC 24
Peak memory 209244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120442004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.4120442004
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2292827044
Short name T313
Test name
Test status
Simulation time 5588109810 ps
CPU time 11.89 seconds
Started Oct 12 12:57:03 AM UTC 24
Finished Oct 12 12:57:17 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2292827044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.2292827044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.902706693
Short name T80
Test name
Test status
Simulation time 8983845290 ps
CPU time 8.82 seconds
Started Oct 12 12:57:02 AM UTC 24
Finished Oct 12 12:57:12 AM UTC 24
Peak memory 209368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902706693 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.902706693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2727443762
Short name T779
Test name
Test status
Simulation time 36041942421 ps
CPU time 65.38 seconds
Started Oct 12 01:04:40 AM UTC 24
Finished Oct 12 01:05:47 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727443762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_with_pre_cond.2727443762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.486251140
Short name T797
Test name
Test status
Simulation time 54160285611 ps
CPU time 181.67 seconds
Started Oct 12 01:04:40 AM UTC 24
Finished Oct 12 01:07:44 AM UTC 24
Peak memory 209544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486251140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_with_pre_cond.486251140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2173231316
Short name T772
Test name
Test status
Simulation time 36811362870 ps
CPU time 33.07 seconds
Started Oct 12 01:04:40 AM UTC 24
Finished Oct 12 01:05:14 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173231316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_with_pre_cond.2173231316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.832209983
Short name T790
Test name
Test status
Simulation time 48203273610 ps
CPU time 139.43 seconds
Started Oct 12 01:04:40 AM UTC 24
Finished Oct 12 01:07:02 AM UTC 24
Peak memory 209416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832209983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_with_pre_cond.832209983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.697420576
Short name T802
Test name
Test status
Simulation time 77819777418 ps
CPU time 213.55 seconds
Started Oct 12 01:04:40 AM UTC 24
Finished Oct 12 01:08:17 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697420576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.697420576
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1022820939
Short name T804
Test name
Test status
Simulation time 119197327180 ps
CPU time 276.31 seconds
Started Oct 12 01:04:41 AM UTC 24
Finished Oct 12 01:09:21 AM UTC 24
Peak memory 209680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022820939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_with_pre_cond.1022820939
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1184777938
Short name T773
Test name
Test status
Simulation time 25589501408 ps
CPU time 34.27 seconds
Started Oct 12 01:04:41 AM UTC 24
Finished Oct 12 01:05:17 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184777938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.1184777938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3599060105
Short name T776
Test name
Test status
Simulation time 38770415194 ps
CPU time 35.94 seconds
Started Oct 12 01:04:46 AM UTC 24
Finished Oct 12 01:05:24 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599060105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.3599060105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2009568321
Short name T390
Test name
Test status
Simulation time 198489214924 ps
CPU time 266.08 seconds
Started Oct 12 01:04:48 AM UTC 24
Finished Oct 12 01:09:17 AM UTC 24
Peak memory 209548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009568321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_with_pre_cond.2009568321
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2730022121
Short name T798
Test name
Test status
Simulation time 51731971822 ps
CPU time 178.7 seconds
Started Oct 12 01:04:48 AM UTC 24
Finished Oct 12 01:07:49 AM UTC 24
Peak memory 209508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730022121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.2730022121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2502543
Short name T438
Test name
Test status
Simulation time 2015210116 ps
CPU time 3.07 seconds
Started Oct 12 12:57:10 AM UTC 24
Finished Oct 12 12:57:14 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502543 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.2502543
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.938628466
Short name T74
Test name
Test status
Simulation time 3234473527 ps
CPU time 9.65 seconds
Started Oct 12 12:57:08 AM UTC 24
Finished Oct 12 12:57:19 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938628466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.938628466
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1558833624
Short name T43
Test name
Test status
Simulation time 128216010046 ps
CPU time 83.69 seconds
Started Oct 12 12:57:10 AM UTC 24
Finished Oct 12 12:58:36 AM UTC 24
Peak memory 209468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558833624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.1558833624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2966363233
Short name T435
Test name
Test status
Simulation time 4389090510 ps
CPU time 4.21 seconds
Started Oct 12 12:57:06 AM UTC 24
Finished Oct 12 12:57:12 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966363233 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.2966363233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.988048774
Short name T53
Test name
Test status
Simulation time 3862048506 ps
CPU time 9.02 seconds
Started Oct 12 12:57:10 AM UTC 24
Finished Oct 12 12:57:20 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988048774 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.988048774
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1000458349
Short name T434
Test name
Test status
Simulation time 2632475462 ps
CPU time 2.62 seconds
Started Oct 12 12:57:06 AM UTC 24
Finished Oct 12 12:57:10 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000458349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1000458349
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.61070328
Short name T92
Test name
Test status
Simulation time 2464325974 ps
CPU time 3.51 seconds
Started Oct 12 12:57:05 AM UTC 24
Finished Oct 12 12:57:10 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61070328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.61070328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.861829878
Short name T103
Test name
Test status
Simulation time 2213596086 ps
CPU time 1.94 seconds
Started Oct 12 12:57:05 AM UTC 24
Finished Oct 12 12:57:08 AM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861829878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.861829878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.799725369
Short name T105
Test name
Test status
Simulation time 2118190411 ps
CPU time 3.6 seconds
Started Oct 12 12:57:04 AM UTC 24
Finished Oct 12 12:57:09 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799725369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.799725369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.2569305026
Short name T258
Test name
Test status
Simulation time 187776318812 ps
CPU time 521.77 seconds
Started Oct 12 12:57:10 AM UTC 24
Finished Oct 12 01:05:58 AM UTC 24
Peak memory 209548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569305026 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.2569305026
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4180185991
Short name T142
Test name
Test status
Simulation time 24725473333 ps
CPU time 24.15 seconds
Started Oct 12 12:57:10 AM UTC 24
Finished Oct 12 12:57:36 AM UTC 24
Peak memory 217896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4180185991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.4180185991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.4283151714
Short name T789
Test name
Test status
Simulation time 34385747616 ps
CPU time 115.69 seconds
Started Oct 12 01:04:49 AM UTC 24
Finished Oct 12 01:06:47 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283151714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.4283151714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2507705720
Short name T806
Test name
Test status
Simulation time 128713959871 ps
CPU time 482.86 seconds
Started Oct 12 01:04:51 AM UTC 24
Finished Oct 12 01:12:59 AM UTC 24
Peak memory 209620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507705720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_with_pre_cond.2507705720
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3502602243
Short name T375
Test name
Test status
Simulation time 77776742561 ps
CPU time 30.41 seconds
Started Oct 12 01:04:53 AM UTC 24
Finished Oct 12 01:05:25 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502602243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_with_pre_cond.3502602243
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2027828042
Short name T778
Test name
Test status
Simulation time 22097050718 ps
CPU time 26.88 seconds
Started Oct 12 01:04:58 AM UTC 24
Finished Oct 12 01:05:26 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027828042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_with_pre_cond.2027828042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.220576836
Short name T391
Test name
Test status
Simulation time 86704158349 ps
CPU time 171.65 seconds
Started Oct 12 01:05:09 AM UTC 24
Finished Oct 12 01:08:03 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220576836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_with_pre_cond.220576836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.40246046
Short name T780
Test name
Test status
Simulation time 49361277721 ps
CPU time 35.54 seconds
Started Oct 12 01:05:14 AM UTC 24
Finished Oct 12 01:05:51 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40246046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.40246046
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1571857625
Short name T784
Test name
Test status
Simulation time 51250392718 ps
CPU time 47.32 seconds
Started Oct 12 01:05:14 AM UTC 24
Finished Oct 12 01:06:03 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571857625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_with_pre_cond.1571857625
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.489336199
Short name T386
Test name
Test status
Simulation time 67995512896 ps
CPU time 14.38 seconds
Started Oct 12 01:05:15 AM UTC 24
Finished Oct 12 01:05:31 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489336199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.489336199
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1061688149
Short name T801
Test name
Test status
Simulation time 62404032189 ps
CPU time 174.02 seconds
Started Oct 12 01:05:16 AM UTC 24
Finished Oct 12 01:08:12 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061688149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.1061688149
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.3156415813
Short name T176
Test name
Test status
Simulation time 2023276796 ps
CPU time 4.33 seconds
Started Oct 12 12:57:15 AM UTC 24
Finished Oct 12 12:57:20 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156415813 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.3156415813
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1909268649
Short name T128
Test name
Test status
Simulation time 3303071916 ps
CPU time 12.15 seconds
Started Oct 12 12:57:13 AM UTC 24
Finished Oct 12 12:57:26 AM UTC 24
Peak memory 209444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909268649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.1909268649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2654774526
Short name T245
Test name
Test status
Simulation time 56049574127 ps
CPU time 154.07 seconds
Started Oct 12 12:57:13 AM UTC 24
Finished Oct 12 12:59:50 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654774526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.2654774526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.88935706
Short name T441
Test name
Test status
Simulation time 2842300300 ps
CPU time 2.81 seconds
Started Oct 12 12:57:13 AM UTC 24
Finished Oct 12 12:57:17 AM UTC 24
Peak memory 209300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88935706 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.88935706
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.2464547917
Short name T55
Test name
Test status
Simulation time 2390580066 ps
CPU time 3.9 seconds
Started Oct 12 12:57:13 AM UTC 24
Finished Oct 12 12:57:18 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464547917 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.2464547917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.122383314
Short name T181
Test name
Test status
Simulation time 2617900900 ps
CPU time 4.7 seconds
Started Oct 12 12:57:13 AM UTC 24
Finished Oct 12 12:57:19 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122383314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.122383314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.3049020925
Short name T320
Test name
Test status
Simulation time 2527904496 ps
CPU time 2.24 seconds
Started Oct 12 12:57:11 AM UTC 24
Finished Oct 12 12:57:15 AM UTC 24
Peak memory 209372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049020925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3049020925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.833343297
Short name T442
Test name
Test status
Simulation time 2249597228 ps
CPU time 4.74 seconds
Started Oct 12 12:57:11 AM UTC 24
Finished Oct 12 12:57:17 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833343297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.833343297
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.761712524
Short name T432
Test name
Test status
Simulation time 2593709023 ps
CPU time 1.57 seconds
Started Oct 12 12:57:11 AM UTC 24
Finished Oct 12 12:57:14 AM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761712524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.761712524
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.3714160251
Short name T440
Test name
Test status
Simulation time 2136716507 ps
CPU time 3.55 seconds
Started Oct 12 12:57:11 AM UTC 24
Finished Oct 12 12:57:16 AM UTC 24
Peak memory 209508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714160251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3714160251
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1264570370
Short name T458
Test name
Test status
Simulation time 7901652071 ps
CPU time 32.86 seconds
Started Oct 12 12:57:15 AM UTC 24
Finished Oct 12 12:57:49 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264570370 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.1264570370
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1430894478
Short name T131
Test name
Test status
Simulation time 3361776131 ps
CPU time 11.75 seconds
Started Oct 12 12:57:15 AM UTC 24
Finished Oct 12 12:57:28 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1430894478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1430894478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.649430043
Short name T87
Test name
Test status
Simulation time 3573630539 ps
CPU time 3.52 seconds
Started Oct 12 12:57:13 AM UTC 24
Finished Oct 12 12:57:18 AM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649430043 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.649430043
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.61674844
Short name T785
Test name
Test status
Simulation time 55204163570 ps
CPU time 42.3 seconds
Started Oct 12 01:05:22 AM UTC 24
Finished Oct 12 01:06:06 AM UTC 24
Peak memory 209616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61674844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.61674844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3046129004
Short name T387
Test name
Test status
Simulation time 65139594635 ps
CPU time 51.77 seconds
Started Oct 12 01:05:24 AM UTC 24
Finished Oct 12 01:06:17 AM UTC 24
Peak memory 209548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046129004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.3046129004
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3221003017
Short name T782
Test name
Test status
Simulation time 36912194860 ps
CPU time 33.79 seconds
Started Oct 12 01:05:25 AM UTC 24
Finished Oct 12 01:06:01 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221003017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_with_pre_cond.3221003017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.518117293
Short name T771
Test name
Test status
Simulation time 24835356137 ps
CPU time 42.36 seconds
Started Oct 12 01:05:25 AM UTC 24
Finished Oct 12 01:06:09 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518117293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_with_pre_cond.518117293
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1530908916
Short name T786
Test name
Test status
Simulation time 39416985210 ps
CPU time 44.71 seconds
Started Oct 12 01:05:25 AM UTC 24
Finished Oct 12 01:06:12 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530908916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.1530908916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.538400312
Short name T788
Test name
Test status
Simulation time 23333899646 ps
CPU time 78.02 seconds
Started Oct 12 01:05:25 AM UTC 24
Finished Oct 12 01:06:45 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538400312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.538400312
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3945743708
Short name T787
Test name
Test status
Simulation time 35551540338 ps
CPU time 71.17 seconds
Started Oct 12 01:05:27 AM UTC 24
Finished Oct 12 01:06:40 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945743708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.3945743708
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.4262075080
Short name T793
Test name
Test status
Simulation time 37726429081 ps
CPU time 110.43 seconds
Started Oct 12 01:05:31 AM UTC 24
Finished Oct 12 01:07:24 AM UTC 24
Peak memory 209468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262075080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_with_pre_cond.4262075080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1759801033
Short name T800
Test name
Test status
Simulation time 78278142781 ps
CPU time 140.31 seconds
Started Oct 12 01:05:37 AM UTC 24
Finished Oct 12 01:07:59 AM UTC 24
Peak memory 209488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759801033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_with_pre_cond.1759801033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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