UART Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	24.440s	6.284ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.650s	37.992us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	23.686us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.500s	332.715us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.660s	158.565us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.190s	30.873us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	23.686us	20	20	100.00
		uart_csr_aliasing	0.660s	158.565us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.975m	260.251ms	50	50	100.00
V2	parity	uart_smoke	24.440s	6.284ms	50	50	100.00
		uart_tx_rx	5.975m	260.251ms	50	50	100.00
V2	parity_error	uart_intr	38.687m	1.751s	48	50	96.00
		uart_rx_parity_err	18.679m	381.570ms	50	50	100.00
V2	watermark	uart_tx_rx	5.975m	260.251ms	50	50	100.00
		uart_intr	38.687m	1.751s	48	50	96.00
V2	fifo_full	uart_fifo_full	10.492m	209.685ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.302m	273.590ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	5.728m	114.627ms	299	300	99.67
V2	rx_frame_err	uart_intr	38.687m	1.751s	48	50	96.00
V2	rx_break_err	uart_intr	38.687m	1.751s	48	50	96.00
V2	rx_timeout	uart_intr	38.687m	1.751s	48	50	96.00
V2	perf	uart_perf	23.451m	26.909ms	50	50	100.00
V2	sys_loopback	uart_loopback	18.640s	8.080ms	50	50	100.00
V2	line_loopback	uart_loopback	18.640s	8.080ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.591m	205.453ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.068m	43.354ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	26.450s	6.615ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	45.940s	5.236ms	41	50	82.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	15.493m	159.845ms	50	50	100.00
V2	stress_all	uart_stress_all	38.340m	276.695ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	37.634m	409.977ms	100	100	100.00
V2	alert_test	uart_alert_test	0.650s	18.439us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	14.339us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.590s	118.478us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.590s	118.478us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.650s	37.992us	5	5	100.00
		uart_csr_rw	0.660s	23.686us	20	20	100.00
		uart_csr_aliasing	0.660s	158.565us	5	5	100.00
		uart_same_csr_outstanding	0.800s	32.240us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.650s	37.992us	5	5	100.00
		uart_csr_rw	0.660s	23.686us	20	20	100.00
		uart_csr_aliasing	0.660s	158.565us	5	5	100.00
		uart_same_csr_outstanding	0.800s	32.240us	20	20	100.00
V2		TOTAL			1178	1190	98.99
V2S	tl_intg_err	uart_sec_cm	0.830s	69.798us	5	5	100.00
		uart_tl_intg_err	1.340s	308.023us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.340s	308.023us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1308	1320	99.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	16	84.21
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.29	99.80	98.45	100.00	--	99.76	100.00	97.72

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 9 failures:

Test uart_rx_oversample has 9 failures.

15.uart_rx_oversample.2799815707
Line 217, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 346009297 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (61824 [0xf180] vs 61696 [0xf100]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 363776174 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/9
  UVM_INFO @ 390351614 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/9
  UVM_INFO @ 408776534 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/9
  UVM_INFO @ 834756177 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/9

17.uart_rx_oversample.1648096927
Line 215, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_rx_oversample/latest/run.log

  UVM_ERROR @  16507048 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (48086 [0xbbd6] vs 30637 [0x77ad]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  33726157 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 1/5
  UVM_INFO @ 345637336 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/5
  UVM_ERROR @ 364708789 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (55712 [0xd9a0] vs 45888 [0xb340]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 381927898 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/5

... and 7 more failures.

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_intr has 1 failures.

21.uart_intr.3510723411
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_intr/latest/run.log

  UVM_ERROR @ 383204338471 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 383204338471 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 6c
  UVM_ERROR @ 383360838471 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 383360838471 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 6c
  UVM_ERROR @ 383517463471 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_intr has 1 failures.
  - 37.uart_intr.3939963740
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_intr/latest/run.log
```
  Job ID: smart:dd5e404b-58df-4a08-824c-48993ba2ed0a
```

UVM_ERROR (uart_scoreboard.sv:420) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

Test uart_fifo_reset has 1 failures.

96.uart_fifo_reset.2643987918
Line 215, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/96.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1157521 ps: (uart_scoreboard.sv:420) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
  UVM_INFO @ 632427721 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/10
  UVM_INFO @ 2612157737 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/10
  UVM_INFO @ 4280200696 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/10
  UVM_INFO @ 6936921125 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/10