Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	347	1			T2	5		T3	1		T7	1
all_values[1]	347	1			T2	5		T3	1		T7	1
all_values[2]	347	1			T2	5		T3	1		T7	1
all_values[3]	347	1			T2	5		T3	1		T7	1
all_values[4]	347	1			T2	5		T3	1		T7	1
all_values[5]	347	1			T2	5		T3	1		T7	1
all_values[6]	347	1			T2	5		T3	1		T7	1
all_values[7]	347	1			T2	5		T3	1		T7	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1447

1

T2

26

T3

8

T7

8

auto[1]

1329

1

T2

14

T9

25

T12

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1731

1

T2

27

T3

8

T7

8

auto[1]

1045

1

T2

13

T9

9

T12

16

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	124	1			T2	2		T3	1		T7	1
all_values[0]	auto[0]	auto[1]	69	1			T10	5		T71	2		T72	2
all_values[0]	auto[1]	auto[0]	97	1			T2	3		T12	1		T10	1
all_values[0]	auto[1]	auto[1]	57	1			T9	1		T11	2		T13	2
all_values[1]	auto[0]	auto[0]	97	1			T3	1		T7	1		T16	1
all_values[1]	auto[0]	auto[1]	63	1			T12	1		T10	2		T73	1
all_values[1]	auto[1]	auto[0]	117	1			T2	1		T9	3		T12	2
all_values[1]	auto[1]	auto[1]	70	1			T2	4		T12	2		T10	1
all_values[2]	auto[0]	auto[0]	113	1			T2	4		T3	1		T7	1
all_values[2]	auto[0]	auto[1]	55	1			T2	1		T9	1		T10	2
all_values[2]	auto[1]	auto[0]	104	1			T9	4		T12	4		T10	3
all_values[2]	auto[1]	auto[1]	75	1			T12	1		T11	1		T13	1
all_values[3]	auto[0]	auto[0]	128	1			T2	1		T3	1		T7	1
all_values[3]	auto[0]	auto[1]	67	1			T2	2		T12	2		T10	5
all_values[3]	auto[1]	auto[0]	90	1			T2	2		T9	3		T12	2
all_values[3]	auto[1]	auto[1]	62	1			T10	1		T73	3		T13	2
all_values[4]	auto[0]	auto[0]	129	1			T2	4		T3	1		T7	1
all_values[4]	auto[0]	auto[1]	64	1			T12	1		T10	3		T73	2
all_values[4]	auto[1]	auto[0]	98	1			T9	3		T10	1		T11	3
all_values[4]	auto[1]	auto[1]	56	1			T2	1		T12	1		T71	3
all_values[5]	auto[0]	auto[0]	116	1			T2	2		T3	1		T7	1
all_values[5]	auto[0]	auto[1]	70	1			T2	2		T12	2		T10	4
all_values[5]	auto[1]	auto[0]	99	1			T2	1		T9	1		T10	1
all_values[5]	auto[1]	auto[1]	62	1			T9	2		T12	2		T10	2
all_values[6]	auto[0]	auto[0]	115	1			T2	4		T3	1		T7	1
all_values[6]	auto[0]	auto[1]	75	1			T9	1		T12	2		T73	1
all_values[6]	auto[1]	auto[0]	90	1			T2	1		T9	4		T12	1
all_values[6]	auto[1]	auto[1]	67	1			T10	2		T13	1		T71	3
all_values[7]	auto[0]	auto[0]	105	1			T2	2		T3	1		T7	1
all_values[7]	auto[0]	auto[1]	57	1			T2	2		T9	1		T12	1
all_values[7]	auto[1]	auto[0]	109	1			T9	1		T11	1		T13	4
all_values[7]	auto[1]	auto[1]	76	1			T2	1		T9	3		T12	1