Total Groups Coverage Summary 

COVERED	EXPECTED	SCORE	COVERED	EXPECTED	INST SCORE	WEIGHT
348	4763	7.31	348	4763	7.31	1

Total groups in report: 21

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NAME	COVERED	EXPECTED	SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING	COMMENT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg	0	2	0.00	0.00	1	100	1	1	64	64
uart_agent_pkg::uart_agent_cov::uart_cg	0	3661	0.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg	0	46	0.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::fifo_level_cg	0	649	0.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::noise_filter_cg	0	8	0.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::rx_watermark_cg	1	8	12.50		1	100	1	0	64	64
uart_agent_pkg::uart_agent_cov::uart_reset_cg	5	35	14.29		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::tx_watermark_cg	1	7	14.29		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::rx_break_err_cg	1	4	25.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::rx_timeout_cg	1	3	33.33		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::rx_parity_err_cg	1	2	50.00		1	100	1	0	64	64
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg	12	15	80.00	100.00	1	100	1	1	64	64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg	13	14	92.86	100.00	1	100	1	1	64	64
alert_esc_agent_pkg::alert_handshake_complete_cg	3	3	100.00	100.00	1	100	1	1	64	64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}	44	44	100.00		1	100	1	0	64	64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}	44	44	100.00		1	100	1	0	64	64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}	62	62	100.00		1	100	1	0	64	64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg	4	4	100.00	100.00	1	100	1	1	64	64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1}	1	1	100.00	100.00	1	100	1	1	64	64
tl_agent_pkg::pending_req_on_rst_cg	2	2	100.00	100.00	1	100	1	1	64	64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}	137	137	100.00	100.00	1	100	1	1	64	64