Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
65.84 64.36 63.61 96.20 63.57 100.00 7.31


Total tests in report: 165
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.56 60.56 61.47 61.47 52.56 52.56 93.19 93.19 58.81 58.81 95.05 95.05 2.29 2.29 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3490240483
63.60 3.04 64.05 2.58 59.57 7.02 95.55 2.36 62.62 3.81 95.38 0.33 4.43 2.14 /workspace/coverage/cover_reg_top/49.uart_intr_test.3399462175
64.96 1.36 64.26 0.21 62.19 2.62 98.95 3.40 62.86 0.24 95.71 0.33 5.82 1.39 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1489014887
65.57 0.61 64.26 0.00 62.19 0.00 98.95 0.00 62.86 0.00 99.34 3.63 5.84 0.02 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2969859500
65.87 0.30 64.36 0.10 62.78 0.59 98.95 0.00 63.57 0.71 99.67 0.33 5.90 0.06 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.627102235
66.11 0.23 64.36 0.00 62.78 0.00 99.48 0.52 63.57 0.00 99.67 0.00 6.78 0.88 /workspace/coverage/cover_reg_top/6.uart_intr_test.2218981139
66.21 0.10 64.36 0.00 63.14 0.36 99.48 0.00 63.57 0.00 99.67 0.00 7.05 0.27 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3020148042
66.28 0.07 64.36 0.00 63.50 0.36 99.48 0.00 63.57 0.00 99.67 0.00 7.10 0.04 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1013523387
66.33 0.06 64.36 0.00 63.50 0.00 99.48 0.00 63.57 0.00 100.00 0.33 7.10 0.00 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.195565716
66.35 0.02 64.36 0.00 63.50 0.00 99.48 0.00 63.57 0.00 100.00 0.00 7.22 0.13 /workspace/coverage/cover_reg_top/9.uart_intr_test.1281052828
66.37 0.02 64.36 0.00 63.61 0.12 99.48 0.00 63.57 0.00 100.00 0.00 7.22 0.00 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3918963061
66.38 0.01 64.36 0.00 63.61 0.00 99.48 0.00 63.57 0.00 100.00 0.00 7.26 0.04 /workspace/coverage/cover_reg_top/1.uart_intr_test.1737183112
66.38 0.01 64.36 0.00 63.61 0.00 99.48 0.00 63.57 0.00 100.00 0.00 7.29 0.02 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1033777858
66.39 0.01 64.36 0.00 63.61 0.00 99.48 0.00 63.57 0.00 100.00 0.00 7.31 0.02 /workspace/coverage/cover_reg_top/30.uart_intr_test.333399808

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1941193108
/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2904053619
/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3278768076
/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3664335354
/workspace/coverage/cover_reg_top/0.uart_csr_rw.2838884920
/workspace/coverage/cover_reg_top/0.uart_intr_test.2678606589
/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1371735336
/workspace/coverage/cover_reg_top/0.uart_tl_errors.540121751
/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.732716461
/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2465259952
/workspace/coverage/cover_reg_top/1.uart_csr_rw.2733736376
/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3696232747
/workspace/coverage/cover_reg_top/1.uart_tl_errors.2712615284
/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2595264356
/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1447149064
/workspace/coverage/cover_reg_top/10.uart_csr_rw.591729226
/workspace/coverage/cover_reg_top/10.uart_intr_test.1188197306
/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1297548533
/workspace/coverage/cover_reg_top/10.uart_tl_errors.3079199385
/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.36885655
/workspace/coverage/cover_reg_top/11.uart_intr_test.262353977
/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.448468302
/workspace/coverage/cover_reg_top/11.uart_tl_errors.3052842823
/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2168709537
/workspace/coverage/cover_reg_top/12.uart_csr_rw.1174200551
/workspace/coverage/cover_reg_top/12.uart_intr_test.961086622
/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4139308746
/workspace/coverage/cover_reg_top/12.uart_tl_errors.1442338306
/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2170097114
/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1971669213
/workspace/coverage/cover_reg_top/13.uart_csr_rw.2464585657
/workspace/coverage/cover_reg_top/13.uart_intr_test.564268825
/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3179344067
/workspace/coverage/cover_reg_top/13.uart_tl_errors.4286420057
/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2751878869
/workspace/coverage/cover_reg_top/14.uart_csr_rw.1855572873
/workspace/coverage/cover_reg_top/14.uart_intr_test.1319536936
/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3044345982
/workspace/coverage/cover_reg_top/14.uart_tl_errors.189764245
/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3073500058
/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1527972108
/workspace/coverage/cover_reg_top/15.uart_csr_rw.104670068
/workspace/coverage/cover_reg_top/15.uart_intr_test.722691657
/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2805859905
/workspace/coverage/cover_reg_top/15.uart_tl_errors.4119275100
/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1112502705
/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.836488306
/workspace/coverage/cover_reg_top/16.uart_csr_rw.1441400475
/workspace/coverage/cover_reg_top/16.uart_intr_test.4289769874
/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3968501567
/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2437300949
/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.272366715
/workspace/coverage/cover_reg_top/17.uart_csr_rw.4040519759
/workspace/coverage/cover_reg_top/17.uart_intr_test.3178551481
/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.863071728
/workspace/coverage/cover_reg_top/17.uart_tl_errors.3266965440
/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3675004913
/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.792366243
/workspace/coverage/cover_reg_top/18.uart_csr_rw.912707464
/workspace/coverage/cover_reg_top/18.uart_intr_test.657823327
/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.4175350318
/workspace/coverage/cover_reg_top/18.uart_tl_errors.232108033
/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1665855723
/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3204058998
/workspace/coverage/cover_reg_top/19.uart_csr_rw.2754943856
/workspace/coverage/cover_reg_top/19.uart_intr_test.1408333286
/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2136094971
/workspace/coverage/cover_reg_top/19.uart_tl_errors.435567707
/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3212961238
/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3962494824
/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.310752146
/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4003713934
/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1973691312
/workspace/coverage/cover_reg_top/2.uart_csr_rw.3291640049
/workspace/coverage/cover_reg_top/2.uart_intr_test.861200634
/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3372388725
/workspace/coverage/cover_reg_top/2.uart_tl_errors.763568339
/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2638167747
/workspace/coverage/cover_reg_top/20.uart_intr_test.3808540763
/workspace/coverage/cover_reg_top/21.uart_intr_test.834976644
/workspace/coverage/cover_reg_top/22.uart_intr_test.2016437923
/workspace/coverage/cover_reg_top/23.uart_intr_test.2513484767
/workspace/coverage/cover_reg_top/24.uart_intr_test.2666116537
/workspace/coverage/cover_reg_top/25.uart_intr_test.3980704822
/workspace/coverage/cover_reg_top/26.uart_intr_test.1422804707
/workspace/coverage/cover_reg_top/27.uart_intr_test.4241263500
/workspace/coverage/cover_reg_top/28.uart_intr_test.103413828
/workspace/coverage/cover_reg_top/29.uart_intr_test.347087435
/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2442875316
/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4100465749
/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2265738255
/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.102818435
/workspace/coverage/cover_reg_top/3.uart_csr_rw.2813868049
/workspace/coverage/cover_reg_top/3.uart_intr_test.1243861780
/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2014385469
/workspace/coverage/cover_reg_top/3.uart_tl_errors.1494701223
/workspace/coverage/cover_reg_top/31.uart_intr_test.2498326332
/workspace/coverage/cover_reg_top/32.uart_intr_test.566158617
/workspace/coverage/cover_reg_top/33.uart_intr_test.567026168
/workspace/coverage/cover_reg_top/34.uart_intr_test.3731238398
/workspace/coverage/cover_reg_top/35.uart_intr_test.2827635163
/workspace/coverage/cover_reg_top/36.uart_intr_test.1375631577
/workspace/coverage/cover_reg_top/37.uart_intr_test.1842216771
/workspace/coverage/cover_reg_top/38.uart_intr_test.2362548815
/workspace/coverage/cover_reg_top/39.uart_intr_test.3647451505
/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4051128593
/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1013564340
/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1612694591
/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.506346604
/workspace/coverage/cover_reg_top/4.uart_csr_rw.523206574
/workspace/coverage/cover_reg_top/4.uart_intr_test.3068345150
/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2210451671
/workspace/coverage/cover_reg_top/4.uart_tl_errors.2188835264
/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1855608744
/workspace/coverage/cover_reg_top/40.uart_intr_test.652509137
/workspace/coverage/cover_reg_top/41.uart_intr_test.1435800236
/workspace/coverage/cover_reg_top/42.uart_intr_test.3958209252
/workspace/coverage/cover_reg_top/43.uart_intr_test.2544068275
/workspace/coverage/cover_reg_top/44.uart_intr_test.2575704187
/workspace/coverage/cover_reg_top/45.uart_intr_test.541115989
/workspace/coverage/cover_reg_top/46.uart_intr_test.2477018839
/workspace/coverage/cover_reg_top/47.uart_intr_test.3927016630
/workspace/coverage/cover_reg_top/48.uart_intr_test.3643958671
/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1974421480
/workspace/coverage/cover_reg_top/5.uart_csr_rw.3960417796
/workspace/coverage/cover_reg_top/5.uart_intr_test.1387866259
/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1683459643
/workspace/coverage/cover_reg_top/5.uart_tl_errors.3293503743
/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.252605627
/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1937844863
/workspace/coverage/cover_reg_top/6.uart_csr_rw.3179905662
/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1880307719
/workspace/coverage/cover_reg_top/6.uart_tl_errors.2212678331
/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3911711985
/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1266870311
/workspace/coverage/cover_reg_top/7.uart_csr_rw.1257276127
/workspace/coverage/cover_reg_top/7.uart_intr_test.2043715439
/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1209121390
/workspace/coverage/cover_reg_top/7.uart_tl_errors.2171855190
/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1335662361
/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.443493467
/workspace/coverage/cover_reg_top/8.uart_csr_rw.1545024794
/workspace/coverage/cover_reg_top/8.uart_intr_test.3779126251
/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1784722783
/workspace/coverage/cover_reg_top/8.uart_tl_errors.2942275737
/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.379538233
/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1691177412
/workspace/coverage/cover_reg_top/9.uart_csr_rw.3409229523
/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1316509924
/workspace/coverage/cover_reg_top/9.uart_tl_errors.2040119894
/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2204603884



Total test records in report: 165
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1297548533 Dec 20 12:24:32 PM PST 23 Dec 20 12:25:03 PM PST 23 79959848 ps
T2 /workspace/coverage/cover_reg_top/27.uart_intr_test.4241263500 Dec 20 12:25:17 PM PST 23 Dec 20 12:25:38 PM PST 23 14428536 ps
T3 /workspace/coverage/cover_reg_top/14.uart_tl_errors.189764245 Dec 20 12:25:34 PM PST 23 Dec 20 12:26:04 PM PST 23 61474184 ps
T7 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1489014887 Dec 20 12:24:46 PM PST 23 Dec 20 12:25:19 PM PST 23 100230396 ps
T4 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.252605627 Dec 20 12:24:18 PM PST 23 Dec 20 12:24:54 PM PST 23 137989662 ps
T5 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1971669213 Dec 20 12:25:21 PM PST 23 Dec 20 12:25:46 PM PST 23 25753076 ps
T6 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.627102235 Dec 20 12:26:04 PM PST 23 Dec 20 12:26:32 PM PST 23 13506617 ps
T16 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2040119894 Dec 20 12:25:36 PM PST 23 Dec 20 12:26:07 PM PST 23 416410576 ps
T8 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3490240483 Dec 20 12:24:57 PM PST 23 Dec 20 12:25:23 PM PST 23 82963491 ps
T17 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3266965440 Dec 20 12:24:28 PM PST 23 Dec 20 12:25:01 PM PST 23 26522091 ps
T21 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1527972108 Dec 20 12:25:21 PM PST 23 Dec 20 12:25:45 PM PST 23 55115150 ps
T14 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2904053619 Dec 20 12:26:37 PM PST 23 Dec 20 12:27:12 PM PST 23 640358012 ps
T24 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2838884920 Dec 20 12:24:49 PM PST 23 Dec 20 12:25:19 PM PST 23 20022125 ps
T31 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.792366243 Dec 20 12:24:35 PM PST 23 Dec 20 12:25:09 PM PST 23 54195095 ps
T32 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2813868049 Dec 20 12:24:26 PM PST 23 Dec 20 12:24:59 PM PST 23 128546707 ps
T33 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3204058998 Dec 20 12:25:38 PM PST 23 Dec 20 12:26:08 PM PST 23 17815594 ps
T25 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1371735336 Dec 20 12:25:15 PM PST 23 Dec 20 12:25:35 PM PST 23 27552296 ps
T15 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4100465749 Dec 20 12:25:30 PM PST 23 Dec 20 12:25:59 PM PST 23 63694266 ps
T18 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.443493467 Dec 20 12:25:07 PM PST 23 Dec 20 12:25:28 PM PST 23 42465774 ps
T19 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1266870311 Dec 20 12:24:42 PM PST 23 Dec 20 12:25:15 PM PST 23 21775559 ps
T77 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2168709537 Dec 20 12:25:29 PM PST 23 Dec 20 12:26:00 PM PST 23 15384049 ps
T20 /workspace/coverage/cover_reg_top/15.uart_tl_errors.4119275100 Dec 20 12:27:41 PM PST 23 Dec 20 12:28:17 PM PST 23 41696931 ps
T55 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3291640049 Dec 20 12:25:17 PM PST 23 Dec 20 12:25:38 PM PST 23 19058706 ps
T26 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2733736376 Dec 20 12:24:20 PM PST 23 Dec 20 12:24:54 PM PST 23 53399240 ps
T41 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.36885655 Dec 20 12:24:49 PM PST 23 Dec 20 12:25:20 PM PST 23 34690140 ps
T9 /workspace/coverage/cover_reg_top/49.uart_intr_test.3399462175 Dec 20 12:25:24 PM PST 23 Dec 20 12:25:49 PM PST 23 13869500 ps
T22 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3020148042 Dec 20 12:24:28 PM PST 23 Dec 20 12:25:01 PM PST 23 98395551 ps
T23 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3079199385 Dec 20 12:26:15 PM PST 23 Dec 20 12:26:49 PM PST 23 274964532 ps
T12 /workspace/coverage/cover_reg_top/1.uart_intr_test.1737183112 Dec 20 12:25:58 PM PST 23 Dec 20 12:26:21 PM PST 23 14488594 ps
T10 /workspace/coverage/cover_reg_top/4.uart_intr_test.3068345150 Dec 20 12:24:20 PM PST 23 Dec 20 12:24:54 PM PST 23 15944031 ps
T11 /workspace/coverage/cover_reg_top/17.uart_intr_test.3178551481 Dec 20 12:24:38 PM PST 23 Dec 20 12:25:13 PM PST 23 13483119 ps
T27 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1683459643 Dec 20 12:25:14 PM PST 23 Dec 20 12:25:33 PM PST 23 102330760 ps
T73 /workspace/coverage/cover_reg_top/29.uart_intr_test.347087435 Dec 20 12:25:08 PM PST 23 Dec 20 12:25:28 PM PST 23 25086718 ps
T13 /workspace/coverage/cover_reg_top/25.uart_intr_test.3980704822 Dec 20 12:24:31 PM PST 23 Dec 20 12:25:03 PM PST 23 36491244 ps
T28 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2014385469 Dec 20 12:24:56 PM PST 23 Dec 20 12:25:23 PM PST 23 26973326 ps
T71 /workspace/coverage/cover_reg_top/6.uart_intr_test.2218981139 Dec 20 12:28:47 PM PST 23 Dec 20 12:29:21 PM PST 23 58790381 ps
T72 /workspace/coverage/cover_reg_top/9.uart_intr_test.1281052828 Dec 20 12:24:34 PM PST 23 Dec 20 12:25:07 PM PST 23 39348887 ps
T29 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2969859500 Dec 20 12:24:31 PM PST 23 Dec 20 12:25:03 PM PST 23 15585932 ps
T30 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3960417796 Dec 20 12:25:20 PM PST 23 Dec 20 12:25:43 PM PST 23 13765937 ps
T66 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3911711985 Dec 20 12:24:35 PM PST 23 Dec 20 12:25:09 PM PST 23 43596930 ps
T56 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2210451671 Dec 20 12:25:05 PM PST 23 Dec 20 12:25:26 PM PST 23 29005215 ps
T69 /workspace/coverage/cover_reg_top/47.uart_intr_test.3927016630 Dec 20 12:25:50 PM PST 23 Dec 20 12:26:16 PM PST 23 24053013 ps
T57 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1880307719 Dec 20 12:24:25 PM PST 23 Dec 20 12:24:58 PM PST 23 32266387 ps
T67 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1442338306 Dec 20 12:25:35 PM PST 23 Dec 20 12:26:06 PM PST 23 118199218 ps
T78 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1494701223 Dec 20 12:29:33 PM PST 23 Dec 20 12:29:56 PM PST 23 373441000 ps
T74 /workspace/coverage/cover_reg_top/2.uart_intr_test.861200634 Dec 20 12:26:07 PM PST 23 Dec 20 12:26:33 PM PST 23 106603654 ps
T75 /workspace/coverage/cover_reg_top/7.uart_intr_test.2043715439 Dec 20 12:25:19 PM PST 23 Dec 20 12:25:42 PM PST 23 16328028 ps
T59 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2437300949 Dec 20 12:25:23 PM PST 23 Dec 20 12:25:49 PM PST 23 181270366 ps
T62 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3675004913 Dec 20 12:25:19 PM PST 23 Dec 20 12:25:42 PM PST 23 957753306 ps
T76 /workspace/coverage/cover_reg_top/13.uart_intr_test.564268825 Dec 20 12:24:50 PM PST 23 Dec 20 12:25:20 PM PST 23 28705191 ps
T68 /workspace/coverage/cover_reg_top/15.uart_csr_rw.104670068 Dec 20 12:24:26 PM PST 23 Dec 20 12:24:58 PM PST 23 45774859 ps
T79 /workspace/coverage/cover_reg_top/10.uart_intr_test.1188197306 Dec 20 12:24:20 PM PST 23 Dec 20 12:24:54 PM PST 23 69620870 ps
T58 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4003713934 Dec 20 12:24:35 PM PST 23 Dec 20 12:25:09 PM PST 23 16280100 ps
T80 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.863071728 Dec 20 12:25:59 PM PST 23 Dec 20 12:26:23 PM PST 23 21283361 ps
T60 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1013523387 Dec 20 12:24:59 PM PST 23 Dec 20 12:25:24 PM PST 23 90453388 ps
T81 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2754943856 Dec 20 12:24:30 PM PST 23 Dec 20 12:25:02 PM PST 23 22057219 ps
T82 /workspace/coverage/cover_reg_top/12.uart_intr_test.961086622 Dec 20 12:24:31 PM PST 23 Dec 20 12:25:03 PM PST 23 14107918 ps
T83 /workspace/coverage/cover_reg_top/18.uart_csr_rw.912707464 Dec 20 12:24:44 PM PST 23 Dec 20 12:25:17 PM PST 23 15457112 ps
T64 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3918963061 Dec 20 12:24:38 PM PST 23 Dec 20 12:25:13 PM PST 23 678486474 ps
T84 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2942275737 Dec 20 12:24:31 PM PST 23 Dec 20 12:25:04 PM PST 23 54650372 ps
T85 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3179344067 Dec 20 12:25:12 PM PST 23 Dec 20 12:25:30 PM PST 23 24584946 ps
T86 /workspace/coverage/cover_reg_top/18.uart_tl_errors.232108033 Dec 20 12:24:48 PM PST 23 Dec 20 12:25:20 PM PST 23 95363411 ps
T87 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2805859905 Dec 20 12:25:18 PM PST 23 Dec 20 12:25:40 PM PST 23 29757521 ps
T88 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1447149064 Dec 20 12:25:15 PM PST 23 Dec 20 12:25:34 PM PST 23 216561290 ps
T34 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3179905662 Dec 20 12:26:12 PM PST 23 Dec 20 12:26:41 PM PST 23 27133548 ps
T45 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1112502705 Dec 20 12:25:13 PM PST 23 Dec 20 12:25:33 PM PST 23 116576624 ps
T46 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.4175350318 Dec 20 12:25:12 PM PST 23 Dec 20 12:25:31 PM PST 23 21013850 ps
T35 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1257276127 Dec 20 12:24:34 PM PST 23 Dec 20 12:25:07 PM PST 23 30239644 ps
T47 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.379538233 Dec 20 12:24:28 PM PST 23 Dec 20 12:25:02 PM PST 23 171906973 ps
T48 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1691177412 Dec 20 12:24:44 PM PST 23 Dec 20 12:25:17 PM PST 23 211283843 ps
T49 /workspace/coverage/cover_reg_top/16.uart_intr_test.4289769874 Dec 20 12:24:17 PM PST 23 Dec 20 12:24:53 PM PST 23 25406609 ps
T50 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1013564340 Dec 20 12:24:19 PM PST 23 Dec 20 12:24:55 PM PST 23 63343399 ps
T51 /workspace/coverage/cover_reg_top/39.uart_intr_test.3647451505 Dec 20 12:25:19 PM PST 23 Dec 20 12:25:42 PM PST 23 51354655 ps
T36 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1612694591 Dec 20 12:24:53 PM PST 23 Dec 20 12:25:21 PM PST 23 48809615 ps
T89 /workspace/coverage/cover_reg_top/37.uart_intr_test.1842216771 Dec 20 12:26:17 PM PST 23 Dec 20 12:26:50 PM PST 23 23803672 ps
T90 /workspace/coverage/cover_reg_top/31.uart_intr_test.2498326332 Dec 20 12:25:17 PM PST 23 Dec 20 12:25:38 PM PST 23 23492603 ps
T91 /workspace/coverage/cover_reg_top/19.uart_intr_test.1408333286 Dec 20 12:25:16 PM PST 23 Dec 20 12:25:36 PM PST 23 37915145 ps
T92 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.102818435 Dec 20 12:25:52 PM PST 23 Dec 20 12:26:18 PM PST 23 211300224 ps
T93 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.506346604 Dec 20 12:25:13 PM PST 23 Dec 20 12:25:32 PM PST 23 82998544 ps
T94 /workspace/coverage/cover_reg_top/11.uart_intr_test.262353977 Dec 20 12:24:23 PM PST 23 Dec 20 12:24:56 PM PST 23 46875891 ps
T42 /workspace/coverage/cover_reg_top/10.uart_csr_rw.591729226 Dec 20 12:24:45 PM PST 23 Dec 20 12:25:18 PM PST 23 17892122 ps
T61 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1665855723 Dec 20 12:24:45 PM PST 23 Dec 20 12:25:18 PM PST 23 332003622 ps
T95 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3696232747 Dec 20 12:24:33 PM PST 23 Dec 20 12:25:05 PM PST 23 56081835 ps
T96 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1316509924 Dec 20 12:24:29 PM PST 23 Dec 20 12:25:01 PM PST 23 64153740 ps
T97 /workspace/coverage/cover_reg_top/44.uart_intr_test.2575704187 Dec 20 12:25:57 PM PST 23 Dec 20 12:26:21 PM PST 23 59267134 ps
T98 /workspace/coverage/cover_reg_top/23.uart_intr_test.2513484767 Dec 20 12:24:38 PM PST 23 Dec 20 12:25:13 PM PST 23 11422395 ps
T43 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.310752146 Dec 20 12:25:17 PM PST 23 Dec 20 12:25:39 PM PST 23 58750646 ps
T99 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2638167747 Dec 20 12:25:27 PM PST 23 Dec 20 12:25:54 PM PST 23 47560884 ps
T100 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3293503743 Dec 20 12:24:27 PM PST 23 Dec 20 12:25:01 PM PST 23 123413989 ps
T101 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.272366715 Dec 20 12:24:36 PM PST 23 Dec 20 12:25:11 PM PST 23 31398137 ps
T102 /workspace/coverage/cover_reg_top/24.uart_intr_test.2666116537 Dec 20 12:25:05 PM PST 23 Dec 20 12:25:27 PM PST 23 52749338 ps
T103 /workspace/coverage/cover_reg_top/45.uart_intr_test.541115989 Dec 20 12:25:39 PM PST 23 Dec 20 12:26:08 PM PST 23 44768156 ps
T104 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1209121390 Dec 20 12:25:25 PM PST 23 Dec 20 12:25:52 PM PST 23 64680516 ps
T105 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2212678331 Dec 20 12:26:21 PM PST 23 Dec 20 12:26:55 PM PST 23 64243634 ps
T63 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1855608744 Dec 20 12:24:30 PM PST 23 Dec 20 12:25:03 PM PST 23 85225459 ps
T37 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3409229523 Dec 20 12:24:23 PM PST 23 Dec 20 12:24:56 PM PST 23 41920513 ps
T70 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2170097114 Dec 20 12:25:21 PM PST 23 Dec 20 12:25:46 PM PST 23 94300900 ps
T106 /workspace/coverage/cover_reg_top/40.uart_intr_test.652509137 Dec 20 12:25:53 PM PST 23 Dec 20 12:26:18 PM PST 23 13810290 ps
T107 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3962494824 Dec 20 12:25:51 PM PST 23 Dec 20 12:26:17 PM PST 23 216988563 ps
T108 /workspace/coverage/cover_reg_top/42.uart_intr_test.3958209252 Dec 20 12:26:17 PM PST 23 Dec 20 12:26:51 PM PST 23 40965676 ps
T109 /workspace/coverage/cover_reg_top/8.uart_intr_test.3779126251 Dec 20 12:24:12 PM PST 23 Dec 20 12:24:50 PM PST 23 11486882 ps
T38 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2464585657 Dec 20 12:25:48 PM PST 23 Dec 20 12:26:14 PM PST 23 43655622 ps
T39 /workspace/coverage/cover_reg_top/4.uart_csr_rw.523206574 Dec 20 12:24:25 PM PST 23 Dec 20 12:24:58 PM PST 23 38925459 ps
T40 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1941193108 Dec 20 12:24:18 PM PST 23 Dec 20 12:24:53 PM PST 23 12741894 ps
T110 /workspace/coverage/cover_reg_top/48.uart_intr_test.3643958671 Dec 20 12:25:55 PM PST 23 Dec 20 12:26:20 PM PST 23 16803076 ps
T111 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3664335354 Dec 20 12:24:19 PM PST 23 Dec 20 12:24:54 PM PST 23 33986816 ps
T112 /workspace/coverage/cover_reg_top/30.uart_intr_test.333399808 Dec 20 12:24:31 PM PST 23 Dec 20 12:25:03 PM PST 23 15413806 ps
T113 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2465259952 Dec 20 12:24:16 PM PST 23 Dec 20 12:24:53 PM PST 23 104913794 ps
T114 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2751878869 Dec 20 12:26:01 PM PST 23 Dec 20 12:26:25 PM PST 23 92028730 ps
T115 /workspace/coverage/cover_reg_top/14.uart_intr_test.1319536936 Dec 20 12:25:27 PM PST 23 Dec 20 12:25:54 PM PST 23 11680809 ps
T116 /workspace/coverage/cover_reg_top/43.uart_intr_test.2544068275 Dec 20 12:25:06 PM PST 23 Dec 20 12:25:27 PM PST 23 190210368 ps
T117 /workspace/coverage/cover_reg_top/1.uart_tl_errors.2712615284 Dec 20 12:24:22 PM PST 23 Dec 20 12:24:56 PM PST 23 51031729 ps
T118 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1973691312 Dec 20 12:24:27 PM PST 23 Dec 20 12:25:00 PM PST 23 111547071 ps
T44 /workspace/coverage/cover_reg_top/17.uart_csr_rw.4040519759 Dec 20 12:24:40 PM PST 23 Dec 20 12:25:13 PM PST 23 14759796 ps
T119 /workspace/coverage/cover_reg_top/34.uart_intr_test.3731238398 Dec 20 12:26:49 PM PST 23 Dec 20 12:27:19 PM PST 23 13022029 ps
T120 /workspace/coverage/cover_reg_top/26.uart_intr_test.1422804707 Dec 20 12:25:45 PM PST 23 Dec 20 12:26:14 PM PST 23 14917170 ps
T121 /workspace/coverage/cover_reg_top/2.uart_tl_errors.763568339 Dec 20 12:24:49 PM PST 23 Dec 20 12:25:20 PM PST 23 31786429 ps
T122 /workspace/coverage/cover_reg_top/5.uart_intr_test.1387866259 Dec 20 12:25:28 PM PST 23 Dec 20 12:25:55 PM PST 23 14736789 ps
T123 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2265738255 Dec 20 12:24:36 PM PST 23 Dec 20 12:25:14 PM PST 23 55115583 ps
T124 /workspace/coverage/cover_reg_top/32.uart_intr_test.566158617 Dec 20 12:25:15 PM PST 23 Dec 20 12:25:34 PM PST 23 35619322 ps
T125 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1441400475 Dec 20 12:24:34 PM PST 23 Dec 20 12:25:07 PM PST 23 41068831 ps
T126 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1937844863 Dec 20 12:25:23 PM PST 23 Dec 20 12:25:53 PM PST 23 77939587 ps
T127 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3052842823 Dec 20 12:24:31 PM PST 23 Dec 20 12:25:03 PM PST 23 216963513 ps
T128 /workspace/coverage/cover_reg_top/15.uart_intr_test.722691657 Dec 20 12:25:47 PM PST 23 Dec 20 12:26:14 PM PST 23 13636495 ps
T52 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4051128593 Dec 20 12:24:20 PM PST 23 Dec 20 12:24:55 PM PST 23 57699077 ps
T129 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2442875316 Dec 20 12:24:36 PM PST 23 Dec 20 12:25:11 PM PST 23 17910009 ps
T130 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1545024794 Dec 20 12:24:49 PM PST 23 Dec 20 12:25:19 PM PST 23 12290210 ps
T65 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3073500058 Dec 20 12:26:00 PM PST 23 Dec 20 12:26:24 PM PST 23 185645606 ps
T131 /workspace/coverage/cover_reg_top/0.uart_tl_errors.540121751 Dec 20 12:24:17 PM PST 23 Dec 20 12:24:54 PM PST 23 37860459 ps
T132 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4139308746 Dec 20 12:24:21 PM PST 23 Dec 20 12:24:55 PM PST 23 299271908 ps
T133 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2595264356 Dec 20 12:24:27 PM PST 23 Dec 20 12:25:00 PM PST 23 321995317 ps
T134 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.732716461 Dec 20 12:25:18 PM PST 23 Dec 20 12:25:40 PM PST 23 89923656 ps
T135 /workspace/coverage/cover_reg_top/13.uart_tl_errors.4286420057 Dec 20 12:25:12 PM PST 23 Dec 20 12:25:33 PM PST 23 126605060 ps
T53 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.195565716 Dec 20 12:24:39 PM PST 23 Dec 20 12:25:13 PM PST 23 23518721 ps
T136 /workspace/coverage/cover_reg_top/28.uart_intr_test.103413828 Dec 20 12:25:06 PM PST 23 Dec 20 12:25:27 PM PST 23 21447331 ps
T137 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2171855190 Dec 20 12:24:35 PM PST 23 Dec 20 12:25:10 PM PST 23 86252456 ps
T138 /workspace/coverage/cover_reg_top/20.uart_intr_test.3808540763 Dec 20 12:24:37 PM PST 23 Dec 20 12:25:12 PM PST 23 18805716 ps
T139 /workspace/coverage/cover_reg_top/38.uart_intr_test.2362548815 Dec 20 12:25:26 PM PST 23 Dec 20 12:25:52 PM PST 23 13457181 ps
T140 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1784722783 Dec 20 12:24:28 PM PST 23 Dec 20 12:25:00 PM PST 23 53058537 ps
T141 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.448468302 Dec 20 12:25:49 PM PST 23 Dec 20 12:26:19 PM PST 23 77780132 ps
T142 /workspace/coverage/cover_reg_top/22.uart_intr_test.2016437923 Dec 20 12:24:39 PM PST 23 Dec 20 12:25:13 PM PST 23 12287505 ps
T54 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1174200551 Dec 20 12:24:33 PM PST 23 Dec 20 12:25:06 PM PST 23 30645032 ps
T143 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1033777858 Dec 20 12:25:17 PM PST 23 Dec 20 12:25:38 PM PST 23 36300112 ps
T144 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3044345982 Dec 20 12:25:14 PM PST 23 Dec 20 12:25:34 PM PST 23 27281686 ps
T145 /workspace/coverage/cover_reg_top/36.uart_intr_test.1375631577 Dec 20 12:24:31 PM PST 23 Dec 20 12:25:03 PM PST 23 41288076 ps
T146 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1335662361 Dec 20 12:25:19 PM PST 23 Dec 20 12:25:43 PM PST 23 253926080 ps
T147 /workspace/coverage/cover_reg_top/35.uart_intr_test.2827635163 Dec 20 12:24:18 PM PST 23 Dec 20 12:24:53 PM PST 23 27914660 ps
T148 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3968501567 Dec 20 12:24:25 PM PST 23 Dec 20 12:24:58 PM PST 23 20316256 ps
T149 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1855572873 Dec 20 12:24:30 PM PST 23 Dec 20 12:25:02 PM PST 23 39455721 ps
T150 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2136094971 Dec 20 12:24:54 PM PST 23 Dec 20 12:25:22 PM PST 23 30417098 ps
T151 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2204603884 Dec 20 12:25:39 PM PST 23 Dec 20 12:26:09 PM PST 23 59494093 ps
T152 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3278768076 Dec 20 12:24:20 PM PST 23 Dec 20 12:24:54 PM PST 23 15106990 ps
T153 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3212961238 Dec 20 12:25:14 PM PST 23 Dec 20 12:25:34 PM PST 23 87484313 ps
T154 /workspace/coverage/cover_reg_top/21.uart_intr_test.834976644 Dec 20 12:24:35 PM PST 23 Dec 20 12:25:09 PM PST 23 12103493 ps
T155 /workspace/coverage/cover_reg_top/33.uart_intr_test.567026168 Dec 20 12:24:27 PM PST 23 Dec 20 12:25:00 PM PST 23 37814740 ps
T156 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.836488306 Dec 20 12:24:34 PM PST 23 Dec 20 12:25:08 PM PST 23 260381619 ps
T157 /workspace/coverage/cover_reg_top/46.uart_intr_test.2477018839 Dec 20 12:25:46 PM PST 23 Dec 20 12:26:13 PM PST 23 30212350 ps
T158 /workspace/coverage/cover_reg_top/0.uart_intr_test.2678606589 Dec 20 12:24:16 PM PST 23 Dec 20 12:24:53 PM PST 23 43836031 ps
T159 /workspace/coverage/cover_reg_top/41.uart_intr_test.1435800236 Dec 20 12:26:09 PM PST 23 Dec 20 12:26:37 PM PST 23 25162651 ps
T160 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1974421480 Dec 20 12:24:30 PM PST 23 Dec 20 12:25:02 PM PST 23 21374236 ps
T161 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2188835264 Dec 20 12:24:32 PM PST 23 Dec 20 12:25:05 PM PST 23 66109083 ps
T162 /workspace/coverage/cover_reg_top/3.uart_intr_test.1243861780 Dec 20 12:24:37 PM PST 23 Dec 20 12:25:10 PM PST 23 49162655 ps
T163 /workspace/coverage/cover_reg_top/18.uart_intr_test.657823327 Dec 20 12:25:22 PM PST 23 Dec 20 12:25:46 PM PST 23 23770432 ps
T164 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3372388725 Dec 20 12:26:08 PM PST 23 Dec 20 12:26:35 PM PST 23 18310987 ps
T165 /workspace/coverage/cover_reg_top/19.uart_tl_errors.435567707 Dec 20 12:24:38 PM PST 23 Dec 20 12:25:14 PM PST 23 50130023 ps

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3490240483
Short name T8
Test name
Test status
Simulation time 82963491 ps
CPU time 0.98 seconds
Started Dec 20 12:24:57 PM PST 23
Finished Dec 20 12:25:23 PM PST 23
Peak memory 199128 kb
Host smart-fc67cbe3-58b2-40f3-b8c1-d996de0e0ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490240483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3490240483
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3399462175
Short name T9
Test name
Test status
Simulation time 13869500 ps
CPU time 0.55 seconds
Started Dec 20 12:25:24 PM PST 23
Finished Dec 20 12:25:49 PM PST 23
Peak memory 194544 kb
Host smart-2034c94e-3747-439b-9ecd-737eed30b8e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399462175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3399462175
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1489014887
Short name T7
Test name
Test status
Simulation time 100230396 ps
CPU time 2.22 seconds
Started Dec 20 12:24:46 PM PST 23
Finished Dec 20 12:25:19 PM PST 23
Peak memory 200196 kb
Host smart-1eb94437-1eca-4b12-bde8-f3bd6d63e15c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489014887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1489014887
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2969859500
Short name T29
Test name
Test status
Simulation time 15585932 ps
CPU time 0.6 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 195604 kb
Host smart-9e4b0116-0ab3-4345-a2fb-bdfbb460cbdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969859500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2969859500
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.627102235
Short name T6
Test name
Test status
Simulation time 13506617 ps
CPU time 0.57 seconds
Started Dec 20 12:26:04 PM PST 23
Finished Dec 20 12:26:32 PM PST 23
Peak memory 195580 kb
Host smart-ff1d6a84-a702-4a55-aba6-62708dc8b325
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627102235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.627102235
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2218981139
Short name T71
Test name
Test status
Simulation time 58790381 ps
CPU time 0.55 seconds
Started Dec 20 12:28:47 PM PST 23
Finished Dec 20 12:29:21 PM PST 23
Peak memory 184768 kb
Host smart-8a0e9ae7-ea5e-4c1e-8561-10c1aacaa9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218981139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2218981139
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3020148042
Short name T22
Test name
Test status
Simulation time 98395551 ps
CPU time 1.28 seconds
Started Dec 20 12:24:28 PM PST 23
Finished Dec 20 12:25:01 PM PST 23
Peak memory 199376 kb
Host smart-fbdf4d68-5e99-4e9a-9355-42187d8556b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020148042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3020148042
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1013523387
Short name T60
Test name
Test status
Simulation time 90453388 ps
CPU time 1.26 seconds
Started Dec 20 12:24:59 PM PST 23
Finished Dec 20 12:25:24 PM PST 23
Peak memory 199456 kb
Host smart-8175f221-1d3a-49ea-b188-b403604b6470
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013523387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1013523387
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.195565716
Short name T53
Test name
Test status
Simulation time 23518721 ps
CPU time 0.63 seconds
Started Dec 20 12:24:39 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 195592 kb
Host smart-7ccc055a-9ad9-4304-9f00-85cdfea5da80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195565716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.195565716
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1281052828
Short name T72
Test name
Test status
Simulation time 39348887 ps
CPU time 0.55 seconds
Started Dec 20 12:24:34 PM PST 23
Finished Dec 20 12:25:07 PM PST 23
Peak memory 185344 kb
Host smart-7948047b-d27d-427d-9402-3f3292f47dfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281052828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1281052828
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3918963061
Short name T64
Test name
Test status
Simulation time 678486474 ps
CPU time 1.39 seconds
Started Dec 20 12:24:38 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 199500 kb
Host smart-fccc7ee0-5dec-4695-b09a-716287d63563
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918963061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3918963061
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1737183112
Short name T12
Test name
Test status
Simulation time 14488594 ps
CPU time 0.62 seconds
Started Dec 20 12:25:58 PM PST 23
Finished Dec 20 12:26:21 PM PST 23
Peak memory 185300 kb
Host smart-b1ab8b12-8132-4fc6-846f-98996c707034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737183112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1737183112
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1033777858
Short name T143
Test name
Test status
Simulation time 36300112 ps
CPU time 1.62 seconds
Started Dec 20 12:25:17 PM PST 23
Finished Dec 20 12:25:38 PM PST 23
Peak memory 200228 kb
Host smart-8da0270d-422a-4107-a129-f4736620d453
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033777858 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1033777858
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.333399808
Short name T112
Test name
Test status
Simulation time 15413806 ps
CPU time 0.58 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 185308 kb
Host smart-ebe2d485-a80c-4bf7-9473-e3412bfa3e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333399808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.333399808
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1941193108
Short name T40
Test name
Test status
Simulation time 12741894 ps
CPU time 0.64 seconds
Started Dec 20 12:24:18 PM PST 23
Finished Dec 20 12:24:53 PM PST 23
Peak memory 195520 kb
Host smart-a699b781-ab05-4fe7-8306-6c14e32635af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941193108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1941193108
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2904053619
Short name T14
Test name
Test status
Simulation time 640358012 ps
CPU time 2.19 seconds
Started Dec 20 12:26:37 PM PST 23
Finished Dec 20 12:27:12 PM PST 23
Peak memory 197968 kb
Host smart-caad769c-4144-475f-9714-c994b3167d61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904053619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2904053619
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3278768076
Short name T152
Test name
Test status
Simulation time 15106990 ps
CPU time 0.54 seconds
Started Dec 20 12:24:20 PM PST 23
Finished Dec 20 12:24:54 PM PST 23
Peak memory 195560 kb
Host smart-eaaca77e-871d-435a-958f-5263144c8bbe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278768076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3278768076
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3664335354
Short name T111
Test name
Test status
Simulation time 33986816 ps
CPU time 0.93 seconds
Started Dec 20 12:24:19 PM PST 23
Finished Dec 20 12:24:54 PM PST 23
Peak memory 200028 kb
Host smart-36b117c8-6e84-4dfb-8596-255ad6226353
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664335354 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3664335354
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2838884920
Short name T24
Test name
Test status
Simulation time 20022125 ps
CPU time 0.6 seconds
Started Dec 20 12:24:49 PM PST 23
Finished Dec 20 12:25:19 PM PST 23
Peak memory 195628 kb
Host smart-d78addf4-efa8-47fc-bf94-e33afbacf656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838884920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2838884920
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2678606589
Short name T158
Test name
Test status
Simulation time 43836031 ps
CPU time 0.56 seconds
Started Dec 20 12:24:16 PM PST 23
Finished Dec 20 12:24:53 PM PST 23
Peak memory 185264 kb
Host smart-ee77ce1e-043a-408c-bf21-3cde528a583d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678606589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2678606589
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1371735336
Short name T25
Test name
Test status
Simulation time 27552296 ps
CPU time 0.73 seconds
Started Dec 20 12:25:15 PM PST 23
Finished Dec 20 12:25:35 PM PST 23
Peak memory 196972 kb
Host smart-36e1c1b1-ab48-477c-b64e-6e1fc627ee85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371735336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1371735336
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.540121751
Short name T131
Test name
Test status
Simulation time 37860459 ps
CPU time 1.89 seconds
Started Dec 20 12:24:17 PM PST 23
Finished Dec 20 12:24:54 PM PST 23
Peak memory 200216 kb
Host smart-d9cff008-c3e3-480d-925b-9b9fe8ee3bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540121751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.540121751
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.732716461
Short name T134
Test name
Test status
Simulation time 89923656 ps
CPU time 1.3 seconds
Started Dec 20 12:25:18 PM PST 23
Finished Dec 20 12:25:40 PM PST 23
Peak memory 199292 kb
Host smart-71f4feae-3bac-400f-9f6b-a2e99de90f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732716461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.732716461
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2465259952
Short name T113
Test name
Test status
Simulation time 104913794 ps
CPU time 1.36 seconds
Started Dec 20 12:24:16 PM PST 23
Finished Dec 20 12:24:53 PM PST 23
Peak memory 197412 kb
Host smart-9d984e82-10de-4e22-9f03-af6f66d80abf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465259952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2465259952
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2733736376
Short name T26
Test name
Test status
Simulation time 53399240 ps
CPU time 0.59 seconds
Started Dec 20 12:24:20 PM PST 23
Finished Dec 20 12:24:54 PM PST 23
Peak memory 195652 kb
Host smart-ca3b2ca0-a5a9-4b19-8ab1-fcfd77ae6f2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733736376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2733736376
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3696232747
Short name T95
Test name
Test status
Simulation time 56081835 ps
CPU time 0.76 seconds
Started Dec 20 12:24:33 PM PST 23
Finished Dec 20 12:25:05 PM PST 23
Peak memory 197808 kb
Host smart-fcfded3a-bab4-4393-a174-5685d8a2e2f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696232747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3696232747
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2712615284
Short name T117
Test name
Test status
Simulation time 51031729 ps
CPU time 1.15 seconds
Started Dec 20 12:24:22 PM PST 23
Finished Dec 20 12:24:56 PM PST 23
Peak memory 200084 kb
Host smart-97137458-8840-47b7-a90f-bd31841a7d87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712615284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2712615284
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2595264356
Short name T133
Test name
Test status
Simulation time 321995317 ps
CPU time 1.4 seconds
Started Dec 20 12:24:27 PM PST 23
Finished Dec 20 12:25:00 PM PST 23
Peak memory 199540 kb
Host smart-d8132c19-539f-4287-a779-485bd65a77ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595264356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2595264356
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1447149064
Short name T88
Test name
Test status
Simulation time 216561290 ps
CPU time 0.97 seconds
Started Dec 20 12:25:15 PM PST 23
Finished Dec 20 12:25:34 PM PST 23
Peak memory 200072 kb
Host smart-d6b9f5e6-fae2-4f6d-b6ab-d356aa64cb95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447149064 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1447149064
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.591729226
Short name T42
Test name
Test status
Simulation time 17892122 ps
CPU time 0.59 seconds
Started Dec 20 12:24:45 PM PST 23
Finished Dec 20 12:25:18 PM PST 23
Peak memory 195616 kb
Host smart-e7e33649-b4ab-4cde-9016-827c141a5a9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591729226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.591729226
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1188197306
Short name T79
Test name
Test status
Simulation time 69620870 ps
CPU time 0.6 seconds
Started Dec 20 12:24:20 PM PST 23
Finished Dec 20 12:24:54 PM PST 23
Peak memory 185228 kb
Host smart-9708c26e-0fb6-4f5f-95d8-0b7da6607673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188197306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1188197306
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1297548533
Short name T1
Test name
Test status
Simulation time 79959848 ps
CPU time 0.64 seconds
Started Dec 20 12:24:32 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 195844 kb
Host smart-ce56f2ce-be58-434a-89c9-ec4746786bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297548533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1297548533
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3079199385
Short name T23
Test name
Test status
Simulation time 274964532 ps
CPU time 2.36 seconds
Started Dec 20 12:26:15 PM PST 23
Finished Dec 20 12:26:49 PM PST 23
Peak memory 200192 kb
Host smart-9d3426b6-a979-4016-b8a6-be4e32eb7b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079199385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3079199385
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.36885655
Short name T41
Test name
Test status
Simulation time 34690140 ps
CPU time 0.9 seconds
Started Dec 20 12:24:49 PM PST 23
Finished Dec 20 12:25:20 PM PST 23
Peak memory 200016 kb
Host smart-af7a5bc6-fa4e-46ba-a7fa-fdc0055bdde4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36885655 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.36885655
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.262353977
Short name T94
Test name
Test status
Simulation time 46875891 ps
CPU time 0.55 seconds
Started Dec 20 12:24:23 PM PST 23
Finished Dec 20 12:24:56 PM PST 23
Peak memory 185356 kb
Host smart-96780809-ad75-4309-8e9f-d922bf4b3b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262353977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.262353977
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.448468302
Short name T141
Test name
Test status
Simulation time 77780132 ps
CPU time 0.69 seconds
Started Dec 20 12:25:49 PM PST 23
Finished Dec 20 12:26:19 PM PST 23
Peak memory 197036 kb
Host smart-44419901-b8e3-4695-b3b7-09a9a37fb2cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448468302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.448468302
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3052842823
Short name T127
Test name
Test status
Simulation time 216963513 ps
CPU time 1.12 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 200172 kb
Host smart-2f94cd8b-5389-437c-8131-8cdb5127a185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052842823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3052842823
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2168709537
Short name T77
Test name
Test status
Simulation time 15384049 ps
CPU time 0.74 seconds
Started Dec 20 12:25:29 PM PST 23
Finished Dec 20 12:26:00 PM PST 23
Peak memory 198476 kb
Host smart-34af19a5-d179-48b0-8fc1-e30149499e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168709537 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2168709537
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1174200551
Short name T54
Test name
Test status
Simulation time 30645032 ps
CPU time 0.54 seconds
Started Dec 20 12:24:33 PM PST 23
Finished Dec 20 12:25:06 PM PST 23
Peak memory 195600 kb
Host smart-bfd67233-4f59-463a-9f5d-096a84b0002a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174200551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1174200551
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.961086622
Short name T82
Test name
Test status
Simulation time 14107918 ps
CPU time 0.56 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 185296 kb
Host smart-50c29312-10f0-4c1c-8893-1a69945d2395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961086622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.961086622
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4139308746
Short name T132
Test name
Test status
Simulation time 299271908 ps
CPU time 0.72 seconds
Started Dec 20 12:24:21 PM PST 23
Finished Dec 20 12:24:55 PM PST 23
Peak memory 197284 kb
Host smart-6166d8c3-edd1-4bd8-bab5-a74b85d37a4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139308746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.4139308746
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1442338306
Short name T67
Test name
Test status
Simulation time 118199218 ps
CPU time 1.32 seconds
Started Dec 20 12:25:35 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 200228 kb
Host smart-02971f6e-5c81-4ace-8e66-bb9a898b564b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442338306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1442338306
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2170097114
Short name T70
Test name
Test status
Simulation time 94300900 ps
CPU time 0.91 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:46 PM PST 23
Peak memory 198768 kb
Host smart-e78219b7-7bad-400c-9e5f-a3e529c4f80a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170097114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2170097114
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1971669213
Short name T5
Test name
Test status
Simulation time 25753076 ps
CPU time 1.32 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:46 PM PST 23
Peak memory 200200 kb
Host smart-08bea7ab-e7e5-4f1b-80a0-7356e3ba88bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971669213 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1971669213
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2464585657
Short name T38
Test name
Test status
Simulation time 43655622 ps
CPU time 0.56 seconds
Started Dec 20 12:25:48 PM PST 23
Finished Dec 20 12:26:14 PM PST 23
Peak memory 195596 kb
Host smart-7b44999c-61fc-4c0c-af2a-0a14dceceba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464585657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2464585657
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.564268825
Short name T76
Test name
Test status
Simulation time 28705191 ps
CPU time 0.55 seconds
Started Dec 20 12:24:50 PM PST 23
Finished Dec 20 12:25:20 PM PST 23
Peak memory 185308 kb
Host smart-697c927e-bb1e-42b1-a42c-a6bbc05a447c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564268825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.564268825
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3179344067
Short name T85
Test name
Test status
Simulation time 24584946 ps
CPU time 0.65 seconds
Started Dec 20 12:25:12 PM PST 23
Finished Dec 20 12:25:30 PM PST 23
Peak memory 195912 kb
Host smart-4e8e0ea0-693f-4837-b6d5-97fdac143196
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179344067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3179344067
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.4286420057
Short name T135
Test name
Test status
Simulation time 126605060 ps
CPU time 2.14 seconds
Started Dec 20 12:25:12 PM PST 23
Finished Dec 20 12:25:33 PM PST 23
Peak memory 200188 kb
Host smart-f5d4cc31-91e6-4966-9701-89bb227c4861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286420057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4286420057
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2751878869
Short name T114
Test name
Test status
Simulation time 92028730 ps
CPU time 0.97 seconds
Started Dec 20 12:26:01 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 199968 kb
Host smart-17f605fc-ae0c-4613-b637-bf084f4db866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751878869 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2751878869
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1855572873
Short name T149
Test name
Test status
Simulation time 39455721 ps
CPU time 0.54 seconds
Started Dec 20 12:24:30 PM PST 23
Finished Dec 20 12:25:02 PM PST 23
Peak memory 195680 kb
Host smart-d10cafa1-83b6-4c5d-b428-4747b103543d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855572873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1855572873
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1319536936
Short name T115
Test name
Test status
Simulation time 11680809 ps
CPU time 0.55 seconds
Started Dec 20 12:25:27 PM PST 23
Finished Dec 20 12:25:54 PM PST 23
Peak memory 194540 kb
Host smart-5429c31e-a14a-49ec-be1a-d20b99715188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319536936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1319536936
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3044345982
Short name T144
Test name
Test status
Simulation time 27281686 ps
CPU time 0.74 seconds
Started Dec 20 12:25:14 PM PST 23
Finished Dec 20 12:25:34 PM PST 23
Peak memory 197240 kb
Host smart-8c7d5ec5-d770-4906-b7cf-4a0e20a77d46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044345982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3044345982
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.189764245
Short name T3
Test name
Test status
Simulation time 61474184 ps
CPU time 1.39 seconds
Started Dec 20 12:25:34 PM PST 23
Finished Dec 20 12:26:04 PM PST 23
Peak memory 200216 kb
Host smart-f67d9d02-f9d8-40e5-b635-7cb70cb33d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189764245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.189764245
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3073500058
Short name T65
Test name
Test status
Simulation time 185645606 ps
CPU time 1.23 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:24 PM PST 23
Peak memory 199460 kb
Host smart-16465c60-29a4-4552-b8ec-8f243ec7c0d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073500058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3073500058
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1527972108
Short name T21
Test name
Test status
Simulation time 55115150 ps
CPU time 0.62 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:45 PM PST 23
Peak memory 196816 kb
Host smart-870220ab-00fb-4830-9910-9497e4064c30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527972108 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1527972108
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.104670068
Short name T68
Test name
Test status
Simulation time 45774859 ps
CPU time 0.57 seconds
Started Dec 20 12:24:26 PM PST 23
Finished Dec 20 12:24:58 PM PST 23
Peak memory 195612 kb
Host smart-e90fdcf6-9fa8-4870-97eb-7bb63b8365ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104670068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.104670068
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.722691657
Short name T128
Test name
Test status
Simulation time 13636495 ps
CPU time 0.57 seconds
Started Dec 20 12:25:47 PM PST 23
Finished Dec 20 12:26:14 PM PST 23
Peak memory 185296 kb
Host smart-80e2fb8b-306b-4b3d-9692-90a8ab7339d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722691657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.722691657
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2805859905
Short name T87
Test name
Test status
Simulation time 29757521 ps
CPU time 0.76 seconds
Started Dec 20 12:25:18 PM PST 23
Finished Dec 20 12:25:40 PM PST 23
Peak memory 196184 kb
Host smart-378f1494-89f1-42cd-a5fe-5e15f0f48bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805859905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2805859905
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4119275100
Short name T20
Test name
Test status
Simulation time 41696931 ps
CPU time 1.93 seconds
Started Dec 20 12:27:41 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 200220 kb
Host smart-0e655def-0188-43b7-bed1-39c44dca6269
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119275100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4119275100
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1112502705
Short name T45
Test name
Test status
Simulation time 116576624 ps
CPU time 1.34 seconds
Started Dec 20 12:25:13 PM PST 23
Finished Dec 20 12:25:33 PM PST 23
Peak memory 199492 kb
Host smart-aeba1996-3a1a-428d-9672-f4fa33e7c594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112502705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1112502705
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.836488306
Short name T156
Test name
Test status
Simulation time 260381619 ps
CPU time 0.89 seconds
Started Dec 20 12:24:34 PM PST 23
Finished Dec 20 12:25:08 PM PST 23
Peak memory 200040 kb
Host smart-12155b05-b77c-4fb4-bdad-149a409ce3ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836488306 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.836488306
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1441400475
Short name T125
Test name
Test status
Simulation time 41068831 ps
CPU time 0.59 seconds
Started Dec 20 12:24:34 PM PST 23
Finished Dec 20 12:25:07 PM PST 23
Peak memory 195640 kb
Host smart-167780b3-53e0-4c7a-8c9a-057180bc7321
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441400475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1441400475
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.4289769874
Short name T49
Test name
Test status
Simulation time 25406609 ps
CPU time 0.58 seconds
Started Dec 20 12:24:17 PM PST 23
Finished Dec 20 12:24:53 PM PST 23
Peak memory 194564 kb
Host smart-66aec800-d9d9-4ec2-ae76-05ea1f72de0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289769874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.4289769874
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3968501567
Short name T148
Test name
Test status
Simulation time 20316256 ps
CPU time 0.64 seconds
Started Dec 20 12:24:25 PM PST 23
Finished Dec 20 12:24:58 PM PST 23
Peak memory 195776 kb
Host smart-826171ad-7cb9-404b-9723-da2aae033937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968501567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3968501567
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2437300949
Short name T59
Test name
Test status
Simulation time 181270366 ps
CPU time 1.33 seconds
Started Dec 20 12:25:23 PM PST 23
Finished Dec 20 12:25:49 PM PST 23
Peak memory 199420 kb
Host smart-b100148d-5fe7-471e-ac47-80f7f2a0e7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437300949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2437300949
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.272366715
Short name T101
Test name
Test status
Simulation time 31398137 ps
CPU time 0.72 seconds
Started Dec 20 12:24:36 PM PST 23
Finished Dec 20 12:25:11 PM PST 23
Peak memory 197780 kb
Host smart-c4734119-780f-4065-bb22-7087554a83ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272366715 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.272366715
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.4040519759
Short name T44
Test name
Test status
Simulation time 14759796 ps
CPU time 0.6 seconds
Started Dec 20 12:24:40 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 195720 kb
Host smart-2b02aadf-4a4f-47a6-b656-ee0a609dbfc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040519759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.4040519759
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3178551481
Short name T11
Test name
Test status
Simulation time 13483119 ps
CPU time 0.59 seconds
Started Dec 20 12:24:38 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 185308 kb
Host smart-1beae297-7db7-4aa1-85e2-7921099ac200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178551481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3178551481
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.863071728
Short name T80
Test name
Test status
Simulation time 21283361 ps
CPU time 0.65 seconds
Started Dec 20 12:25:59 PM PST 23
Finished Dec 20 12:26:23 PM PST 23
Peak memory 195888 kb
Host smart-4570b859-965f-48bd-b13f-29a13680d4bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863071728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.863071728
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3266965440
Short name T17
Test name
Test status
Simulation time 26522091 ps
CPU time 1.28 seconds
Started Dec 20 12:24:28 PM PST 23
Finished Dec 20 12:25:01 PM PST 23
Peak memory 200228 kb
Host smart-4b33e29c-a0b1-4783-8286-02a746acf443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266965440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3266965440
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3675004913
Short name T62
Test name
Test status
Simulation time 957753306 ps
CPU time 1.31 seconds
Started Dec 20 12:25:19 PM PST 23
Finished Dec 20 12:25:42 PM PST 23
Peak memory 199388 kb
Host smart-79096324-b25c-42e9-ae46-55c2d7caf814
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675004913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3675004913
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.792366243
Short name T31
Test name
Test status
Simulation time 54195095 ps
CPU time 0.69 seconds
Started Dec 20 12:24:35 PM PST 23
Finished Dec 20 12:25:09 PM PST 23
Peak memory 196564 kb
Host smart-dd745a0a-0ca8-4f83-aeb2-098307b61c7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792366243 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.792366243
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.912707464
Short name T83
Test name
Test status
Simulation time 15457112 ps
CPU time 0.62 seconds
Started Dec 20 12:24:44 PM PST 23
Finished Dec 20 12:25:17 PM PST 23
Peak memory 195760 kb
Host smart-2bc43ffd-804c-4a9b-bd39-6373b53a20b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912707464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.912707464
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.657823327
Short name T163
Test name
Test status
Simulation time 23770432 ps
CPU time 0.56 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:46 PM PST 23
Peak memory 185208 kb
Host smart-801b33cf-465c-427b-99c5-266fb0b57508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657823327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.657823327
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.4175350318
Short name T46
Test name
Test status
Simulation time 21013850 ps
CPU time 0.66 seconds
Started Dec 20 12:25:12 PM PST 23
Finished Dec 20 12:25:31 PM PST 23
Peak memory 196064 kb
Host smart-a091dd37-a842-4b3c-9f0a-641197eb056a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175350318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.4175350318
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.232108033
Short name T86
Test name
Test status
Simulation time 95363411 ps
CPU time 2.03 seconds
Started Dec 20 12:24:48 PM PST 23
Finished Dec 20 12:25:20 PM PST 23
Peak memory 200204 kb
Host smart-77cea82f-bc49-4cd2-a299-2c900264981d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232108033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.232108033
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1665855723
Short name T61
Test name
Test status
Simulation time 332003622 ps
CPU time 0.97 seconds
Started Dec 20 12:24:45 PM PST 23
Finished Dec 20 12:25:18 PM PST 23
Peak memory 199112 kb
Host smart-90d1a5c9-c9bb-4238-8de2-e7a542f61d61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665855723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1665855723
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3204058998
Short name T33
Test name
Test status
Simulation time 17815594 ps
CPU time 0.66 seconds
Started Dec 20 12:25:38 PM PST 23
Finished Dec 20 12:26:08 PM PST 23
Peak memory 197180 kb
Host smart-abad851f-4755-4afc-913e-0571254e2bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204058998 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3204058998
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2754943856
Short name T81
Test name
Test status
Simulation time 22057219 ps
CPU time 0.57 seconds
Started Dec 20 12:24:30 PM PST 23
Finished Dec 20 12:25:02 PM PST 23
Peak memory 195624 kb
Host smart-0946812a-1a9f-4c32-87df-2ab35c9d3e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754943856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2754943856
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1408333286
Short name T91
Test name
Test status
Simulation time 37915145 ps
CPU time 0.56 seconds
Started Dec 20 12:25:16 PM PST 23
Finished Dec 20 12:25:36 PM PST 23
Peak memory 194360 kb
Host smart-334baa22-329e-4b6a-b1ef-1f96cc641774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408333286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1408333286
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2136094971
Short name T150
Test name
Test status
Simulation time 30417098 ps
CPU time 0.73 seconds
Started Dec 20 12:24:54 PM PST 23
Finished Dec 20 12:25:22 PM PST 23
Peak memory 196088 kb
Host smart-b8154cf7-c17a-420a-9c35-443b95acda31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136094971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2136094971
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.435567707
Short name T165
Test name
Test status
Simulation time 50130023 ps
CPU time 2.36 seconds
Started Dec 20 12:24:38 PM PST 23
Finished Dec 20 12:25:14 PM PST 23
Peak memory 200216 kb
Host smart-01270f99-1cad-4dc1-949e-4130f2a13311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435567707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.435567707
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3212961238
Short name T153
Test name
Test status
Simulation time 87484313 ps
CPU time 1.31 seconds
Started Dec 20 12:25:14 PM PST 23
Finished Dec 20 12:25:34 PM PST 23
Peak memory 199188 kb
Host smart-c7aefa90-0bb5-46e9-806c-ece3fddfb3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212961238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3212961238
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3962494824
Short name T107
Test name
Test status
Simulation time 216988563 ps
CPU time 0.66 seconds
Started Dec 20 12:25:51 PM PST 23
Finished Dec 20 12:26:17 PM PST 23
Peak memory 195624 kb
Host smart-bc86907c-1d3f-4849-84d9-808bbd3e9c65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962494824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3962494824
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.310752146
Short name T43
Test name
Test status
Simulation time 58750646 ps
CPU time 2.24 seconds
Started Dec 20 12:25:17 PM PST 23
Finished Dec 20 12:25:39 PM PST 23
Peak memory 197756 kb
Host smart-febb47e4-419a-47d1-bcee-e40aad329e7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310752146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.310752146
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4003713934
Short name T58
Test name
Test status
Simulation time 16280100 ps
CPU time 0.6 seconds
Started Dec 20 12:24:35 PM PST 23
Finished Dec 20 12:25:09 PM PST 23
Peak memory 195636 kb
Host smart-f4518fc1-e051-4f05-9d2c-2feef23adb53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003713934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4003713934
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1973691312
Short name T118
Test name
Test status
Simulation time 111547071 ps
CPU time 0.94 seconds
Started Dec 20 12:24:27 PM PST 23
Finished Dec 20 12:25:00 PM PST 23
Peak memory 199480 kb
Host smart-fbaa3e68-da38-434b-b948-7f55052f222e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973691312 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1973691312
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3291640049
Short name T55
Test name
Test status
Simulation time 19058706 ps
CPU time 0.62 seconds
Started Dec 20 12:25:17 PM PST 23
Finished Dec 20 12:25:38 PM PST 23
Peak memory 195836 kb
Host smart-e8f322b6-5fd0-4701-9cfe-6c193191ec85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291640049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3291640049
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.861200634
Short name T74
Test name
Test status
Simulation time 106603654 ps
CPU time 0.54 seconds
Started Dec 20 12:26:07 PM PST 23
Finished Dec 20 12:26:33 PM PST 23
Peak memory 185284 kb
Host smart-26441058-a40c-466e-b454-cca76bf88244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861200634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.861200634
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3372388725
Short name T164
Test name
Test status
Simulation time 18310987 ps
CPU time 0.66 seconds
Started Dec 20 12:26:08 PM PST 23
Finished Dec 20 12:26:35 PM PST 23
Peak memory 195704 kb
Host smart-7aa98d1a-8292-401a-a54e-838d6afc66a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372388725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3372388725
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.763568339
Short name T121
Test name
Test status
Simulation time 31786429 ps
CPU time 1.61 seconds
Started Dec 20 12:24:49 PM PST 23
Finished Dec 20 12:25:20 PM PST 23
Peak memory 200176 kb
Host smart-94be58a2-3830-4129-bf1d-7bb3651d137c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763568339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.763568339
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2638167747
Short name T99
Test name
Test status
Simulation time 47560884 ps
CPU time 0.92 seconds
Started Dec 20 12:25:27 PM PST 23
Finished Dec 20 12:25:54 PM PST 23
Peak memory 199108 kb
Host smart-086aeaaf-0fbb-4ab0-917c-9f067586e09b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638167747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2638167747
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3808540763
Short name T138
Test name
Test status
Simulation time 18805716 ps
CPU time 0.57 seconds
Started Dec 20 12:24:37 PM PST 23
Finished Dec 20 12:25:12 PM PST 23
Peak memory 185220 kb
Host smart-564e66c1-198c-49ad-8542-40c37b29dfb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808540763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3808540763
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.834976644
Short name T154
Test name
Test status
Simulation time 12103493 ps
CPU time 0.54 seconds
Started Dec 20 12:24:35 PM PST 23
Finished Dec 20 12:25:09 PM PST 23
Peak memory 185148 kb
Host smart-666af197-509c-4fea-8427-975016ce9216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834976644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.834976644
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2016437923
Short name T142
Test name
Test status
Simulation time 12287505 ps
CPU time 0.57 seconds
Started Dec 20 12:24:39 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 185312 kb
Host smart-ac7d4fe4-65a4-4122-ab98-daa2091149ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016437923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2016437923
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2513484767
Short name T98
Test name
Test status
Simulation time 11422395 ps
CPU time 0.55 seconds
Started Dec 20 12:24:38 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 185184 kb
Host smart-2e3d65ab-3946-4b00-a95b-ff03d2fa8cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513484767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2513484767
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2666116537
Short name T102
Test name
Test status
Simulation time 52749338 ps
CPU time 0.59 seconds
Started Dec 20 12:25:05 PM PST 23
Finished Dec 20 12:25:27 PM PST 23
Peak memory 185276 kb
Host smart-85d64cf3-203b-4609-a11f-654417f9159f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666116537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2666116537
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3980704822
Short name T13
Test name
Test status
Simulation time 36491244 ps
CPU time 0.54 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 194532 kb
Host smart-6fcabaf5-27c9-4c63-a79f-118955480bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980704822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3980704822
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1422804707
Short name T120
Test name
Test status
Simulation time 14917170 ps
CPU time 0.58 seconds
Started Dec 20 12:25:45 PM PST 23
Finished Dec 20 12:26:14 PM PST 23
Peak memory 185296 kb
Host smart-a2b38d64-a649-4721-b8f3-f0554fc42ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422804707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1422804707
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.4241263500
Short name T2
Test name
Test status
Simulation time 14428536 ps
CPU time 0.56 seconds
Started Dec 20 12:25:17 PM PST 23
Finished Dec 20 12:25:38 PM PST 23
Peak memory 185276 kb
Host smart-9675be1d-b2ee-4ccd-b26a-de03dbc203de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241263500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4241263500
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.103413828
Short name T136
Test name
Test status
Simulation time 21447331 ps
CPU time 0.56 seconds
Started Dec 20 12:25:06 PM PST 23
Finished Dec 20 12:25:27 PM PST 23
Peak memory 194592 kb
Host smart-b6d4c0c5-3f77-4daf-8712-a6a6e4b0e38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103413828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.103413828
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.347087435
Short name T73
Test name
Test status
Simulation time 25086718 ps
CPU time 0.56 seconds
Started Dec 20 12:25:08 PM PST 23
Finished Dec 20 12:25:28 PM PST 23
Peak memory 185236 kb
Host smart-bccfca89-32b2-4dea-87a8-f94f9a2f7c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347087435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.347087435
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2442875316
Short name T129
Test name
Test status
Simulation time 17910009 ps
CPU time 0.75 seconds
Started Dec 20 12:24:36 PM PST 23
Finished Dec 20 12:25:11 PM PST 23
Peak memory 196308 kb
Host smart-a41db375-3c29-48da-aeaf-ac423ffff9c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442875316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2442875316
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4100465749
Short name T15
Test name
Test status
Simulation time 63694266 ps
CPU time 1.4 seconds
Started Dec 20 12:25:30 PM PST 23
Finished Dec 20 12:25:59 PM PST 23
Peak memory 197820 kb
Host smart-20e596b6-55cd-4406-83ec-7e3de3371325
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100465749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4100465749
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2265738255
Short name T123
Test name
Test status
Simulation time 55115583 ps
CPU time 0.61 seconds
Started Dec 20 12:24:36 PM PST 23
Finished Dec 20 12:25:14 PM PST 23
Peak memory 195688 kb
Host smart-49dce480-46d1-4901-bb0f-103691c92d5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265738255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2265738255
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.102818435
Short name T92
Test name
Test status
Simulation time 211300224 ps
CPU time 0.9 seconds
Started Dec 20 12:25:52 PM PST 23
Finished Dec 20 12:26:18 PM PST 23
Peak memory 199964 kb
Host smart-20cc46e2-2ae3-48d3-8373-46d36bd81fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102818435 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.102818435
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2813868049
Short name T32
Test name
Test status
Simulation time 128546707 ps
CPU time 0.55 seconds
Started Dec 20 12:24:26 PM PST 23
Finished Dec 20 12:24:59 PM PST 23
Peak memory 195660 kb
Host smart-a7986b1b-0c41-442f-ac36-c5510defee2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813868049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2813868049
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1243861780
Short name T162
Test name
Test status
Simulation time 49162655 ps
CPU time 0.55 seconds
Started Dec 20 12:24:37 PM PST 23
Finished Dec 20 12:25:10 PM PST 23
Peak memory 194536 kb
Host smart-5ff0b9bf-c51d-4cf3-b44c-ad0233119501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243861780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1243861780
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2014385469
Short name T28
Test name
Test status
Simulation time 26973326 ps
CPU time 0.69 seconds
Started Dec 20 12:24:56 PM PST 23
Finished Dec 20 12:25:23 PM PST 23
Peak memory 197008 kb
Host smart-6555fc03-19f6-45b1-bf62-bc4ac41fab28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014385469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2014385469
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1494701223
Short name T78
Test name
Test status
Simulation time 373441000 ps
CPU time 2.25 seconds
Started Dec 20 12:29:33 PM PST 23
Finished Dec 20 12:29:56 PM PST 23
Peak memory 199972 kb
Host smart-070b2062-a7e6-4860-94ca-673a62063dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494701223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1494701223
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2498326332
Short name T90
Test name
Test status
Simulation time 23492603 ps
CPU time 0.55 seconds
Started Dec 20 12:25:17 PM PST 23
Finished Dec 20 12:25:38 PM PST 23
Peak memory 194540 kb
Host smart-daa2a500-a4a2-4ab2-a66e-870f27e70fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498326332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2498326332
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.566158617
Short name T124
Test name
Test status
Simulation time 35619322 ps
CPU time 0.59 seconds
Started Dec 20 12:25:15 PM PST 23
Finished Dec 20 12:25:34 PM PST 23
Peak memory 194420 kb
Host smart-4c1e1048-50d0-4953-addd-d2eb135f0694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566158617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.566158617
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.567026168
Short name T155
Test name
Test status
Simulation time 37814740 ps
CPU time 0.54 seconds
Started Dec 20 12:24:27 PM PST 23
Finished Dec 20 12:25:00 PM PST 23
Peak memory 185292 kb
Host smart-d4544cff-b465-491d-90aa-148aaedb6a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567026168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.567026168
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3731238398
Short name T119
Test name
Test status
Simulation time 13022029 ps
CPU time 0.55 seconds
Started Dec 20 12:26:49 PM PST 23
Finished Dec 20 12:27:19 PM PST 23
Peak memory 185276 kb
Host smart-ab602347-3c02-4313-b8ff-0f5571a0171d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731238398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3731238398
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2827635163
Short name T147
Test name
Test status
Simulation time 27914660 ps
CPU time 0.54 seconds
Started Dec 20 12:24:18 PM PST 23
Finished Dec 20 12:24:53 PM PST 23
Peak memory 185264 kb
Host smart-19d714f3-b6a0-4562-a5ab-6e1da5c9a267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827635163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2827635163
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1375631577
Short name T145
Test name
Test status
Simulation time 41288076 ps
CPU time 0.53 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 185348 kb
Host smart-31564693-a4fa-43e1-a862-8a6ab0635bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375631577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1375631577
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1842216771
Short name T89
Test name
Test status
Simulation time 23803672 ps
CPU time 0.53 seconds
Started Dec 20 12:26:17 PM PST 23
Finished Dec 20 12:26:50 PM PST 23
Peak memory 185308 kb
Host smart-1e522c7c-df53-4eb5-85ec-577bb36fda7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842216771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1842216771
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2362548815
Short name T139
Test name
Test status
Simulation time 13457181 ps
CPU time 0.55 seconds
Started Dec 20 12:25:26 PM PST 23
Finished Dec 20 12:25:52 PM PST 23
Peak memory 185304 kb
Host smart-be1e363e-748c-406e-9f70-ba7021331242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362548815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2362548815
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3647451505
Short name T51
Test name
Test status
Simulation time 51354655 ps
CPU time 0.55 seconds
Started Dec 20 12:25:19 PM PST 23
Finished Dec 20 12:25:42 PM PST 23
Peak memory 185340 kb
Host smart-f334b610-1391-4e1e-8dd3-0cc0c3bbd703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647451505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3647451505
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4051128593
Short name T52
Test name
Test status
Simulation time 57699077 ps
CPU time 0.78 seconds
Started Dec 20 12:24:20 PM PST 23
Finished Dec 20 12:24:55 PM PST 23
Peak memory 196488 kb
Host smart-f05fc048-43e0-4769-b749-dd8cd671cf29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051128593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.4051128593
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1013564340
Short name T50
Test name
Test status
Simulation time 63343399 ps
CPU time 1.34 seconds
Started Dec 20 12:24:19 PM PST 23
Finished Dec 20 12:24:55 PM PST 23
Peak memory 197780 kb
Host smart-e5342831-3efa-46b7-8412-6935010b247e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013564340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1013564340
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1612694591
Short name T36
Test name
Test status
Simulation time 48809615 ps
CPU time 0.58 seconds
Started Dec 20 12:24:53 PM PST 23
Finished Dec 20 12:25:21 PM PST 23
Peak memory 195620 kb
Host smart-cc363cce-f163-4f2b-916b-6883f159c0c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612694591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1612694591
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.506346604
Short name T93
Test name
Test status
Simulation time 82998544 ps
CPU time 0.83 seconds
Started Dec 20 12:25:13 PM PST 23
Finished Dec 20 12:25:32 PM PST 23
Peak memory 200000 kb
Host smart-54144156-a940-4fbc-94f9-54cda8fe05b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506346604 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.506346604
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.523206574
Short name T39
Test name
Test status
Simulation time 38925459 ps
CPU time 0.61 seconds
Started Dec 20 12:24:25 PM PST 23
Finished Dec 20 12:24:58 PM PST 23
Peak memory 195620 kb
Host smart-a43d819b-5a4c-4b80-9e95-d3a056110579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523206574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.523206574
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3068345150
Short name T10
Test name
Test status
Simulation time 15944031 ps
CPU time 0.58 seconds
Started Dec 20 12:24:20 PM PST 23
Finished Dec 20 12:24:54 PM PST 23
Peak memory 185276 kb
Host smart-ef0076b5-3f35-4de6-a333-b2e057a2a065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068345150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3068345150
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2210451671
Short name T56
Test name
Test status
Simulation time 29005215 ps
CPU time 0.73 seconds
Started Dec 20 12:25:05 PM PST 23
Finished Dec 20 12:25:26 PM PST 23
Peak memory 196964 kb
Host smart-a07cc81d-506a-4d86-9300-abbf16e874ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210451671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2210451671
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2188835264
Short name T161
Test name
Test status
Simulation time 66109083 ps
CPU time 1.32 seconds
Started Dec 20 12:24:32 PM PST 23
Finished Dec 20 12:25:05 PM PST 23
Peak memory 200200 kb
Host smart-84f65999-fb22-42d8-978a-16761568ccc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188835264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2188835264
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1855608744
Short name T63
Test name
Test status
Simulation time 85225459 ps
CPU time 1.2 seconds
Started Dec 20 12:24:30 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 199136 kb
Host smart-ef08a272-d04c-4a0c-91f3-6774b61dad6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855608744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1855608744
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.652509137
Short name T106
Test name
Test status
Simulation time 13810290 ps
CPU time 0.6 seconds
Started Dec 20 12:25:53 PM PST 23
Finished Dec 20 12:26:18 PM PST 23
Peak memory 185352 kb
Host smart-027da561-6381-4091-94df-b5f62551e2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652509137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.652509137
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1435800236
Short name T159
Test name
Test status
Simulation time 25162651 ps
CPU time 0.56 seconds
Started Dec 20 12:26:09 PM PST 23
Finished Dec 20 12:26:37 PM PST 23
Peak memory 194536 kb
Host smart-89d6b91a-65bf-4576-8100-4e1787735fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435800236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1435800236
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3958209252
Short name T108
Test name
Test status
Simulation time 40965676 ps
CPU time 0.55 seconds
Started Dec 20 12:26:17 PM PST 23
Finished Dec 20 12:26:51 PM PST 23
Peak memory 194560 kb
Host smart-846e9e2c-a32f-433f-b02a-4acb2c407447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958209252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3958209252
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2544068275
Short name T116
Test name
Test status
Simulation time 190210368 ps
CPU time 0.57 seconds
Started Dec 20 12:25:06 PM PST 23
Finished Dec 20 12:25:27 PM PST 23
Peak memory 194488 kb
Host smart-e1f19d61-6a7b-4793-808f-b72cf356d108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544068275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2544068275
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2575704187
Short name T97
Test name
Test status
Simulation time 59267134 ps
CPU time 0.54 seconds
Started Dec 20 12:25:57 PM PST 23
Finished Dec 20 12:26:21 PM PST 23
Peak memory 185264 kb
Host smart-afa00fdd-d776-4d73-9ce8-06a6b46cecaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575704187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2575704187
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.541115989
Short name T103
Test name
Test status
Simulation time 44768156 ps
CPU time 0.6 seconds
Started Dec 20 12:25:39 PM PST 23
Finished Dec 20 12:26:08 PM PST 23
Peak memory 185300 kb
Host smart-9824bf65-fd3d-4f8c-9868-08b35b345ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541115989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.541115989
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2477018839
Short name T157
Test name
Test status
Simulation time 30212350 ps
CPU time 0.54 seconds
Started Dec 20 12:25:46 PM PST 23
Finished Dec 20 12:26:13 PM PST 23
Peak memory 194368 kb
Host smart-314dccbc-ec03-4a38-b570-815f2dc28ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477018839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2477018839
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3927016630
Short name T69
Test name
Test status
Simulation time 24053013 ps
CPU time 0.54 seconds
Started Dec 20 12:25:50 PM PST 23
Finished Dec 20 12:26:16 PM PST 23
Peak memory 185144 kb
Host smart-fc32222c-2660-4d6d-8e52-2b5637f53531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927016630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3927016630
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3643958671
Short name T110
Test name
Test status
Simulation time 16803076 ps
CPU time 0.58 seconds
Started Dec 20 12:25:55 PM PST 23
Finished Dec 20 12:26:20 PM PST 23
Peak memory 194536 kb
Host smart-bf204d94-7b83-4e0b-973e-a7c37414a79e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643958671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3643958671
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1974421480
Short name T160
Test name
Test status
Simulation time 21374236 ps
CPU time 1.12 seconds
Started Dec 20 12:24:30 PM PST 23
Finished Dec 20 12:25:02 PM PST 23
Peak memory 200208 kb
Host smart-3a6f8cb8-c7c0-4ee2-af9f-2106e68cdd15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974421480 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1974421480
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3960417796
Short name T30
Test name
Test status
Simulation time 13765937 ps
CPU time 0.59 seconds
Started Dec 20 12:25:20 PM PST 23
Finished Dec 20 12:25:43 PM PST 23
Peak memory 195676 kb
Host smart-184f0b68-b8bb-467b-9193-f619e1aefa3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960417796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3960417796
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1387866259
Short name T122
Test name
Test status
Simulation time 14736789 ps
CPU time 0.58 seconds
Started Dec 20 12:25:28 PM PST 23
Finished Dec 20 12:25:55 PM PST 23
Peak memory 194576 kb
Host smart-cf1702e5-6ec0-4bb1-a9b9-f6c929f1bd1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387866259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1387866259
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1683459643
Short name T27
Test name
Test status
Simulation time 102330760 ps
CPU time 0.76 seconds
Started Dec 20 12:25:14 PM PST 23
Finished Dec 20 12:25:33 PM PST 23
Peak memory 197236 kb
Host smart-d143893e-ad2f-4184-88e8-244eb4adb458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683459643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1683459643
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3293503743
Short name T100
Test name
Test status
Simulation time 123413989 ps
CPU time 1.88 seconds
Started Dec 20 12:24:27 PM PST 23
Finished Dec 20 12:25:01 PM PST 23
Peak memory 200284 kb
Host smart-ec5482c3-2aca-4323-9570-aa16795edfe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293503743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3293503743
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.252605627
Short name T4
Test name
Test status
Simulation time 137989662 ps
CPU time 0.97 seconds
Started Dec 20 12:24:18 PM PST 23
Finished Dec 20 12:24:54 PM PST 23
Peak memory 199140 kb
Host smart-e79517fd-d194-490e-bd3c-525b06aba083
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252605627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.252605627
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1937844863
Short name T126
Test name
Test status
Simulation time 77939587 ps
CPU time 0.72 seconds
Started Dec 20 12:25:23 PM PST 23
Finished Dec 20 12:25:53 PM PST 23
Peak memory 199844 kb
Host smart-dc1f9f82-ac10-4b4e-a222-03f787c828b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937844863 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1937844863
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3179905662
Short name T34
Test name
Test status
Simulation time 27133548 ps
CPU time 0.56 seconds
Started Dec 20 12:26:12 PM PST 23
Finished Dec 20 12:26:41 PM PST 23
Peak memory 195556 kb
Host smart-8d7e1f89-1044-4953-8b2a-4f4a00c26167
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179905662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3179905662
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1880307719
Short name T57
Test name
Test status
Simulation time 32266387 ps
CPU time 0.65 seconds
Started Dec 20 12:24:25 PM PST 23
Finished Dec 20 12:24:58 PM PST 23
Peak memory 195944 kb
Host smart-6b74d217-c5db-4def-9cea-c03a66be4971
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880307719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1880307719
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2212678331
Short name T105
Test name
Test status
Simulation time 64243634 ps
CPU time 1.42 seconds
Started Dec 20 12:26:21 PM PST 23
Finished Dec 20 12:26:55 PM PST 23
Peak memory 200228 kb
Host smart-ebdbd367-705f-460a-a4f7-2b88d6cf9ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212678331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2212678331
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3911711985
Short name T66
Test name
Test status
Simulation time 43596930 ps
CPU time 0.93 seconds
Started Dec 20 12:24:35 PM PST 23
Finished Dec 20 12:25:09 PM PST 23
Peak memory 198988 kb
Host smart-93177c39-666d-4e4d-9264-f4fb65ecc9ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911711985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3911711985
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1266870311
Short name T19
Test name
Test status
Simulation time 21775559 ps
CPU time 0.97 seconds
Started Dec 20 12:24:42 PM PST 23
Finished Dec 20 12:25:15 PM PST 23
Peak memory 199952 kb
Host smart-b790bc7a-c690-4db4-8714-426e1af984a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266870311 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1266870311
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1257276127
Short name T35
Test name
Test status
Simulation time 30239644 ps
CPU time 0.56 seconds
Started Dec 20 12:24:34 PM PST 23
Finished Dec 20 12:25:07 PM PST 23
Peak memory 195644 kb
Host smart-2865e03f-a69c-4d56-ae54-538c0309de9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257276127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1257276127
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2043715439
Short name T75
Test name
Test status
Simulation time 16328028 ps
CPU time 0.57 seconds
Started Dec 20 12:25:19 PM PST 23
Finished Dec 20 12:25:42 PM PST 23
Peak memory 185264 kb
Host smart-eaebd6e4-3b14-41d4-a5ff-004e52ff329c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043715439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2043715439
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1209121390
Short name T104
Test name
Test status
Simulation time 64680516 ps
CPU time 0.71 seconds
Started Dec 20 12:25:25 PM PST 23
Finished Dec 20 12:25:52 PM PST 23
Peak memory 196988 kb
Host smart-60bc4634-4f1e-4be1-811b-b0b7c92a87b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209121390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1209121390
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2171855190
Short name T137
Test name
Test status
Simulation time 86252456 ps
CPU time 1.84 seconds
Started Dec 20 12:24:35 PM PST 23
Finished Dec 20 12:25:10 PM PST 23
Peak memory 200212 kb
Host smart-564fef1b-2c98-44ea-8f22-e4e46033cb77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171855190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2171855190
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1335662361
Short name T146
Test name
Test status
Simulation time 253926080 ps
CPU time 1.15 seconds
Started Dec 20 12:25:19 PM PST 23
Finished Dec 20 12:25:43 PM PST 23
Peak memory 199252 kb
Host smart-4d607bc8-daf8-415d-8eb6-012df6e7ada0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335662361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1335662361
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.443493467
Short name T18
Test name
Test status
Simulation time 42465774 ps
CPU time 1.08 seconds
Started Dec 20 12:25:07 PM PST 23
Finished Dec 20 12:25:28 PM PST 23
Peak memory 200244 kb
Host smart-5a3a2a24-7dfa-49b8-a7a4-34d534776d8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443493467 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.443493467
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1545024794
Short name T130
Test name
Test status
Simulation time 12290210 ps
CPU time 0.61 seconds
Started Dec 20 12:24:49 PM PST 23
Finished Dec 20 12:25:19 PM PST 23
Peak memory 195580 kb
Host smart-e7d34137-4a9e-4642-9ff4-e4ae00607ec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545024794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1545024794
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3779126251
Short name T109
Test name
Test status
Simulation time 11486882 ps
CPU time 0.54 seconds
Started Dec 20 12:24:12 PM PST 23
Finished Dec 20 12:24:50 PM PST 23
Peak memory 185280 kb
Host smart-4a896ac3-1b49-47fe-b31e-7bf3df6d7a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779126251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3779126251
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1784722783
Short name T140
Test name
Test status
Simulation time 53058537 ps
CPU time 0.63 seconds
Started Dec 20 12:24:28 PM PST 23
Finished Dec 20 12:25:00 PM PST 23
Peak memory 195648 kb
Host smart-88d8eb2d-7608-408d-82c2-5842185dd7e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784722783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1784722783
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2942275737
Short name T84
Test name
Test status
Simulation time 54650372 ps
CPU time 1.54 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:04 PM PST 23
Peak memory 200212 kb
Host smart-3a093de8-9290-4788-95c9-5f71e93ce6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942275737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2942275737
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.379538233
Short name T47
Test name
Test status
Simulation time 171906973 ps
CPU time 1.17 seconds
Started Dec 20 12:24:28 PM PST 23
Finished Dec 20 12:25:02 PM PST 23
Peak memory 199196 kb
Host smart-bfea31c9-4d72-43f2-906a-b3ee1fa929b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379538233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.379538233
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1691177412
Short name T48
Test name
Test status
Simulation time 211283843 ps
CPU time 0.82 seconds
Started Dec 20 12:24:44 PM PST 23
Finished Dec 20 12:25:17 PM PST 23
Peak memory 199312 kb
Host smart-f521bb69-b312-435c-9eab-e16b4f944a64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691177412 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1691177412
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3409229523
Short name T37
Test name
Test status
Simulation time 41920513 ps
CPU time 0.63 seconds
Started Dec 20 12:24:23 PM PST 23
Finished Dec 20 12:24:56 PM PST 23
Peak memory 195640 kb
Host smart-5d8b83b6-e7fb-4fbb-a6cd-fe255e5875be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409229523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3409229523
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1316509924
Short name T96
Test name
Test status
Simulation time 64153740 ps
CPU time 0.72 seconds
Started Dec 20 12:24:29 PM PST 23
Finished Dec 20 12:25:01 PM PST 23
Peak memory 197332 kb
Host smart-1cb9b27e-a124-46c9-a453-a23bc193a8e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316509924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1316509924
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2040119894
Short name T16
Test name
Test status
Simulation time 416410576 ps
CPU time 1.99 seconds
Started Dec 20 12:25:36 PM PST 23
Finished Dec 20 12:26:07 PM PST 23
Peak memory 200100 kb
Host smart-d4d42a4b-b9f8-4a03-9c82-c12faad69ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040119894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2040119894
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2204603884
Short name T151
Test name
Test status
Simulation time 59494093 ps
CPU time 0.94 seconds
Started Dec 20 12:25:39 PM PST 23
Finished Dec 20 12:26:09 PM PST 23
Peak memory 199220 kb
Host smart-ada447ba-d78b-4fcf-a1d2-14ca7dee4cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204603884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2204603884
Directory /workspace/9.uart_tl_intg_err/latest
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