Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	347	1			T2	5		T3	1		T7	1
all_pins[1]	347	1			T2	5		T3	1		T7	1
all_pins[2]	347	1			T2	5		T3	1		T7	1
all_pins[3]	347	1			T2	5		T3	1		T7	1
all_pins[4]	347	1			T2	5		T3	1		T7	1
all_pins[5]	347	1			T2	5		T3	1		T7	1
all_pins[6]	347	1			T2	5		T3	1		T7	1
all_pins[7]	347	1			T2	5		T3	1		T7	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2251	1			T2	34		T3	8		T7	8
values[0x1]	525	1			T2	6		T9	6		T12	7
transitions[0x0=>0x1]	366	1			T2	5		T9	5		T12	5
transitions[0x1=>0x0]	380	1			T2	6		T9	6		T12	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	290	1			T2	5		T3	1		T7	1
all_pins[0]	values[0x1]	57	1			T9	1		T11	2		T13	2
all_pins[0]	transitions[0x0=>0x1]	40	1			T9	1		T11	1		T72	5
all_pins[0]	transitions[0x1=>0x0]	53	1			T2	4		T12	2		T10	1
all_pins[1]	values[0x0]	277	1			T2	1		T3	1		T7	1
all_pins[1]	values[0x1]	70	1			T2	4		T12	2		T10	1
all_pins[1]	transitions[0x0=>0x1]	53	1			T2	4		T12	2		T10	1
all_pins[1]	transitions[0x1=>0x0]	58	1			T12	1		T11	1		T13	1
all_pins[2]	values[0x0]	272	1			T2	5		T3	1		T7	1
all_pins[2]	values[0x1]	75	1			T12	1		T11	1		T13	1
all_pins[2]	transitions[0x0=>0x1]	56	1			T12	1		T11	1		T71	1
all_pins[2]	transitions[0x1=>0x0]	43	1			T10	1		T73	3		T13	1
all_pins[3]	values[0x0]	285	1			T2	5		T3	1		T7	1
all_pins[3]	values[0x1]	62	1			T10	1		T73	3		T13	2
all_pins[3]	transitions[0x0=>0x1]	46	1			T10	1		T73	3		T13	2
all_pins[3]	transitions[0x1=>0x0]	40	1			T2	1		T12	1		T71	2
all_pins[4]	values[0x0]	291	1			T2	4		T3	1		T7	1
all_pins[4]	values[0x1]	56	1			T2	1		T12	1		T71	3
all_pins[4]	transitions[0x0=>0x1]	45	1			T2	1		T72	1		T74	2
all_pins[4]	transitions[0x1=>0x0]	51	1			T9	2		T12	1		T10	2
all_pins[5]	values[0x0]	285	1			T2	5		T3	1		T7	1
all_pins[5]	values[0x1]	62	1			T9	2		T12	2		T10	2
all_pins[5]	transitions[0x0=>0x1]	41	1			T9	2		T12	2		T10	1
all_pins[5]	transitions[0x1=>0x0]	46	1			T10	1		T13	1		T71	2
all_pins[6]	values[0x0]	280	1			T2	5		T3	1		T7	1
all_pins[6]	values[0x1]	67	1			T10	2		T13	1		T71	3
all_pins[6]	transitions[0x0=>0x1]	39	1			T13	1		T71	3		T72	4
all_pins[6]	transitions[0x1=>0x0]	48	1			T2	1		T9	3		T12	1
all_pins[7]	values[0x0]	271	1			T2	4		T3	1		T7	1
all_pins[7]	values[0x1]	76	1			T2	1		T9	3		T12	1
all_pins[7]	transitions[0x0=>0x1]	46	1			T9	2		T10	3		T11	1
all_pins[7]	transitions[0x1=>0x0]	41	1			T9	1		T11	2		T13	2