Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T2	4		T9	4		T12	4
all_values[1]	278	1			T2	4		T9	4		T12	4
all_values[2]	278	1			T2	4		T9	4		T12	4
all_values[3]	278	1			T2	4		T9	4		T12	4
all_values[4]	278	1			T2	4		T9	4		T12	4
all_values[5]	278	1			T2	4		T9	4		T12	4
all_values[6]	278	1			T2	4		T9	4		T12	4
all_values[7]	278	1			T2	4		T9	4		T12	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1203

1

T2

22

T9

21

T12

14

auto[1]

1021

1

T2

10

T9

11

T12

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

855

1

T2

15

T9

15

T12

13

auto[1]

1369

1

T2

17

T9

17

T12

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1306

1

T2

20

T9

20

T12

21

auto[1]

918

1

T2

12

T9

12

T12

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	59	1			T2	2		T9	2		T12	2
all_values[0]	auto[0]	auto[0]	auto[1]	26	1			T10	2		T75	2		T51	1
all_values[0]	auto[0]	auto[1]	auto[0]	51	1			T2	1		T12	2		T11	3
all_values[0]	auto[0]	auto[1]	auto[1]	25	1			T9	1		T10	1		T11	1
all_values[0]	auto[1]	auto[0]	auto[1]	69	1			T2	1		T9	1		T10	3
all_values[0]	auto[1]	auto[1]	auto[1]	48	1			T11	2		T13	1		T72	2
all_values[1]	auto[0]	auto[0]	auto[0]	50	1			T9	2		T10	1		T11	1
all_values[1]	auto[0]	auto[0]	auto[1]	28	1			T12	1		T10	1		T11	1
all_values[1]	auto[0]	auto[1]	auto[0]	54	1			T9	1		T12	1		T10	2
all_values[1]	auto[0]	auto[1]	auto[1]	31	1			T2	2		T12	1		T73	1
all_values[1]	auto[1]	auto[0]	auto[1]	61	1			T2	1		T9	1		T12	1
all_values[1]	auto[1]	auto[1]	auto[1]	54	1			T2	1		T10	1		T73	1
all_values[2]	auto[0]	auto[0]	auto[0]	67	1			T2	3		T10	2		T11	1
all_values[2]	auto[0]	auto[0]	auto[1]	22	1			T10	1		T11	1		T73	1
all_values[2]	auto[0]	auto[1]	auto[0]	44	1			T9	2		T12	2		T10	2
all_values[2]	auto[0]	auto[1]	auto[1]	38	1			T72	1		T69	1		T76	3
all_values[2]	auto[1]	auto[0]	auto[1]	60	1			T2	1		T9	2		T10	2
all_values[2]	auto[1]	auto[1]	auto[1]	47	1			T12	2		T11	1		T13	2
all_values[3]	auto[0]	auto[0]	auto[0]	64	1			T2	1		T9	1		T10	1
all_values[3]	auto[0]	auto[0]	auto[1]	30	1			T2	1		T12	1		T10	3
all_values[3]	auto[0]	auto[1]	auto[0]	35	1			T2	1		T9	1		T12	2
all_values[3]	auto[0]	auto[1]	auto[1]	30	1			T73	1		T13	1		T71	1
all_values[3]	auto[1]	auto[0]	auto[1]	59	1			T9	2		T10	1		T11	2
all_values[3]	auto[1]	auto[1]	auto[1]	60	1			T2	1		T12	1		T10	2
all_values[4]	auto[0]	auto[0]	auto[0]	68	1			T2	2		T9	2		T12	1
all_values[4]	auto[0]	auto[0]	auto[1]	28	1			T10	1		T73	1		T72	2
all_values[4]	auto[0]	auto[1]	auto[0]	47	1			T9	1		T11	3		T13	1
all_values[4]	auto[0]	auto[1]	auto[1]	25	1			T12	1		T71	1		T74	1
all_values[4]	auto[1]	auto[0]	auto[1]	59	1			T2	1		T9	1		T12	1
all_values[4]	auto[1]	auto[1]	auto[1]	51	1			T2	1		T12	1		T10	1
all_values[5]	auto[0]	auto[0]	auto[0]	56	1			T2	1		T9	2		T11	1
all_values[5]	auto[0]	auto[0]	auto[1]	27	1			T2	1		T12	1		T10	2
all_values[5]	auto[0]	auto[1]	auto[0]	49	1			T11	2		T13	2		T71	1
all_values[5]	auto[0]	auto[1]	auto[1]	27	1			T9	1		T12	1		T11	2
all_values[5]	auto[1]	auto[0]	auto[1]	67	1			T2	1		T9	1		T10	3
all_values[5]	auto[1]	auto[1]	auto[1]	52	1			T2	1		T12	2		T10	2
all_values[6]	auto[0]	auto[0]	auto[0]	61	1			T2	3		T12	1		T10	1
all_values[6]	auto[0]	auto[0]	auto[1]	34	1			T9	1		T12	1		T13	2
all_values[6]	auto[0]	auto[1]	auto[0]	46	1			T2	1		T9	1		T12	1
all_values[6]	auto[0]	auto[1]	auto[1]	29	1			T71	1		T72	2		T69	1
all_values[6]	auto[1]	auto[0]	auto[1]	63	1			T9	1		T12	1		T10	1
all_values[6]	auto[1]	auto[1]	auto[1]	45	1			T9	1		T10	2		T71	2
all_values[7]	auto[0]	auto[0]	auto[0]	55	1			T12	1		T10	1		T11	4
all_values[7]	auto[0]	auto[0]	auto[1]	24	1			T2	1		T9	1		T12	1
all_values[7]	auto[0]	auto[1]	auto[0]	49	1			T13	3		T71	2		T72	1
all_values[7]	auto[0]	auto[1]	auto[1]	27	1			T9	1		T10	1		T11	1
all_values[7]	auto[1]	auto[0]	auto[1]	66	1			T2	2		T9	1		T12	1
all_values[7]	auto[1]	auto[1]	auto[1]	57	1			T2	1		T9	1		T12	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal