UART Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	28.460s	6.063ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	50.085us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.620s	25.216us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.320s	57.157us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.700s	14.465us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.460s	99.153us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.620s	25.216us	20	20	100.00
		uart_csr_aliasing	0.700s	14.465us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.226m	68.660ms	50	50	100.00
V2	parity	uart_smoke	28.460s	6.063ms	50	50	100.00
		uart_tx_rx	2.226m	68.660ms	50	50	100.00
V2	parity_error	uart_intr	51.792m	2.418s	47	50	94.00
		uart_rx_parity_err	17.397m	125.263ms	49	50	98.00
V2	watermark	uart_tx_rx	2.226m	68.660ms	50	50	100.00
		uart_intr	51.792m	2.418s	47	50	94.00
V2	fifo_full	uart_fifo_full	5.381m	280.486ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.823m	191.917ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.923m	156.790ms	300	300	100.00
V2	rx_frame_err	uart_intr	51.792m	2.418s	47	50	94.00
V2	rx_break_err	uart_intr	51.792m	2.418s	47	50	94.00
V2	rx_timeout	uart_intr	51.792m	2.418s	47	50	94.00
V2	perf	uart_perf	25.531m	29.289ms	50	50	100.00
V2	sys_loopback	uart_loopback	33.850s	13.630ms	43	50	86.00
V2	line_loopback	uart_loopback	33.850s	13.630ms	43	50	86.00
V2	rx_noise_filter	uart_noise_filter	5.032m	125.896ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.678m	69.951ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	24.780s	6.673ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	44.240s	4.269ms	40	50	80.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	22.655m	173.478ms	49	50	98.00
V2	stress_all	uart_stress_all	31.336m	284.122ms	49	50	98.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	30.439m	264.919ms	99	100	99.00
V2	alert_test	uart_alert_test	0.600s	14.834us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	29.551us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.260s	455.358us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.260s	455.358us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	50.085us	5	5	100.00
		uart_csr_rw	0.620s	25.216us	20	20	100.00
		uart_csr_aliasing	0.700s	14.465us	5	5	100.00
		uart_same_csr_outstanding	0.800s	306.514us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	50.085us	5	5	100.00
		uart_csr_rw	0.620s	25.216us	20	20	100.00
		uart_csr_aliasing	0.700s	14.465us	5	5	100.00
		uart_same_csr_outstanding	0.800s	306.514us	20	20	100.00
V2		TOTAL			1166	1190	97.98
V2S	tl_intg_err	uart_sec_cm	0.890s	59.708us	5	5	100.00
		uart_tl_intg_err	1.330s	928.903us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.330s	928.903us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1296	1320	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	12	63.16
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.30	99.79	98.45	100.00	--	99.76	100.00	97.77

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 10 failures:

Test uart_rx_oversample has 10 failures.

6.uart_rx_oversample.27013015705644239926745501844634232091900419381038843570210680813382532604240
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 340508318 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (3680 [0xe60] vs 2612 [0xa34]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 349151227 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (40699 [0x9efb] vs 24441 [0x5f79]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 357481242 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/6
  UVM_ERROR @ 357936994 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (15615 [0x3cff] vs 39547 [0x9a7b]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 371937078 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (44595 [0xae33] vs 55131 [0xd75b]) Regname: uart_reg_block.val.rx reset value: 0x0

14.uart_rx_oversample.96105977551068559885864149411937083928070306779470065796782382234991430264548
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 1682736561 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (47210 [0xb86a] vs 47194 [0xb85a]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 1691176895 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 9/11
  UVM_ERROR @ 1691463921 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (31503 [0x7b0f] vs 31375 [0x7a8f]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 2111569154 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 10/11
  UVM_INFO @ 2326921865 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 11/11

... and 8 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 6 failures:

Test uart_loopback has 5 failures.

17.uart_loopback.1822440569387547178636752625478965311048235610549749774774373950547687053260
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_loopback/latest/run.log

  UVM_ERROR @ 663871884 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (218 [0xda] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 663871884 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 218 [0xda]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 663934386 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/7
  UVM_INFO @ 1717176422 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/7
  UVM_INFO @ 2382874807 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/7

34.uart_loopback.46383090277186187512570874788838838990619085272508965100419033582976425740687
Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/34.uart_loopback/latest/run.log

  UVM_ERROR @ 5952455477 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (136 [0x88] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 5952455477 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 136 [0x88]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 5952669761 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/14
  UVM_INFO @ 7098732021 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/14
  UVM_INFO @ 7943832403 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 12/14

... and 3 more failures.

Test uart_stress_all_with_rand_reset has 1 failures.

18.uart_stress_all_with_rand_reset.110880602935477450794539485234846115211441403830403715653225334663246366654180
Line 463, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 48634445093 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (46 [0x2e] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 48634445093 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 46 [0x2e]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 48635278433 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/12
  UVM_INFO @ 48649278545 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 12/12
  UVM_ERROR @ 48671820392 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test uart_intr has 2 failures.

8.uart_intr.104813615248288550452338724797173325991741240308238733384275299458244721199529
Line 284, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_intr/latest/run.log

  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.uart_intr.63871171412895107693988535825022280059386374058422050268191631427876107724177
Line 260, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/28.uart_intr/latest/run.log

  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test uart_rx_parity_err has 1 failures.

12.uart_rx_parity_err.115067526388049255878131462385453350953696743839384057742050981122327179022095
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_rx_parity_err/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:

Test uart_loopback has 2 failures.

15.uart_loopback.77276044203555302652156632896504306663438021128286613583468159658856870670406
Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_loopback/latest/run.log

  UVM_ERROR @ 10729689021 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 10729689021 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 10729689021 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 10729689021 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
  UVM_INFO @ 10734751521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

18.uart_loopback.13818741917791374297363573137987862588152877963420170253979683419288507176498
Line 267, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_loopback/latest/run.log

  UVM_ERROR @ 11395510270 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 11395510270 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 11400676938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 1 failures:

Test uart_stress_all has 1 failures.

15.uart_stress_all.33447932648620776877153963791526933000544422228394549357239894578004917826032
Line 278, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_stress_all/latest/run.log

  UVM_ERROR @ 182376806668 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 182376806668 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
  UVM_INFO @ 182398334578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_intr has 1 failures.
  - 31.uart_intr.2428124601004359379300510013496337529091962913784558431727763423460331298225
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_intr/latest/run.log
```
  Job ID: smart:617a67c0-a561-48dc-af0a-73155117e20e
```

UVM_ERROR (uart_scoreboard.sv:380) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

34.uart_long_xfer_wo_dly.34134865431509212130960443765940530109495831327476188221948532499894108727277
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 38880222187 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 38959222819 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 39374932027 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 39442109035 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 39948583675 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1