Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15379	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

20295

1

T1

132

T2

71

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18091	1			T1	441		T2	232		T3	20
values[0x0]	8580	1			T1	103		T2	48		T3	12
values[0x1]	9003	1			T1	99		T2	53		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11225	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24449

1

T1

286

T2

151

T3

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	89	1			T1	6		T6	1		T14	1
valid_sources[0x01]	93	1			T1	1		T14	1		T26	1
valid_sources[0x02]	171	1			T1	1		T6	1		T11	1
valid_sources[0x03]	169	1			T1	3		T6	1		T11	2
valid_sources[0x04]	116	1			T1	2		T11	1		T14	1
valid_sources[0x05]	171	1			T1	3		T5	1		T6	1
valid_sources[0x06]	145	1			T1	5		T2	5		T14	1
valid_sources[0x07]	273	1			T1	2		T3	1		T11	1
valid_sources[0x08]	121	1			T1	2		T14	4		T32	2
valid_sources[0x09]	156	1			T1	1		T3	1		T15	6
valid_sources[0x0a]	297	1			T1	1		T6	1		T42	1
valid_sources[0x0b]	132	1			T1	4		T11	1		T14	2
valid_sources[0x0c]	108	1			T2	1		T34	1		T15	1
valid_sources[0x0d]	129	1			T1	2		T6	2		T14	2
valid_sources[0x0e]	115	1			T1	1		T14	3		T26	3
valid_sources[0x0f]	135	1			T1	2		T14	2		T26	15
valid_sources[0x10]	160	1			T1	4		T2	5		T34	1
valid_sources[0x11]	155	1			T1	7		T2	7		T6	1
valid_sources[0x12]	125	1			T1	2		T42	4		T16	1
valid_sources[0x13]	156	1			T1	4		T2	3		T11	1
valid_sources[0x14]	165	1			T1	1		T2	1		T6	2
valid_sources[0x15]	114	1			T1	3		T11	2		T14	1
valid_sources[0x16]	111	1			T1	3		T11	1		T14	1
valid_sources[0x17]	95	1			T1	4		T3	2		T11	3
valid_sources[0x18]	137	1			T2	4		T14	2		T34	1
valid_sources[0x19]	107	1			T1	2		T6	2		T14	1
valid_sources[0x1a]	124	1			T1	3		T6	1		T11	1
valid_sources[0x1b]	108	1			T1	1		T2	1		T6	1
valid_sources[0x1c]	88	1			T1	3		T3	1		T6	1
valid_sources[0x1d]	183	1			T1	2		T5	1		T6	2
valid_sources[0x1e]	76	1			T1	2		T8	1		T26	3
valid_sources[0x1f]	96	1			T1	3		T11	3		T14	1
valid_sources[0x20]	98	1			T1	1		T14	3		T27	1
valid_sources[0x21]	143	1			T1	2		T14	3		T42	3
valid_sources[0x22]	79	1			T1	1		T5	1		T11	1
valid_sources[0x23]	122	1			T11	1		T26	1		T15	6
valid_sources[0x24]	160	1			T1	1		T27	1		T15	1
valid_sources[0x25]	97	1			T1	1		T6	1		T14	2
valid_sources[0x26]	149	1			T1	2		T2	4		T11	3
valid_sources[0x27]	103	1			T1	4		T14	2		T34	1
valid_sources[0x28]	130	1			T1	2		T2	5		T42	1
valid_sources[0x29]	176	1			T14	2		T26	1		T41	2
valid_sources[0x2a]	159	1			T1	1		T11	1		T14	3
valid_sources[0x2b]	140	1			T1	1		T2	12		T14	1
valid_sources[0x2c]	113	1			T6	1		T14	2		T25	6
valid_sources[0x2d]	99	1			T1	1		T6	1		T34	2
valid_sources[0x2e]	126	1			T1	2		T14	3		T26	1
valid_sources[0x2f]	218	1			T1	2		T2	4		T15	1
valid_sources[0x30]	156	1			T1	5		T11	1		T8	3
valid_sources[0x31]	154	1			T1	1		T2	4		T3	1
valid_sources[0x32]	106	1			T1	2		T5	1		T11	2
valid_sources[0x33]	115	1			T1	2		T2	1		T14	2
valid_sources[0x34]	108	1			T1	4		T11	1		T14	2
valid_sources[0x35]	153	1			T1	1		T14	1		T16	2
valid_sources[0x36]	441	1			T1	5		T2	2		T11	1
valid_sources[0x37]	162	1			T1	1		T6	1		T34	1
valid_sources[0x38]	121	1			T1	3		T2	14		T11	1
valid_sources[0x39]	182	1			T1	2		T14	1		T32	1
valid_sources[0x3a]	133	1			T1	3		T11	1		T14	4
valid_sources[0x3b]	160	1			T1	7		T8	2		T41	1
valid_sources[0x3c]	213	1			T1	5		T2	7		T14	3
valid_sources[0x3d]	123	1			T1	4		T14	4		T33	2
valid_sources[0x3e]	192	1			T1	3		T6	1		T14	1
valid_sources[0x3f]	192	1			T6	1		T11	1		T14	3
valid_sources[0x40]	121	1			T1	5		T11	1		T14	1
valid_sources[0x41]	77	1			T1	1		T6	1		T14	1
valid_sources[0x42]	142	1			T1	6		T6	1		T11	2
valid_sources[0x43]	178	1			T1	4		T6	1		T42	2
valid_sources[0x44]	115	1			T4	1		T41	4		T15	3
valid_sources[0x45]	124	1			T1	3		T42	1		T16	5
valid_sources[0x46]	138	1			T1	1		T2	3		T11	2
valid_sources[0x47]	125	1			T1	1		T14	2		T26	1
valid_sources[0x48]	159	1			T1	2		T6	1		T14	2
valid_sources[0x49]	108	1			T1	5		T2	3		T14	3
valid_sources[0x4a]	136	1			T1	5		T2	10		T34	1
valid_sources[0x4b]	126	1			T1	2		T6	3		T14	1
valid_sources[0x4c]	206	1			T1	1		T11	1		T14	3
valid_sources[0x4d]	139	1			T1	2		T6	1		T14	4
valid_sources[0x4e]	204	1			T1	2		T2	1		T14	2
valid_sources[0x4f]	190	1			T1	1		T6	1		T32	2
valid_sources[0x50]	139	1			T1	5		T6	2		T14	3
valid_sources[0x51]	111	1			T1	7		T6	1		T8	5
valid_sources[0x52]	114	1			T1	1		T3	1		T34	1
valid_sources[0x53]	128	1			T11	8		T14	1		T41	1
valid_sources[0x54]	196	1			T1	1		T2	2		T13	12
valid_sources[0x55]	91	1			T1	2		T6	1		T42	1
valid_sources[0x56]	176	1			T1	3		T3	2		T11	1
valid_sources[0x57]	159	1			T1	5		T11	1		T14	1
valid_sources[0x58]	111	1			T1	1		T2	2		T14	2
valid_sources[0x59]	118	1			T1	6		T14	2		T34	1
valid_sources[0x5a]	154	1			T1	3		T14	3		T10	22
valid_sources[0x5b]	136	1			T1	4		T11	5		T14	1
valid_sources[0x5c]	185	1			T1	1		T2	16		T11	1
valid_sources[0x5d]	89	1			T1	1		T6	1		T14	1
valid_sources[0x5e]	274	1			T1	7		T2	2		T13	12
valid_sources[0x5f]	112	1			T1	5		T6	1		T14	2
valid_sources[0x60]	134	1			T1	1		T8	1		T14	3
valid_sources[0x61]	92	1			T1	3		T11	2		T14	2
valid_sources[0x62]	156	1			T1	5		T2	3		T6	1
valid_sources[0x63]	114	1			T1	6		T6	1		T14	1
valid_sources[0x64]	112	1			T1	4		T2	4		T3	1
valid_sources[0x65]	143	1			T1	5		T2	5		T11	2
valid_sources[0x66]	128	1			T1	1		T5	1		T11	3
valid_sources[0x67]	126	1			T1	2		T2	4		T6	2
valid_sources[0x68]	180	1			T1	6		T2	1		T14	2
valid_sources[0x69]	133	1			T2	8		T11	2		T15	3
valid_sources[0x6a]	134	1			T1	3		T5	1		T6	1
valid_sources[0x6b]	161	1			T1	6		T2	2		T6	1
valid_sources[0x6c]	156	1			T1	2		T7	14		T11	1
valid_sources[0x6d]	106	1			T1	3		T14	3		T4	7
valid_sources[0x6e]	140	1			T1	7		T6	1		T11	2
valid_sources[0x6f]	147	1			T1	2		T6	2		T34	2
valid_sources[0x70]	105	1			T1	6		T5	1		T14	3
valid_sources[0x71]	158	1			T1	1		T13	12		T14	2
valid_sources[0x72]	118	1			T1	3		T8	1		T14	2
valid_sources[0x73]	106	1			T1	2		T14	1		T16	4
valid_sources[0x74]	110	1			T14	1		T34	1		T15	1
valid_sources[0x75]	118	1			T1	3		T5	1		T11	2
valid_sources[0x76]	139	1			T1	4		T14	2		T34	1
valid_sources[0x77]	146	1			T1	3		T2	5		T6	1
valid_sources[0x78]	191	1			T1	2		T11	1		T14	1
valid_sources[0x79]	100	1			T14	1		T34	1		T16	3
valid_sources[0x7a]	152	1			T1	2		T3	1		T5	1
valid_sources[0x7b]	108	1			T1	4		T6	2		T14	2
valid_sources[0x7c]	145	1			T1	1		T2	1		T6	1
valid_sources[0x7d]	140	1			T1	2		T3	2		T12	1
valid_sources[0x7e]	118	1			T11	1		T12	4		T14	1
valid_sources[0x7f]	186	1			T1	1		T6	1		T14	1
valid_sources[0x80]	160	1			T1	2		T2	2		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8138

1

T1

39

T2

19

T3

11

values[0x0]

all_enables

biggest_size

6442

1

T1

53

T2

29

T3

6

values[0x1]

all_enables

biggest_size

5715

1

T1

40

T2

23

T3

2