Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
33.14	0.00	0.00	99.43				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	512269	9459	0	0
ctrl_rd_A	512269	2699	0	0
intr_enable_rd_A	512269	2510	0	0
ovrd_rd_A	512269	1642	0	0
timeout_ctrl_rd_A	512269	1673	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512269	9459	0	0
T1	8288	4	0	0
T2	4563	1	0	0
T3	690	0	0	0
T5	1360	0	0	0
T6	2536	254	0	0
T7	860	0	0	0
T9	1081	0	0	0
T11	3036	502	0	0
T12	830	0	0	0
T13	1421	0	0	0
T14	0	262	0	0
T15	0	451	0	0
T16	0	345	0	0
T17	0	2	0	0
T18	0	10	0	0
T42	0	34	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512269	2699	0	0
T1	8288	342	0	0
T2	4563	0	0	0
T3	690	0	0	0
T4	0	5	0	0
T5	1360	0	0	0
T6	2536	0	0	0
T7	860	0	0	0
T9	1081	0	0	0
T11	3036	0	0	0
T12	830	0	0	0
T13	1421	0	0	0
T15	0	9	0	0
T17	0	40	0	0
T23	0	21	0	0
T25	0	14	0	0
T26	0	47	0	0
T27	0	16	0	0
T33	0	39	0	0
T34	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512269	2510	0	0
T1	8288	437	0	0
T2	4563	0	0	0
T3	690	0	0	0
T5	1360	0	0	0
T6	2536	0	0	0
T7	860	0	0	0
T9	1081	0	0	0
T11	3036	0	0	0
T12	830	0	0	0
T13	1421	0	0	0
T15	0	24	0	0
T17	0	69	0	0
T23	0	3	0	0
T25	0	15	0	0
T26	0	48	0	0
T33	0	7	0	0
T34	0	8	0	0
T41	0	24	0	0
T43	0	6	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512269	1642	0	0
T1	8288	118	0	0
T2	4563	0	0	0
T3	690	0	0	0
T4	0	9	0	0
T5	1360	0	0	0
T6	2536	0	0	0
T7	860	0	0	0
T9	1081	0	0	0
T11	3036	0	0	0
T12	830	0	0	0
T13	1421	0	0	0
T15	0	22	0	0
T17	0	19	0	0
T18	0	11	0	0
T23	0	15	0	0
T27	0	7	0	0
T29	0	30	0	0
T33	0	3	0	0
T34	0	5	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512269	1673	0	0
T1	8288	143	0	0
T2	4563	0	0	0
T3	690	0	0	0
T5	1360	0	0	0
T6	2536	0	0	0
T7	860	0	0	0
T9	1081	0	0	0
T11	3036	0	0	0
T12	830	0	0	0
T13	1421	0	0	0
T15	0	27	0	0
T17	0	34	0	0
T23	0	8	0	0
T25	0	6	0	0
T26	0	46	0	0
T27	0	9	0	0
T29	0	64	0	0
T33	0	10	0	0
T34	0	15	0	0