Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15635	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

20650

1

T1

504

T2

9

T3

184

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18447	1			T1	180		T2	20		T3	93
values[0x0]	8726	1			T1	193		T2	8		T3	53
values[0x1]	9112	1			T1	200		T2	12		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11417	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24868

1

T1

520

T2

16

T3

184

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	97	1			T1	2		T7	1		T5	4
valid_sources[0x01]	113	1			T1	1		T5	8		T13	3
valid_sources[0x02]	121	1			T1	1		T4	16		T5	2
valid_sources[0x03]	206	1			T1	1		T5	2		T13	2
valid_sources[0x04]	239	1			T1	4		T5	2		T13	3
valid_sources[0x05]	225	1			T8	1		T13	2		T14	1
valid_sources[0x06]	65	1			T1	4		T2	1		T7	1
valid_sources[0x07]	101	1			T1	3		T5	11		T13	2
valid_sources[0x08]	106	1			T1	5		T3	9		T13	1
valid_sources[0x09]	168	1			T1	3		T3	6		T4	57
valid_sources[0x0a]	276	1			T1	4		T2	1		T4	10
valid_sources[0x0b]	82	1			T1	1		T5	1		T13	3
valid_sources[0x0c]	112	1			T1	1		T5	1		T13	2
valid_sources[0x0d]	149	1			T5	2		T8	1		T13	5
valid_sources[0x0e]	216	1			T1	5		T7	1		T13	3
valid_sources[0x0f]	66	1			T1	3		T5	3		T8	1
valid_sources[0x10]	142	1			T7	1		T5	1		T12	2
valid_sources[0x11]	123	1			T1	7		T3	4		T5	1
valid_sources[0x12]	89	1			T1	1		T7	1		T5	3
valid_sources[0x13]	137	1			T1	1		T3	3		T5	6
valid_sources[0x14]	117	1			T1	2		T13	3		T14	1
valid_sources[0x15]	109	1			T1	1		T13	5		T29	3
valid_sources[0x16]	134	1			T5	6		T12	7		T13	2
valid_sources[0x17]	82	1			T1	3		T2	1		T7	1
valid_sources[0x18]	67	1			T3	1		T7	1		T5	8
valid_sources[0x19]	122	1			T1	7		T7	1		T5	1
valid_sources[0x1a]	112	1			T1	3		T5	2		T12	4
valid_sources[0x1b]	83	1			T1	1		T3	5		T13	4
valid_sources[0x1c]	212	1			T1	2		T7	2		T8	1
valid_sources[0x1d]	81	1			T1	1		T5	4		T13	4
valid_sources[0x1e]	118	1			T1	2		T2	1		T7	2
valid_sources[0x1f]	146	1			T5	2		T12	9		T13	2
valid_sources[0x20]	88	1			T1	1		T7	1		T5	4
valid_sources[0x21]	101	1			T1	2		T3	3		T7	1
valid_sources[0x22]	66	1			T1	3		T3	2		T7	1
valid_sources[0x23]	86	1			T1	8		T7	1		T5	4
valid_sources[0x24]	98	1			T1	1		T13	3		T15	3
valid_sources[0x25]	64	1			T1	3		T3	5		T13	4
valid_sources[0x26]	242	1			T1	4		T5	9		T13	3
valid_sources[0x27]	93	1			T1	2		T5	3		T8	1
valid_sources[0x28]	113	1			T5	13		T13	1		T22	2
valid_sources[0x29]	133	1			T1	8		T5	3		T13	2
valid_sources[0x2a]	394	1			T1	1		T3	5		T13	4
valid_sources[0x2b]	101	1			T7	1		T5	3		T13	3
valid_sources[0x2c]	89	1			T1	4		T3	4		T5	5
valid_sources[0x2d]	218	1			T4	9		T5	1		T13	1
valid_sources[0x2e]	90	1			T1	4		T5	2		T11	2
valid_sources[0x2f]	76	1			T2	1		T13	3		T14	1
valid_sources[0x30]	97	1			T1	1		T7	1		T5	6
valid_sources[0x31]	113	1			T1	1		T2	2		T7	1
valid_sources[0x32]	72	1			T7	1		T5	4		T8	1
valid_sources[0x33]	133	1			T1	4		T4	36		T5	3
valid_sources[0x34]	94	1			T1	1		T3	1		T13	2
valid_sources[0x35]	257	1			T1	2		T13	4		T23	2
valid_sources[0x36]	75	1			T13	6		T26	2		T54	5
valid_sources[0x37]	204	1			T1	2		T7	1		T5	7
valid_sources[0x38]	124	1			T5	3		T13	4		T23	2
valid_sources[0x39]	235	1			T1	2		T2	1		T5	2
valid_sources[0x3a]	76	1			T1	3		T7	1		T5	1
valid_sources[0x3b]	360	1			T1	2		T7	1		T5	7
valid_sources[0x3c]	299	1			T5	6		T13	1		T22	2
valid_sources[0x3d]	134	1			T3	3		T5	2		T13	2
valid_sources[0x3e]	114	1			T1	5		T7	1		T4	16
valid_sources[0x3f]	125	1			T1	4		T7	1		T5	4
valid_sources[0x40]	82	1			T1	3		T5	2		T13	1
valid_sources[0x41]	140	1			T5	1		T13	3		T22	2
valid_sources[0x42]	116	1			T1	3		T4	3		T5	5
valid_sources[0x43]	126	1			T1	3		T3	5		T5	7
valid_sources[0x44]	99	1			T7	2		T13	4		T9	16
valid_sources[0x45]	93	1			T1	2		T5	2		T13	8
valid_sources[0x46]	199	1			T1	4		T5	2		T13	1
valid_sources[0x47]	101	1			T1	2		T3	3		T13	6
valid_sources[0x48]	98	1			T1	4		T5	13		T13	6
valid_sources[0x49]	69	1			T1	5		T5	3		T13	2
valid_sources[0x4a]	175	1			T1	1		T4	8		T13	4
valid_sources[0x4b]	67	1			T1	2		T3	5		T5	2
valid_sources[0x4c]	144	1			T1	1		T5	8		T13	3
valid_sources[0x4d]	129	1			T1	6		T3	3		T4	3
valid_sources[0x4e]	69	1			T1	2		T5	3		T13	5
valid_sources[0x4f]	74	1			T1	2		T13	4		T22	1
valid_sources[0x50]	244	1			T2	1		T3	5		T13	1
valid_sources[0x51]	281	1			T1	2		T5	2		T13	5
valid_sources[0x52]	250	1			T1	2		T13	5		T22	1
valid_sources[0x53]	196	1			T1	3		T3	2		T5	5
valid_sources[0x54]	77	1			T5	1		T13	5		T14	4
valid_sources[0x55]	106	1			T1	3		T5	2		T13	6
valid_sources[0x56]	269	1			T3	7		T5	5		T13	1
valid_sources[0x57]	84	1			T1	3		T3	11		T5	1
valid_sources[0x58]	106	1			T1	3		T5	3		T13	3
valid_sources[0x59]	391	1			T1	3		T5	1		T13	5
valid_sources[0x5a]	271	1			T5	2		T12	77		T13	2
valid_sources[0x5b]	60	1			T1	2		T5	2		T8	1
valid_sources[0x5c]	115	1			T1	2		T7	1		T5	4
valid_sources[0x5d]	184	1			T1	3		T5	4		T13	3
valid_sources[0x5e]	103	1			T7	1		T5	3		T14	3
valid_sources[0x5f]	95	1			T1	2		T7	2		T5	4
valid_sources[0x60]	153	1			T1	3		T2	1		T4	11
valid_sources[0x61]	112	1			T1	2		T5	4		T12	9
valid_sources[0x62]	231	1			T3	3		T13	3		T15	2
valid_sources[0x63]	75	1			T1	3		T5	1		T13	3
valid_sources[0x64]	211	1			T1	2		T13	3		T14	1
valid_sources[0x65]	170	1			T1	1		T13	6		T10	40
valid_sources[0x66]	99	1			T1	1		T5	3		T8	1
valid_sources[0x67]	73	1			T1	2		T3	1		T7	1
valid_sources[0x68]	100	1			T1	5		T13	5		T14	1
valid_sources[0x69]	274	1			T1	10		T13	2		T22	1
valid_sources[0x6a]	114	1			T1	1		T7	1		T13	3
valid_sources[0x6b]	76	1			T1	1		T2	2		T13	4
valid_sources[0x6c]	105	1			T13	1		T14	1		T15	3
valid_sources[0x6d]	185	1			T7	1		T13	2		T14	1
valid_sources[0x6e]	139	1			T1	3		T2	5		T5	7
valid_sources[0x6f]	78	1			T1	3		T7	1		T5	1
valid_sources[0x70]	77	1			T7	1		T5	1		T13	8
valid_sources[0x71]	96	1			T1	6		T3	3		T5	4
valid_sources[0x72]	125	1			T1	1		T2	1		T3	3
valid_sources[0x73]	89	1			T2	1		T13	3		T22	2
valid_sources[0x74]	123	1			T1	3		T5	1		T13	1
valid_sources[0x75]	81	1			T1	1		T7	1		T5	1
valid_sources[0x76]	136	1			T1	1		T5	2		T13	3
valid_sources[0x77]	164	1			T1	6		T4	68		T5	2
valid_sources[0x78]	143	1			T1	5		T3	3		T11	2
valid_sources[0x79]	198	1			T1	4		T5	1		T13	3
valid_sources[0x7a]	257	1			T1	1		T3	6		T5	8
valid_sources[0x7b]	199	1			T1	3		T5	3		T13	3
valid_sources[0x7c]	78	1			T1	3		T4	4		T5	1
valid_sources[0x7d]	174	1			T1	1		T4	41		T5	1
valid_sources[0x7e]	130	1			T7	1		T4	7		T13	1
valid_sources[0x7f]	65	1			T1	1		T5	1		T13	3
valid_sources[0x80]	127	1			T1	1		T12	16		T13	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8104

1

T1

131

T2

7

T3

92

values[0x0]

all_enables

biggest_size

6630

1

T1

189

T3

53

T6

2

values[0x1]

all_enables

biggest_size

5916

1

T1

184

T2

2

T3

39