Unified Coverage Report :: Module :: uart_tx

Module : uart_tx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_core.uart_tx	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.uart_core.uart_tx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		uart_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : uart_tx

	Line No.	Total	Covered	Percent
TOTAL		29	0	0.00
CONT_ASSIGN	32	1	0	0.00
ALWAYS	35	6	0	0.00
ALWAYS	46	7	0	0.00
ALWAYS	58	14	0	0.00
CONT_ASSIGN	77	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
35	0	1
36	0	1
37	0	1
38	0	1
39	0	1
41	0	1
46	0	1
47	0	1
48	0	1
49	0	1
51	0	1
52	0	1
53	0	1
58	0	1
59	0	1
60	0	1
61	0	1
63	0	1
64	0	1
65	0	1
66	0	1
67	0	1
68	0	1
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
77	0	1

---

Cond Coverage for Module : uart_tx

	Total	Covered	Percent
Conditions	13	0	0.00
Logical	13	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       67
 SUB-EXPRESSION (parity_enable ? wr_parity : 1'b1)
                 ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       68
 EXPRESSION (parity_enable ? 4'd11 : 4'd10)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       69
 EXPRESSION (tick_baud_q && (bit_cnt_q != 4'b0))
             -----1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       69
 SUB-EXPRESSION (bit_cnt_q != 4'b0)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       77
 EXPRESSION (tx_enable ? (bit_cnt_q == 4'b0) : 1'b1)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       77
 SUB-EXPRESSION (bit_cnt_q == 4'b0)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : uart_tx

	Line No.	Total	Covered	Percent
Branches		12	0	0.00
TERNARY	77	2	0	0.00
IF	35	3	0	0.00
IF	46	2	0	0.00
IF	58	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	77	(tx_enable) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	35	if ((!rst_ni))
-2-:	38	if (tick_baud_x16)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	46	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	58	if ((!tx_enable))
-2-:	66	if (wr)
-3-:	68	(parity_enable) ? 
-4-:	69	if ((tick_baud_q && (bit_cnt_q != 4'b0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	1	-	Not Covered
0	1	0	-	Not Covered
0	0	-	1	Not Covered
0	0	-	0	Not Covered