Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
32.95	0.00	0.00	98.86				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	522814	9416	0	0
ctrl_rd_A	522814	4252	0	0
intr_enable_rd_A	522814	3767	0	0
ovrd_rd_A	522814	1905	0	0
timeout_ctrl_rd_A	522814	1952	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522814	9416	0	0
T1	2159	117	0	0
T2	1167	0	0	0
T3	1211	0	0	0
T4	8760	1	0	0
T5	10756	4	0	0
T6	837	0	0	0
T7	816	0	0	0
T8	1379	0	0	0
T11	1339	0	0	0
T12	2961	323	0	0
T13	0	661	0	0
T14	0	45	0	0
T15	0	636	0	0
T16	0	37	0	0
T17	0	9	0	0
T51	0	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522814	4252	0	0
T4	8760	261	0	0
T5	10756	0	0	0
T8	1379	0	0	0
T9	1450	0	0	0
T10	1274	0	0	0
T11	1339	0	0	0
T12	2961	0	0	0
T13	12242	0	0	0
T14	0	33	0	0
T19	0	24	0	0
T20	0	7	0	0
T21	0	14	0	0
T22	1923	0	0	0
T24	0	1	0	0
T26	0	51	0	0
T29	1012	0	0	0
T51	0	185	0	0
T52	0	124	0	0
T54	0	227	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522814	3767	0	0
T2	1167	8	0	0
T3	1211	0	0	0
T4	8760	186	0	0
T5	10756	0	0	0
T6	837	0	0	0
T7	816	0	0	0
T8	1379	0	0	0
T9	0	14	0	0
T11	1339	0	0	0
T12	2961	0	0	0
T13	12242	0	0	0
T14	0	29	0	0
T19	0	9	0	0
T20	0	54	0	0
T22	0	24	0	0
T24	0	37	0	0
T26	0	34	0	0
T51	0	164	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522814	1905	0	0
T4	8760	75	0	0
T5	10756	0	0	0
T8	1379	0	0	0
T9	1450	0	0	0
T10	1274	0	0	0
T11	1339	0	0	0
T12	2961	0	0	0
T13	12242	0	0	0
T14	0	24	0	0
T19	0	2	0	0
T20	0	10	0	0
T21	0	43	0	0
T22	1923	13	0	0
T24	0	9	0	0
T26	0	29	0	0
T29	1012	0	0	0
T51	0	60	0	0
T54	0	49	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522814	1952	0	0
T4	8760	69	0	0
T5	10756	0	0	0
T8	1379	0	0	0
T9	1450	0	0	0
T10	1274	0	0	0
T11	1339	0	0	0
T12	2961	0	0	0
T13	12242	0	0	0
T14	0	19	0	0
T19	0	1	0	0
T20	0	17	0	0
T21	0	58	0	0
T22	1923	23	0	0
T26	0	51	0	0
T29	1012	0	0	0
T51	0	36	0	0
T52	0	66	0	0
T54	0	72	0	0