UART Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	36.810s	11.098ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	55.024us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	95.363us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.640s	509.816us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	93.028us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.410s	31.476us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	95.363us	20	20	100.00
		uart_csr_aliasing	0.820s	93.028us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.574m	78.681ms	50	50	100.00
V2	parity	uart_smoke	36.810s	11.098ms	50	50	100.00
		uart_tx_rx	2.574m	78.681ms	50	50	100.00
V2	parity_error	uart_intr	16.648m	646.325ms	50	50	100.00
		uart_rx_parity_err	6.274m	108.895ms	50	50	100.00
V2	watermark	uart_tx_rx	2.574m	78.681ms	50	50	100.00
		uart_intr	16.648m	646.325ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.376m	154.420ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.422m	298.691ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	5.716m	113.402ms	300	300	100.00
V2	rx_frame_err	uart_intr	16.648m	646.325ms	50	50	100.00
V2	rx_break_err	uart_intr	16.648m	646.325ms	50	50	100.00
V2	rx_timeout	uart_intr	16.648m	646.325ms	50	50	100.00
V2	perf	uart_perf	29.264m	33.908ms	50	50	100.00
V2	sys_loopback	uart_loopback	29.860s	12.712ms	50	50	100.00
V2	line_loopback	uart_loopback	29.860s	12.712ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	1.790m	98.048ms	7	50	14.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	55.000s	35.561ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	38.290s	6.554ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.131m	7.158ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	31.616m	200.877ms	50	50	100.00
V2	stress_all	uart_stress_all	28.467m	126.913ms	41	50	82.00
V2	alert_test	uart_alert_test	0.620s	13.794us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	43.618us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.530s	462.681us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.530s	462.681us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	55.024us	5	5	100.00
		uart_csr_rw	0.670s	95.363us	20	20	100.00
		uart_csr_aliasing	0.820s	93.028us	5	5	100.00
		uart_same_csr_outstanding	0.790s	174.387us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	55.024us	5	5	100.00
		uart_csr_rw	0.670s	95.363us	20	20	100.00
		uart_csr_aliasing	0.820s	93.028us	5	5	100.00
		uart_same_csr_outstanding	0.790s	174.387us	20	20	100.00
V2		TOTAL			1038	1090	95.23
V2S	tl_intg_err	uart_sec_cm	0.880s	70.017us	5	5	100.00
		uart_tl_intg_err	1.530s	83.886us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.530s	83.886us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.316m	184.457ms	69	100	69.00
V3		TOTAL			69	100	69.00
		TOTAL			1237	1320	93.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.50

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 42 failures:

Test uart_noise_filter has 21 failures.

1.uart_noise_filter.36806783571177480579964485322310550530454859076630902238480147012104259310485
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_noise_filter/latest/run.log

  UVM_ERROR @ 30726748310 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 30727748309 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 30728653070 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 30730462592 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 30731367353 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

2.uart_noise_filter.47011365868348972447561282946379492636085826949823999309848026991147849783468
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_noise_filter/latest/run.log

  UVM_ERROR @ 26612554918 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 27169324078 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0
  UVM_ERROR @ 27169382902 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 27169441726 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (149 [0x95] vs 95 [0x5f]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 27169500550 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

... and 19 more failures.

Test uart_stress_all_with_rand_reset has 15 failures.

9.uart_stress_all_with_rand_reset.56515621172190384456272634433254092138873686092764232083370812033591333809880
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  10856711 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  34540195 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  34540195 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @  90886683 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/779
  UVM_INFO @ 109141639 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/779

11.uart_stress_all_with_rand_reset.8261429420796303118382475458310190045916118854300116752621760300041904980518
Line 465, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 120543332005 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 120561443098 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 120570443089 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 120579776413 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_INFO @ 120788776204 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/647

... and 13 more failures.

Test uart_stress_all has 6 failures.

13.uart_stress_all.63400357037830791487220173772243119851555811271026191204716490769476281134510
Line 407, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_stress_all/latest/run.log

  UVM_ERROR @ 112930667575 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 112930667575 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 114289575642 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 114289575642 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 115331265225 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (245 [0xf5] vs 234 [0xea]) reg name: uart_reg_block.rdata

26.uart_stress_all.104777364260547879328783906471363676754499781708250203204488606310388780545189
Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/26.uart_stress_all/latest/run.log

  UVM_ERROR @ 25950254922 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 26501425998 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 26501425998 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 27814269834 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 27814269834 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1

... and 4 more failures.

UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 16 failures:

Test uart_stress_all has 2 failures.

2.uart_stress_all.60457442567868115329482995351564237455728225592590478430009427218321840802998
Line 273, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all/latest/run.log

  UVM_ERROR @ 33266873400 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 33266883400 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 33266893400 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 33382993400 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 33382993400 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1

33.uart_stress_all.17659951310656182190455128315379526021468810292431683998940022272524414533043
Line 294, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/33.uart_stress_all/latest/run.log

  UVM_ERROR @ 247024872258 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 247024912258 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 247024952258 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (153 [0x99] vs 246 [0xf6]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 247089032258 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 247089072258 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

Test uart_stress_all_with_rand_reset has 7 failures.

4.uart_stress_all_with_rand_reset.80024505072404847850207294136734889158665609805714406982323680400354940690562
Line 630, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 426507249023 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 426507749023 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 426508124023 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (234 [0xea] vs 253 [0xfd]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 426509499023 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 426509749023 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (234 [0xea] vs 223 [0xdf]) reg name: uart_reg_block.rdata

20.uart_stress_all_with_rand_reset.28765877123586140824538497471207342358634809408599810880624525244333715850037
Line 315, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4093122561 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 4093132978 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 4093143395 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 126 [0x7e]) reg name: uart_reg_block.rdata
  UVM_INFO @ 4101206153 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/596
  UVM_ERROR @ 4212865976 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 5 more failures.

Test uart_noise_filter has 7 failures.

8.uart_noise_filter.44022639143745605668990126779733373371062082238187988370508674814888539182336
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_noise_filter/latest/run.log

  UVM_ERROR @ 38509962305 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 38510007760 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 38510325945 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 229 [0xe5]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 38510735040 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 38510780495 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

14.uart_noise_filter.23094899395103005198465114888553127854195552552647432136931972393584131816090
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_noise_filter/latest/run.log

  UVM_ERROR @ 28217562148 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 10,                                 clk_pulses: 0
  UVM_ERROR @ 28217602148 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 28217642148 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (119 [0x77] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 28217682148 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 28217722148 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (119 [0x77] vs 255 [0xff]) reg name: uart_reg_block.rdata

... and 5 more failures.

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 13 failures:

Test uart_noise_filter has 10 failures.

3.uart_noise_filter.20348040870735809343679823484886762595976945986911186718408943009679969352447
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_noise_filter/latest/run.log

  UVM_ERROR @ 3455329850 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 3455329850 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 3455329850 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 5264849850 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 5264849850 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1

6.uart_noise_filter.5262701207654021752290651739803470481145038802839246119819111741056053398834
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_noise_filter/latest/run.log

  UVM_ERROR @ 29277504612 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 29277504612 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 29287879612 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 29287879612 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 29791504612 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0

... and 8 more failures.

Test uart_stress_all has 1 failures.

18.uart_stress_all.72591458185914739611573065539822080017411062292561575861383317497587938596741
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_stress_all/latest/run.log

  UVM_ERROR @ 5729196844 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 5729196844 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 5729196844 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 5941956844 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5,                                 clk_pulses: 0
  UVM_ERROR @ 5942036844 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (71 [0x47] vs 255 [0xff]) reg name: uart_reg_block.rdata

Test uart_stress_all_with_rand_reset has 2 failures.

38.uart_stress_all_with_rand_reset.88156025418269674806502094307940475513623116443624178366685883400970996655148
Line 308, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 19488327934 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_INFO @ 19725627934 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 19/689
  UVM_INFO @ 19941127934 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 20/689
  UVM_ERROR @ 20017127934 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 16,                                 clk_pulses: 0
  UVM_ERROR @ 20017527934 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (130 [0x82] vs 255 [0xff]) reg name: uart_reg_block.rdata

72.uart_stress_all_with_rand_reset.105458430702428453790199434350649894151281909251297791831772574008030354108578
Line 324, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11905269380 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 11905269380 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 11905269380 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @ 11949166988 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 16/678
  UVM_ERROR @ 11964085236 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 27,                                 clk_pulses: 0

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr has 4 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

7.uart_stress_all_with_rand_reset.26935105992224524509009523251728826333059004618714953885651236752749828159565
Line 447, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 39322271749 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 39322271749 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
  UVM_ERROR @ 39402272389 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 39402272389 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
  UVM_ERROR @ 39490439761 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 19,                                 clk_pulses: 0

36.uart_stress_all_with_rand_reset.47600153166186387184598637386350938241766224830542561595022701388377046370167
Line 728, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 96126454212 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 96126454212 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 96126454212 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
  UVM_ERROR @ 96129054186 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 96129054186 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark

Test uart_noise_filter has 2 failures.

36.uart_noise_filter.18525741622040215941579986036087548188568349266376365210039151329056032141110
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_noise_filter/latest/run.log

  UVM_ERROR @ 11985646147 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 12835446147 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 12835446147 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 13283846147 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 13283846147 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

42.uart_noise_filter.104726163511195408663770414491878108537711985115837705774277216500966790726392
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/42.uart_noise_filter/latest/run.log

  UVM_ERROR @ 180195244 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 180195244 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 180195244 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
  UVM_ERROR @ 182257711 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 182257711 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 3 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

0.uart_stress_all_with_rand_reset.91610086195133049087523737879026924063481479479279535116751637361334196439702
Line 317, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3718513048 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 3718513048 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
  UVM_ERROR @ 3730653048 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 3730653048 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
  UVM_INFO @ 3736643048 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/80

78.uart_stress_all_with_rand_reset.1041949832095595273563410280942498923417747105968256430971683784543373073112
Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 491755576 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 491755576 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
  UVM_INFO @ 512145576 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/658
  UVM_ERROR @ 514315576 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 514315576 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark

Test uart_noise_filter has 1 failures.

34.uart_noise_filter.14667185039119477271219502657287701525625167855394448098957953300552321682271
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/34.uart_noise_filter/latest/run.log

  UVM_ERROR @ 276760940 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 282219317 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 307344518 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 307386185 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 307427852 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:

Test uart_noise_filter has 1 failures.

16.uart_noise_filter.109687158554692023709657179906072903623873736940072415751945546461361068392480
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_noise_filter/latest/run.log

  UVM_ERROR @  60206583 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @  60206583 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @  60206583 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @  62878642 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @  62878642 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr

Test uart_stress_all_with_rand_reset has 1 failures.

50.uart_stress_all_with_rand_reset.884625085000662478783958964765296926364308058545257191626091652790822216520
Line 490, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 45419431924 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 45441709880 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/985
  UVM_ERROR @ 45591655524 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 45591683302 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 45591711080 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata

UVM_ERROR (uart_intr_vseq.sv:325) [uart_intr_vseq] Check failed act_intr_state & exp_mask == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

1.uart_stress_all_with_rand_reset.45853671183645186004521946051921419675557512130988446946681900710034628696689
Line 330, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 26169092299 ps: (uart_intr_vseq.sv:325) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state & exp_mask == exp (16 [0x10] vs 0 [0x0])
  UVM_INFO @ 26793892299 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 11/347
  UVM_INFO @ 27561292299 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/3
  UVM_INFO @ 27564092299 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark

UVM_ERROR (cip_base_vseq.sv:828) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

3.uart_stress_all_with_rand_reset.56480971643917804262371999219071162853372242040186949371577791641510223851780
Line 723, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 82798886525 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 82798902940 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 82798902940 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 10/10
  UVM_INFO @ 82798906525 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 1 failures:

Test uart_noise_filter has 1 failures.

21.uart_noise_filter.105834059638566376110899349971604513402305509243100471634291412714332372182792
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_noise_filter/latest/run.log

  UVM_ERROR @  14652617 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 35467519571 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/8
  UVM_ERROR @ 35658562766 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 35658562766 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 35658562766 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1