UART Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	27.960s	5.720ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.560s	1.042ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	14.573us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.740s	1.028ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	38.189us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.420s	28.177us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	14.573us	20	20	100.00
		uart_csr_aliasing	0.790s	38.189us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.942m	45.196ms	50	50	100.00
V2	parity	uart_smoke	27.960s	5.720ms	50	50	100.00
		uart_tx_rx	4.942m	45.196ms	50	50	100.00
V2	parity_error	uart_intr	8.479m	241.233ms	49	50	98.00
		uart_rx_parity_err	8.745m	150.771ms	50	50	100.00
V2	watermark	uart_tx_rx	4.942m	45.196ms	50	50	100.00
		uart_intr	8.479m	241.233ms	49	50	98.00
V2	fifo_full	uart_fifo_full	8.060m	206.452ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.423m	138.044ms	49	50	98.00
V2	fifo_reset	uart_fifo_reset	16.491m	96.655ms	299	300	99.67
V2	rx_frame_err	uart_intr	8.479m	241.233ms	49	50	98.00
V2	rx_break_err	uart_intr	8.479m	241.233ms	49	50	98.00
V2	rx_timeout	uart_intr	8.479m	241.233ms	49	50	98.00
V2	perf	uart_perf	25.930m	28.367ms	50	50	100.00
V2	sys_loopback	uart_loopback	30.070s	9.109ms	50	50	100.00
V2	line_loopback	uart_loopback	30.070s	9.109ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.275m	100.050ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.205m	46.034ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	32.920s	6.232ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.136m	7.078ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.708m	140.909ms	50	50	100.00
V2	stress_all	uart_stress_all	44.639m	463.575ms	50	50	100.00
V2	alert_test	uart_alert_test	0.620s	13.655us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	93.810us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.210s	103.976us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.210s	103.976us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.560s	1.042ms	5	5	100.00
		uart_csr_rw	0.660s	14.573us	20	20	100.00
		uart_csr_aliasing	0.790s	38.189us	5	5	100.00
		uart_same_csr_outstanding	0.810s	34.800us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.560s	1.042ms	5	5	100.00
		uart_csr_rw	0.660s	14.573us	20	20	100.00
		uart_csr_aliasing	0.790s	38.189us	5	5	100.00
		uart_same_csr_outstanding	0.810s	34.800us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	0.840s	227.928us	5	5	100.00
		uart_tl_intg_err	1.390s	134.124us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.390s	134.124us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	38.616m	213.876ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1314	1320	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_intr has 1 failures.

14.uart_intr.43124099676652271652358721192925017425900086947480884961300815198321899444843
Line 321, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_intr/latest/run.log

  UVM_ERROR @ 30819679985 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 30914058005 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 32633279685 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 4/4
  UVM_INFO @ 32645300743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

Test uart_fifo_overflow has 1 failures.

20.uart_fifo_overflow.76600738693710179206222239476020981353646535983375784044910826671772857393866
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_fifo_overflow/latest/run.log

  UVM_ERROR @   1715291 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 27726478754 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/9
  UVM_INFO @ 28015633845 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/9
  UVM_INFO @ 28275108143 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/9
  UVM_INFO @ 28404345288 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/9

Test uart_fifo_reset has 1 failures.

255.uart_fifo_reset.110649801618319617539639991175526342841197946835785763018675555068487324221249
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/255.uart_fifo_reset/latest/run.log

  UVM_ERROR @   3242461 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 1072435225 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
  UVM_INFO @ 14140302925 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
  UVM_INFO @ 38317285813 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
  UVM_INFO @ 39334083421 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6

UVM_ERROR (cip_base_vseq.sv:825) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

19.uart_stress_all_with_rand_reset.82200131461091682922725732254591958734413687986646271178220453998983331923797
Line 568, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 100083129037 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 100083137025 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 100083137025 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 100083150314 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2

UVM_ERROR (uart_scoreboard.sv:444) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: RxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

22.uart_stress_all_with_rand_reset.86529493054788090623044870391873277516785034414503703089482006309796652686409
Line 1403, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 514375431784 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: RxWatermark
  UVM_INFO @ 515410322416 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 8/8
  UVM_INFO @ 515704736536 ps: (uart_stress_all_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_stress_all_vseq] starting stress_all sub-sequence uart_rx_start_bit_filter_vseq
  UVM_INFO @ 518580053656 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_start_bit_filter_vseq] finished run 1/2
  UVM_INFO @ 519914476096 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_start_bit_filter_vseq] finished run 2/2

UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

67.uart_stress_all_with_rand_reset.2764671553548074099153895405071917942889792128101000757208132556059055930501
Line 292, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13838609393 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 13961551553 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/10
  UVM_INFO @ 14199847577 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 32/337
  UVM_INFO @ 16029626921 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 33/337
  UVM_INFO @ 16435453697 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 34/337