UART Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	21.630s	5.692ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	66.584us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.700s	58.152us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.680s	908.526us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.830s	29.142us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.150s	44.488us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.700s	58.152us	20	20	100.00
		uart_csr_aliasing	0.830s	29.142us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.695m	95.363ms	50	50	100.00
V2	parity	uart_smoke	21.630s	5.692ms	50	50	100.00
		uart_tx_rx	4.695m	95.363ms	50	50	100.00
V2	parity_error	uart_intr	4.288m	142.924ms	50	50	100.00
		uart_rx_parity_err	9.372m	341.587ms	50	50	100.00
V2	watermark	uart_tx_rx	4.695m	95.363ms	50	50	100.00
		uart_intr	4.288m	142.924ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.504m	256.102ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.488m	180.325ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.538m	309.014ms	300	300	100.00
V2	rx_frame_err	uart_intr	4.288m	142.924ms	50	50	100.00
V2	rx_break_err	uart_intr	4.288m	142.924ms	50	50	100.00
V2	rx_timeout	uart_intr	4.288m	142.924ms	50	50	100.00
V2	perf	uart_perf	23.049m	27.688ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.300s	5.886ms	50	50	100.00
V2	line_loopback	uart_loopback	25.300s	5.886ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.115m	101.015ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.035m	44.300ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	33.930s	11.952ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.169m	8.016ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	16.662m	157.757ms	50	50	100.00
V2	stress_all	uart_stress_all	22.274m	321.771ms	49	50	98.00
V2	alert_test	uart_alert_test	0.630s	17.290us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	34.116us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.360s	47.125us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.360s	47.125us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	66.584us	5	5	100.00
		uart_csr_rw	0.700s	58.152us	20	20	100.00
		uart_csr_aliasing	0.830s	29.142us	5	5	100.00
		uart_same_csr_outstanding	0.820s	22.231us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	66.584us	5	5	100.00
		uart_csr_rw	0.700s	58.152us	20	20	100.00
		uart_csr_aliasing	0.830s	29.142us	5	5	100.00
		uart_same_csr_outstanding	0.820s	22.231us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.920s	467.754us	5	5	100.00
		uart_tl_intg_err	1.360s	1.012ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.360s	1.012ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	25.007m	470.166ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1316	1320	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.50

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:

Test uart_stress_all has 1 failures.

0.uart_stress_all.77999882096355062349271732677418577603114359524678410663405337518808381863773
Line 316, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all/latest/run.log

  UVM_ERROR @ 294542674429 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 299184800557 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 9/10
  UVM_INFO @ 307083267981 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 10/10
  UVM_INFO @ 312963904649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test uart_stress_all_with_rand_reset has 1 failures.

11.uart_stress_all_with_rand_reset.103408918156977395400179765185375493461307098180881429879514153016102329133016
Line 897, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 170114441839 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 170161533219 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout
  UVM_INFO @ 170460036204 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 556/747
  UVM_INFO @ 170548127994 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 557/747

UVM_ERROR (cip_base_vseq.sv:749) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

22.uart_stress_all_with_rand_reset.99718949511091788899596766093907868175551686012365136892639762728717350070601
Line 439, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12728691669 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 12728691669 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 4/10
  UVM_INFO @ 12728761669 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 4/10

UVM_ERROR (cip_base_vseq.sv:825) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

79.uart_stress_all_with_rand_reset.43035800440135675792916798752947919226146895234495029896373329224008024176799
Line 277, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1053975258 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1053979667 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1053979667 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 1053985258 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1