Line Coverage for Module :
uart
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
77 // Alerts
78 1/1 assign alert_test = {
Tests: T1 T2 T3
Cond Coverage for Module :
uart
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 78
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T34,T87 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T6,T33,T34 |
Toggle Coverage for Module :
uart
| Total | Covered | Percent |
Totals |
37 |
37 |
100.00 |
Total Bits |
354 |
354 |
100.00 |
Total Bits 0->1 |
177 |
177 |
100.00 |
Total Bits 1->0 |
177 |
177 |
100.00 |
| | | |
Ports |
37 |
37 |
100.00 |
Port Bits |
354 |
354 |
100.00 |
Port Bits 0->1 |
177 |
177 |
100.00 |
Port Bits 1->0 |
177 |
177 |
100.00 |
Port Details
| | | | | | |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T31,T32 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T7,T10,T17 |
Yes |
T7,T10,T17 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T21,T28,T29 |
Yes |
T21,T28,T29 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T5,T6,T33 |
Yes |
T5,T6,T33 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T5,T6,T33 |
Yes |
T5,T6,T33 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
cio_tx_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T4,T10,T11 |
Yes |
T4,T10,T11 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T4,T7,T10 |
Yes |
T4,T7,T9 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T4,T11,T17 |
Yes |
T4,T11,T17 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T4,T11,T16 |
Yes |
T4,T11,T16 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T13,T18,T19 |
Yes |
T13,T18,T19 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T14,T20,T19 |
Yes |
T14,T20,T19 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T21,T22,T25 |
Yes |
T21,T22,T25 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T17,T12,T50 |
Yes |
T17,T12,T50 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T23,T20,T19 |
Yes |
T23,T20,T19 |
OUTPUT |
*Tests covering at least one bit in the range
Assert Coverage for Module :
uart
Assertion Details
AlertsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
80 |
0 |
0 |
T5 |
6230 |
20 |
0 |
0 |
T6 |
1189 |
0 |
0 |
0 |
T7 |
158078 |
0 |
0 |
0 |
T8 |
69107 |
0 |
0 |
0 |
T9 |
42884 |
0 |
0 |
0 |
T10 |
397823 |
0 |
0 |
0 |
T11 |
922229 |
0 |
0 |
0 |
T14 |
202217 |
0 |
0 |
0 |
T15 |
121124 |
0 |
0 |
0 |
T16 |
211455 |
0 |
0 |
0 |
T31 |
0 |
10 |
0 |
0 |
T32 |
0 |
20 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T88 |
0 |
10 |
0 |
0 |
RxBreakErrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
RxFrameErrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
RxOverflowKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
RxParityErrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
RxTimeoutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
RxWatermarkKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
TxDoneKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
TxEmptyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
TxEnIsOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
TxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |
TxWatermarkKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20654 |
20559 |
0 |
0 |
T2 |
102062 |
101996 |
0 |
0 |
T3 |
34780 |
34715 |
0 |
0 |
T4 |
93578 |
93519 |
0 |
0 |
T5 |
6230 |
4710 |
0 |
0 |
T6 |
1189 |
1124 |
0 |
0 |
T7 |
158078 |
157988 |
0 |
0 |
T8 |
69107 |
69032 |
0 |
0 |
T9 |
42884 |
42825 |
0 |
0 |
T10 |
397823 |
397745 |
0 |
0 |