Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	907551	0	0
ctrl_rd_A	2147483647	20536	0	0
intr_enable_rd_A	2147483647	20045	0	0
ovrd_rd_A	2147483647	20539	0	0
timeout_ctrl_rd_A	2147483647	20189	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	907551	0	0
T21	444484	19994	0	0
T22	0	3770	0	0
T26	0	6962	0	0
T28	0	7465	0	0
T29	0	9269	0	0
T35	0	9190	0	0
T36	0	9036	0	0
T37	0	8154	0	0
T38	0	8240	0	0
T39	0	10636	0	0
T40	901653	0	0	0
T41	501513	0	0	0
T42	92233	0	0	0
T43	260270	0	0	0
T44	6286	0	0	0
T45	1269	0	0	0
T46	404284	0	0	0
T47	123289	0	0	0
T48	136824	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20536	0	0
T22	106882	0	0	0
T25	451566	0	0	0
T26	0	987	0	0
T28	295670	835	0	0
T29	211890	0	0	0
T52	80025	0	0	0
T89	0	761	0	0
T90	0	833	0	0
T91	0	217	0	0
T92	0	672	0	0
T93	0	952	0	0
T94	0	534	0	0
T95	0	125	0	0
T96	0	415	0	0
T97	81879	0	0	0
T98	349128	0	0	0
T99	65643	0	0	0
T100	1243	0	0	0
T101	137139	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20045	0	0
T22	106882	0	0	0
T25	451566	0	0	0
T26	0	868	0	0
T28	295670	806	0	0
T29	211890	0	0	0
T52	80025	0	0	0
T89	0	678	0	0
T90	0	745	0	0
T91	0	233	0	0
T92	0	697	0	0
T97	81879	0	0	0
T98	349128	0	0	0
T99	65643	0	0	0
T100	1243	0	0	0
T101	137139	0	0	0
T102	0	7	0	0
T103	0	9	0	0
T104	0	9	0	0
T105	0	28	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20539	0	0
T22	106882	0	0	0
T25	451566	0	0	0
T26	0	1021	0	0
T28	295670	935	0	0
T29	211890	0	0	0
T52	80025	0	0	0
T89	0	795	0	0
T90	0	856	0	0
T91	0	195	0	0
T92	0	847	0	0
T93	0	831	0	0
T94	0	525	0	0
T95	0	124	0	0
T96	0	475	0	0
T97	81879	0	0	0
T98	349128	0	0	0
T99	65643	0	0	0
T100	1243	0	0	0
T101	137139	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20189	0	0
T22	106882	0	0	0
T25	451566	0	0	0
T26	0	999	0	0
T28	295670	925	0	0
T29	211890	0	0	0
T52	80025	0	0	0
T89	0	779	0	0
T90	0	809	0	0
T91	0	196	0	0
T92	0	829	0	0
T93	0	721	0	0
T94	0	549	0	0
T95	0	163	0	0
T96	0	485	0	0
T97	81879	0	0	0
T98	349128	0	0	0
T99	65643	0	0	0
T100	1243	0	0	0
T101	137139	0	0	0