| T234 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/153.uart_fifo_reset.297704431 |
|
|
Sep 04 10:45:26 AM UTC 24 |
Sep 04 10:46:53 AM UTC 24 |
155115347027 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/173.uart_fifo_reset.195137820 |
|
|
Sep 04 10:45:57 AM UTC 24 |
Sep 04 10:46:54 AM UTC 24 |
112807658845 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/183.uart_fifo_reset.3575176560 |
|
|
Sep 04 10:46:14 AM UTC 24 |
Sep 04 10:46:57 AM UTC 24 |
51369874485 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/205.uart_fifo_reset.1565951891 |
|
|
Sep 04 10:46:47 AM UTC 24 |
Sep 04 10:46:58 AM UTC 24 |
4491430359 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_perf.2069574112 |
|
|
Sep 04 10:25:56 AM UTC 24 |
Sep 04 10:46:58 AM UTC 24 |
23092445437 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_perf.2436036854 |
|
|
Sep 04 10:37:39 AM UTC 24 |
Sep 04 10:46:59 AM UTC 24 |
28709894483 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2066895900 |
|
|
Sep 04 10:45:55 AM UTC 24 |
Sep 04 10:47:00 AM UTC 24 |
92075623376 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/198.uart_fifo_reset.3034458079 |
|
|
Sep 04 10:46:42 AM UTC 24 |
Sep 04 10:47:01 AM UTC 24 |
40639740638 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/195.uart_fifo_reset.634863867 |
|
|
Sep 04 10:46:37 AM UTC 24 |
Sep 04 10:47:04 AM UTC 24 |
49737036394 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/209.uart_fifo_reset.1752292487 |
|
|
Sep 04 10:46:53 AM UTC 24 |
Sep 04 10:47:06 AM UTC 24 |
25361049393 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/192.uart_fifo_reset.2071675657 |
|
|
Sep 04 10:46:33 AM UTC 24 |
Sep 04 10:47:08 AM UTC 24 |
8841193408 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/168.uart_fifo_reset.2482086627 |
|
|
Sep 04 10:45:46 AM UTC 24 |
Sep 04 10:47:08 AM UTC 24 |
183188429025 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/142.uart_fifo_reset.576706835 |
|
|
Sep 04 10:45:06 AM UTC 24 |
Sep 04 10:47:11 AM UTC 24 |
31682200823 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/145.uart_fifo_reset.4135719892 |
|
|
Sep 04 10:45:10 AM UTC 24 |
Sep 04 10:47:11 AM UTC 24 |
59736896234 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/170.uart_fifo_reset.2448156718 |
|
|
Sep 04 10:45:51 AM UTC 24 |
Sep 04 10:47:13 AM UTC 24 |
33006994930 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/193.uart_fifo_reset.2886171934 |
|
|
Sep 04 10:46:36 AM UTC 24 |
Sep 04 10:47:13 AM UTC 24 |
31533072322 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/148.uart_fifo_reset.3331823471 |
|
|
Sep 04 10:45:13 AM UTC 24 |
Sep 04 10:47:13 AM UTC 24 |
133525785091 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/187.uart_fifo_reset.3486167575 |
|
|
Sep 04 10:46:19 AM UTC 24 |
Sep 04 10:47:15 AM UTC 24 |
41218595261 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/197.uart_fifo_reset.4149041878 |
|
|
Sep 04 10:46:42 AM UTC 24 |
Sep 04 10:47:16 AM UTC 24 |
25360786135 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/186.uart_fifo_reset.1882943319 |
|
|
Sep 04 10:46:15 AM UTC 24 |
Sep 04 10:47:17 AM UTC 24 |
31052776230 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/105.uart_fifo_reset.3363666302 |
|
|
Sep 04 10:44:00 AM UTC 24 |
Sep 04 10:47:17 AM UTC 24 |
108790717165 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/190.uart_fifo_reset.2213847561 |
|
|
Sep 04 10:46:26 AM UTC 24 |
Sep 04 10:47:17 AM UTC 24 |
20321021779 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/114.uart_fifo_reset.1888451324 |
|
|
Sep 04 10:44:17 AM UTC 24 |
Sep 04 10:47:18 AM UTC 24 |
132263910187 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_stress_all.2386531077 |
|
|
Sep 04 10:33:59 AM UTC 24 |
Sep 04 10:47:18 AM UTC 24 |
171461314114 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/203.uart_fifo_reset.3929174829 |
|
|
Sep 04 10:46:46 AM UTC 24 |
Sep 04 10:47:21 AM UTC 24 |
90017938160 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2447844510 |
|
|
Sep 04 10:46:46 AM UTC 24 |
Sep 04 10:47:22 AM UTC 24 |
17747795392 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1179770556 |
|
|
Sep 04 10:46:55 AM UTC 24 |
Sep 04 10:47:22 AM UTC 24 |
28077266342 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3719935582 |
|
|
Sep 04 10:47:01 AM UTC 24 |
Sep 04 10:47:25 AM UTC 24 |
49883563016 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/214.uart_fifo_reset.207497849 |
|
|
Sep 04 10:47:00 AM UTC 24 |
Sep 04 10:47:27 AM UTC 24 |
11643096510 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/212.uart_fifo_reset.582904826 |
|
|
Sep 04 10:46:59 AM UTC 24 |
Sep 04 10:47:27 AM UTC 24 |
20103263514 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/231.uart_fifo_reset.4036483724 |
|
|
Sep 04 10:47:19 AM UTC 24 |
Sep 04 10:47:28 AM UTC 24 |
6184449196 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/156.uart_fifo_reset.2602367225 |
|
|
Sep 04 10:45:29 AM UTC 24 |
Sep 04 10:47:29 AM UTC 24 |
81514634441 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/199.uart_fifo_reset.3661340095 |
|
|
Sep 04 10:46:43 AM UTC 24 |
Sep 04 10:47:31 AM UTC 24 |
80117903970 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/184.uart_fifo_reset.3988151502 |
|
|
Sep 04 10:46:14 AM UTC 24 |
Sep 04 10:47:33 AM UTC 24 |
167250621607 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/201.uart_fifo_reset.2102379594 |
|
|
Sep 04 10:46:43 AM UTC 24 |
Sep 04 10:47:38 AM UTC 24 |
189920751123 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2881368374 |
|
|
Sep 04 10:46:51 AM UTC 24 |
Sep 04 10:47:43 AM UTC 24 |
111246553184 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/235.uart_fifo_reset.2389553064 |
|
|
Sep 04 10:47:22 AM UTC 24 |
Sep 04 10:47:44 AM UTC 24 |
19459268929 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/213.uart_fifo_reset.2238540232 |
|
|
Sep 04 10:47:00 AM UTC 24 |
Sep 04 10:47:45 AM UTC 24 |
208918920147 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_perf.1555836692 |
|
|
Sep 04 10:34:54 AM UTC 24 |
Sep 04 10:47:45 AM UTC 24 |
15384221170 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/154.uart_fifo_reset.4201540538 |
|
|
Sep 04 10:45:27 AM UTC 24 |
Sep 04 10:47:47 AM UTC 24 |
88953644780 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/78.uart_fifo_reset.269602601 |
|
|
Sep 04 10:42:29 AM UTC 24 |
Sep 04 10:47:48 AM UTC 24 |
139094966423 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2513730305 |
|
|
Sep 04 10:47:15 AM UTC 24 |
Sep 04 10:47:51 AM UTC 24 |
20679651414 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/211.uart_fifo_reset.332845703 |
|
|
Sep 04 10:46:59 AM UTC 24 |
Sep 04 10:47:52 AM UTC 24 |
27816397377 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1078702753 |
|
|
Sep 04 10:47:09 AM UTC 24 |
Sep 04 10:47:54 AM UTC 24 |
75722635884 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/234.uart_fifo_reset.2045240399 |
|
|
Sep 04 10:47:22 AM UTC 24 |
Sep 04 10:47:55 AM UTC 24 |
68061393339 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/227.uart_fifo_reset.1717215323 |
|
|
Sep 04 10:47:17 AM UTC 24 |
Sep 04 10:47:59 AM UTC 24 |
111107849498 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/159.uart_fifo_reset.315655128 |
|
|
Sep 04 10:45:33 AM UTC 24 |
Sep 04 10:47:59 AM UTC 24 |
58541334145 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/243.uart_fifo_reset.3775801160 |
|
|
Sep 04 10:47:39 AM UTC 24 |
Sep 04 10:47:59 AM UTC 24 |
135054157301 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/207.uart_fifo_reset.4252531958 |
|
|
Sep 04 10:46:51 AM UTC 24 |
Sep 04 10:48:01 AM UTC 24 |
137067384273 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2517203065 |
|
|
Sep 04 10:47:18 AM UTC 24 |
Sep 04 10:48:04 AM UTC 24 |
16799141980 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/236.uart_fifo_reset.1272007386 |
|
|
Sep 04 10:47:25 AM UTC 24 |
Sep 04 10:48:05 AM UTC 24 |
94810313420 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/253.uart_fifo_reset.1340861940 |
|
|
Sep 04 10:47:56 AM UTC 24 |
Sep 04 10:48:06 AM UTC 24 |
24936258315 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/218.uart_fifo_reset.4285611442 |
|
|
Sep 04 10:47:07 AM UTC 24 |
Sep 04 10:48:09 AM UTC 24 |
140704340535 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/232.uart_fifo_reset.21025806 |
|
|
Sep 04 10:47:19 AM UTC 24 |
Sep 04 10:48:09 AM UTC 24 |
149081346131 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/108.uart_fifo_reset.3134866151 |
|
|
Sep 04 10:44:05 AM UTC 24 |
Sep 04 10:48:12 AM UTC 24 |
129300318417 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/246.uart_fifo_reset.4138827012 |
|
|
Sep 04 10:47:46 AM UTC 24 |
Sep 04 10:48:12 AM UTC 24 |
42234161841 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/177.uart_fifo_reset.280293472 |
|
|
Sep 04 10:46:05 AM UTC 24 |
Sep 04 10:48:13 AM UTC 24 |
147779583215 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/222.uart_fifo_reset.1267362597 |
|
|
Sep 04 10:47:12 AM UTC 24 |
Sep 04 10:48:13 AM UTC 24 |
69526233608 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/251.uart_fifo_reset.3354126223 |
|
|
Sep 04 10:47:53 AM UTC 24 |
Sep 04 10:48:13 AM UTC 24 |
98761084263 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/241.uart_fifo_reset.773090945 |
|
|
Sep 04 10:47:32 AM UTC 24 |
Sep 04 10:48:13 AM UTC 24 |
59838630576 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/228.uart_fifo_reset.4133849499 |
|
|
Sep 04 10:47:18 AM UTC 24 |
Sep 04 10:48:16 AM UTC 24 |
110224673077 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3106914901 |
|
|
Sep 04 10:46:37 AM UTC 24 |
Sep 04 10:48:17 AM UTC 24 |
170597591126 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/217.uart_fifo_reset.1622411701 |
|
|
Sep 04 10:47:04 AM UTC 24 |
Sep 04 10:48:18 AM UTC 24 |
129666695224 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/244.uart_fifo_reset.4081284420 |
|
|
Sep 04 10:47:44 AM UTC 24 |
Sep 04 10:48:20 AM UTC 24 |
17296125996 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/224.uart_fifo_reset.595219123 |
|
|
Sep 04 10:47:15 AM UTC 24 |
Sep 04 10:48:27 AM UTC 24 |
67839959449 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/263.uart_fifo_reset.472896332 |
|
|
Sep 04 10:48:12 AM UTC 24 |
Sep 04 10:48:28 AM UTC 24 |
36299401992 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1220620661 |
|
|
Sep 04 10:47:02 AM UTC 24 |
Sep 04 10:48:29 AM UTC 24 |
28238810144 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/219.uart_fifo_reset.3717386590 |
|
|
Sep 04 10:47:09 AM UTC 24 |
Sep 04 10:48:32 AM UTC 24 |
111174784515 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/239.uart_fifo_reset.3259231673 |
|
|
Sep 04 10:47:29 AM UTC 24 |
Sep 04 10:48:33 AM UTC 24 |
78789863275 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/255.uart_fifo_reset.2545098242 |
|
|
Sep 04 10:48:00 AM UTC 24 |
Sep 04 10:48:33 AM UTC 24 |
74256762983 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/259.uart_fifo_reset.270897670 |
|
|
Sep 04 10:48:05 AM UTC 24 |
Sep 04 10:48:33 AM UTC 24 |
87301664880 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/250.uart_fifo_reset.3293033479 |
|
|
Sep 04 10:47:53 AM UTC 24 |
Sep 04 10:48:33 AM UTC 24 |
20436650826 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1618742140 |
|
|
Sep 04 10:47:55 AM UTC 24 |
Sep 04 10:48:34 AM UTC 24 |
19987685433 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/269.uart_fifo_reset.1200591939 |
|
|
Sep 04 10:48:17 AM UTC 24 |
Sep 04 10:48:34 AM UTC 24 |
15093192663 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3100055412 |
|
|
Sep 04 10:47:46 AM UTC 24 |
Sep 04 10:48:35 AM UTC 24 |
158399530053 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/262.uart_fifo_reset.1039956591 |
|
|
Sep 04 10:48:10 AM UTC 24 |
Sep 04 10:48:36 AM UTC 24 |
27549656306 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/135.uart_fifo_reset.3911691993 |
|
|
Sep 04 10:44:52 AM UTC 24 |
Sep 04 10:48:37 AM UTC 24 |
127709507198 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1724114988 |
|
|
Sep 04 10:48:10 AM UTC 24 |
Sep 04 10:48:38 AM UTC 24 |
15222249504 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/248.uart_fifo_reset.1327279415 |
|
|
Sep 04 10:47:47 AM UTC 24 |
Sep 04 10:48:39 AM UTC 24 |
13259127602 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/267.uart_fifo_reset.3004049314 |
|
|
Sep 04 10:48:14 AM UTC 24 |
Sep 04 10:48:41 AM UTC 24 |
8311522066 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2904775346 |
|
|
Sep 04 10:48:02 AM UTC 24 |
Sep 04 10:48:46 AM UTC 24 |
168073140630 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1652531305 |
|
|
Sep 04 10:46:15 AM UTC 24 |
Sep 04 10:48:54 AM UTC 24 |
92759608307 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/238.uart_fifo_reset.3465034365 |
|
|
Sep 04 10:47:29 AM UTC 24 |
Sep 04 10:48:55 AM UTC 24 |
135449240386 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/281.uart_fifo_reset.2036996245 |
|
|
Sep 04 10:48:35 AM UTC 24 |
Sep 04 10:48:58 AM UTC 24 |
11841831229 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/245.uart_fifo_reset.1631597164 |
|
|
Sep 04 10:47:44 AM UTC 24 |
Sep 04 10:49:00 AM UTC 24 |
135096308782 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/268.uart_fifo_reset.4189753451 |
|
|
Sep 04 10:48:15 AM UTC 24 |
Sep 04 10:49:01 AM UTC 24 |
55152052455 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_perf.3557693757 |
|
|
Sep 04 10:23:16 AM UTC 24 |
Sep 04 10:49:01 AM UTC 24 |
27887628053 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/200.uart_fifo_reset.962814728 |
|
|
Sep 04 10:46:43 AM UTC 24 |
Sep 04 10:49:01 AM UTC 24 |
49817664546 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/282.uart_fifo_reset.3250709129 |
|
|
Sep 04 10:48:35 AM UTC 24 |
Sep 04 10:49:03 AM UTC 24 |
284073775485 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3368246171 |
|
|
Sep 04 10:47:18 AM UTC 24 |
Sep 04 10:49:04 AM UTC 24 |
100176922828 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2377761704 |
|
|
Sep 04 10:48:05 AM UTC 24 |
Sep 04 10:49:05 AM UTC 24 |
33420229568 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3005253879 |
|
|
Sep 04 10:46:21 AM UTC 24 |
Sep 04 10:49:05 AM UTC 24 |
172048232159 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1570761785 |
|
|
Sep 04 10:47:11 AM UTC 24 |
Sep 04 10:49:05 AM UTC 24 |
67308258287 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/273.uart_fifo_reset.3199541742 |
|
|
Sep 04 10:48:28 AM UTC 24 |
Sep 04 10:49:05 AM UTC 24 |
25501483758 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3551547927 |
|
|
Sep 04 10:48:36 AM UTC 24 |
Sep 04 10:49:07 AM UTC 24 |
41151116363 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/272.uart_fifo_reset.3638009803 |
|
|
Sep 04 10:48:21 AM UTC 24 |
Sep 04 10:49:09 AM UTC 24 |
137775215696 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/274.uart_fifo_reset.775263344 |
|
|
Sep 04 10:48:28 AM UTC 24 |
Sep 04 10:49:13 AM UTC 24 |
164897089629 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/191.uart_fifo_reset.928923110 |
|
|
Sep 04 10:46:29 AM UTC 24 |
Sep 04 10:49:13 AM UTC 24 |
102988438369 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3314387466 |
|
|
Sep 04 10:48:38 AM UTC 24 |
Sep 04 10:49:15 AM UTC 24 |
72027902384 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/260.uart_fifo_reset.1109784092 |
|
|
Sep 04 10:48:07 AM UTC 24 |
Sep 04 10:49:15 AM UTC 24 |
42564679332 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/202.uart_fifo_reset.1245166678 |
|
|
Sep 04 10:46:45 AM UTC 24 |
Sep 04 10:49:17 AM UTC 24 |
138441908468 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/208.uart_fifo_reset.3156157190 |
|
|
Sep 04 10:46:52 AM UTC 24 |
Sep 04 10:49:17 AM UTC 24 |
94793459499 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/292.uart_fifo_reset.1106511684 |
|
|
Sep 04 10:49:00 AM UTC 24 |
Sep 04 10:49:18 AM UTC 24 |
30261328452 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/240.uart_fifo_reset.1271695944 |
|
|
Sep 04 10:47:30 AM UTC 24 |
Sep 04 10:49:18 AM UTC 24 |
138734439056 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2767621586 |
|
|
Sep 04 10:48:29 AM UTC 24 |
Sep 04 10:49:19 AM UTC 24 |
21207866544 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/294.uart_fifo_reset.3301918814 |
|
|
Sep 04 10:49:02 AM UTC 24 |
Sep 04 10:49:23 AM UTC 24 |
37268465182 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/291.uart_fifo_reset.4254061341 |
|
|
Sep 04 10:48:56 AM UTC 24 |
Sep 04 10:49:29 AM UTC 24 |
46656380095 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2840588773 |
|
|
Sep 04 10:48:34 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
98787644556 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/266.uart_fifo_reset.150860934 |
|
|
Sep 04 10:48:14 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
92419824769 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/289.uart_fifo_reset.768537276 |
|
|
Sep 04 10:48:47 AM UTC 24 |
Sep 04 10:49:34 AM UTC 24 |
98491010844 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/297.uart_fifo_reset.3165597812 |
|
|
Sep 04 10:49:04 AM UTC 24 |
Sep 04 10:49:36 AM UTC 24 |
48987716679 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3434927248 |
|
|
Sep 04 10:49:02 AM UTC 24 |
Sep 04 10:49:37 AM UTC 24 |
53207385238 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/264.uart_fifo_reset.2007755221 |
|
|
Sep 04 10:48:13 AM UTC 24 |
Sep 04 10:49:37 AM UTC 24 |
143950212765 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/270.uart_fifo_reset.2986801603 |
|
|
Sep 04 10:48:18 AM UTC 24 |
Sep 04 10:49:45 AM UTC 24 |
160944774345 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/233.uart_fifo_reset.1095403081 |
|
|
Sep 04 10:47:22 AM UTC 24 |
Sep 04 10:49:47 AM UTC 24 |
72647358463 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2257627400 |
|
|
Sep 04 10:48:35 AM UTC 24 |
Sep 04 10:49:49 AM UTC 24 |
33393419162 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/287.uart_fifo_reset.2430121120 |
|
|
Sep 04 10:48:40 AM UTC 24 |
Sep 04 10:49:51 AM UTC 24 |
139025603867 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/277.uart_fifo_reset.2538553457 |
|
|
Sep 04 10:48:34 AM UTC 24 |
Sep 04 10:49:57 AM UTC 24 |
171071092936 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/196.uart_fifo_reset.2940781336 |
|
|
Sep 04 10:46:38 AM UTC 24 |
Sep 04 10:49:58 AM UTC 24 |
111114538367 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3319925069 |
|
|
Sep 04 10:46:26 AM UTC 24 |
Sep 04 10:49:59 AM UTC 24 |
363705302591 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/256.uart_fifo_reset.3733850484 |
|
|
Sep 04 10:48:00 AM UTC 24 |
Sep 04 10:50:00 AM UTC 24 |
58183625767 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1387570669 |
|
|
Sep 04 10:49:04 AM UTC 24 |
Sep 04 10:50:00 AM UTC 24 |
94337283678 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2962293470 |
|
|
Sep 04 10:48:34 AM UTC 24 |
Sep 04 10:50:01 AM UTC 24 |
47646043352 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/237.uart_fifo_reset.3605336139 |
|
|
Sep 04 10:47:27 AM UTC 24 |
Sep 04 10:50:02 AM UTC 24 |
55282450411 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/290.uart_fifo_reset.3916942663 |
|
|
Sep 04 10:48:56 AM UTC 24 |
Sep 04 10:50:07 AM UTC 24 |
139479624861 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2573051979 |
|
|
Sep 04 10:49:02 AM UTC 24 |
Sep 04 10:50:14 AM UTC 24 |
32972600226 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/223.uart_fifo_reset.895561340 |
|
|
Sep 04 10:47:13 AM UTC 24 |
Sep 04 10:50:18 AM UTC 24 |
122260878888 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/293.uart_fifo_reset.3734383967 |
|
|
Sep 04 10:49:01 AM UTC 24 |
Sep 04 10:50:27 AM UTC 24 |
56530438617 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/254.uart_fifo_reset.3331265993 |
|
|
Sep 04 10:48:00 AM UTC 24 |
Sep 04 10:50:31 AM UTC 24 |
90418329655 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2672864963 |
|
|
Sep 04 10:47:49 AM UTC 24 |
Sep 04 10:50:34 AM UTC 24 |
118647335273 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1132423390 |
|
|
Sep 04 10:47:34 AM UTC 24 |
Sep 04 10:50:43 AM UTC 24 |
137105871854 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/102.uart_fifo_reset.1939380615 |
|
|
Sep 04 10:43:59 AM UTC 24 |
Sep 04 10:51:02 AM UTC 24 |
92958261308 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_stress_all.341416909 |
|
|
Sep 04 10:25:22 AM UTC 24 |
Sep 04 10:51:26 AM UTC 24 |
292252655201 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/271.uart_fifo_reset.2285436245 |
|
|
Sep 04 10:48:19 AM UTC 24 |
Sep 04 10:51:28 AM UTC 24 |
148708146572 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_stress_all.2717243190 |
|
|
Sep 04 10:40:28 AM UTC 24 |
Sep 04 10:51:36 AM UTC 24 |
411459993871 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/286.uart_fifo_reset.427301183 |
|
|
Sep 04 10:48:39 AM UTC 24 |
Sep 04 10:51:43 AM UTC 24 |
119268520652 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.3296968682 |
|
|
Sep 04 10:39:01 AM UTC 24 |
Sep 04 10:51:49 AM UTC 24 |
149460531093 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/288.uart_fifo_reset.2555697264 |
|
|
Sep 04 10:48:41 AM UTC 24 |
Sep 04 10:51:53 AM UTC 24 |
121190301566 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/265.uart_fifo_reset.1879052543 |
|
|
Sep 04 10:48:14 AM UTC 24 |
Sep 04 10:52:04 AM UTC 24 |
96607339268 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/299.uart_fifo_reset.4166033553 |
|
|
Sep 04 10:49:07 AM UTC 24 |
Sep 04 10:52:04 AM UTC 24 |
108618309550 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_perf.833532585 |
|
|
Sep 04 10:33:50 AM UTC 24 |
Sep 04 10:52:05 AM UTC 24 |
23054597141 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_stress_all.974371286 |
|
|
Sep 04 10:31:32 AM UTC 24 |
Sep 04 10:52:08 AM UTC 24 |
265730424066 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/157.uart_fifo_reset.4008101269 |
|
|
Sep 04 10:45:30 AM UTC 24 |
Sep 04 10:52:26 AM UTC 24 |
53789685200 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.1607500543 |
|
|
Sep 04 10:35:50 AM UTC 24 |
Sep 04 10:52:48 AM UTC 24 |
140397878151 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/280.uart_fifo_reset.75722090 |
|
|
Sep 04 10:48:35 AM UTC 24 |
Sep 04 10:52:56 AM UTC 24 |
83550544381 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/150.uart_fifo_reset.2899630328 |
|
|
Sep 04 10:45:16 AM UTC 24 |
Sep 04 10:53:00 AM UTC 24 |
120693084356 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/284.uart_fifo_reset.4093972055 |
|
|
Sep 04 10:48:37 AM UTC 24 |
Sep 04 10:53:10 AM UTC 24 |
156684657640 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/226.uart_fifo_reset.3158895958 |
|
|
Sep 04 10:47:16 AM UTC 24 |
Sep 04 10:53:21 AM UTC 24 |
165670974527 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_perf.2283544760 |
|
|
Sep 04 10:40:22 AM UTC 24 |
Sep 04 10:54:11 AM UTC 24 |
17874347401 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/90.uart_fifo_reset.727679437 |
|
|
Sep 04 10:43:22 AM UTC 24 |
Sep 04 10:56:23 AM UTC 24 |
105212325078 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_perf.1348086544 |
|
|
Sep 04 10:34:31 AM UTC 24 |
Sep 04 11:02:05 AM UTC 24 |
30851518109 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.734790113 |
|
|
Sep 04 10:49:07 AM UTC 24 |
Sep 04 10:49:09 AM UTC 24 |
59106599 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1935998333 |
|
|
Sep 04 10:49:07 AM UTC 24 |
Sep 04 10:49:09 AM UTC 24 |
12307034 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.64347685 |
|
|
Sep 04 10:49:07 AM UTC 24 |
Sep 04 10:49:09 AM UTC 24 |
324214915 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1497253485 |
|
|
Sep 04 10:49:08 AM UTC 24 |
Sep 04 10:49:10 AM UTC 24 |
17689172 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.284970100 |
|
|
Sep 04 10:49:07 AM UTC 24 |
Sep 04 10:49:11 AM UTC 24 |
45933418 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.1522957894 |
|
|
Sep 04 10:49:09 AM UTC 24 |
Sep 04 10:49:11 AM UTC 24 |
172205320 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.1997091247 |
|
|
Sep 04 10:49:10 AM UTC 24 |
Sep 04 10:49:12 AM UTC 24 |
13053095 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2030371293 |
|
|
Sep 04 10:49:10 AM UTC 24 |
Sep 04 10:49:12 AM UTC 24 |
187820298 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.3409384075 |
|
|
Sep 04 10:49:09 AM UTC 24 |
Sep 04 10:49:14 AM UTC 24 |
418935753 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1587272119 |
|
|
Sep 04 10:49:10 AM UTC 24 |
Sep 04 10:49:14 AM UTC 24 |
351472432 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.4120940352 |
|
|
Sep 04 10:49:11 AM UTC 24 |
Sep 04 10:49:14 AM UTC 24 |
639839819 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.2959471140 |
|
|
Sep 04 10:49:12 AM UTC 24 |
Sep 04 10:49:14 AM UTC 24 |
143308302 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3325122922 |
|
|
Sep 04 10:49:13 AM UTC 24 |
Sep 04 10:49:14 AM UTC 24 |
15613432 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.2728144348 |
|
|
Sep 04 10:49:13 AM UTC 24 |
Sep 04 10:49:14 AM UTC 24 |
14535287 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.1586812266 |
|
|
Sep 04 10:49:14 AM UTC 24 |
Sep 04 10:49:16 AM UTC 24 |
36633582 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2496201939 |
|
|
Sep 04 10:49:15 AM UTC 24 |
Sep 04 10:49:17 AM UTC 24 |
16408382 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.620185279 |
|
|
Sep 04 10:49:15 AM UTC 24 |
Sep 04 10:49:17 AM UTC 24 |
35623123 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2419907969 |
|
|
Sep 04 10:49:15 AM UTC 24 |
Sep 04 10:49:17 AM UTC 24 |
128081399 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1481009488 |
|
|
Sep 04 10:49:15 AM UTC 24 |
Sep 04 10:49:17 AM UTC 24 |
75513550 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.1299448453 |
|
|
Sep 04 10:49:15 AM UTC 24 |
Sep 04 10:49:18 AM UTC 24 |
42829611 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.905135122 |
|
|
Sep 04 10:49:15 AM UTC 24 |
Sep 04 10:49:18 AM UTC 24 |
214220106 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3007283719 |
|
|
Sep 04 10:49:14 AM UTC 24 |
Sep 04 10:49:18 AM UTC 24 |
175822640 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.4017368801 |
|
|
Sep 04 10:49:16 AM UTC 24 |
Sep 04 10:49:18 AM UTC 24 |
63810913 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3382131766 |
|
|
Sep 04 10:49:16 AM UTC 24 |
Sep 04 10:49:18 AM UTC 24 |
20619597 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.626805360 |
|
|
Sep 04 10:49:17 AM UTC 24 |
Sep 04 10:49:19 AM UTC 24 |
65705825 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.4273898132 |
|
|
Sep 04 10:49:18 AM UTC 24 |
Sep 04 10:49:20 AM UTC 24 |
36350941 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.3561187175 |
|
|
Sep 04 10:49:18 AM UTC 24 |
Sep 04 10:49:20 AM UTC 24 |
49866069 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3459089917 |
|
|
Sep 04 10:49:18 AM UTC 24 |
Sep 04 10:49:20 AM UTC 24 |
27499066 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.1367350738 |
|
|
Sep 04 10:49:16 AM UTC 24 |
Sep 04 10:49:21 AM UTC 24 |
583429695 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.890378044 |
|
|
Sep 04 10:49:19 AM UTC 24 |
Sep 04 10:49:21 AM UTC 24 |
34886193 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3318457277 |
|
|
Sep 04 10:49:19 AM UTC 24 |
Sep 04 10:49:21 AM UTC 24 |
13787648 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1379147206 |
|
|
Sep 04 10:49:19 AM UTC 24 |
Sep 04 10:49:21 AM UTC 24 |
49774437 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.3527667992 |
|
|
Sep 04 10:49:19 AM UTC 24 |
Sep 04 10:49:21 AM UTC 24 |
76302357 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1408268820 |
|
|
Sep 04 10:49:19 AM UTC 24 |
Sep 04 10:49:21 AM UTC 24 |
83752165 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1148517049 |
|
|
Sep 04 10:49:19 AM UTC 24 |
Sep 04 10:49:21 AM UTC 24 |
81007573 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.2487884416 |
|
|
Sep 04 10:49:19 AM UTC 24 |
Sep 04 10:49:22 AM UTC 24 |
146663845 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2084330339 |
|
|
Sep 04 10:49:19 AM UTC 24 |
Sep 04 10:49:23 AM UTC 24 |
245007183 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.1033133934 |
|
|
Sep 04 10:49:21 AM UTC 24 |
Sep 04 10:49:23 AM UTC 24 |
42246474 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.119649646 |
|
|
Sep 04 10:49:21 AM UTC 24 |
Sep 04 10:49:23 AM UTC 24 |
48220206 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.1276712300 |
|
|
Sep 04 10:49:21 AM UTC 24 |
Sep 04 10:49:23 AM UTC 24 |
44599431 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.3037725717 |
|
|
Sep 04 10:49:19 AM UTC 24 |
Sep 04 10:49:24 AM UTC 24 |
111165754 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.801529686 |
|
|
Sep 04 10:49:21 AM UTC 24 |
Sep 04 10:49:24 AM UTC 24 |
94260421 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2188907978 |
|
|
Sep 04 10:49:23 AM UTC 24 |
Sep 04 10:49:25 AM UTC 24 |
56789658 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3381055137 |
|
|
Sep 04 10:49:22 AM UTC 24 |
Sep 04 10:49:25 AM UTC 24 |
12943928 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2770612340 |
|
|
Sep 04 10:49:22 AM UTC 24 |
Sep 04 10:49:25 AM UTC 24 |
23141110 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.178567113 |
|
|
Sep 04 10:49:23 AM UTC 24 |
Sep 04 10:49:25 AM UTC 24 |
21272081 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.1689890718 |
|
|
Sep 04 10:49:23 AM UTC 24 |
Sep 04 10:49:25 AM UTC 24 |
30443154 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3705079854 |
|
|
Sep 04 10:49:22 AM UTC 24 |
Sep 04 10:49:25 AM UTC 24 |
17256009 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3754656002 |
|
|
Sep 04 10:49:23 AM UTC 24 |
Sep 04 10:49:25 AM UTC 24 |
46146337 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.4028011784 |
|
|
Sep 04 10:49:23 AM UTC 24 |
Sep 04 10:49:25 AM UTC 24 |
75994250 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.534146595 |
|
|
Sep 04 10:49:23 AM UTC 24 |
Sep 04 10:49:26 AM UTC 24 |
162509161 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.447768964 |
|
|
Sep 04 10:49:24 AM UTC 24 |
Sep 04 10:49:26 AM UTC 24 |
10695395 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.3303004225 |
|
|
Sep 04 10:49:24 AM UTC 24 |
Sep 04 10:49:27 AM UTC 24 |
30418537 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.2935164805 |
|
|
Sep 04 10:49:24 AM UTC 24 |
Sep 04 10:49:27 AM UTC 24 |
39170184 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3087660188 |
|
|
Sep 04 10:49:24 AM UTC 24 |
Sep 04 10:49:28 AM UTC 24 |
162614569 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.2363162972 |
|
|
Sep 04 10:49:26 AM UTC 24 |
Sep 04 10:49:28 AM UTC 24 |
12221992 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.98066288 |
|
|
Sep 04 10:49:26 AM UTC 24 |
Sep 04 10:49:28 AM UTC 24 |
13424359 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2211634433 |
|
|
Sep 04 10:49:24 AM UTC 24 |
Sep 04 10:49:28 AM UTC 24 |
155318768 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2329804887 |
|
|
Sep 04 10:49:26 AM UTC 24 |
Sep 04 10:49:28 AM UTC 24 |
47427846 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3372377845 |
|
|
Sep 04 10:49:26 AM UTC 24 |
Sep 04 10:49:28 AM UTC 24 |
115100659 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3204671918 |
|
|
Sep 04 10:49:26 AM UTC 24 |
Sep 04 10:49:28 AM UTC 24 |
61376230 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.1482326490 |
|
|
Sep 04 10:49:26 AM UTC 24 |
Sep 04 10:49:29 AM UTC 24 |
73132343 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.3159230183 |
|
|
Sep 04 10:49:26 AM UTC 24 |
Sep 04 10:49:29 AM UTC 24 |
237294648 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.942358791 |
|
|
Sep 04 10:49:28 AM UTC 24 |
Sep 04 10:49:30 AM UTC 24 |
23499123 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1027640543 |
|
|
Sep 04 10:49:26 AM UTC 24 |
Sep 04 10:49:30 AM UTC 24 |
140771824 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.3959368548 |
|
|
Sep 04 10:49:28 AM UTC 24 |
Sep 04 10:49:30 AM UTC 24 |
26612180 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3715238636 |
|
|
Sep 04 10:49:28 AM UTC 24 |
Sep 04 10:49:30 AM UTC 24 |
77772676 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3359196260 |
|
|
Sep 04 10:49:28 AM UTC 24 |
Sep 04 10:49:30 AM UTC 24 |
25703939 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.2028652106 |
|
|
Sep 04 10:49:27 AM UTC 24 |
Sep 04 10:49:31 AM UTC 24 |
503685926 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3126252599 |
|
|
Sep 04 10:49:29 AM UTC 24 |
Sep 04 10:49:31 AM UTC 24 |
45009825 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2437748503 |
|
|
Sep 04 10:49:29 AM UTC 24 |
Sep 04 10:49:32 AM UTC 24 |
17356305 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.3480368110 |
|
|
Sep 04 10:49:29 AM UTC 24 |
Sep 04 10:49:32 AM UTC 24 |
11479740 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.3604447178 |
|
|
Sep 04 10:49:29 AM UTC 24 |
Sep 04 10:49:32 AM UTC 24 |
57636043 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2152905026 |
|
|
Sep 04 10:49:28 AM UTC 24 |
Sep 04 10:49:32 AM UTC 24 |
195945793 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3166558817 |
|
|
Sep 04 10:49:29 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
90037354 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1164749634 |
|
|
Sep 04 10:49:31 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
21064709 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1871783121 |
|
|
Sep 04 10:49:29 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
220740694 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2117106662 |
|
|
Sep 04 10:49:31 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
24204205 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.10262505 |
|
|
Sep 04 10:49:31 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
28918551 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1260125537 |
|
|
Sep 04 10:49:29 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
53103039 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3927504544 |
|
|
Sep 04 10:49:31 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
30636189 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1539630496 |
|
|
Sep 04 10:49:31 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
17604586 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.2877631786 |
|
|
Sep 04 10:49:31 AM UTC 24 |
Sep 04 10:49:33 AM UTC 24 |
18075061 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.3793417887 |
|
|
Sep 04 10:49:31 AM UTC 24 |
Sep 04 10:49:34 AM UTC 24 |
330430452 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2184488303 |
|
|
Sep 04 10:49:31 AM UTC 24 |
Sep 04 10:49:34 AM UTC 24 |
42825413 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.1138749664 |
|
|
Sep 04 10:49:33 AM UTC 24 |
Sep 04 10:49:35 AM UTC 24 |
14518755 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1184425224 |
|
|
Sep 04 10:49:33 AM UTC 24 |
Sep 04 10:49:35 AM UTC 24 |
124573144 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.856392749 |
|
|
Sep 04 10:49:33 AM UTC 24 |
Sep 04 10:49:35 AM UTC 24 |
16708408 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1054067985 |
|
|
Sep 04 10:49:33 AM UTC 24 |
Sep 04 10:49:35 AM UTC 24 |
20607638 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.1908547463 |
|
|
Sep 04 10:49:33 AM UTC 24 |
Sep 04 10:49:36 AM UTC 24 |
161731912 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.1499409506 |
|
|
Sep 04 10:49:33 AM UTC 24 |
Sep 04 10:49:36 AM UTC 24 |
96377663 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3666309580 |
|
|
Sep 04 10:49:56 AM UTC 24 |
Sep 04 10:49:57 AM UTC 24 |
12702325 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.3899261530 |
|
|
Sep 04 10:49:36 AM UTC 24 |
Sep 04 10:49:38 AM UTC 24 |
21825458 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.543904225 |
|
|
Sep 04 10:49:36 AM UTC 24 |
Sep 04 10:49:38 AM UTC 24 |
18751379 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.100146581 |
|
|
Sep 04 10:49:36 AM UTC 24 |
Sep 04 10:49:38 AM UTC 24 |
54109297 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1882794590 |
|
|
Sep 04 10:49:36 AM UTC 24 |
Sep 04 10:49:38 AM UTC 24 |
11099269 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1730074125 |
|
|
Sep 04 10:49:36 AM UTC 24 |
Sep 04 10:49:38 AM UTC 24 |
20991310 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.89898281 |
|
|
Sep 04 10:49:36 AM UTC 24 |
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