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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1316
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T1253 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.564686304 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:38 AM UTC 24 11025881 ps
T1254 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.4239161328 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:39 AM UTC 24 17263608 ps
T1255 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2091205122 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:39 AM UTC 24 155731238 ps
T1256 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3132030091 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:39 AM UTC 24 158120814 ps
T1257 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.422989345 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:39 AM UTC 24 57477128 ps
T1258 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.3313083358 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:39 AM UTC 24 317196579 ps
T1259 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3349500898 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:39 AM UTC 24 452888248 ps
T1260 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2302947239 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:39 AM UTC 24 376169124 ps
T1261 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.520889123 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:39 AM UTC 24 1159021027 ps
T1262 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1621320896 Sep 04 10:49:36 AM UTC 24 Sep 04 10:49:39 AM UTC 24 53148286 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.344372888 Sep 04 10:49:38 AM UTC 24 Sep 04 10:49:40 AM UTC 24 47470351 ps
T1263 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.3482055841 Sep 04 10:49:38 AM UTC 24 Sep 04 10:49:40 AM UTC 24 27579252 ps
T1264 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1366886485 Sep 04 10:49:38 AM UTC 24 Sep 04 10:49:40 AM UTC 24 161698910 ps
T1265 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2800951598 Sep 04 10:49:38 AM UTC 24 Sep 04 10:49:40 AM UTC 24 31438202 ps
T1266 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2847466378 Sep 04 10:49:38 AM UTC 24 Sep 04 10:49:40 AM UTC 24 44204764 ps
T1267 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.1347322416 Sep 04 10:49:38 AM UTC 24 Sep 04 10:49:41 AM UTC 24 318668594 ps
T1268 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1395080348 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 30167355 ps
T1269 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2196396151 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 36013284 ps
T1270 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.3473186167 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 28565607 ps
T1271 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4038122946 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 34165777 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.901885297 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 106044096 ps
T1272 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.1268675117 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 169247292 ps
T1273 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3496926495 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 98621119 ps
T1274 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3796793094 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 14396982 ps
T1275 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3556219744 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 20913265 ps
T1276 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3500369274 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 15880914 ps
T1277 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.4240026815 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:44 AM UTC 24 22013564 ps
T1278 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1190514485 Sep 04 10:49:43 AM UTC 24 Sep 04 10:49:45 AM UTC 24 43182382 ps
T1279 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.2097511626 Sep 04 10:49:43 AM UTC 24 Sep 04 10:49:45 AM UTC 24 14070597 ps
T1280 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.3669681269 Sep 04 10:49:43 AM UTC 24 Sep 04 10:49:45 AM UTC 24 15039772 ps
T1281 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2577571271 Sep 04 10:49:43 AM UTC 24 Sep 04 10:49:45 AM UTC 24 18601982 ps
T1282 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.855603687 Sep 04 10:49:43 AM UTC 24 Sep 04 10:49:45 AM UTC 24 44866311 ps
T1283 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3127482594 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:45 AM UTC 24 155788961 ps
T1284 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2021004432 Sep 04 10:49:43 AM UTC 24 Sep 04 10:49:45 AM UTC 24 34253049 ps
T1285 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.330789433 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:45 AM UTC 24 26063043 ps
T1286 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.432021248 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:45 AM UTC 24 95189043 ps
T1287 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3619402402 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:45 AM UTC 24 315525944 ps
T1288 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.514435011 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:45 AM UTC 24 190415294 ps
T1289 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1759950354 Sep 04 10:49:42 AM UTC 24 Sep 04 10:49:46 AM UTC 24 394517415 ps
T1290 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2207753714 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 13571340 ps
T1291 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1583929661 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 45425540 ps
T1292 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1902506667 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 14954690 ps
T1293 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3608712461 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 103297962 ps
T1294 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.2870946240 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 13182083 ps
T1295 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.957431314 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 56252667 ps
T1296 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.4257477571 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 13464440 ps
T1297 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1068298400 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 29963303 ps
T1298 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.1281570635 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 34804309 ps
T1299 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.499789406 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 21878568 ps
T1300 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.4006604635 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 11092876 ps
T1301 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.971308957 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 14274839 ps
T1302 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.328417574 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 56402685 ps
T1303 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2151891569 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 12590176 ps
T1304 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3154366609 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 110251485 ps
T1305 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.2106926637 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 16083020 ps
T1306 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3261131184 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 50494831 ps
T1307 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.2725190699 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 44498490 ps
T1308 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2987038870 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 17574011 ps
T1309 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1811616846 Sep 04 10:49:49 AM UTC 24 Sep 04 10:49:50 AM UTC 24 27598388 ps
T1310 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3545785192 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:50 AM UTC 24 11745917 ps
T1311 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1746523477 Sep 04 10:49:49 AM UTC 24 Sep 04 10:49:51 AM UTC 24 13375170 ps
T1312 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.728937003 Sep 04 10:49:48 AM UTC 24 Sep 04 10:49:51 AM UTC 24 29058191 ps
T1313 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.373757195 Sep 04 10:49:49 AM UTC 24 Sep 04 10:49:51 AM UTC 24 25529292 ps
T1314 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.743526740 Sep 04 10:49:50 AM UTC 24 Sep 04 10:49:52 AM UTC 24 13762547 ps
T1315 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.548887673 Sep 04 10:49:50 AM UTC 24 Sep 04 10:49:52 AM UTC 24 25697217 ps
T1316 /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2519022250 Sep 04 10:49:56 AM UTC 24 Sep 04 10:49:57 AM UTC 24 13736219 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_fifo_full.3929016426
Short name T3
Test name
Test status
Simulation time 154738901903 ps
CPU time 143.33 seconds
Started Sep 04 10:07:00 AM UTC 24
Finished Sep 04 10:09:26 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929016426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3929016426
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.3905882135
Short name T18
Test name
Test status
Simulation time 54674359065 ps
CPU time 53.24 seconds
Started Sep 04 10:06:04 AM UTC 24
Finished Sep 04 10:06:59 AM UTC 24
Peak memory 217624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3905882135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_
with_rand_reset.3905882135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_stress_all.4186799378
Short name T94
Test name
Test status
Simulation time 285549691010 ps
CPU time 491.23 seconds
Started Sep 04 10:06:06 AM UTC 24
Finished Sep 04 10:14:23 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186799378 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4186799378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_fifo_full.4255441978
Short name T19
Test name
Test status
Simulation time 61713679168 ps
CPU time 24.93 seconds
Started Sep 04 10:05:59 AM UTC 24
Finished Sep 04 10:06:26 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255441978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4255441978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.4256790147
Short name T273
Test name
Test status
Simulation time 117970498123 ps
CPU time 278.95 seconds
Started Sep 04 10:06:14 AM UTC 24
Finished Sep 04 10:10:57 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256790147 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4256790147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_stress_all.2229167281
Short name T11
Test name
Test status
Simulation time 54881896790 ps
CPU time 10.61 seconds
Started Sep 04 10:06:04 AM UTC 24
Finished Sep 04 10:06:16 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229167281 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2229167281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.2702827960
Short name T25
Test name
Test status
Simulation time 18417685139 ps
CPU time 106.04 seconds
Started Sep 04 10:06:06 AM UTC 24
Finished Sep 04 10:07:54 AM UTC 24
Peak memory 219680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2702827960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_
with_rand_reset.2702827960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.1989678022
Short name T263
Test name
Test status
Simulation time 88446611198 ps
CPU time 86.21 seconds
Started Sep 04 10:14:02 AM UTC 24
Finished Sep 04 10:15:30 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989678022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1989678022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.1974467959
Short name T97
Test name
Test status
Simulation time 296587236817 ps
CPU time 145.14 seconds
Started Sep 04 10:08:04 AM UTC 24
Finished Sep 04 10:10:32 AM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974467959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1974467959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_sec_cm.3678529427
Short name T26
Test name
Test status
Simulation time 110296127 ps
CPU time 1.36 seconds
Started Sep 04 10:06:07 AM UTC 24
Finished Sep 04 10:06:10 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678529427 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3678529427
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_stress_all.1327899958
Short name T183
Test name
Test status
Simulation time 325516250549 ps
CPU time 633.79 seconds
Started Sep 04 10:11:05 AM UTC 24
Finished Sep 04 10:21:46 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327899958 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1327899958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1479220002
Short name T144
Test name
Test status
Simulation time 35671658182 ps
CPU time 38.64 seconds
Started Sep 04 10:10:23 AM UTC 24
Finished Sep 04 10:11:03 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479220002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1479220002
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.142557818
Short name T168
Test name
Test status
Simulation time 74327396060 ps
CPU time 162.72 seconds
Started Sep 04 10:08:57 AM UTC 24
Finished Sep 04 10:11:43 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142557818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.142557818
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_stress_all.2631546738
Short name T125
Test name
Test status
Simulation time 74638494366 ps
CPU time 134.8 seconds
Started Sep 04 10:10:10 AM UTC 24
Finished Sep 04 10:12:27 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631546738 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2631546738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1935998333
Short name T53
Test name
Test status
Simulation time 12307034 ps
CPU time 0.86 seconds
Started Sep 04 10:49:07 AM UTC 24
Finished Sep 04 10:49:09 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935998333 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1935998333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_stress_all.3373887911
Short name T146
Test name
Test status
Simulation time 352056885333 ps
CPU time 449.98 seconds
Started Sep 04 10:15:54 AM UTC 24
Finished Sep 04 10:23:30 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373887911 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3373887911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_perf.3881321643
Short name T52
Test name
Test status
Simulation time 17881832419 ps
CPU time 124.76 seconds
Started Sep 04 10:07:33 AM UTC 24
Finished Sep 04 10:09:40 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881321643 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3881321643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_noise_filter.925269600
Short name T111
Test name
Test status
Simulation time 73297714923 ps
CPU time 70.15 seconds
Started Sep 04 10:06:31 AM UTC 24
Finished Sep 04 10:07:43 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925269600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.925269600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_stress_all.1569633285
Short name T332
Test name
Test status
Simulation time 203699243481 ps
CPU time 797.06 seconds
Started Sep 04 10:06:15 AM UTC 24
Finished Sep 04 10:19:41 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569633285 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1569633285
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.2266316703
Short name T36
Test name
Test status
Simulation time 8222625605 ps
CPU time 97.88 seconds
Started Sep 04 10:09:04 AM UTC 24
Finished Sep 04 10:10:44 AM UTC 24
Peak memory 219700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2266316703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_
with_rand_reset.2266316703
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.4120940352
Short name T78
Test name
Test status
Simulation time 639839819 ps
CPU time 1.79 seconds
Started Sep 04 10:49:11 AM UTC 24
Finished Sep 04 10:49:14 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120940352 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.4120940352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_fifo_full.236497029
Short name T123
Test name
Test status
Simulation time 413488598105 ps
CPU time 106.23 seconds
Started Sep 04 10:16:51 AM UTC 24
Finished Sep 04 10:18:39 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236497029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.236497029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.4094752098
Short name T305
Test name
Test status
Simulation time 63083026440 ps
CPU time 287.19 seconds
Started Sep 04 10:13:20 AM UTC 24
Finished Sep 04 10:18:11 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094752098 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4094752098
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_stress_all.2463103443
Short name T93
Test name
Test status
Simulation time 197218099124 ps
CPU time 276.12 seconds
Started Sep 04 10:06:55 AM UTC 24
Finished Sep 04 10:11:34 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463103443 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2463103443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.4099808956
Short name T118
Test name
Test status
Simulation time 37119978313 ps
CPU time 76.03 seconds
Started Sep 04 10:07:55 AM UTC 24
Finished Sep 04 10:09:13 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099808956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4099808956
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_alert_test.1613415214
Short name T5
Test name
Test status
Simulation time 41620393 ps
CPU time 0.78 seconds
Started Sep 04 10:06:04 AM UTC 24
Finished Sep 04 10:06:06 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613415214 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1613415214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_stress_all.3005845171
Short name T143
Test name
Test status
Simulation time 132947947688 ps
CPU time 97.5 seconds
Started Sep 04 10:24:52 AM UTC 24
Finished Sep 04 10:26:31 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005845171 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3005845171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.2120809763
Short name T137
Test name
Test status
Simulation time 170220393646 ps
CPU time 39.66 seconds
Started Sep 04 10:12:38 AM UTC 24
Finished Sep 04 10:13:19 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120809763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2120809763
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_fifo_full.1778358518
Short name T95
Test name
Test status
Simulation time 157774291415 ps
CPU time 107.06 seconds
Started Sep 04 10:06:10 AM UTC 24
Finished Sep 04 10:07:59 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778358518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1778358518
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_stress_all.2161116083
Short name T113
Test name
Test status
Simulation time 163738047152 ps
CPU time 103.1 seconds
Started Sep 04 10:07:43 AM UTC 24
Finished Sep 04 10:09:28 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161116083 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2161116083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_noise_filter.1016237160
Short name T112
Test name
Test status
Simulation time 250734401774 ps
CPU time 114.66 seconds
Started Sep 04 10:06:05 AM UTC 24
Finished Sep 04 10:08:02 AM UTC 24
Peak memory 219920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016237160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1016237160
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.1997091247
Short name T65
Test name
Test status
Simulation time 13053095 ps
CPU time 0.91 seconds
Started Sep 04 10:49:10 AM UTC 24
Finished Sep 04 10:49:12 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997091247 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.1997091247
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_noise_filter.3181077415
Short name T340
Test name
Test status
Simulation time 156819737552 ps
CPU time 113.94 seconds
Started Sep 04 10:19:11 AM UTC 24
Finished Sep 04 10:21:07 AM UTC 24
Peak memory 217296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181077415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3181077415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_stress_all.904556780
Short name T345
Test name
Test status
Simulation time 405489199753 ps
CPU time 571.09 seconds
Started Sep 04 10:14:18 AM UTC 24
Finished Sep 04 10:23:55 AM UTC 24
Peak memory 219704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904556780 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.904556780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_noise_filter.2942893691
Short name T267
Test name
Test status
Simulation time 139630025693 ps
CPU time 129.49 seconds
Started Sep 04 10:08:51 AM UTC 24
Finished Sep 04 10:11:03 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942893691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2942893691
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.2770248859
Short name T39
Test name
Test status
Simulation time 5740279652 ps
CPU time 41.14 seconds
Started Sep 04 10:11:43 AM UTC 24
Finished Sep 04 10:12:26 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2770248859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_
with_rand_reset.2770248859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_stress_all.2337185803
Short name T584
Test name
Test status
Simulation time 436807743493 ps
CPU time 664.68 seconds
Started Sep 04 10:16:38 AM UTC 24
Finished Sep 04 10:27:50 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337185803 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2337185803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_intr.3428740818
Short name T373
Test name
Test status
Simulation time 40141921666 ps
CPU time 48.81 seconds
Started Sep 04 10:16:11 AM UTC 24
Finished Sep 04 10:17:01 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428740818 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3428740818
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/51.uart_fifo_reset.293869608
Short name T174
Test name
Test status
Simulation time 339411741998 ps
CPU time 56.19 seconds
Started Sep 04 10:40:36 AM UTC 24
Finished Sep 04 10:41:34 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293869608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.293869608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/51.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.2454216616
Short name T20
Test name
Test status
Simulation time 23726547639 ps
CPU time 42.47 seconds
Started Sep 04 10:06:01 AM UTC 24
Finished Sep 04 10:06:46 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454216616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2454216616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/140.uart_fifo_reset.1525161622
Short name T244
Test name
Test status
Simulation time 21153412652 ps
CPU time 66 seconds
Started Sep 04 10:44:58 AM UTC 24
Finished Sep 04 10:46:06 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525161622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1525161622
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/140.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_stress_all.123440008
Short name T567
Test name
Test status
Simulation time 142313356184 ps
CPU time 546.36 seconds
Started Sep 04 10:17:35 AM UTC 24
Finished Sep 04 10:26:49 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123440008 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.123440008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.2934236115
Short name T298
Test name
Test status
Simulation time 56648156949 ps
CPU time 58.98 seconds
Started Sep 04 10:12:31 AM UTC 24
Finished Sep 04 10:13:31 AM UTC 24
Peak memory 221948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2934236115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all
_with_rand_reset.2934236115
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_fifo_reset.2977887908
Short name T227
Test name
Test status
Simulation time 137771619204 ps
CPU time 188.01 seconds
Started Sep 04 10:16:09 AM UTC 24
Finished Sep 04 10:19:20 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977887908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2977887908
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_stress_all.2575364909
Short name T218
Test name
Test status
Simulation time 564116563845 ps
CPU time 835.03 seconds
Started Sep 04 10:08:21 AM UTC 24
Finished Sep 04 10:22:25 AM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575364909 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2575364909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/218.uart_fifo_reset.4285611442
Short name T1099
Test name
Test status
Simulation time 140704340535 ps
CPU time 60.79 seconds
Started Sep 04 10:47:07 AM UTC 24
Finished Sep 04 10:48:09 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285611442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4285611442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/218.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_stress_all.3056914160
Short name T389
Test name
Test status
Simulation time 137546873768 ps
CPU time 730.68 seconds
Started Sep 04 10:26:05 AM UTC 24
Finished Sep 04 10:38:24 AM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056914160 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3056914160
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.566728887
Short name T164
Test name
Test status
Simulation time 72422385222 ps
CPU time 44.02 seconds
Started Sep 04 10:37:43 AM UTC 24
Finished Sep 04 10:38:29 AM UTC 24
Peak memory 221912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=566728887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all_
with_rand_reset.566728887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_noise_filter.959297804
Short name T266
Test name
Test status
Simulation time 130468493792 ps
CPU time 133.51 seconds
Started Sep 04 10:08:02 AM UTC 24
Finished Sep 04 10:10:18 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959297804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.959297804
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_tx_rx.4226874303
Short name T356
Test name
Test status
Simulation time 103941824371 ps
CPU time 147.89 seconds
Started Sep 04 10:20:46 AM UTC 24
Finished Sep 04 10:23:16 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226874303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4226874303
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/291.uart_fifo_reset.4254061341
Short name T253
Test name
Test status
Simulation time 46656380095 ps
CPU time 32.02 seconds
Started Sep 04 10:48:56 AM UTC 24
Finished Sep 04 10:49:29 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254061341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.4254061341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/291.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_fifo_reset.2489203560
Short name T136
Test name
Test status
Simulation time 178159455252 ps
CPU time 87.35 seconds
Started Sep 04 10:10:28 AM UTC 24
Finished Sep 04 10:11:58 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489203560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2489203560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/105.uart_fifo_reset.3363666302
Short name T199
Test name
Test status
Simulation time 108790717165 ps
CPU time 194.25 seconds
Started Sep 04 10:44:00 AM UTC 24
Finished Sep 04 10:47:17 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363666302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3363666302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/105.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.1016748511
Short name T105
Test name
Test status
Simulation time 10792990961 ps
CPU time 127.84 seconds
Started Sep 04 10:14:15 AM UTC 24
Finished Sep 04 10:16:25 AM UTC 24
Peak memory 225412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1016748511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all
_with_rand_reset.1016748511
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/161.uart_fifo_reset.515197776
Short name T1033
Test name
Test status
Simulation time 11764582298 ps
CPU time 38.76 seconds
Started Sep 04 10:45:33 AM UTC 24
Finished Sep 04 10:46:13 AM UTC 24
Peak memory 208428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515197776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.515197776
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/161.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/277.uart_fifo_reset.2538553457
Short name T176
Test name
Test status
Simulation time 171071092936 ps
CPU time 81.52 seconds
Started Sep 04 10:48:34 AM UTC 24
Finished Sep 04 10:49:57 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538553457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2538553457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/277.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2840588773
Short name T1143
Test name
Test status
Simulation time 98787644556 ps
CPU time 57.42 seconds
Started Sep 04 10:48:34 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840588773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2840588773
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/278.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_fifo_reset.3772172347
Short name T205
Test name
Test status
Simulation time 70684768248 ps
CPU time 29.64 seconds
Started Sep 04 10:32:48 AM UTC 24
Finished Sep 04 10:33:19 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772172347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3772172347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_stress_all.2317613427
Short name T868
Test name
Test status
Simulation time 658287352255 ps
CPU time 252.71 seconds
Started Sep 04 10:35:07 AM UTC 24
Finished Sep 04 10:39:23 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317613427 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2317613427
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.909033588
Short name T100
Test name
Test status
Simulation time 43173620485 ps
CPU time 76.44 seconds
Started Sep 04 10:09:48 AM UTC 24
Finished Sep 04 10:11:06 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909033588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.909033588
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_fifo_full.3423601360
Short name T258
Test name
Test status
Simulation time 162441812470 ps
CPU time 130.01 seconds
Started Sep 04 10:10:21 AM UTC 24
Finished Sep 04 10:12:34 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423601360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3423601360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2174769229
Short name T16
Test name
Test status
Simulation time 21092758602 ps
CPU time 32.44 seconds
Started Sep 04 10:06:05 AM UTC 24
Finished Sep 04 10:06:39 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174769229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2174769229
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/133.uart_fifo_reset.3486093990
Short name T231
Test name
Test status
Simulation time 34719083626 ps
CPU time 33.49 seconds
Started Sep 04 10:44:49 AM UTC 24
Finished Sep 04 10:45:24 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486093990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3486093990
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/133.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_noise_filter.634811855
Short name T447
Test name
Test status
Simulation time 29959906519 ps
CPU time 58.43 seconds
Started Sep 04 10:15:31 AM UTC 24
Finished Sep 04 10:16:31 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634811855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.634811855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_stress_all.1137678540
Short name T167
Test name
Test status
Simulation time 179136598694 ps
CPU time 263.18 seconds
Started Sep 04 10:18:47 AM UTC 24
Finished Sep 04 10:23:13 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137678540 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1137678540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.3696845707
Short name T490
Test name
Test status
Simulation time 11990617639 ps
CPU time 45.68 seconds
Started Sep 04 10:21:56 AM UTC 24
Finished Sep 04 10:22:43 AM UTC 24
Peak memory 219840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3696845707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all
_with_rand_reset.3696845707
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/84.uart_fifo_reset.554574360
Short name T245
Test name
Test status
Simulation time 144023811421 ps
CPU time 50.53 seconds
Started Sep 04 10:42:53 AM UTC 24
Finished Sep 04 10:43:45 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554574360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.554574360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/84.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1871783121
Short name T109
Test name
Test status
Simulation time 220740694 ps
CPU time 1.92 seconds
Started Sep 04 10:49:29 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 200720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871783121 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1871783121
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_fifo_reset.1435750476
Short name T12
Test name
Test status
Simulation time 18570888780 ps
CPU time 14.79 seconds
Started Sep 04 10:06:00 AM UTC 24
Finished Sep 04 10:06:16 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435750476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1435750476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_fifo_full.2234513440
Short name T121
Test name
Test status
Simulation time 63427277925 ps
CPU time 50.21 seconds
Started Sep 04 10:11:52 AM UTC 24
Finished Sep 04 10:12:43 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234513440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2234513440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/110.uart_fifo_reset.1988965866
Short name T193
Test name
Test status
Simulation time 70431405319 ps
CPU time 56.16 seconds
Started Sep 04 10:44:08 AM UTC 24
Finished Sep 04 10:45:06 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988965866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1988965866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/110.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/113.uart_fifo_reset.2678874864
Short name T229
Test name
Test status
Simulation time 50957631151 ps
CPU time 65.71 seconds
Started Sep 04 10:44:17 AM UTC 24
Finished Sep 04 10:45:25 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678874864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2678874864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/113.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.348300291
Short name T128
Test name
Test status
Simulation time 30622322333 ps
CPU time 34.19 seconds
Started Sep 04 10:13:45 AM UTC 24
Finished Sep 04 10:14:20 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348300291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.348300291
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/120.uart_fifo_reset.3531095556
Short name T1047
Test name
Test status
Simulation time 170750941111 ps
CPU time 130.21 seconds
Started Sep 04 10:44:30 AM UTC 24
Finished Sep 04 10:46:42 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531095556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3531095556
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/120.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/130.uart_fifo_reset.1393337016
Short name T233
Test name
Test status
Simulation time 35976587903 ps
CPU time 28.49 seconds
Started Sep 04 10:44:44 AM UTC 24
Finished Sep 04 10:45:14 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393337016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1393337016
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/130.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/138.uart_fifo_reset.1052647287
Short name T240
Test name
Test status
Simulation time 15234719422 ps
CPU time 29.64 seconds
Started Sep 04 10:44:54 AM UTC 24
Finished Sep 04 10:45:25 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052647287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1052647287
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/138.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_tx_rx.1325866825
Short name T316
Test name
Test status
Simulation time 85229256530 ps
CPU time 57.76 seconds
Started Sep 04 10:16:04 AM UTC 24
Finished Sep 04 10:17:03 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325866825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1325866825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/153.uart_fifo_reset.297704431
Short name T234
Test name
Test status
Simulation time 155115347027 ps
CPU time 84.95 seconds
Started Sep 04 10:45:26 AM UTC 24
Finished Sep 04 10:46:53 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297704431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.297704431
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/153.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/160.uart_fifo_reset.2444535760
Short name T222
Test name
Test status
Simulation time 25007117622 ps
CPU time 39.14 seconds
Started Sep 04 10:45:33 AM UTC 24
Finished Sep 04 10:46:13 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444535760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2444535760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/160.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.360446817
Short name T348
Test name
Test status
Simulation time 27153718249 ps
CPU time 56.67 seconds
Started Sep 04 10:18:12 AM UTC 24
Finished Sep 04 10:19:11 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360446817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.360446817
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1652531305
Short name T211
Test name
Test status
Simulation time 92759608307 ps
CPU time 157.04 seconds
Started Sep 04 10:46:15 AM UTC 24
Finished Sep 04 10:48:54 AM UTC 24
Peak memory 208564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652531305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1652531305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/185.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/195.uart_fifo_reset.634863867
Short name T254
Test name
Test status
Simulation time 49737036394 ps
CPU time 24.99 seconds
Started Sep 04 10:46:37 AM UTC 24
Finished Sep 04 10:47:04 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634863867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.634863867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/195.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/211.uart_fifo_reset.332845703
Short name T251
Test name
Test status
Simulation time 27816397377 ps
CPU time 51.87 seconds
Started Sep 04 10:46:59 AM UTC 24
Finished Sep 04 10:47:52 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332845703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.332845703
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/211.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/238.uart_fifo_reset.3465034365
Short name T1124
Test name
Test status
Simulation time 135449240386 ps
CPU time 84.5 seconds
Started Sep 04 10:47:29 AM UTC 24
Finished Sep 04 10:48:55 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465034365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3465034365
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/238.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/240.uart_fifo_reset.1271695944
Short name T170
Test name
Test status
Simulation time 138734439056 ps
CPU time 106.64 seconds
Started Sep 04 10:47:30 AM UTC 24
Finished Sep 04 10:49:18 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271695944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1271695944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/240.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/246.uart_fifo_reset.4138827012
Short name T248
Test name
Test status
Simulation time 42234161841 ps
CPU time 24.35 seconds
Started Sep 04 10:47:46 AM UTC 24
Finished Sep 04 10:48:12 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138827012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.4138827012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/246.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/255.uart_fifo_reset.2545098242
Short name T246
Test name
Test status
Simulation time 74256762983 ps
CPU time 31.61 seconds
Started Sep 04 10:48:00 AM UTC 24
Finished Sep 04 10:48:33 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545098242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2545098242
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/255.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_fifo_reset.2333053384
Short name T238
Test name
Test status
Simulation time 122367506786 ps
CPU time 383.16 seconds
Started Sep 04 10:25:35 AM UTC 24
Finished Sep 04 10:32:03 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333053384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2333053384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/262.uart_fifo_reset.1039956591
Short name T247
Test name
Test status
Simulation time 27549656306 ps
CPU time 24.45 seconds
Started Sep 04 10:48:10 AM UTC 24
Finished Sep 04 10:48:36 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039956591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1039956591
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/262.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_fifo_reset.3244466074
Short name T243
Test name
Test status
Simulation time 224737342860 ps
CPU time 120.16 seconds
Started Sep 04 10:39:17 AM UTC 24
Finished Sep 04 10:41:20 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244466074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3244466074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/67.uart_fifo_reset.669128082
Short name T175
Test name
Test status
Simulation time 192674681870 ps
CPU time 78.39 seconds
Started Sep 04 10:41:38 AM UTC 24
Finished Sep 04 10:42:58 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669128082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.669128082
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/67.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.1522957894
Short name T1187
Test name
Test status
Simulation time 172205320 ps
CPU time 1.11 seconds
Started Sep 04 10:49:09 AM UTC 24
Finished Sep 04 10:49:11 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522957894 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1522957894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.3409384075
Short name T1189
Test name
Test status
Simulation time 418935753 ps
CPU time 3.59 seconds
Started Sep 04 10:49:09 AM UTC 24
Finished Sep 04 10:49:14 AM UTC 24
Peak memory 202756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409384075 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3409384075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2030371293
Short name T1188
Test name
Test status
Simulation time 187820298 ps
CPU time 0.93 seconds
Started Sep 04 10:49:10 AM UTC 24
Finished Sep 04 10:49:12 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2030371293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r
eset.2030371293
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1497253485
Short name T1185
Test name
Test status
Simulation time 17689172 ps
CPU time 0.85 seconds
Started Sep 04 10:49:08 AM UTC 24
Finished Sep 04 10:49:10 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497253485 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1497253485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.734790113
Short name T1184
Test name
Test status
Simulation time 59106599 ps
CPU time 0.86 seconds
Started Sep 04 10:49:07 AM UTC 24
Finished Sep 04 10:49:09 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734790113 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.734790113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.284970100
Short name T1186
Test name
Test status
Simulation time 45933418 ps
CPU time 3.01 seconds
Started Sep 04 10:49:07 AM UTC 24
Finished Sep 04 10:49:11 AM UTC 24
Peak memory 202684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284970100 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.284970100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.64347685
Short name T77
Test name
Test status
Simulation time 324214915 ps
CPU time 1.44 seconds
Started Sep 04 10:49:07 AM UTC 24
Finished Sep 04 10:49:09 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64347685 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.64347685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.1586812266
Short name T1192
Test name
Test status
Simulation time 36633582 ps
CPU time 1.13 seconds
Started Sep 04 10:49:14 AM UTC 24
Finished Sep 04 10:49:16 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586812266 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1586812266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3007283719
Short name T1196
Test name
Test status
Simulation time 175822640 ps
CPU time 3.53 seconds
Started Sep 04 10:49:14 AM UTC 24
Finished Sep 04 10:49:18 AM UTC 24
Peak memory 202824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007283719 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3007283719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3325122922
Short name T54
Test name
Test status
Simulation time 15613432 ps
CPU time 0.91 seconds
Started Sep 04 10:49:13 AM UTC 24
Finished Sep 04 10:49:14 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325122922 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3325122922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1481009488
Short name T1194
Test name
Test status
Simulation time 75513550 ps
CPU time 1.4 seconds
Started Sep 04 10:49:15 AM UTC 24
Finished Sep 04 10:49:17 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1481009488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r
eset.1481009488
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.2728144348
Short name T66
Test name
Test status
Simulation time 14535287 ps
CPU time 0.92 seconds
Started Sep 04 10:49:13 AM UTC 24
Finished Sep 04 10:49:14 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728144348 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2728144348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.2959471140
Short name T1191
Test name
Test status
Simulation time 143308302 ps
CPU time 0.82 seconds
Started Sep 04 10:49:12 AM UTC 24
Finished Sep 04 10:49:14 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959471140 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2959471140
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.620185279
Short name T67
Test name
Test status
Simulation time 35623123 ps
CPU time 0.98 seconds
Started Sep 04 10:49:15 AM UTC 24
Finished Sep 04 10:49:17 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620185279 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.620185279
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1587272119
Short name T1190
Test name
Test status
Simulation time 351472432 ps
CPU time 2.66 seconds
Started Sep 04 10:49:10 AM UTC 24
Finished Sep 04 10:49:14 AM UTC 24
Peak memory 202672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587272119 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1587272119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1539630496
Short name T1239
Test name
Test status
Simulation time 17604586 ps
CPU time 1.11 seconds
Started Sep 04 10:49:31 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1539630496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_
reset.1539630496
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1164749634
Short name T1234
Test name
Test status
Simulation time 21064709 ps
CPU time 0.76 seconds
Started Sep 04 10:49:31 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164749634 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1164749634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2117106662
Short name T1235
Test name
Test status
Simulation time 24204205 ps
CPU time 0.87 seconds
Started Sep 04 10:49:31 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117106662 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2117106662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.10262505
Short name T1236
Test name
Test status
Simulation time 28918551 ps
CPU time 1.07 seconds
Started Sep 04 10:49:31 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10262505 -assert nopostproc +UVM_
TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.10262505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1260125537
Short name T1237
Test name
Test status
Simulation time 53103039 ps
CPU time 2.28 seconds
Started Sep 04 10:49:29 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 202104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260125537 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1260125537
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1054067985
Short name T1244
Test name
Test status
Simulation time 20607638 ps
CPU time 1.32 seconds
Started Sep 04 10:49:33 AM UTC 24
Finished Sep 04 10:49:35 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1054067985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_
reset.1054067985
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.2877631786
Short name T1240
Test name
Test status
Simulation time 18075061 ps
CPU time 0.87 seconds
Started Sep 04 10:49:31 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877631786 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2877631786
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3927504544
Short name T1238
Test name
Test status
Simulation time 30636189 ps
CPU time 0.89 seconds
Started Sep 04 10:49:31 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927504544 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3927504544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1184425224
Short name T1243
Test name
Test status
Simulation time 124573144 ps
CPU time 0.71 seconds
Started Sep 04 10:49:33 AM UTC 24
Finished Sep 04 10:49:35 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184425224 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.1184425224
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2184488303
Short name T1241
Test name
Test status
Simulation time 42825413 ps
CPU time 2.11 seconds
Started Sep 04 10:49:31 AM UTC 24
Finished Sep 04 10:49:34 AM UTC 24
Peak memory 202616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184488303 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2184488303
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.3793417887
Short name T81
Test name
Test status
Simulation time 330430452 ps
CPU time 1.77 seconds
Started Sep 04 10:49:31 AM UTC 24
Finished Sep 04 10:49:34 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793417887 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3793417887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.100146581
Short name T1250
Test name
Test status
Simulation time 54109297 ps
CPU time 0.87 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:38 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=100146581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_r
eset.100146581
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.856392749
Short name T60
Test name
Test status
Simulation time 16708408 ps
CPU time 0.83 seconds
Started Sep 04 10:49:33 AM UTC 24
Finished Sep 04 10:49:35 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856392749 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.856392749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.1138749664
Short name T1242
Test name
Test status
Simulation time 14518755 ps
CPU time 0.77 seconds
Started Sep 04 10:49:33 AM UTC 24
Finished Sep 04 10:49:35 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138749664 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1138749664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.543904225
Short name T1249
Test name
Test status
Simulation time 18751379 ps
CPU time 0.79 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:38 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543904225 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.543904225
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.1499409506
Short name T1246
Test name
Test status
Simulation time 96377663 ps
CPU time 1.44 seconds
Started Sep 04 10:49:33 AM UTC 24
Finished Sep 04 10:49:36 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499409506 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1499409506
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.1908547463
Short name T1245
Test name
Test status
Simulation time 161731912 ps
CPU time 1.31 seconds
Started Sep 04 10:49:33 AM UTC 24
Finished Sep 04 10:49:36 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908547463 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1908547463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2091205122
Short name T1255
Test name
Test status
Simulation time 155731238 ps
CPU time 1.04 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:39 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2091205122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_
reset.2091205122
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.89898281
Short name T61
Test name
Test status
Simulation time 18196438 ps
CPU time 0.79 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:38 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89898281 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.89898281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.3899261530
Short name T1248
Test name
Test status
Simulation time 21825458 ps
CPU time 0.57 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:38 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899261530 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3899261530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1730074125
Short name T1252
Test name
Test status
Simulation time 20991310 ps
CPU time 0.85 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:38 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730074125 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.1730074125
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.422989345
Short name T1257
Test name
Test status
Simulation time 57477128 ps
CPU time 1.56 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:39 AM UTC 24
Peak memory 203608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422989345 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.422989345
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3132030091
Short name T1256
Test name
Test status
Simulation time 158120814 ps
CPU time 1.32 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:39 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132030091 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3132030091
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2302947239
Short name T1260
Test name
Test status
Simulation time 376169124 ps
CPU time 1.39 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:39 AM UTC 24
Peak memory 201480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2302947239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_
reset.2302947239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.2255224379
Short name T62
Test name
Test status
Simulation time 30566439 ps
CPU time 0.92 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:38 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255224379 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2255224379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1882794590
Short name T1251
Test name
Test status
Simulation time 11099269 ps
CPU time 0.65 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:38 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882794590 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1882794590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.4239161328
Short name T1254
Test name
Test status
Simulation time 17263608 ps
CPU time 0.89 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:39 AM UTC 24
Peak memory 203740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239161328 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.4239161328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1621320896
Short name T1262
Test name
Test status
Simulation time 53148286 ps
CPU time 1.69 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:39 AM UTC 24
Peak memory 201640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621320896 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1621320896
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3349500898
Short name T1259
Test name
Test status
Simulation time 452888248 ps
CPU time 1.4 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:39 AM UTC 24
Peak memory 201700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349500898 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3349500898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2800951598
Short name T1265
Test name
Test status
Simulation time 31438202 ps
CPU time 0.95 seconds
Started Sep 04 10:49:38 AM UTC 24
Finished Sep 04 10:49:40 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2800951598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_
reset.2800951598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.344372888
Short name T63
Test name
Test status
Simulation time 47470351 ps
CPU time 0.73 seconds
Started Sep 04 10:49:38 AM UTC 24
Finished Sep 04 10:49:40 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344372888 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.344372888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.564686304
Short name T1253
Test name
Test status
Simulation time 11025881 ps
CPU time 0.83 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:38 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564686304 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.564686304
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.3482055841
Short name T1263
Test name
Test status
Simulation time 27579252 ps
CPU time 0.82 seconds
Started Sep 04 10:49:38 AM UTC 24
Finished Sep 04 10:49:40 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482055841 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.3482055841
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.3313083358
Short name T1258
Test name
Test status
Simulation time 317196579 ps
CPU time 1.24 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:39 AM UTC 24
Peak memory 201640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313083358 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3313083358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.520889123
Short name T1261
Test name
Test status
Simulation time 1159021027 ps
CPU time 1.47 seconds
Started Sep 04 10:49:36 AM UTC 24
Finished Sep 04 10:49:39 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520889123 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.520889123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2196396151
Short name T1269
Test name
Test status
Simulation time 36013284 ps
CPU time 0.73 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2196396151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_
reset.2196396151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.3473186167
Short name T1270
Test name
Test status
Simulation time 28565607 ps
CPU time 0.87 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473186167 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3473186167
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1366886485
Short name T1264
Test name
Test status
Simulation time 161698910 ps
CPU time 0.71 seconds
Started Sep 04 10:49:38 AM UTC 24
Finished Sep 04 10:49:40 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366886485 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1366886485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1395080348
Short name T1268
Test name
Test status
Simulation time 30167355 ps
CPU time 0.78 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395080348 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.1395080348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2847466378
Short name T1266
Test name
Test status
Simulation time 44204764 ps
CPU time 1.15 seconds
Started Sep 04 10:49:38 AM UTC 24
Finished Sep 04 10:49:40 AM UTC 24
Peak memory 201644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847466378 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2847466378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.1347322416
Short name T1267
Test name
Test status
Simulation time 318668594 ps
CPU time 1.35 seconds
Started Sep 04 10:49:38 AM UTC 24
Finished Sep 04 10:49:41 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347322416 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1347322416
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.330789433
Short name T1285
Test name
Test status
Simulation time 26063043 ps
CPU time 1.53 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 203680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=330789433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_r
eset.330789433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.901885297
Short name T64
Test name
Test status
Simulation time 106044096 ps
CPU time 0.67 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901885297 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.901885297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4038122946
Short name T1271
Test name
Test status
Simulation time 34165777 ps
CPU time 0.67 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038122946 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4038122946
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3496926495
Short name T1273
Test name
Test status
Simulation time 98621119 ps
CPU time 0.77 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496926495 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.3496926495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3619402402
Short name T1287
Test name
Test status
Simulation time 315525944 ps
CPU time 2.07 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 202672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619402402 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3619402402
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.1268675117
Short name T1272
Test name
Test status
Simulation time 169247292 ps
CPU time 0.86 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268675117 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1268675117
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3556219744
Short name T1275
Test name
Test status
Simulation time 20913265 ps
CPU time 0.8 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3556219744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_
reset.3556219744
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3500369274
Short name T1276
Test name
Test status
Simulation time 15880914 ps
CPU time 0.9 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500369274 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3500369274
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3796793094
Short name T1274
Test name
Test status
Simulation time 14396982 ps
CPU time 0.72 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796793094 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3796793094
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.4240026815
Short name T1277
Test name
Test status
Simulation time 22013564 ps
CPU time 0.88 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:44 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240026815 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.4240026815
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.514435011
Short name T1288
Test name
Test status
Simulation time 190415294 ps
CPU time 2.02 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 202692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514435011 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.514435011
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3127482594
Short name T1283
Test name
Test status
Simulation time 155788961 ps
CPU time 1.46 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127482594 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3127482594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.855603687
Short name T1282
Test name
Test status
Simulation time 44866311 ps
CPU time 0.73 seconds
Started Sep 04 10:49:43 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=855603687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_r
eset.855603687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.2097511626
Short name T1279
Test name
Test status
Simulation time 14070597 ps
CPU time 0.67 seconds
Started Sep 04 10:49:43 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 201148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097511626 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2097511626
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1190514485
Short name T1278
Test name
Test status
Simulation time 43182382 ps
CPU time 0.69 seconds
Started Sep 04 10:49:43 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190514485 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1190514485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2021004432
Short name T1284
Test name
Test status
Simulation time 34253049 ps
CPU time 0.93 seconds
Started Sep 04 10:49:43 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021004432 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.2021004432
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1759950354
Short name T1289
Test name
Test status
Simulation time 394517415 ps
CPU time 1.99 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:46 AM UTC 24
Peak memory 203288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759950354 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1759950354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.432021248
Short name T1286
Test name
Test status
Simulation time 95189043 ps
CPU time 1.54 seconds
Started Sep 04 10:49:42 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432021248 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.432021248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3382131766
Short name T1197
Test name
Test status
Simulation time 20619597 ps
CPU time 0.99 seconds
Started Sep 04 10:49:16 AM UTC 24
Finished Sep 04 10:49:18 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382131766 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3382131766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.1367350738
Short name T1200
Test name
Test status
Simulation time 583429695 ps
CPU time 3.21 seconds
Started Sep 04 10:49:16 AM UTC 24
Finished Sep 04 10:49:21 AM UTC 24
Peak memory 202884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367350738 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1367350738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2419907969
Short name T55
Test name
Test status
Simulation time 128081399 ps
CPU time 0.85 seconds
Started Sep 04 10:49:15 AM UTC 24
Finished Sep 04 10:49:17 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419907969 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2419907969
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3459089917
Short name T1199
Test name
Test status
Simulation time 27499066 ps
CPU time 1.84 seconds
Started Sep 04 10:49:18 AM UTC 24
Finished Sep 04 10:49:20 AM UTC 24
Peak memory 203744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3459089917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_r
eset.3459089917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.4017368801
Short name T56
Test name
Test status
Simulation time 63810913 ps
CPU time 0.91 seconds
Started Sep 04 10:49:16 AM UTC 24
Finished Sep 04 10:49:18 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017368801 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4017368801
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2496201939
Short name T1193
Test name
Test status
Simulation time 16408382 ps
CPU time 0.86 seconds
Started Sep 04 10:49:15 AM UTC 24
Finished Sep 04 10:49:17 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496201939 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2496201939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.626805360
Short name T68
Test name
Test status
Simulation time 65705825 ps
CPU time 0.97 seconds
Started Sep 04 10:49:17 AM UTC 24
Finished Sep 04 10:49:19 AM UTC 24
Peak memory 205728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626805360 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.626805360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.1299448453
Short name T1195
Test name
Test status
Simulation time 42829611 ps
CPU time 1.57 seconds
Started Sep 04 10:49:15 AM UTC 24
Finished Sep 04 10:49:18 AM UTC 24
Peak memory 201644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299448453 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1299448453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.905135122
Short name T79
Test name
Test status
Simulation time 214220106 ps
CPU time 1.86 seconds
Started Sep 04 10:49:15 AM UTC 24
Finished Sep 04 10:49:18 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905135122 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.905135122
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2577571271
Short name T1281
Test name
Test status
Simulation time 18601982 ps
CPU time 0.68 seconds
Started Sep 04 10:49:43 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577571271 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2577571271
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.3669681269
Short name T1280
Test name
Test status
Simulation time 15039772 ps
CPU time 0.55 seconds
Started Sep 04 10:49:43 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669681269 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3669681269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.2870946240
Short name T1294
Test name
Test status
Simulation time 13182083 ps
CPU time 0.68 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870946240 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2870946240
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1583929661
Short name T1291
Test name
Test status
Simulation time 45425540 ps
CPU time 0.63 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583929661 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1583929661
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2207753714
Short name T1290
Test name
Test status
Simulation time 13571340 ps
CPU time 0.64 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207753714 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2207753714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.957431314
Short name T1295
Test name
Test status
Simulation time 56252667 ps
CPU time 0.65 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957431314 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.957431314
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3608712461
Short name T1293
Test name
Test status
Simulation time 103297962 ps
CPU time 0.56 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608712461 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3608712461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1902506667
Short name T1292
Test name
Test status
Simulation time 14954690 ps
CPU time 0.53 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902506667 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1902506667
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.4257477571
Short name T1296
Test name
Test status
Simulation time 13464440 ps
CPU time 0.7 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257477571 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4257477571
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.4006604635
Short name T1300
Test name
Test status
Simulation time 11092876 ps
CPU time 0.68 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006604635 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.4006604635
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1379147206
Short name T1203
Test name
Test status
Simulation time 49774437 ps
CPU time 0.89 seconds
Started Sep 04 10:49:19 AM UTC 24
Finished Sep 04 10:49:21 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379147206 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1379147206
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.3037725717
Short name T57
Test name
Test status
Simulation time 111165754 ps
CPU time 3.1 seconds
Started Sep 04 10:49:19 AM UTC 24
Finished Sep 04 10:49:24 AM UTC 24
Peak memory 206328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037725717 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3037725717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.890378044
Short name T1201
Test name
Test status
Simulation time 34886193 ps
CPU time 0.86 seconds
Started Sep 04 10:49:19 AM UTC 24
Finished Sep 04 10:49:21 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890378044 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.890378044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1148517049
Short name T1204
Test name
Test status
Simulation time 81007573 ps
CPU time 1.04 seconds
Started Sep 04 10:49:19 AM UTC 24
Finished Sep 04 10:49:21 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1148517049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r
eset.1148517049
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.3527667992
Short name T69
Test name
Test status
Simulation time 76302357 ps
CPU time 0.93 seconds
Started Sep 04 10:49:19 AM UTC 24
Finished Sep 04 10:49:21 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527667992 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3527667992
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3318457277
Short name T1202
Test name
Test status
Simulation time 13787648 ps
CPU time 0.84 seconds
Started Sep 04 10:49:19 AM UTC 24
Finished Sep 04 10:49:21 AM UTC 24
Peak memory 200896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318457277 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3318457277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1408268820
Short name T70
Test name
Test status
Simulation time 83752165 ps
CPU time 1.07 seconds
Started Sep 04 10:49:19 AM UTC 24
Finished Sep 04 10:49:21 AM UTC 24
Peak memory 201612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408268820 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.1408268820
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.4273898132
Short name T1198
Test name
Test status
Simulation time 36350941 ps
CPU time 1.33 seconds
Started Sep 04 10:49:18 AM UTC 24
Finished Sep 04 10:49:20 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273898132 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4273898132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.3561187175
Short name T84
Test name
Test status
Simulation time 49866069 ps
CPU time 1.33 seconds
Started Sep 04 10:49:18 AM UTC 24
Finished Sep 04 10:49:20 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561187175 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3561187175
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1068298400
Short name T1297
Test name
Test status
Simulation time 29963303 ps
CPU time 0.59 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068298400 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1068298400
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.1281570635
Short name T1298
Test name
Test status
Simulation time 34804309 ps
CPU time 0.63 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281570635 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1281570635
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.499789406
Short name T1299
Test name
Test status
Simulation time 21878568 ps
CPU time 0.65 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499789406 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.499789406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.971308957
Short name T1301
Test name
Test status
Simulation time 14274839 ps
CPU time 0.61 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971308957 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.971308957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3154366609
Short name T1304
Test name
Test status
Simulation time 110251485 ps
CPU time 0.72 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154366609 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3154366609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.2725190699
Short name T1307
Test name
Test status
Simulation time 44498490 ps
CPU time 0.73 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725190699 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2725190699
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2987038870
Short name T1308
Test name
Test status
Simulation time 17574011 ps
CPU time 0.79 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987038870 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2987038870
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2151891569
Short name T1303
Test name
Test status
Simulation time 12590176 ps
CPU time 0.65 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151891569 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2151891569
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3261131184
Short name T1306
Test name
Test status
Simulation time 50494831 ps
CPU time 0.7 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261131184 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3261131184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.328417574
Short name T1302
Test name
Test status
Simulation time 56402685 ps
CPU time 0.59 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328417574 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.328417574
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2770612340
Short name T58
Test name
Test status
Simulation time 23141110 ps
CPU time 0.97 seconds
Started Sep 04 10:49:22 AM UTC 24
Finished Sep 04 10:49:25 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770612340 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2770612340
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.801529686
Short name T1208
Test name
Test status
Simulation time 94260421 ps
CPU time 1.62 seconds
Started Sep 04 10:49:21 AM UTC 24
Finished Sep 04 10:49:24 AM UTC 24
Peak memory 201828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801529686 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.801529686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.1276712300
Short name T1207
Test name
Test status
Simulation time 44599431 ps
CPU time 0.86 seconds
Started Sep 04 10:49:21 AM UTC 24
Finished Sep 04 10:49:23 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276712300 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1276712300
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3705079854
Short name T1211
Test name
Test status
Simulation time 17256009 ps
CPU time 1.07 seconds
Started Sep 04 10:49:22 AM UTC 24
Finished Sep 04 10:49:25 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3705079854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r
eset.3705079854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.1033133934
Short name T71
Test name
Test status
Simulation time 42246474 ps
CPU time 0.85 seconds
Started Sep 04 10:49:21 AM UTC 24
Finished Sep 04 10:49:23 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033133934 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1033133934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.119649646
Short name T1206
Test name
Test status
Simulation time 48220206 ps
CPU time 0.85 seconds
Started Sep 04 10:49:21 AM UTC 24
Finished Sep 04 10:49:23 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119649646 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.119649646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3381055137
Short name T72
Test name
Test status
Simulation time 12943928 ps
CPU time 0.92 seconds
Started Sep 04 10:49:22 AM UTC 24
Finished Sep 04 10:49:25 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381055137 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.3381055137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2084330339
Short name T1205
Test name
Test status
Simulation time 245007183 ps
CPU time 2.14 seconds
Started Sep 04 10:49:19 AM UTC 24
Finished Sep 04 10:49:23 AM UTC 24
Peak memory 202692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084330339 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2084330339
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.2487884416
Short name T107
Test name
Test status
Simulation time 146663845 ps
CPU time 1.33 seconds
Started Sep 04 10:49:19 AM UTC 24
Finished Sep 04 10:49:22 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487884416 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2487884416
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.2106926637
Short name T1305
Test name
Test status
Simulation time 16083020 ps
CPU time 0.69 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106926637 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2106926637
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3545785192
Short name T1310
Test name
Test status
Simulation time 11745917 ps
CPU time 0.64 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545785192 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3545785192
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.728937003
Short name T1312
Test name
Test status
Simulation time 29058191 ps
CPU time 0.64 seconds
Started Sep 04 10:49:48 AM UTC 24
Finished Sep 04 10:49:51 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728937003 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.728937003
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1811616846
Short name T1309
Test name
Test status
Simulation time 27598388 ps
CPU time 0.57 seconds
Started Sep 04 10:49:49 AM UTC 24
Finished Sep 04 10:49:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811616846 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1811616846
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.373757195
Short name T1313
Test name
Test status
Simulation time 25529292 ps
CPU time 0.57 seconds
Started Sep 04 10:49:49 AM UTC 24
Finished Sep 04 10:49:51 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373757195 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.373757195
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1746523477
Short name T1311
Test name
Test status
Simulation time 13375170 ps
CPU time 0.5 seconds
Started Sep 04 10:49:49 AM UTC 24
Finished Sep 04 10:49:51 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746523477 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1746523477
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.743526740
Short name T1314
Test name
Test status
Simulation time 13762547 ps
CPU time 0.61 seconds
Started Sep 04 10:49:50 AM UTC 24
Finished Sep 04 10:49:52 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743526740 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.743526740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.548887673
Short name T1315
Test name
Test status
Simulation time 25697217 ps
CPU time 0.57 seconds
Started Sep 04 10:49:50 AM UTC 24
Finished Sep 04 10:49:52 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548887673 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.548887673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2519022250
Short name T1316
Test name
Test status
Simulation time 13736219 ps
CPU time 0.67 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:57 AM UTC 24
Peak memory 201492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519022250 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2519022250
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3666309580
Short name T1247
Test name
Test status
Simulation time 12702325 ps
CPU time 0.6 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:57 AM UTC 24
Peak memory 201436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666309580 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3666309580
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3754656002
Short name T1212
Test name
Test status
Simulation time 46146337 ps
CPU time 1.09 seconds
Started Sep 04 10:49:23 AM UTC 24
Finished Sep 04 10:49:25 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3754656002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r
eset.3754656002
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.1689890718
Short name T1210
Test name
Test status
Simulation time 30443154 ps
CPU time 0.75 seconds
Started Sep 04 10:49:23 AM UTC 24
Finished Sep 04 10:49:25 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689890718 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1689890718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2188907978
Short name T1209
Test name
Test status
Simulation time 56789658 ps
CPU time 0.85 seconds
Started Sep 04 10:49:23 AM UTC 24
Finished Sep 04 10:49:25 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188907978 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2188907978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.178567113
Short name T73
Test name
Test status
Simulation time 21272081 ps
CPU time 0.76 seconds
Started Sep 04 10:49:23 AM UTC 24
Finished Sep 04 10:49:25 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178567113 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.178567113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.534146595
Short name T1213
Test name
Test status
Simulation time 162509161 ps
CPU time 2 seconds
Started Sep 04 10:49:23 AM UTC 24
Finished Sep 04 10:49:26 AM UTC 24
Peak memory 201324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534146595 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.534146595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.4028011784
Short name T82
Test name
Test status
Simulation time 75994250 ps
CPU time 1.55 seconds
Started Sep 04 10:49:23 AM UTC 24
Finished Sep 04 10:49:25 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028011784 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4028011784
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3204671918
Short name T1221
Test name
Test status
Simulation time 61376230 ps
CPU time 1.31 seconds
Started Sep 04 10:49:26 AM UTC 24
Finished Sep 04 10:49:28 AM UTC 24
Peak memory 203744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3204671918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r
eset.3204671918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.3303004225
Short name T59
Test name
Test status
Simulation time 30418537 ps
CPU time 0.8 seconds
Started Sep 04 10:49:24 AM UTC 24
Finished Sep 04 10:49:27 AM UTC 24
Peak memory 201304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303004225 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3303004225
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.447768964
Short name T1214
Test name
Test status
Simulation time 10695395 ps
CPU time 0.68 seconds
Started Sep 04 10:49:24 AM UTC 24
Finished Sep 04 10:49:26 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447768964 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.447768964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.2935164805
Short name T1215
Test name
Test status
Simulation time 39170184 ps
CPU time 0.97 seconds
Started Sep 04 10:49:24 AM UTC 24
Finished Sep 04 10:49:27 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935164805 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.2935164805
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2211634433
Short name T1218
Test name
Test status
Simulation time 155318768 ps
CPU time 2.18 seconds
Started Sep 04 10:49:24 AM UTC 24
Finished Sep 04 10:49:28 AM UTC 24
Peak memory 204728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211634433 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2211634433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3087660188
Short name T83
Test name
Test status
Simulation time 162614569 ps
CPU time 1.9 seconds
Started Sep 04 10:49:24 AM UTC 24
Finished Sep 04 10:49:28 AM UTC 24
Peak memory 201332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087660188 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3087660188
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3372377845
Short name T1220
Test name
Test status
Simulation time 115100659 ps
CPU time 1.1 seconds
Started Sep 04 10:49:26 AM UTC 24
Finished Sep 04 10:49:28 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3372377845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r
eset.3372377845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.98066288
Short name T1217
Test name
Test status
Simulation time 13424359 ps
CPU time 0.87 seconds
Started Sep 04 10:49:26 AM UTC 24
Finished Sep 04 10:49:28 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98066288 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.98066288
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.2363162972
Short name T1216
Test name
Test status
Simulation time 12221992 ps
CPU time 0.87 seconds
Started Sep 04 10:49:26 AM UTC 24
Finished Sep 04 10:49:28 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363162972 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2363162972
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2329804887
Short name T1219
Test name
Test status
Simulation time 47427846 ps
CPU time 0.89 seconds
Started Sep 04 10:49:26 AM UTC 24
Finished Sep 04 10:49:28 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329804887 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.2329804887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.3159230183
Short name T1223
Test name
Test status
Simulation time 237294648 ps
CPU time 1.76 seconds
Started Sep 04 10:49:26 AM UTC 24
Finished Sep 04 10:49:29 AM UTC 24
Peak memory 201644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159230183 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3159230183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.1482326490
Short name T1222
Test name
Test status
Simulation time 73132343 ps
CPU time 1.68 seconds
Started Sep 04 10:49:26 AM UTC 24
Finished Sep 04 10:49:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482326490 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1482326490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3359196260
Short name T1228
Test name
Test status
Simulation time 25703939 ps
CPU time 0.94 seconds
Started Sep 04 10:49:28 AM UTC 24
Finished Sep 04 10:49:30 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3359196260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r
eset.3359196260
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.3959368548
Short name T1226
Test name
Test status
Simulation time 26612180 ps
CPU time 0.86 seconds
Started Sep 04 10:49:28 AM UTC 24
Finished Sep 04 10:49:30 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959368548 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3959368548
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.942358791
Short name T1224
Test name
Test status
Simulation time 23499123 ps
CPU time 0.81 seconds
Started Sep 04 10:49:28 AM UTC 24
Finished Sep 04 10:49:30 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942358791 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.942358791
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3715238636
Short name T1227
Test name
Test status
Simulation time 77772676 ps
CPU time 0.91 seconds
Started Sep 04 10:49:28 AM UTC 24
Finished Sep 04 10:49:30 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715238636 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.3715238636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1027640543
Short name T1225
Test name
Test status
Simulation time 140771824 ps
CPU time 2.44 seconds
Started Sep 04 10:49:26 AM UTC 24
Finished Sep 04 10:49:30 AM UTC 24
Peak memory 204740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027640543 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1027640543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.2028652106
Short name T80
Test name
Test status
Simulation time 503685926 ps
CPU time 1.84 seconds
Started Sep 04 10:49:27 AM UTC 24
Finished Sep 04 10:49:31 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028652106 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2028652106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2437748503
Short name T1230
Test name
Test status
Simulation time 17356305 ps
CPU time 0.97 seconds
Started Sep 04 10:49:29 AM UTC 24
Finished Sep 04 10:49:32 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2437748503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r
eset.2437748503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3126252599
Short name T1229
Test name
Test status
Simulation time 45009825 ps
CPU time 0.65 seconds
Started Sep 04 10:49:29 AM UTC 24
Finished Sep 04 10:49:31 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126252599 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3126252599
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.3480368110
Short name T1231
Test name
Test status
Simulation time 11479740 ps
CPU time 0.86 seconds
Started Sep 04 10:49:29 AM UTC 24
Finished Sep 04 10:49:32 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480368110 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3480368110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.3604447178
Short name T1232
Test name
Test status
Simulation time 57636043 ps
CPU time 1.09 seconds
Started Sep 04 10:49:29 AM UTC 24
Finished Sep 04 10:49:32 AM UTC 24
Peak memory 205724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604447178 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.3604447178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2152905026
Short name T1233
Test name
Test status
Simulation time 195945793 ps
CPU time 3.31 seconds
Started Sep 04 10:49:28 AM UTC 24
Finished Sep 04 10:49:32 AM UTC 24
Peak memory 204740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152905026 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2152905026
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3166558817
Short name T108
Test name
Test status
Simulation time 90037354 ps
CPU time 1.89 seconds
Started Sep 04 10:49:29 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166558817 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3166558817
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.575267501
Short name T27
Test name
Test status
Simulation time 58037728877 ps
CPU time 53.15 seconds
Started Sep 04 10:05:59 AM UTC 24
Finished Sep 04 10:06:54 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575267501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.575267501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_intr.3216057529
Short name T4
Test name
Test status
Simulation time 6688032562 ps
CPU time 3.94 seconds
Started Sep 04 10:06:00 AM UTC 24
Finished Sep 04 10:06:05 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216057529 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3216057529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.2508076488
Short name T553
Test name
Test status
Simulation time 107588151929 ps
CPU time 1194.27 seconds
Started Sep 04 10:06:03 AM UTC 24
Finished Sep 04 10:26:10 AM UTC 24
Peak memory 212220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508076488 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2508076488
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_loopback.3741032092
Short name T8
Test name
Test status
Simulation time 2987563153 ps
CPU time 4.61 seconds
Started Sep 04 10:06:02 AM UTC 24
Finished Sep 04 10:06:08 AM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741032092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3741032092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_noise_filter.1025612684
Short name T303
Test name
Test status
Simulation time 104775911706 ps
CPU time 244.52 seconds
Started Sep 04 10:06:01 AM UTC 24
Finished Sep 04 10:10:09 AM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025612684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1025612684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_perf.3765932093
Short name T272
Test name
Test status
Simulation time 15551551438 ps
CPU time 196.36 seconds
Started Sep 04 10:06:03 AM UTC 24
Finished Sep 04 10:09:22 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765932093 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3765932093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_rx_oversample.899068787
Short name T75
Test name
Test status
Simulation time 3755096896 ps
CPU time 25.06 seconds
Started Sep 04 10:06:00 AM UTC 24
Finished Sep 04 10:06:27 AM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899068787 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.899068787
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.2581001882
Short name T13
Test name
Test status
Simulation time 40258030360 ps
CPU time 7.05 seconds
Started Sep 04 10:06:01 AM UTC 24
Finished Sep 04 10:06:10 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581001882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2581001882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_sec_cm.2747947648
Short name T6
Test name
Test status
Simulation time 128178690 ps
CPU time 1.18 seconds
Started Sep 04 10:06:04 AM UTC 24
Finished Sep 04 10:06:06 AM UTC 24
Peak memory 240196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747947648 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2747947648
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_smoke.936237280
Short name T1
Test name
Test status
Simulation time 908103021 ps
CPU time 2.39 seconds
Started Sep 04 10:05:59 AM UTC 24
Finished Sep 04 10:06:03 AM UTC 24
Peak memory 208468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936237280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.uart_smoke.936237280
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.3165128995
Short name T2
Test name
Test status
Simulation time 1238643647 ps
CPU time 2.14 seconds
Started Sep 04 10:06:01 AM UTC 24
Finished Sep 04 10:06:05 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165128995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3165128995
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/0.uart_tx_rx.3309458235
Short name T48
Test name
Test status
Simulation time 110697489660 ps
CPU time 46.46 seconds
Started Sep 04 10:05:59 AM UTC 24
Finished Sep 04 10:06:47 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309458235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3309458235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/0.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_alert_test.4041397881
Short name T30
Test name
Test status
Simulation time 16982194 ps
CPU time 0.62 seconds
Started Sep 04 10:06:09 AM UTC 24
Finished Sep 04 10:06:10 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041397881 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4041397881
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_fifo_full.3621847512
Short name T96
Test name
Test status
Simulation time 211503290325 ps
CPU time 96.25 seconds
Started Sep 04 10:06:04 AM UTC 24
Finished Sep 04 10:07:42 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621847512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3621847512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.923021997
Short name T15
Test name
Test status
Simulation time 8571235507 ps
CPU time 6.98 seconds
Started Sep 04 10:06:05 AM UTC 24
Finished Sep 04 10:06:13 AM UTC 24
Peak memory 208012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923021997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.923021997
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.3375049604
Short name T465
Test name
Test status
Simulation time 108299226913 ps
CPU time 764.38 seconds
Started Sep 04 10:06:06 AM UTC 24
Finished Sep 04 10:18:59 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375049604 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3375049604
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_loopback.2849491455
Short name T9
Test name
Test status
Simulation time 357576613 ps
CPU time 1.29 seconds
Started Sep 04 10:06:06 AM UTC 24
Finished Sep 04 10:06:08 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849491455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2849491455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_perf.382004900
Short name T563
Test name
Test status
Simulation time 21319196809 ps
CPU time 1220.29 seconds
Started Sep 04 10:06:06 AM UTC 24
Finished Sep 04 10:26:41 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382004900 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.382004900
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_rx_oversample.4152613138
Short name T42
Test name
Test status
Simulation time 6019166192 ps
CPU time 61.04 seconds
Started Sep 04 10:06:05 AM UTC 24
Finished Sep 04 10:07:08 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152613138 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.4152613138
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2957377764
Short name T315
Test name
Test status
Simulation time 42153873694 ps
CPU time 146.73 seconds
Started Sep 04 10:06:06 AM UTC 24
Finished Sep 04 10:08:36 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957377764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2957377764
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.4254849091
Short name T29
Test name
Test status
Simulation time 3547992425 ps
CPU time 6.84 seconds
Started Sep 04 10:06:06 AM UTC 24
Finished Sep 04 10:06:14 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254849091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4254849091
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_smoke.4126139155
Short name T7
Test name
Test status
Simulation time 716056677 ps
CPU time 2.75 seconds
Started Sep 04 10:06:04 AM UTC 24
Finished Sep 04 10:06:08 AM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126139155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4126139155
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.1297788802
Short name T10
Test name
Test status
Simulation time 2533414494 ps
CPU time 2.2 seconds
Started Sep 04 10:06:06 AM UTC 24
Finished Sep 04 10:06:09 AM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297788802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1297788802
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/1.uart_tx_rx.790009088
Short name T44
Test name
Test status
Simulation time 65852881825 ps
CPU time 75.65 seconds
Started Sep 04 10:06:04 AM UTC 24
Finished Sep 04 10:07:22 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790009088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.790009088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_alert_test.2657475895
Short name T424
Test name
Test status
Simulation time 10714874 ps
CPU time 0.83 seconds
Started Sep 04 10:12:33 AM UTC 24
Finished Sep 04 10:12:35 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657475895 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2657475895
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.1882566108
Short name T277
Test name
Test status
Simulation time 13202475954 ps
CPU time 22.52 seconds
Started Sep 04 10:11:54 AM UTC 24
Finished Sep 04 10:12:18 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882566108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1882566108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_fifo_reset.370055795
Short name T135
Test name
Test status
Simulation time 39382697139 ps
CPU time 91.68 seconds
Started Sep 04 10:11:56 AM UTC 24
Finished Sep 04 10:13:30 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370055795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.370055795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_intr.4093058218
Short name T363
Test name
Test status
Simulation time 2887129298 ps
CPU time 13.29 seconds
Started Sep 04 10:12:07 AM UTC 24
Finished Sep 04 10:12:22 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093058218 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.4093058218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.2620036237
Short name T457
Test name
Test status
Simulation time 308276360193 ps
CPU time 317.18 seconds
Started Sep 04 10:12:30 AM UTC 24
Finished Sep 04 10:17:51 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620036237 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2620036237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_loopback.694292073
Short name T423
Test name
Test status
Simulation time 4334620652 ps
CPU time 4.32 seconds
Started Sep 04 10:12:27 AM UTC 24
Finished Sep 04 10:12:32 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694292073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.uart_loopback.694292073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_noise_filter.3404922359
Short name T268
Test name
Test status
Simulation time 35871254084 ps
CPU time 114.96 seconds
Started Sep 04 10:12:16 AM UTC 24
Finished Sep 04 10:14:14 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404922359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3404922359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_perf.2218445415
Short name T344
Test name
Test status
Simulation time 28660237945 ps
CPU time 381.16 seconds
Started Sep 04 10:12:28 AM UTC 24
Finished Sep 04 10:18:53 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218445415 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2218445415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_rx_oversample.355095419
Short name T422
Test name
Test status
Simulation time 1375066056 ps
CPU time 6.21 seconds
Started Sep 04 10:11:58 AM UTC 24
Finished Sep 04 10:12:06 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355095419 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.355095419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.3692347115
Short name T283
Test name
Test status
Simulation time 23393120049 ps
CPU time 73.96 seconds
Started Sep 04 10:12:22 AM UTC 24
Finished Sep 04 10:13:38 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692347115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3692347115
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.3218079619
Short name T333
Test name
Test status
Simulation time 59322299138 ps
CPU time 18.11 seconds
Started Sep 04 10:12:18 AM UTC 24
Finished Sep 04 10:12:38 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218079619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3218079619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_smoke.951530684
Short name T347
Test name
Test status
Simulation time 754645331 ps
CPU time 1.8 seconds
Started Sep 04 10:11:49 AM UTC 24
Finished Sep 04 10:11:51 AM UTC 24
Peak memory 206448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951530684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.uart_smoke.951530684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_stress_all.1551934176
Short name T353
Test name
Test status
Simulation time 51823004813 ps
CPU time 620.42 seconds
Started Sep 04 10:12:33 AM UTC 24
Finished Sep 04 10:23:01 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551934176 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1551934176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.206246292
Short name T366
Test name
Test status
Simulation time 9282985048 ps
CPU time 8.01 seconds
Started Sep 04 10:12:22 AM UTC 24
Finished Sep 04 10:12:32 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206246292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.206246292
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/10.uart_tx_rx.3491265440
Short name T275
Test name
Test status
Simulation time 63910722613 ps
CPU time 177.36 seconds
Started Sep 04 10:11:52 AM UTC 24
Finished Sep 04 10:14:52 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491265440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3491265440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/10.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/100.uart_fifo_reset.113859055
Short name T993
Test name
Test status
Simulation time 182884153361 ps
CPU time 47.72 seconds
Started Sep 04 10:43:54 AM UTC 24
Finished Sep 04 10:44:43 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113859055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.113859055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/100.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/101.uart_fifo_reset.1736386878
Short name T201
Test name
Test status
Simulation time 88821286821 ps
CPU time 29.07 seconds
Started Sep 04 10:43:58 AM UTC 24
Finished Sep 04 10:44:29 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736386878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1736386878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/101.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/102.uart_fifo_reset.1939380615
Short name T1164
Test name
Test status
Simulation time 92958261308 ps
CPU time 416.69 seconds
Started Sep 04 10:43:59 AM UTC 24
Finished Sep 04 10:51:02 AM UTC 24
Peak memory 210116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939380615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1939380615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/102.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/103.uart_fifo_reset.609941569
Short name T991
Test name
Test status
Simulation time 81572783780 ps
CPU time 36.85 seconds
Started Sep 04 10:44:00 AM UTC 24
Finished Sep 04 10:44:38 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609941569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.609941569
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/103.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/104.uart_fifo_reset.3528508002
Short name T237
Test name
Test status
Simulation time 34867626156 ps
CPU time 46.87 seconds
Started Sep 04 10:44:00 AM UTC 24
Finished Sep 04 10:44:48 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528508002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3528508002
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/104.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/106.uart_fifo_reset.1815708800
Short name T1041
Test name
Test status
Simulation time 140162257580 ps
CPU time 149.68 seconds
Started Sep 04 10:44:05 AM UTC 24
Finished Sep 04 10:46:37 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815708800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1815708800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/106.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/107.uart_fifo_reset.1690350826
Short name T1044
Test name
Test status
Simulation time 124344210674 ps
CPU time 153.86 seconds
Started Sep 04 10:44:05 AM UTC 24
Finished Sep 04 10:46:41 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690350826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1690350826
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/107.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/108.uart_fifo_reset.3134866151
Short name T1100
Test name
Test status
Simulation time 129300318417 ps
CPU time 243.43 seconds
Started Sep 04 10:44:05 AM UTC 24
Finished Sep 04 10:48:12 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134866151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3134866151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/108.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/109.uart_fifo_reset.3458184274
Short name T203
Test name
Test status
Simulation time 117812329370 ps
CPU time 57.17 seconds
Started Sep 04 10:44:07 AM UTC 24
Finished Sep 04 10:45:06 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458184274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3458184274
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/109.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_alert_test.79284379
Short name T428
Test name
Test status
Simulation time 46016410 ps
CPU time 0.84 seconds
Started Sep 04 10:13:32 AM UTC 24
Finished Sep 04 10:13:34 AM UTC 24
Peak memory 204368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79284379 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.79284379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_fifo_full.1987126726
Short name T380
Test name
Test status
Simulation time 85930166500 ps
CPU time 33.31 seconds
Started Sep 04 10:12:38 AM UTC 24
Finished Sep 04 10:13:13 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987126726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1987126726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_fifo_reset.2541739522
Short name T179
Test name
Test status
Simulation time 28763540684 ps
CPU time 65.8 seconds
Started Sep 04 10:12:39 AM UTC 24
Finished Sep 04 10:13:47 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541739522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2541739522
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_intr.54882695
Short name T101
Test name
Test status
Simulation time 12987826540 ps
CPU time 10.37 seconds
Started Sep 04 10:12:45 AM UTC 24
Finished Sep 04 10:12:57 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54882695 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.54882695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_loopback.3197204213
Short name T427
Test name
Test status
Simulation time 8394815674 ps
CPU time 15.85 seconds
Started Sep 04 10:13:03 AM UTC 24
Finished Sep 04 10:13:20 AM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197204213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3197204213
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_noise_filter.3752479438
Short name T336
Test name
Test status
Simulation time 49861312583 ps
CPU time 113.23 seconds
Started Sep 04 10:12:48 AM UTC 24
Finished Sep 04 10:14:43 AM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752479438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3752479438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_perf.2874721083
Short name T502
Test name
Test status
Simulation time 13526816013 ps
CPU time 621.88 seconds
Started Sep 04 10:13:14 AM UTC 24
Finished Sep 04 10:23:43 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874721083 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2874721083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_rx_oversample.1051180380
Short name T429
Test name
Test status
Simulation time 6369468297 ps
CPU time 58.03 seconds
Started Sep 04 10:12:44 AM UTC 24
Finished Sep 04 10:13:44 AM UTC 24
Peak memory 208076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051180380 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1051180380
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.3361373470
Short name T287
Test name
Test status
Simulation time 60611850450 ps
CPU time 62.04 seconds
Started Sep 04 10:12:56 AM UTC 24
Finished Sep 04 10:13:59 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361373470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3361373470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.570588392
Short name T426
Test name
Test status
Simulation time 3072081128 ps
CPU time 4.12 seconds
Started Sep 04 10:12:50 AM UTC 24
Finished Sep 04 10:12:55 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570588392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.570588392
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_smoke.3273186472
Short name T361
Test name
Test status
Simulation time 115686045 ps
CPU time 1.32 seconds
Started Sep 04 10:12:35 AM UTC 24
Finished Sep 04 10:12:37 AM UTC 24
Peak memory 206244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273186472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3273186472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_stress_all.3654869807
Short name T585
Test name
Test status
Simulation time 146827340026 ps
CPU time 855.99 seconds
Started Sep 04 10:13:30 AM UTC 24
Finished Sep 04 10:27:56 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654869807 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3654869807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1715793843
Short name T87
Test name
Test status
Simulation time 18183316494 ps
CPU time 64.6 seconds
Started Sep 04 10:13:21 AM UTC 24
Finished Sep 04 10:14:28 AM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1715793843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all
_with_rand_reset.1715793843
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.1589451325
Short name T302
Test name
Test status
Simulation time 4857165751 ps
CPU time 3.3 seconds
Started Sep 04 10:12:58 AM UTC 24
Finished Sep 04 10:13:02 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589451325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1589451325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/11.uart_tx_rx.2373563181
Short name T284
Test name
Test status
Simulation time 67792181974 ps
CPU time 92.64 seconds
Started Sep 04 10:12:36 AM UTC 24
Finished Sep 04 10:14:11 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373563181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2373563181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/11.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/111.uart_fifo_reset.1191906397
Short name T1010
Test name
Test status
Simulation time 58589711886 ps
CPU time 76.76 seconds
Started Sep 04 10:44:09 AM UTC 24
Finished Sep 04 10:45:27 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191906397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1191906397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/111.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/112.uart_fifo_reset.3143319485
Short name T999
Test name
Test status
Simulation time 28499220284 ps
CPU time 36.19 seconds
Started Sep 04 10:44:15 AM UTC 24
Finished Sep 04 10:44:53 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143319485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3143319485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/112.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/114.uart_fifo_reset.1888451324
Short name T1074
Test name
Test status
Simulation time 132263910187 ps
CPU time 178.32 seconds
Started Sep 04 10:44:17 AM UTC 24
Finished Sep 04 10:47:18 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888451324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1888451324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/114.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/115.uart_fifo_reset.1338954920
Short name T998
Test name
Test status
Simulation time 44035749872 ps
CPU time 31.73 seconds
Started Sep 04 10:44:18 AM UTC 24
Finished Sep 04 10:44:51 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338954920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1338954920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/115.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2769773259
Short name T992
Test name
Test status
Simulation time 58267669371 ps
CPU time 15.19 seconds
Started Sep 04 10:44:24 AM UTC 24
Finished Sep 04 10:44:41 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769773259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2769773259
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/116.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/117.uart_fifo_reset.2590547410
Short name T1001
Test name
Test status
Simulation time 81715474934 ps
CPU time 25.45 seconds
Started Sep 04 10:44:27 AM UTC 24
Finished Sep 04 10:44:53 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590547410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2590547410
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/117.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3110312039
Short name T1002
Test name
Test status
Simulation time 35294218492 ps
CPU time 33.09 seconds
Started Sep 04 10:44:28 AM UTC 24
Finished Sep 04 10:45:02 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110312039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3110312039
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/118.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/119.uart_fifo_reset.2310890288
Short name T1019
Test name
Test status
Simulation time 160747022919 ps
CPU time 73.86 seconds
Started Sep 04 10:44:28 AM UTC 24
Finished Sep 04 10:45:43 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310890288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2310890288
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/119.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_alert_test.933958054
Short name T431
Test name
Test status
Simulation time 24015500 ps
CPU time 0.83 seconds
Started Sep 04 10:14:21 AM UTC 24
Finished Sep 04 10:14:23 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933958054 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.933958054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_fifo_full.2981224738
Short name T129
Test name
Test status
Simulation time 63990658152 ps
CPU time 60.84 seconds
Started Sep 04 10:13:40 AM UTC 24
Finished Sep 04 10:14:42 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981224738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2981224738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_fifo_reset.2805111756
Short name T280
Test name
Test status
Simulation time 93648842183 ps
CPU time 247.07 seconds
Started Sep 04 10:13:46 AM UTC 24
Finished Sep 04 10:17:57 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805111756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2805111756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_intr.282748419
Short name T103
Test name
Test status
Simulation time 53759072153 ps
CPU time 12.38 seconds
Started Sep 04 10:13:58 AM UTC 24
Finished Sep 04 10:14:11 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282748419 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.282748419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.2140101623
Short name T483
Test name
Test status
Simulation time 77794483734 ps
CPU time 450.94 seconds
Started Sep 04 10:14:14 AM UTC 24
Finished Sep 04 10:21:50 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140101623 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2140101623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_loopback.3819349825
Short name T430
Test name
Test status
Simulation time 4073545800 ps
CPU time 4.35 seconds
Started Sep 04 10:14:11 AM UTC 24
Finished Sep 04 10:14:17 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819349825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3819349825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_noise_filter.2976177436
Short name T291
Test name
Test status
Simulation time 109243015949 ps
CPU time 106.89 seconds
Started Sep 04 10:13:59 AM UTC 24
Finished Sep 04 10:15:48 AM UTC 24
Peak memory 217604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976177436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2976177436
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_perf.2691867461
Short name T493
Test name
Test status
Simulation time 19680303047 ps
CPU time 539.19 seconds
Started Sep 04 10:14:12 AM UTC 24
Finished Sep 04 10:23:18 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691867461 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2691867461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_rx_oversample.150228245
Short name T434
Test name
Test status
Simulation time 6141574410 ps
CPU time 41.99 seconds
Started Sep 04 10:13:48 AM UTC 24
Finished Sep 04 10:14:31 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150228245 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.150228245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.3817437137
Short name T376
Test name
Test status
Simulation time 5076798175 ps
CPU time 4.17 seconds
Started Sep 04 10:14:00 AM UTC 24
Finished Sep 04 10:14:05 AM UTC 24
Peak memory 205024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817437137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3817437137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_smoke.723995576
Short name T328
Test name
Test status
Simulation time 1037654016 ps
CPU time 2.43 seconds
Started Sep 04 10:13:35 AM UTC 24
Finished Sep 04 10:13:39 AM UTC 24
Peak memory 208380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723995576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.uart_smoke.723995576
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.2528834197
Short name T364
Test name
Test status
Simulation time 1190315229 ps
CPU time 5.08 seconds
Started Sep 04 10:14:06 AM UTC 24
Finished Sep 04 10:14:12 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528834197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2528834197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/12.uart_tx_rx.2453197226
Short name T308
Test name
Test status
Simulation time 71652459356 ps
CPU time 128.85 seconds
Started Sep 04 10:13:39 AM UTC 24
Finished Sep 04 10:15:51 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453197226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2453197226
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/12.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/121.uart_fifo_reset.2818663482
Short name T202
Test name
Test status
Simulation time 16200192659 ps
CPU time 26.46 seconds
Started Sep 04 10:44:30 AM UTC 24
Finished Sep 04 10:44:57 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818663482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2818663482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/121.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/122.uart_fifo_reset.2000387897
Short name T997
Test name
Test status
Simulation time 14272996438 ps
CPU time 16.7 seconds
Started Sep 04 10:44:33 AM UTC 24
Finished Sep 04 10:44:51 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000387897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2000387897
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/122.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/123.uart_fifo_reset.3888340572
Short name T1008
Test name
Test status
Simulation time 13378369039 ps
CPU time 40.94 seconds
Started Sep 04 10:44:33 AM UTC 24
Finished Sep 04 10:45:15 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888340572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3888340572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/123.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/124.uart_fifo_reset.4014684562
Short name T1022
Test name
Test status
Simulation time 49132483213 ps
CPU time 71.01 seconds
Started Sep 04 10:44:36 AM UTC 24
Finished Sep 04 10:45:49 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014684562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.4014684562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/124.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3011298273
Short name T1006
Test name
Test status
Simulation time 21700378029 ps
CPU time 32.84 seconds
Started Sep 04 10:44:37 AM UTC 24
Finished Sep 04 10:45:11 AM UTC 24
Peak memory 208592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011298273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3011298273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/125.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/126.uart_fifo_reset.2938520094
Short name T994
Test name
Test status
Simulation time 31752486142 ps
CPU time 7.59 seconds
Started Sep 04 10:44:37 AM UTC 24
Finished Sep 04 10:44:46 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938520094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2938520094
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/126.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/127.uart_fifo_reset.2766977229
Short name T1004
Test name
Test status
Simulation time 66139405459 ps
CPU time 29.22 seconds
Started Sep 04 10:44:38 AM UTC 24
Finished Sep 04 10:45:09 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766977229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2766977229
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/127.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/128.uart_fifo_reset.1392568081
Short name T1012
Test name
Test status
Simulation time 46208617455 ps
CPU time 48.94 seconds
Started Sep 04 10:44:38 AM UTC 24
Finished Sep 04 10:45:29 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392568081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1392568081
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/128.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/129.uart_fifo_reset.1304814169
Short name T1011
Test name
Test status
Simulation time 135228594204 ps
CPU time 45.74 seconds
Started Sep 04 10:44:41 AM UTC 24
Finished Sep 04 10:45:28 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304814169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1304814169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/129.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_alert_test.4089430075
Short name T436
Test name
Test status
Simulation time 16147100 ps
CPU time 0.79 seconds
Started Sep 04 10:15:17 AM UTC 24
Finished Sep 04 10:15:19 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089430075 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.4089430075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_fifo_full.398861911
Short name T342
Test name
Test status
Simulation time 46303069022 ps
CPU time 46.16 seconds
Started Sep 04 10:14:28 AM UTC 24
Finished Sep 04 10:15:16 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398861911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.398861911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.1221038612
Short name T162
Test name
Test status
Simulation time 129051225673 ps
CPU time 147.76 seconds
Started Sep 04 10:14:28 AM UTC 24
Finished Sep 04 10:16:58 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221038612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1221038612
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_fifo_reset.2559925586
Short name T180
Test name
Test status
Simulation time 163974558110 ps
CPU time 131.62 seconds
Started Sep 04 10:14:29 AM UTC 24
Finished Sep 04 10:16:43 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559925586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2559925586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_intr.2768283525
Short name T323
Test name
Test status
Simulation time 65706253502 ps
CPU time 39.28 seconds
Started Sep 04 10:14:36 AM UTC 24
Finished Sep 04 10:15:17 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768283525 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2768283525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.4062347598
Short name T484
Test name
Test status
Simulation time 236147796544 ps
CPU time 409.14 seconds
Started Sep 04 10:14:59 AM UTC 24
Finished Sep 04 10:21:53 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062347598 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4062347598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_loopback.1659944499
Short name T440
Test name
Test status
Simulation time 9654384531 ps
CPU time 34.41 seconds
Started Sep 04 10:14:56 AM UTC 24
Finished Sep 04 10:15:32 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659944499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1659944499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_noise_filter.3292332321
Short name T321
Test name
Test status
Simulation time 227275393927 ps
CPU time 62.38 seconds
Started Sep 04 10:14:43 AM UTC 24
Finished Sep 04 10:15:47 AM UTC 24
Peak memory 208868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292332321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3292332321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_perf.3015187459
Short name T866
Test name
Test status
Simulation time 20454274986 ps
CPU time 1444.26 seconds
Started Sep 04 10:14:57 AM UTC 24
Finished Sep 04 10:39:17 AM UTC 24
Peak memory 212228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015187459 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3015187459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_rx_oversample.3711788152
Short name T438
Test name
Test status
Simulation time 6214625927 ps
CPU time 55.95 seconds
Started Sep 04 10:14:32 AM UTC 24
Finished Sep 04 10:15:30 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711788152 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3711788152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.2711830862
Short name T132
Test name
Test status
Simulation time 31741494184 ps
CPU time 29.33 seconds
Started Sep 04 10:14:46 AM UTC 24
Finished Sep 04 10:15:16 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711830862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2711830862
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.458714266
Short name T378
Test name
Test status
Simulation time 3977263053 ps
CPU time 11.66 seconds
Started Sep 04 10:14:43 AM UTC 24
Finished Sep 04 10:14:56 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458714266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.458714266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_smoke.90677618
Short name T433
Test name
Test status
Simulation time 767386294 ps
CPU time 2.6 seconds
Started Sep 04 10:14:24 AM UTC 24
Finished Sep 04 10:14:28 AM UTC 24
Peak memory 207108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90677618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_smoke.90677618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_stress_all.1935645405
Short name T309
Test name
Test status
Simulation time 200572100945 ps
CPU time 204.98 seconds
Started Sep 04 10:15:17 AM UTC 24
Finished Sep 04 10:18:45 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935645405 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1935645405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.3309205919
Short name T349
Test name
Test status
Simulation time 4943592849 ps
CPU time 108.69 seconds
Started Sep 04 10:15:09 AM UTC 24
Finished Sep 04 10:17:00 AM UTC 24
Peak memory 221772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3309205919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all
_with_rand_reset.3309205919
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.3150080983
Short name T435
Test name
Test status
Simulation time 1413079355 ps
CPU time 4.55 seconds
Started Sep 04 10:14:53 AM UTC 24
Finished Sep 04 10:14:58 AM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150080983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3150080983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/13.uart_tx_rx.987346453
Short name T432
Test name
Test status
Simulation time 2205617508 ps
CPU time 2.26 seconds
Started Sep 04 10:14:24 AM UTC 24
Finished Sep 04 10:14:27 AM UTC 24
Peak memory 207084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987346453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.987346453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/13.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/131.uart_fifo_reset.2270779640
Short name T1029
Test name
Test status
Simulation time 34293982567 ps
CPU time 68.62 seconds
Started Sep 04 10:44:47 AM UTC 24
Finished Sep 04 10:45:57 AM UTC 24
Peak memory 208604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270779640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2270779640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/131.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/132.uart_fifo_reset.2380167253
Short name T255
Test name
Test status
Simulation time 40376392088 ps
CPU time 81.09 seconds
Started Sep 04 10:44:48 AM UTC 24
Finished Sep 04 10:46:11 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380167253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2380167253
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/132.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/134.uart_fifo_reset.1402679853
Short name T1017
Test name
Test status
Simulation time 29798971076 ps
CPU time 44.79 seconds
Started Sep 04 10:44:52 AM UTC 24
Finished Sep 04 10:45:38 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402679853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1402679853
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/134.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/135.uart_fifo_reset.3911691993
Short name T1119
Test name
Test status
Simulation time 127709507198 ps
CPU time 222.52 seconds
Started Sep 04 10:44:52 AM UTC 24
Finished Sep 04 10:48:37 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911691993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3911691993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/135.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/136.uart_fifo_reset.4193658619
Short name T1026
Test name
Test status
Simulation time 346621725213 ps
CPU time 62.23 seconds
Started Sep 04 10:44:52 AM UTC 24
Finished Sep 04 10:45:56 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193658619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4193658619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/136.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/137.uart_fifo_reset.107829033
Short name T1014
Test name
Test status
Simulation time 70769553676 ps
CPU time 36.84 seconds
Started Sep 04 10:44:54 AM UTC 24
Finished Sep 04 10:45:32 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107829033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.107829033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/137.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/139.uart_fifo_reset.2929748904
Short name T212
Test name
Test status
Simulation time 26651848988 ps
CPU time 32.1 seconds
Started Sep 04 10:44:54 AM UTC 24
Finished Sep 04 10:45:28 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929748904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2929748904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/139.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_alert_test.685793616
Short name T441
Test name
Test status
Simulation time 103965151 ps
CPU time 0.82 seconds
Started Sep 04 10:15:57 AM UTC 24
Finished Sep 04 10:15:58 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685793616 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.685793616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_fifo_full.1305484295
Short name T357
Test name
Test status
Simulation time 147400455432 ps
CPU time 265.8 seconds
Started Sep 04 10:15:20 AM UTC 24
Finished Sep 04 10:19:51 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305484295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1305484295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.2298634267
Short name T338
Test name
Test status
Simulation time 57434287173 ps
CPU time 65.55 seconds
Started Sep 04 10:15:20 AM UTC 24
Finished Sep 04 10:16:29 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298634267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2298634267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_fifo_reset.2687035925
Short name T214
Test name
Test status
Simulation time 29874593331 ps
CPU time 57.15 seconds
Started Sep 04 10:15:21 AM UTC 24
Finished Sep 04 10:16:20 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687035925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2687035925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_intr.1788081803
Short name T288
Test name
Test status
Simulation time 57024491512 ps
CPU time 37.1 seconds
Started Sep 04 10:15:31 AM UTC 24
Finished Sep 04 10:16:09 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788081803 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1788081803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.204630263
Short name T472
Test name
Test status
Simulation time 337619407694 ps
CPU time 259.66 seconds
Started Sep 04 10:15:51 AM UTC 24
Finished Sep 04 10:20:15 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204630263 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.204630263
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_loopback.2692218967
Short name T443
Test name
Test status
Simulation time 8990921207 ps
CPU time 16.31 seconds
Started Sep 04 10:15:48 AM UTC 24
Finished Sep 04 10:16:06 AM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692218967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2692218967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_perf.982508699
Short name T514
Test name
Test status
Simulation time 14420703975 ps
CPU time 497.7 seconds
Started Sep 04 10:15:49 AM UTC 24
Finished Sep 04 10:24:13 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982508699 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.982508699
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_rx_oversample.848655802
Short name T439
Test name
Test status
Simulation time 3616044685 ps
CPU time 5.48 seconds
Started Sep 04 10:15:24 AM UTC 24
Finished Sep 04 10:15:30 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848655802 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.848655802
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.3999664652
Short name T295
Test name
Test status
Simulation time 102168600159 ps
CPU time 120.35 seconds
Started Sep 04 10:15:32 AM UTC 24
Finished Sep 04 10:17:35 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999664652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3999664652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.2425125032
Short name T368
Test name
Test status
Simulation time 4272281674 ps
CPU time 8.1 seconds
Started Sep 04 10:15:31 AM UTC 24
Finished Sep 04 10:15:40 AM UTC 24
Peak memory 205024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425125032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2425125032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_smoke.1629789690
Short name T437
Test name
Test status
Simulation time 513704395 ps
CPU time 1.51 seconds
Started Sep 04 10:15:17 AM UTC 24
Finished Sep 04 10:15:20 AM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629789690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1629789690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.3887829418
Short name T383
Test name
Test status
Simulation time 10730352920 ps
CPU time 56.71 seconds
Started Sep 04 10:15:54 AM UTC 24
Finished Sep 04 10:16:53 AM UTC 24
Peak memory 217908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3887829418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all
_with_rand_reset.3887829418
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.1827119828
Short name T335
Test name
Test status
Simulation time 7142326248 ps
CPU time 11.7 seconds
Started Sep 04 10:15:41 AM UTC 24
Finished Sep 04 10:15:54 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827119828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1827119828
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/14.uart_tx_rx.2334344640
Short name T325
Test name
Test status
Simulation time 36299668815 ps
CPU time 68.14 seconds
Started Sep 04 10:15:18 AM UTC 24
Finished Sep 04 10:16:29 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334344640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2334344640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/14.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/141.uart_fifo_reset.1637560597
Short name T1042
Test name
Test status
Simulation time 108355403183 ps
CPU time 92.05 seconds
Started Sep 04 10:45:03 AM UTC 24
Finished Sep 04 10:46:37 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637560597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1637560597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/141.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/142.uart_fifo_reset.576706835
Short name T1065
Test name
Test status
Simulation time 31682200823 ps
CPU time 122.13 seconds
Started Sep 04 10:45:06 AM UTC 24
Finished Sep 04 10:47:11 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576706835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.576706835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/142.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/143.uart_fifo_reset.3457238283
Short name T1013
Test name
Test status
Simulation time 13756839933 ps
CPU time 24.23 seconds
Started Sep 04 10:45:06 AM UTC 24
Finished Sep 04 10:45:32 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457238283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3457238283
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/143.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/144.uart_fifo_reset.3281359727
Short name T1015
Test name
Test status
Simulation time 14483654056 ps
CPU time 24.77 seconds
Started Sep 04 10:45:09 AM UTC 24
Finished Sep 04 10:45:34 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281359727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3281359727
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/144.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/145.uart_fifo_reset.4135719892
Short name T1066
Test name
Test status
Simulation time 59736896234 ps
CPU time 119.65 seconds
Started Sep 04 10:45:10 AM UTC 24
Finished Sep 04 10:47:11 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135719892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4135719892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/145.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/146.uart_fifo_reset.2667723097
Short name T1023
Test name
Test status
Simulation time 20657338277 ps
CPU time 37.31 seconds
Started Sep 04 10:45:11 AM UTC 24
Finished Sep 04 10:45:49 AM UTC 24
Peak memory 208340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667723097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2667723097
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/146.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/147.uart_fifo_reset.2293347112
Short name T1020
Test name
Test status
Simulation time 127661058464 ps
CPU time 30.73 seconds
Started Sep 04 10:45:12 AM UTC 24
Finished Sep 04 10:45:44 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293347112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2293347112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/147.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/148.uart_fifo_reset.3331823471
Short name T1069
Test name
Test status
Simulation time 133525785091 ps
CPU time 118.42 seconds
Started Sep 04 10:45:13 AM UTC 24
Finished Sep 04 10:47:13 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331823471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3331823471
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/148.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/149.uart_fifo_reset.775342625
Short name T1016
Test name
Test status
Simulation time 7875465678 ps
CPU time 20.09 seconds
Started Sep 04 10:45:15 AM UTC 24
Finished Sep 04 10:45:36 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775342625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.775342625
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/149.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_alert_test.1374190330
Short name T448
Test name
Test status
Simulation time 44946609 ps
CPU time 0.81 seconds
Started Sep 04 10:16:44 AM UTC 24
Finished Sep 04 10:16:46 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374190330 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1374190330
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_fifo_full.1297365028
Short name T148
Test name
Test status
Simulation time 303741786771 ps
CPU time 866.52 seconds
Started Sep 04 10:16:07 AM UTC 24
Finished Sep 04 10:30:43 AM UTC 24
Peak memory 212220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297365028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1297365028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.134933114
Short name T382
Test name
Test status
Simulation time 20424948781 ps
CPU time 27.76 seconds
Started Sep 04 10:16:08 AM UTC 24
Finished Sep 04 10:16:37 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134933114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.134933114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.2548126165
Short name T494
Test name
Test status
Simulation time 124239723267 ps
CPU time 404.82 seconds
Started Sep 04 10:16:32 AM UTC 24
Finished Sep 04 10:23:22 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548126165 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2548126165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_loopback.755089745
Short name T450
Test name
Test status
Simulation time 14614682708 ps
CPU time 24.52 seconds
Started Sep 04 10:16:30 AM UTC 24
Finished Sep 04 10:16:55 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755089745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.uart_loopback.755089745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_noise_filter.3591405362
Short name T312
Test name
Test status
Simulation time 96763087632 ps
CPU time 195 seconds
Started Sep 04 10:16:21 AM UTC 24
Finished Sep 04 10:19:39 AM UTC 24
Peak memory 217552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591405362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3591405362
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_perf.3428629179
Short name T485
Test name
Test status
Simulation time 3978711909 ps
CPU time 324.63 seconds
Started Sep 04 10:16:30 AM UTC 24
Finished Sep 04 10:21:59 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428629179 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3428629179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_rx_oversample.2045245536
Short name T454
Test name
Test status
Simulation time 6092876377 ps
CPU time 86.83 seconds
Started Sep 04 10:16:10 AM UTC 24
Finished Sep 04 10:17:39 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045245536 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2045245536
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.196178412
Short name T334
Test name
Test status
Simulation time 49210386111 ps
CPU time 84.66 seconds
Started Sep 04 10:16:25 AM UTC 24
Finished Sep 04 10:17:52 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196178412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.196178412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.974516751
Short name T445
Test name
Test status
Simulation time 3875075442 ps
CPU time 1.47 seconds
Started Sep 04 10:16:23 AM UTC 24
Finished Sep 04 10:16:26 AM UTC 24
Peak memory 204496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974516751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.974516751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_smoke.1382038257
Short name T442
Test name
Test status
Simulation time 723134283 ps
CPU time 3.27 seconds
Started Sep 04 10:15:59 AM UTC 24
Finished Sep 04 10:16:03 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382038257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1382038257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.2849269610
Short name T339
Test name
Test status
Simulation time 3109576518 ps
CPU time 87.62 seconds
Started Sep 04 10:16:32 AM UTC 24
Finished Sep 04 10:18:01 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2849269610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all
_with_rand_reset.2849269610
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.3895783761
Short name T446
Test name
Test status
Simulation time 1647364389 ps
CPU time 3.35 seconds
Started Sep 04 10:16:26 AM UTC 24
Finished Sep 04 10:16:31 AM UTC 24
Peak memory 208032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895783761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3895783761
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/150.uart_fifo_reset.2899630328
Short name T1178
Test name
Test status
Simulation time 120693084356 ps
CPU time 458.15 seconds
Started Sep 04 10:45:16 AM UTC 24
Finished Sep 04 10:53:00 AM UTC 24
Peak memory 212220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899630328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2899630328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/150.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/151.uart_fifo_reset.4191836169
Short name T1034
Test name
Test status
Simulation time 106600541845 ps
CPU time 48.17 seconds
Started Sep 04 10:45:24 AM UTC 24
Finished Sep 04 10:46:14 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191836169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.4191836169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/151.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/152.uart_fifo_reset.2754294794
Short name T1036
Test name
Test status
Simulation time 18816179387 ps
CPU time 53.28 seconds
Started Sep 04 10:45:25 AM UTC 24
Finished Sep 04 10:46:20 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754294794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2754294794
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/152.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/154.uart_fifo_reset.4201540538
Short name T1088
Test name
Test status
Simulation time 88953644780 ps
CPU time 137.4 seconds
Started Sep 04 10:45:27 AM UTC 24
Finished Sep 04 10:47:47 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201540538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4201540538
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/154.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/155.uart_fifo_reset.1034575271
Short name T1021
Test name
Test status
Simulation time 8718668104 ps
CPU time 15.73 seconds
Started Sep 04 10:45:28 AM UTC 24
Finished Sep 04 10:45:45 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034575271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1034575271
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/155.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/156.uart_fifo_reset.2602367225
Short name T1081
Test name
Test status
Simulation time 81514634441 ps
CPU time 118.46 seconds
Started Sep 04 10:45:29 AM UTC 24
Finished Sep 04 10:47:29 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602367225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2602367225
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/156.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/157.uart_fifo_reset.4008101269
Short name T1175
Test name
Test status
Simulation time 53789685200 ps
CPU time 411.21 seconds
Started Sep 04 10:45:30 AM UTC 24
Finished Sep 04 10:52:26 AM UTC 24
Peak memory 210376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008101269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4008101269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/157.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/158.uart_fifo_reset.2333456530
Short name T189
Test name
Test status
Simulation time 26833574303 ps
CPU time 53.65 seconds
Started Sep 04 10:45:30 AM UTC 24
Finished Sep 04 10:46:25 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333456530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2333456530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/158.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/159.uart_fifo_reset.315655128
Short name T1093
Test name
Test status
Simulation time 58541334145 ps
CPU time 143.88 seconds
Started Sep 04 10:45:33 AM UTC 24
Finished Sep 04 10:47:59 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315655128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.315655128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/159.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_alert_test.2163590832
Short name T455
Test name
Test status
Simulation time 22371600 ps
CPU time 0.81 seconds
Started Sep 04 10:17:39 AM UTC 24
Finished Sep 04 10:17:41 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163590832 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2163590832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.1844208928
Short name T133
Test name
Test status
Simulation time 147261716634 ps
CPU time 198.77 seconds
Started Sep 04 10:16:53 AM UTC 24
Finished Sep 04 10:20:15 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844208928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1844208928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_fifo_reset.3017236488
Short name T350
Test name
Test status
Simulation time 19252646387 ps
CPU time 48.5 seconds
Started Sep 04 10:16:56 AM UTC 24
Finished Sep 04 10:17:46 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017236488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3017236488
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_intr.592580259
Short name T539
Test name
Test status
Simulation time 188302548667 ps
CPU time 500.42 seconds
Started Sep 04 10:17:00 AM UTC 24
Finished Sep 04 10:25:26 AM UTC 24
Peak memory 207140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592580259 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.592580259
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.3850322334
Short name T716
Test name
Test status
Simulation time 115229950957 ps
CPU time 911.02 seconds
Started Sep 04 10:17:30 AM UTC 24
Finished Sep 04 10:32:52 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850322334 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3850322334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_loopback.2034848033
Short name T453
Test name
Test status
Simulation time 2452218625 ps
CPU time 9.67 seconds
Started Sep 04 10:17:22 AM UTC 24
Finished Sep 04 10:17:33 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034848033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2034848033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_noise_filter.3077706045
Short name T358
Test name
Test status
Simulation time 79581099264 ps
CPU time 177.08 seconds
Started Sep 04 10:17:01 AM UTC 24
Finished Sep 04 10:20:00 AM UTC 24
Peak memory 208940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077706045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3077706045
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_perf.3659171366
Short name T791
Test name
Test status
Simulation time 21135946137 ps
CPU time 1111.45 seconds
Started Sep 04 10:17:30 AM UTC 24
Finished Sep 04 10:36:14 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659171366 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3659171366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_rx_oversample.96841907
Short name T452
Test name
Test status
Simulation time 5944076575 ps
CPU time 31.8 seconds
Started Sep 04 10:16:56 AM UTC 24
Finished Sep 04 10:17:30 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96841907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.96841907
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.3462730561
Short name T306
Test name
Test status
Simulation time 62697768106 ps
CPU time 65.93 seconds
Started Sep 04 10:17:04 AM UTC 24
Finished Sep 04 10:18:11 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462730561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3462730561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.2111592868
Short name T375
Test name
Test status
Simulation time 42447751687 ps
CPU time 11.89 seconds
Started Sep 04 10:17:03 AM UTC 24
Finished Sep 04 10:17:16 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111592868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2111592868
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_smoke.1302514488
Short name T449
Test name
Test status
Simulation time 472806010 ps
CPU time 1.08 seconds
Started Sep 04 10:16:47 AM UTC 24
Finished Sep 04 10:16:49 AM UTC 24
Peak memory 206244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302514488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1302514488
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.1879575452
Short name T463
Test name
Test status
Simulation time 14777415247 ps
CPU time 79.23 seconds
Started Sep 04 10:17:33 AM UTC 24
Finished Sep 04 10:18:54 AM UTC 24
Peak memory 224484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1879575452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all
_with_rand_reset.1879575452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.1865149308
Short name T451
Test name
Test status
Simulation time 745721435 ps
CPU time 3.46 seconds
Started Sep 04 10:17:17 AM UTC 24
Finished Sep 04 10:17:21 AM UTC 24
Peak memory 207532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865149308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1865149308
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/16.uart_tx_rx.3457325527
Short name T310
Test name
Test status
Simulation time 118332069908 ps
CPU time 425.64 seconds
Started Sep 04 10:16:50 AM UTC 24
Finished Sep 04 10:24:01 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457325527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3457325527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/16.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2974136169
Short name T1039
Test name
Test status
Simulation time 55894260978 ps
CPU time 56.29 seconds
Started Sep 04 10:45:35 AM UTC 24
Finished Sep 04 10:46:33 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974136169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2974136169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/162.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/163.uart_fifo_reset.2582970012
Short name T1052
Test name
Test status
Simulation time 57980831240 ps
CPU time 72.07 seconds
Started Sep 04 10:45:37 AM UTC 24
Finished Sep 04 10:46:51 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582970012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2582970012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/163.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/164.uart_fifo_reset.4101744884
Short name T1049
Test name
Test status
Simulation time 98324673594 ps
CPU time 64.34 seconds
Started Sep 04 10:45:39 AM UTC 24
Finished Sep 04 10:46:45 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101744884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4101744884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/164.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/165.uart_fifo_reset.4156833297
Short name T1027
Test name
Test status
Simulation time 24166244485 ps
CPU time 12.18 seconds
Started Sep 04 10:45:43 AM UTC 24
Finished Sep 04 10:45:57 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156833297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4156833297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/165.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/166.uart_fifo_reset.2236341116
Short name T1035
Test name
Test status
Simulation time 10131353541 ps
CPU time 32.48 seconds
Started Sep 04 10:45:44 AM UTC 24
Finished Sep 04 10:46:18 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236341116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2236341116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/166.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/168.uart_fifo_reset.2482086627
Short name T1064
Test name
Test status
Simulation time 183188429025 ps
CPU time 79.93 seconds
Started Sep 04 10:45:46 AM UTC 24
Finished Sep 04 10:47:08 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482086627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2482086627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/168.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/169.uart_fifo_reset.2137593667
Short name T1030
Test name
Test status
Simulation time 43419730654 ps
CPU time 16.65 seconds
Started Sep 04 10:45:49 AM UTC 24
Finished Sep 04 10:46:07 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137593667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2137593667
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/169.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_alert_test.1311644930
Short name T462
Test name
Test status
Simulation time 11748481 ps
CPU time 0.83 seconds
Started Sep 04 10:18:49 AM UTC 24
Finished Sep 04 10:18:51 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311644930 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1311644930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_fifo_full.3069923800
Short name T142
Test name
Test status
Simulation time 118330505393 ps
CPU time 38.86 seconds
Started Sep 04 10:17:48 AM UTC 24
Finished Sep 04 10:18:28 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069923800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3069923800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.4175791911
Short name T359
Test name
Test status
Simulation time 175203359925 ps
CPU time 54.59 seconds
Started Sep 04 10:17:52 AM UTC 24
Finished Sep 04 10:18:48 AM UTC 24
Peak memory 208556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175791911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.4175791911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_fifo_reset.2285582177
Short name T207
Test name
Test status
Simulation time 98714462113 ps
CPU time 144.1 seconds
Started Sep 04 10:17:53 AM UTC 24
Finished Sep 04 10:20:20 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285582177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2285582177
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_intr.2144875297
Short name T662
Test name
Test status
Simulation time 382948317879 ps
CPU time 751.45 seconds
Started Sep 04 10:18:02 AM UTC 24
Finished Sep 04 10:30:41 AM UTC 24
Peak memory 209372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144875297 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2144875297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.1672822007
Short name T582
Test name
Test status
Simulation time 80055195563 ps
CPU time 536.19 seconds
Started Sep 04 10:18:34 AM UTC 24
Finished Sep 04 10:27:36 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672822007 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1672822007
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_loopback.3521226742
Short name T461
Test name
Test status
Simulation time 2668380161 ps
CPU time 8.47 seconds
Started Sep 04 10:18:23 AM UTC 24
Finished Sep 04 10:18:33 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521226742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3521226742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_noise_filter.846289230
Short name T459
Test name
Test status
Simulation time 105921835461 ps
CPU time 13.39 seconds
Started Sep 04 10:18:03 AM UTC 24
Finished Sep 04 10:18:17 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846289230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.846289230
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_perf.680641675
Short name T682
Test name
Test status
Simulation time 14206515885 ps
CPU time 777.38 seconds
Started Sep 04 10:18:28 AM UTC 24
Finished Sep 04 10:31:35 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680641675 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.680641675
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_rx_oversample.3458798793
Short name T458
Test name
Test status
Simulation time 3815086255 ps
CPU time 3.11 seconds
Started Sep 04 10:17:58 AM UTC 24
Finished Sep 04 10:18:02 AM UTC 24
Peak memory 208032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458798793 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3458798793
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.4040505440
Short name T460
Test name
Test status
Simulation time 4687078820 ps
CPU time 9.24 seconds
Started Sep 04 10:18:12 AM UTC 24
Finished Sep 04 10:18:23 AM UTC 24
Peak memory 207208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040505440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4040505440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_smoke.1535114661
Short name T456
Test name
Test status
Simulation time 448247550 ps
CPU time 3.88 seconds
Started Sep 04 10:17:41 AM UTC 24
Finished Sep 04 10:17:46 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535114661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1535114661
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.3070053950
Short name T88
Test name
Test status
Simulation time 14534889413 ps
CPU time 57.51 seconds
Started Sep 04 10:18:41 AM UTC 24
Finished Sep 04 10:19:40 AM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3070053950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all
_with_rand_reset.3070053950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.3445473677
Short name T331
Test name
Test status
Simulation time 6657930915 ps
CPU time 36.86 seconds
Started Sep 04 10:18:18 AM UTC 24
Finished Sep 04 10:18:57 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445473677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3445473677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/17.uart_tx_rx.805447780
Short name T286
Test name
Test status
Simulation time 110919191585 ps
CPU time 70.37 seconds
Started Sep 04 10:17:48 AM UTC 24
Finished Sep 04 10:19:00 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805447780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.805447780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/17.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/170.uart_fifo_reset.2448156718
Short name T1067
Test name
Test status
Simulation time 33006994930 ps
CPU time 80.21 seconds
Started Sep 04 10:45:51 AM UTC 24
Finished Sep 04 10:47:13 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448156718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2448156718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/170.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/171.uart_fifo_reset.2115318463
Short name T1038
Test name
Test status
Simulation time 20018039771 ps
CPU time 35.59 seconds
Started Sep 04 10:45:52 AM UTC 24
Finished Sep 04 10:46:29 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115318463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2115318463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/171.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2066895900
Short name T1060
Test name
Test status
Simulation time 92075623376 ps
CPU time 63.74 seconds
Started Sep 04 10:45:55 AM UTC 24
Finished Sep 04 10:47:00 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066895900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2066895900
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/172.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/173.uart_fifo_reset.195137820
Short name T1055
Test name
Test status
Simulation time 112807658845 ps
CPU time 55.31 seconds
Started Sep 04 10:45:57 AM UTC 24
Finished Sep 04 10:46:54 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195137820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.195137820
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/173.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/174.uart_fifo_reset.1836705882
Short name T1048
Test name
Test status
Simulation time 14910878401 ps
CPU time 44.73 seconds
Started Sep 04 10:45:58 AM UTC 24
Finished Sep 04 10:46:44 AM UTC 24
Peak memory 208804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836705882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1836705882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/174.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/175.uart_fifo_reset.2058697489
Short name T1032
Test name
Test status
Simulation time 12654040649 ps
CPU time 13.39 seconds
Started Sep 04 10:45:58 AM UTC 24
Finished Sep 04 10:46:12 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058697489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2058697489
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/175.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/176.uart_fifo_reset.1917364592
Short name T1045
Test name
Test status
Simulation time 28486726509 ps
CPU time 41.9 seconds
Started Sep 04 10:45:58 AM UTC 24
Finished Sep 04 10:46:41 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917364592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1917364592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/176.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/177.uart_fifo_reset.280293472
Short name T1101
Test name
Test status
Simulation time 147779583215 ps
CPU time 125.02 seconds
Started Sep 04 10:46:05 AM UTC 24
Finished Sep 04 10:48:13 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280293472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.280293472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/177.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/178.uart_fifo_reset.2818132265
Short name T1040
Test name
Test status
Simulation time 33263413320 ps
CPU time 27.64 seconds
Started Sep 04 10:46:07 AM UTC 24
Finished Sep 04 10:46:36 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818132265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2818132265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/178.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/179.uart_fifo_reset.1508191183
Short name T256
Test name
Test status
Simulation time 26503108787 ps
CPU time 26.27 seconds
Started Sep 04 10:46:08 AM UTC 24
Finished Sep 04 10:46:36 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508191183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1508191183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/179.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_alert_test.4034709535
Short name T468
Test name
Test status
Simulation time 15614589 ps
CPU time 0.87 seconds
Started Sep 04 10:20:00 AM UTC 24
Finished Sep 04 10:20:02 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034709535 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4034709535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_fifo_full.2893409922
Short name T314
Test name
Test status
Simulation time 52296852213 ps
CPU time 119.65 seconds
Started Sep 04 10:18:55 AM UTC 24
Finished Sep 04 10:20:57 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893409922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2893409922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.4120057662
Short name T138
Test name
Test status
Simulation time 48585902649 ps
CPU time 100.44 seconds
Started Sep 04 10:18:56 AM UTC 24
Finished Sep 04 10:20:38 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120057662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.4120057662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1510688896
Short name T181
Test name
Test status
Simulation time 25904473958 ps
CPU time 86.59 seconds
Started Sep 04 10:18:57 AM UTC 24
Finished Sep 04 10:20:26 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510688896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1510688896
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_intr.278565211
Short name T292
Test name
Test status
Simulation time 34448463409 ps
CPU time 57.25 seconds
Started Sep 04 10:19:00 AM UTC 24
Finished Sep 04 10:19:59 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278565211 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.278565211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.574365007
Short name T515
Test name
Test status
Simulation time 124277071417 ps
CPU time 269.22 seconds
Started Sep 04 10:19:42 AM UTC 24
Finished Sep 04 10:24:15 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574365007 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.574365007
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_loopback.2239897702
Short name T470
Test name
Test status
Simulation time 10812585332 ps
CPU time 23.35 seconds
Started Sep 04 10:19:40 AM UTC 24
Finished Sep 04 10:20:05 AM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239897702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2239897702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_perf.2242668743
Short name T631
Test name
Test status
Simulation time 11486466384 ps
CPU time 599 seconds
Started Sep 04 10:19:41 AM UTC 24
Finished Sep 04 10:29:47 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242668743 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2242668743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_rx_oversample.2819398784
Short name T471
Test name
Test status
Simulation time 7144397012 ps
CPU time 67.25 seconds
Started Sep 04 10:19:00 AM UTC 24
Finished Sep 04 10:20:09 AM UTC 24
Peak memory 208380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819398784 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2819398784
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.3033534059
Short name T371
Test name
Test status
Simulation time 97556070388 ps
CPU time 338.36 seconds
Started Sep 04 10:19:25 AM UTC 24
Finished Sep 04 10:25:07 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033534059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3033534059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.3427450528
Short name T466
Test name
Test status
Simulation time 3845745439 ps
CPU time 6.11 seconds
Started Sep 04 10:19:20 AM UTC 24
Finished Sep 04 10:19:28 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427450528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3427450528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_smoke.1331391685
Short name T464
Test name
Test status
Simulation time 718470527 ps
CPU time 2.19 seconds
Started Sep 04 10:18:52 AM UTC 24
Finished Sep 04 10:18:55 AM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331391685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1331391685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_stress_all.1642064884
Short name T172
Test name
Test status
Simulation time 247856353475 ps
CPU time 441.53 seconds
Started Sep 04 10:19:54 AM UTC 24
Finished Sep 04 10:27:21 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642064884 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1642064884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.2863877021
Short name T89
Test name
Test status
Simulation time 3248123803 ps
CPU time 33.64 seconds
Started Sep 04 10:19:51 AM UTC 24
Finished Sep 04 10:20:26 AM UTC 24
Peak memory 219872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2863877021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all
_with_rand_reset.2863877021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.3353997057
Short name T467
Test name
Test status
Simulation time 7121441062 ps
CPU time 23.53 seconds
Started Sep 04 10:19:29 AM UTC 24
Finished Sep 04 10:19:54 AM UTC 24
Peak memory 208108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353997057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3353997057
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/18.uart_tx_rx.3019420596
Short name T400
Test name
Test status
Simulation time 8831205761 ps
CPU time 28.23 seconds
Started Sep 04 10:18:54 AM UTC 24
Finished Sep 04 10:19:23 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019420596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3019420596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/18.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/180.uart_fifo_reset.3598074900
Short name T1043
Test name
Test status
Simulation time 331152100912 ps
CPU time 28.72 seconds
Started Sep 04 10:46:10 AM UTC 24
Finished Sep 04 10:46:40 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598074900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3598074900
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/180.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1162534081
Short name T1053
Test name
Test status
Simulation time 11942469556 ps
CPU time 38.06 seconds
Started Sep 04 10:46:11 AM UTC 24
Finished Sep 04 10:46:51 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162534081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1162534081
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/181.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/182.uart_fifo_reset.1541289079
Short name T1037
Test name
Test status
Simulation time 14255752599 ps
CPU time 11.64 seconds
Started Sep 04 10:46:12 AM UTC 24
Finished Sep 04 10:46:25 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541289079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1541289079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/182.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/183.uart_fifo_reset.3575176560
Short name T1056
Test name
Test status
Simulation time 51369874485 ps
CPU time 42.51 seconds
Started Sep 04 10:46:14 AM UTC 24
Finished Sep 04 10:46:57 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575176560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3575176560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/183.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/184.uart_fifo_reset.3988151502
Short name T1083
Test name
Test status
Simulation time 167250621607 ps
CPU time 77.27 seconds
Started Sep 04 10:46:14 AM UTC 24
Finished Sep 04 10:47:33 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988151502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3988151502
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/184.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/186.uart_fifo_reset.1882943319
Short name T1072
Test name
Test status
Simulation time 31052776230 ps
CPU time 60.56 seconds
Started Sep 04 10:46:15 AM UTC 24
Finished Sep 04 10:47:17 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882943319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1882943319
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/186.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/187.uart_fifo_reset.3486167575
Short name T1070
Test name
Test status
Simulation time 41218595261 ps
CPU time 54.17 seconds
Started Sep 04 10:46:19 AM UTC 24
Finished Sep 04 10:47:15 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486167575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3486167575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/187.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3005253879
Short name T1132
Test name
Test status
Simulation time 172048232159 ps
CPU time 161.26 seconds
Started Sep 04 10:46:21 AM UTC 24
Finished Sep 04 10:49:05 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005253879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3005253879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/188.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3319925069
Short name T1153
Test name
Test status
Simulation time 363705302591 ps
CPU time 210.06 seconds
Started Sep 04 10:46:26 AM UTC 24
Finished Sep 04 10:49:59 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319925069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3319925069
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/189.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_alert_test.3550297526
Short name T477
Test name
Test status
Simulation time 14799194 ps
CPU time 0.83 seconds
Started Sep 04 10:20:43 AM UTC 24
Finished Sep 04 10:20:45 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550297526 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3550297526
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_fifo_full.1901711371
Short name T482
Test name
Test status
Simulation time 25675783074 ps
CPU time 101.75 seconds
Started Sep 04 10:20:04 AM UTC 24
Finished Sep 04 10:21:48 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901711371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1901711371
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.529606088
Short name T149
Test name
Test status
Simulation time 38366422295 ps
CPU time 37.56 seconds
Started Sep 04 10:20:06 AM UTC 24
Finished Sep 04 10:20:44 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529606088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.529606088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3199675883
Short name T134
Test name
Test status
Simulation time 72426880993 ps
CPU time 116.36 seconds
Started Sep 04 10:20:10 AM UTC 24
Finished Sep 04 10:22:08 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199675883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3199675883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_intr.225679473
Short name T104
Test name
Test status
Simulation time 49571832434 ps
CPU time 25.91 seconds
Started Sep 04 10:20:16 AM UTC 24
Finished Sep 04 10:20:43 AM UTC 24
Peak memory 208948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225679473 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.225679473
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.2718498839
Short name T498
Test name
Test status
Simulation time 73175835314 ps
CPU time 172.02 seconds
Started Sep 04 10:20:33 AM UTC 24
Finished Sep 04 10:23:28 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718498839 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2718498839
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_loopback.3287070596
Short name T476
Test name
Test status
Simulation time 9774296436 ps
CPU time 11.69 seconds
Started Sep 04 10:20:26 AM UTC 24
Finished Sep 04 10:20:39 AM UTC 24
Peak memory 207688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287070596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3287070596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_noise_filter.2329833545
Short name T602
Test name
Test status
Simulation time 128548950066 ps
CPU time 501.56 seconds
Started Sep 04 10:20:21 AM UTC 24
Finished Sep 04 10:28:49 AM UTC 24
Peak memory 208384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329833545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2329833545
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_perf.3505539252
Short name T513
Test name
Test status
Simulation time 15512373771 ps
CPU time 220.35 seconds
Started Sep 04 10:20:27 AM UTC 24
Finished Sep 04 10:24:11 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505539252 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3505539252
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_rx_oversample.2652853348
Short name T473
Test name
Test status
Simulation time 7285592042 ps
CPU time 5 seconds
Started Sep 04 10:20:16 AM UTC 24
Finished Sep 04 10:20:22 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652853348 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2652853348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.3743050001
Short name T141
Test name
Test status
Simulation time 19879196193 ps
CPU time 62.05 seconds
Started Sep 04 10:20:23 AM UTC 24
Finished Sep 04 10:21:27 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743050001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3743050001
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.1871138814
Short name T474
Test name
Test status
Simulation time 1204023966 ps
CPU time 3.37 seconds
Started Sep 04 10:20:21 AM UTC 24
Finished Sep 04 10:20:25 AM UTC 24
Peak memory 205160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871138814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1871138814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_smoke.515860918
Short name T469
Test name
Test status
Simulation time 301556601 ps
CPU time 1.37 seconds
Started Sep 04 10:20:01 AM UTC 24
Finished Sep 04 10:20:04 AM UTC 24
Peak memory 208412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515860918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.uart_smoke.515860918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_stress_all.3412825915
Short name T870
Test name
Test status
Simulation time 202387028759 ps
CPU time 1117.2 seconds
Started Sep 04 10:20:39 AM UTC 24
Finished Sep 04 10:39:29 AM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412825915 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3412825915
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.3710181505
Short name T479
Test name
Test status
Simulation time 812166770 ps
CPU time 26.49 seconds
Started Sep 04 10:20:39 AM UTC 24
Finished Sep 04 10:21:07 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3710181505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all
_with_rand_reset.3710181505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.3309048219
Short name T475
Test name
Test status
Simulation time 975070608 ps
CPU time 5.2 seconds
Started Sep 04 10:20:26 AM UTC 24
Finished Sep 04 10:20:32 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309048219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3309048219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/19.uart_tx_rx.3381992028
Short name T346
Test name
Test status
Simulation time 95190618467 ps
CPU time 289.7 seconds
Started Sep 04 10:20:03 AM UTC 24
Finished Sep 04 10:24:57 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381992028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3381992028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/19.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/190.uart_fifo_reset.2213847561
Short name T1073
Test name
Test status
Simulation time 20321021779 ps
CPU time 49.51 seconds
Started Sep 04 10:46:26 AM UTC 24
Finished Sep 04 10:47:17 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213847561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2213847561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/190.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/191.uart_fifo_reset.928923110
Short name T1137
Test name
Test status
Simulation time 102988438369 ps
CPU time 161.57 seconds
Started Sep 04 10:46:29 AM UTC 24
Finished Sep 04 10:49:13 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928923110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.928923110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/191.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/192.uart_fifo_reset.2071675657
Short name T1063
Test name
Test status
Simulation time 8841193408 ps
CPU time 33.42 seconds
Started Sep 04 10:46:33 AM UTC 24
Finished Sep 04 10:47:08 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071675657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2071675657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/192.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/193.uart_fifo_reset.2886171934
Short name T1068
Test name
Test status
Simulation time 31533072322 ps
CPU time 35.72 seconds
Started Sep 04 10:46:36 AM UTC 24
Finished Sep 04 10:47:13 AM UTC 24
Peak memory 208532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886171934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2886171934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/193.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3106914901
Short name T1106
Test name
Test status
Simulation time 170597591126 ps
CPU time 98.04 seconds
Started Sep 04 10:46:37 AM UTC 24
Finished Sep 04 10:48:17 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106914901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3106914901
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/194.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/196.uart_fifo_reset.2940781336
Short name T1152
Test name
Test status
Simulation time 111114538367 ps
CPU time 198.12 seconds
Started Sep 04 10:46:38 AM UTC 24
Finished Sep 04 10:49:58 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940781336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2940781336
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/196.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/197.uart_fifo_reset.4149041878
Short name T1071
Test name
Test status
Simulation time 25360786135 ps
CPU time 32.87 seconds
Started Sep 04 10:46:42 AM UTC 24
Finished Sep 04 10:47:16 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149041878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4149041878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/197.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/198.uart_fifo_reset.3034458079
Short name T1061
Test name
Test status
Simulation time 40639740638 ps
CPU time 18.11 seconds
Started Sep 04 10:46:42 AM UTC 24
Finished Sep 04 10:47:01 AM UTC 24
Peak memory 208168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034458079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3034458079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/198.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/199.uart_fifo_reset.3661340095
Short name T1082
Test name
Test status
Simulation time 80117903970 ps
CPU time 46.62 seconds
Started Sep 04 10:46:43 AM UTC 24
Finished Sep 04 10:47:31 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661340095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3661340095
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/199.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_alert_test.708469728
Short name T31
Test name
Test status
Simulation time 15471979 ps
CPU time 0.84 seconds
Started Sep 04 10:06:17 AM UTC 24
Finished Sep 04 10:06:19 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708469728 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.708469728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.2021673215
Short name T127
Test name
Test status
Simulation time 131546762162 ps
CPU time 234.62 seconds
Started Sep 04 10:06:10 AM UTC 24
Finished Sep 04 10:10:07 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021673215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2021673215
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1634797087
Short name T110
Test name
Test status
Simulation time 39465513307 ps
CPU time 82.6 seconds
Started Sep 04 10:06:10 AM UTC 24
Finished Sep 04 10:07:34 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634797087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1634797087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_intr.1274749822
Short name T260
Test name
Test status
Simulation time 211498012219 ps
CPU time 182.2 seconds
Started Sep 04 10:06:10 AM UTC 24
Finished Sep 04 10:09:15 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274749822 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1274749822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_loopback.2679364653
Short name T23
Test name
Test status
Simulation time 3540547906 ps
CPU time 15.08 seconds
Started Sep 04 10:06:11 AM UTC 24
Finished Sep 04 10:06:27 AM UTC 24
Peak memory 208520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679364653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2679364653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_noise_filter.2102949332
Short name T43
Test name
Test status
Simulation time 36192250850 ps
CPU time 68.76 seconds
Started Sep 04 10:06:10 AM UTC 24
Finished Sep 04 10:07:20 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102949332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2102949332
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_perf.712512673
Short name T262
Test name
Test status
Simulation time 7720488191 ps
CPU time 324.1 seconds
Started Sep 04 10:06:14 AM UTC 24
Finished Sep 04 10:11:43 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712512673 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.712512673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_rx_oversample.802125181
Short name T17
Test name
Test status
Simulation time 4432130950 ps
CPU time 15.44 seconds
Started Sep 04 10:06:10 AM UTC 24
Finished Sep 04 10:06:26 AM UTC 24
Peak memory 208004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802125181 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.802125181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.533598811
Short name T120
Test name
Test status
Simulation time 211353726310 ps
CPU time 360.15 seconds
Started Sep 04 10:06:11 AM UTC 24
Finished Sep 04 10:12:15 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533598811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.533598811
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.1614150884
Short name T28
Test name
Test status
Simulation time 3356026379 ps
CPU time 1.5 seconds
Started Sep 04 10:06:11 AM UTC 24
Finished Sep 04 10:06:14 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614150884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1614150884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_sec_cm.1156386165
Short name T32
Test name
Test status
Simulation time 75740898 ps
CPU time 1.12 seconds
Started Sep 04 10:06:16 AM UTC 24
Finished Sep 04 10:06:19 AM UTC 24
Peak memory 239512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156386165 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1156386165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_smoke.759021368
Short name T14
Test name
Test status
Simulation time 890781625 ps
CPU time 3.51 seconds
Started Sep 04 10:06:09 AM UTC 24
Finished Sep 04 10:06:13 AM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759021368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.uart_smoke.759021368
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.2214503760
Short name T24
Test name
Test status
Simulation time 5600283670 ps
CPU time 63.09 seconds
Started Sep 04 10:06:14 AM UTC 24
Finished Sep 04 10:07:19 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2214503760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_
with_rand_reset.2214503760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.54852213
Short name T21
Test name
Test status
Simulation time 9209040272 ps
CPU time 17.6 seconds
Started Sep 04 10:06:11 AM UTC 24
Finished Sep 04 10:06:30 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54852213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.54852213
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/2.uart_tx_rx.2580769241
Short name T293
Test name
Test status
Simulation time 56612988199 ps
CPU time 105.2 seconds
Started Sep 04 10:06:09 AM UTC 24
Finished Sep 04 10:07:56 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580769241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2580769241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/2.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_alert_test.1640448845
Short name T487
Test name
Test status
Simulation time 52773396 ps
CPU time 0.83 seconds
Started Sep 04 10:22:07 AM UTC 24
Finished Sep 04 10:22:09 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640448845 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1640448845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_fifo_full.1608629889
Short name T501
Test name
Test status
Simulation time 72799861258 ps
CPU time 167.91 seconds
Started Sep 04 10:20:49 AM UTC 24
Finished Sep 04 10:23:39 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608629889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1608629889
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.3692257912
Short name T139
Test name
Test status
Simulation time 110459422121 ps
CPU time 272.19 seconds
Started Sep 04 10:20:58 AM UTC 24
Finished Sep 04 10:25:34 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692257912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3692257912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_fifo_reset.882382416
Short name T182
Test name
Test status
Simulation time 124760904339 ps
CPU time 114.49 seconds
Started Sep 04 10:21:08 AM UTC 24
Finished Sep 04 10:23:05 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882382416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.882382416
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_intr.2423465434
Short name T492
Test name
Test status
Simulation time 52935447686 ps
CPU time 106.68 seconds
Started Sep 04 10:21:26 AM UTC 24
Finished Sep 04 10:23:15 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423465434 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2423465434
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.1144349088
Short name T545
Test name
Test status
Simulation time 248264635425 ps
CPU time 224.86 seconds
Started Sep 04 10:21:54 AM UTC 24
Finished Sep 04 10:25:42 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144349088 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1144349088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_loopback.231089379
Short name T486
Test name
Test status
Simulation time 9212580655 ps
CPU time 15.66 seconds
Started Sep 04 10:21:50 AM UTC 24
Finished Sep 04 10:22:06 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231089379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_loopback.231089379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_noise_filter.3255384296
Short name T379
Test name
Test status
Simulation time 82594284639 ps
CPU time 80.23 seconds
Started Sep 04 10:21:27 AM UTC 24
Finished Sep 04 10:22:49 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255384296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3255384296
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_perf.2286861586
Short name T352
Test name
Test status
Simulation time 25847102740 ps
CPU time 88.16 seconds
Started Sep 04 10:21:51 AM UTC 24
Finished Sep 04 10:23:21 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286861586 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2286861586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_rx_oversample.530158718
Short name T480
Test name
Test status
Simulation time 4759973938 ps
CPU time 15.87 seconds
Started Sep 04 10:21:08 AM UTC 24
Finished Sep 04 10:21:25 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530158718 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.530158718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.4001711767
Short name T503
Test name
Test status
Simulation time 38254800326 ps
CPU time 118.07 seconds
Started Sep 04 10:21:43 AM UTC 24
Finished Sep 04 10:23:44 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001711767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.4001711767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.657393828
Short name T481
Test name
Test status
Simulation time 2170461566 ps
CPU time 3.18 seconds
Started Sep 04 10:21:38 AM UTC 24
Finished Sep 04 10:21:43 AM UTC 24
Peak memory 205020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657393828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.657393828
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_smoke.3881663998
Short name T478
Test name
Test status
Simulation time 331815307 ps
CPU time 1.42 seconds
Started Sep 04 10:20:46 AM UTC 24
Finished Sep 04 10:20:48 AM UTC 24
Peak memory 206244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881663998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3881663998
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_stress_all.529223750
Short name T106
Test name
Test status
Simulation time 61605853640 ps
CPU time 131.3 seconds
Started Sep 04 10:22:00 AM UTC 24
Finished Sep 04 10:24:13 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529223750 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.529223750
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.3440706109
Short name T365
Test name
Test status
Simulation time 9952033251 ps
CPU time 6.45 seconds
Started Sep 04 10:21:48 AM UTC 24
Finished Sep 04 10:21:55 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440706109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3440706109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/200.uart_fifo_reset.962814728
Short name T1129
Test name
Test status
Simulation time 49817664546 ps
CPU time 136.2 seconds
Started Sep 04 10:46:43 AM UTC 24
Finished Sep 04 10:49:01 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962814728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.962814728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/200.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/201.uart_fifo_reset.2102379594
Short name T1084
Test name
Test status
Simulation time 189920751123 ps
CPU time 53.71 seconds
Started Sep 04 10:46:43 AM UTC 24
Finished Sep 04 10:47:38 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102379594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2102379594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/201.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/202.uart_fifo_reset.1245166678
Short name T1140
Test name
Test status
Simulation time 138441908468 ps
CPU time 149.39 seconds
Started Sep 04 10:46:45 AM UTC 24
Finished Sep 04 10:49:17 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245166678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1245166678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/202.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/203.uart_fifo_reset.3929174829
Short name T1076
Test name
Test status
Simulation time 90017938160 ps
CPU time 33.61 seconds
Started Sep 04 10:46:46 AM UTC 24
Finished Sep 04 10:47:21 AM UTC 24
Peak memory 208456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929174829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3929174829
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/203.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2447844510
Short name T1077
Test name
Test status
Simulation time 17747795392 ps
CPU time 34.35 seconds
Started Sep 04 10:46:46 AM UTC 24
Finished Sep 04 10:47:22 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447844510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2447844510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/204.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/205.uart_fifo_reset.1565951891
Short name T1057
Test name
Test status
Simulation time 4491430359 ps
CPU time 9.39 seconds
Started Sep 04 10:46:47 AM UTC 24
Finished Sep 04 10:46:58 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565951891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1565951891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/205.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2881368374
Short name T1085
Test name
Test status
Simulation time 111246553184 ps
CPU time 50.28 seconds
Started Sep 04 10:46:51 AM UTC 24
Finished Sep 04 10:47:43 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881368374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2881368374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/206.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/207.uart_fifo_reset.4252531958
Short name T1095
Test name
Test status
Simulation time 137067384273 ps
CPU time 67.88 seconds
Started Sep 04 10:46:51 AM UTC 24
Finished Sep 04 10:48:01 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252531958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4252531958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/207.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/208.uart_fifo_reset.3156157190
Short name T161
Test name
Test status
Simulation time 94793459499 ps
CPU time 142.65 seconds
Started Sep 04 10:46:52 AM UTC 24
Finished Sep 04 10:49:17 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156157190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3156157190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/208.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/209.uart_fifo_reset.1752292487
Short name T1062
Test name
Test status
Simulation time 25361049393 ps
CPU time 11.36 seconds
Started Sep 04 10:46:53 AM UTC 24
Finished Sep 04 10:47:06 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752292487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1752292487
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/209.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_alert_test.668009179
Short name T497
Test name
Test status
Simulation time 41551735 ps
CPU time 0.82 seconds
Started Sep 04 10:23:24 AM UTC 24
Finished Sep 04 10:23:26 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668009179 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.668009179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_fifo_full.319862980
Short name T491
Test name
Test status
Simulation time 143023101328 ps
CPU time 24.46 seconds
Started Sep 04 10:22:26 AM UTC 24
Finished Sep 04 10:22:52 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319862980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.319862980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.2879623663
Short name T171
Test name
Test status
Simulation time 156483479753 ps
CPU time 151.19 seconds
Started Sep 04 10:22:38 AM UTC 24
Finished Sep 04 10:25:12 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879623663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2879623663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_fifo_reset.3480283422
Short name T190
Test name
Test status
Simulation time 78795350854 ps
CPU time 131 seconds
Started Sep 04 10:22:40 AM UTC 24
Finished Sep 04 10:24:54 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480283422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3480283422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_intr.1470115196
Short name T317
Test name
Test status
Simulation time 14513507792 ps
CPU time 32.19 seconds
Started Sep 04 10:22:50 AM UTC 24
Finished Sep 04 10:23:23 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470115196 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1470115196
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.2217332758
Short name T598
Test name
Test status
Simulation time 50695372980 ps
CPU time 317 seconds
Started Sep 04 10:23:18 AM UTC 24
Finished Sep 04 10:28:40 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217332758 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2217332758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_loopback.2048929755
Short name T495
Test name
Test status
Simulation time 3842373958 ps
CPU time 5.93 seconds
Started Sep 04 10:23:16 AM UTC 24
Finished Sep 04 10:23:23 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048929755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2048929755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_noise_filter.1335782869
Short name T354
Test name
Test status
Simulation time 114118559746 ps
CPU time 64.45 seconds
Started Sep 04 10:22:53 AM UTC 24
Finished Sep 04 10:23:59 AM UTC 24
Peak memory 208104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335782869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1335782869
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_perf.3557693757
Short name T1128
Test name
Test status
Simulation time 27887628053 ps
CPU time 1528.75 seconds
Started Sep 04 10:23:16 AM UTC 24
Finished Sep 04 10:49:01 AM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557693757 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3557693757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_rx_oversample.2238521719
Short name T504
Test name
Test status
Simulation time 5080112208 ps
CPU time 65.44 seconds
Started Sep 04 10:22:44 AM UTC 24
Finished Sep 04 10:23:51 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238521719 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2238521719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.2777287367
Short name T369
Test name
Test status
Simulation time 74096998688 ps
CPU time 419.55 seconds
Started Sep 04 10:23:06 AM UTC 24
Finished Sep 04 10:30:11 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777287367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2777287367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.3479465669
Short name T496
Test name
Test status
Simulation time 5527291582 ps
CPU time 20.69 seconds
Started Sep 04 10:23:02 AM UTC 24
Finished Sep 04 10:23:24 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479465669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3479465669
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_smoke.3116829027
Short name T488
Test name
Test status
Simulation time 6272609976 ps
CPU time 26.99 seconds
Started Sep 04 10:22:09 AM UTC 24
Finished Sep 04 10:22:37 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116829027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3116829027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_stress_all.2061292894
Short name T635
Test name
Test status
Simulation time 160260205084 ps
CPU time 383.36 seconds
Started Sep 04 10:23:22 AM UTC 24
Finished Sep 04 10:29:50 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061292894 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2061292894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.1171106615
Short name T90
Test name
Test status
Simulation time 11315297673 ps
CPU time 46.89 seconds
Started Sep 04 10:23:21 AM UTC 24
Finished Sep 04 10:24:10 AM UTC 24
Peak memory 225356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1171106615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all
_with_rand_reset.1171106615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.124680667
Short name T372
Test name
Test status
Simulation time 7154514455 ps
CPU time 14.21 seconds
Started Sep 04 10:23:14 AM UTC 24
Finished Sep 04 10:23:29 AM UTC 24
Peak memory 208524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124680667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.124680667
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/21.uart_tx_rx.13871716
Short name T489
Test name
Test status
Simulation time 17327414880 ps
CPU time 27.77 seconds
Started Sep 04 10:22:10 AM UTC 24
Finished Sep 04 10:22:39 AM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13871716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.13871716
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/21.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1179770556
Short name T209
Test name
Test status
Simulation time 28077266342 ps
CPU time 25.98 seconds
Started Sep 04 10:46:55 AM UTC 24
Finished Sep 04 10:47:22 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179770556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1179770556
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/210.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/212.uart_fifo_reset.582904826
Short name T1080
Test name
Test status
Simulation time 20103263514 ps
CPU time 27.46 seconds
Started Sep 04 10:46:59 AM UTC 24
Finished Sep 04 10:47:27 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582904826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.582904826
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/212.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/213.uart_fifo_reset.2238540232
Short name T213
Test name
Test status
Simulation time 208918920147 ps
CPU time 43.79 seconds
Started Sep 04 10:47:00 AM UTC 24
Finished Sep 04 10:47:45 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238540232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2238540232
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/213.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/214.uart_fifo_reset.207497849
Short name T1079
Test name
Test status
Simulation time 11643096510 ps
CPU time 26.12 seconds
Started Sep 04 10:47:00 AM UTC 24
Finished Sep 04 10:47:27 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207497849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.207497849
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/214.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3719935582
Short name T1078
Test name
Test status
Simulation time 49883563016 ps
CPU time 22.6 seconds
Started Sep 04 10:47:01 AM UTC 24
Finished Sep 04 10:47:25 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719935582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3719935582
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/215.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1220620661
Short name T1111
Test name
Test status
Simulation time 28238810144 ps
CPU time 85.34 seconds
Started Sep 04 10:47:02 AM UTC 24
Finished Sep 04 10:48:29 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220620661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1220620661
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/216.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/217.uart_fifo_reset.1622411701
Short name T1107
Test name
Test status
Simulation time 129666695224 ps
CPU time 72.3 seconds
Started Sep 04 10:47:04 AM UTC 24
Finished Sep 04 10:48:18 AM UTC 24
Peak memory 208588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622411701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1622411701
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/217.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/219.uart_fifo_reset.3717386590
Short name T1112
Test name
Test status
Simulation time 111174784515 ps
CPU time 81.21 seconds
Started Sep 04 10:47:09 AM UTC 24
Finished Sep 04 10:48:32 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717386590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3717386590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/219.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_alert_test.4256893439
Short name T507
Test name
Test status
Simulation time 45357452 ps
CPU time 0.81 seconds
Started Sep 04 10:23:59 AM UTC 24
Finished Sep 04 10:24:00 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256893439 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4256893439
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_fifo_full.143488411
Short name T394
Test name
Test status
Simulation time 47462055873 ps
CPU time 44.27 seconds
Started Sep 04 10:23:27 AM UTC 24
Finished Sep 04 10:24:12 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143488411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.143488411
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.3140448242
Short name T155
Test name
Test status
Simulation time 9722595130 ps
CPU time 30.15 seconds
Started Sep 04 10:23:27 AM UTC 24
Finished Sep 04 10:23:58 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140448242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3140448242
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_fifo_reset.3539555659
Short name T130
Test name
Test status
Simulation time 23211132809 ps
CPU time 19.14 seconds
Started Sep 04 10:23:29 AM UTC 24
Finished Sep 04 10:23:49 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539555659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3539555659
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_intr.4061406502
Short name T505
Test name
Test status
Simulation time 8595231694 ps
CPU time 19.54 seconds
Started Sep 04 10:23:31 AM UTC 24
Finished Sep 04 10:23:52 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061406502 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4061406502
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.90804664
Short name T734
Test name
Test status
Simulation time 141115197714 ps
CPU time 583.34 seconds
Started Sep 04 10:23:51 AM UTC 24
Finished Sep 04 10:33:42 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90804664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.90804664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_loopback.1087076416
Short name T509
Test name
Test status
Simulation time 4974107200 ps
CPU time 21.64 seconds
Started Sep 04 10:23:44 AM UTC 24
Finished Sep 04 10:24:07 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087076416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1087076416
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_noise_filter.1053651044
Short name T524
Test name
Test status
Simulation time 107049396078 ps
CPU time 70.1 seconds
Started Sep 04 10:23:31 AM UTC 24
Finished Sep 04 10:24:43 AM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053651044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1053651044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_perf.3613888189
Short name T596
Test name
Test status
Simulation time 14044717215 ps
CPU time 268.51 seconds
Started Sep 04 10:23:50 AM UTC 24
Finished Sep 04 10:28:23 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613888189 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3613888189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_rx_oversample.1819762015
Short name T506
Test name
Test status
Simulation time 7323884255 ps
CPU time 28 seconds
Started Sep 04 10:23:30 AM UTC 24
Finished Sep 04 10:23:59 AM UTC 24
Peak memory 207760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819762015 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1819762015
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.39280470
Short name T147
Test name
Test status
Simulation time 93717777256 ps
CPU time 190.51 seconds
Started Sep 04 10:23:40 AM UTC 24
Finished Sep 04 10:26:53 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39280470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.39280470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.3934087369
Short name T510
Test name
Test status
Simulation time 25250579663 ps
CPU time 28.65 seconds
Started Sep 04 10:23:39 AM UTC 24
Finished Sep 04 10:24:09 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934087369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3934087369
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_smoke.3302503049
Short name T499
Test name
Test status
Simulation time 646250230 ps
CPU time 5.04 seconds
Started Sep 04 10:23:24 AM UTC 24
Finished Sep 04 10:23:30 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302503049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3302503049
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_stress_all.2271254197
Short name T627
Test name
Test status
Simulation time 215142938051 ps
CPU time 340.42 seconds
Started Sep 04 10:23:56 AM UTC 24
Finished Sep 04 10:29:40 AM UTC 24
Peak memory 217580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271254197 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2271254197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.635596644
Short name T517
Test name
Test status
Simulation time 7862438495 ps
CPU time 28.32 seconds
Started Sep 04 10:23:53 AM UTC 24
Finished Sep 04 10:24:22 AM UTC 24
Peak memory 218008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=635596644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all_
with_rand_reset.635596644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.3635125005
Short name T512
Test name
Test status
Simulation time 7191034171 ps
CPU time 24.89 seconds
Started Sep 04 10:23:44 AM UTC 24
Finished Sep 04 10:24:10 AM UTC 24
Peak memory 208556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635125005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3635125005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/22.uart_tx_rx.439672699
Short name T551
Test name
Test status
Simulation time 58284267325 ps
CPU time 151.17 seconds
Started Sep 04 10:23:24 AM UTC 24
Finished Sep 04 10:25:58 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439672699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.439672699
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/22.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1078702753
Short name T1090
Test name
Test status
Simulation time 75722635884 ps
CPU time 43.53 seconds
Started Sep 04 10:47:09 AM UTC 24
Finished Sep 04 10:47:54 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078702753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1078702753
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/220.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1570761785
Short name T232
Test name
Test status
Simulation time 67308258287 ps
CPU time 111.73 seconds
Started Sep 04 10:47:11 AM UTC 24
Finished Sep 04 10:49:05 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570761785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1570761785
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/221.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/222.uart_fifo_reset.1267362597
Short name T1102
Test name
Test status
Simulation time 69526233608 ps
CPU time 58.94 seconds
Started Sep 04 10:47:12 AM UTC 24
Finished Sep 04 10:48:13 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267362597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1267362597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/222.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/223.uart_fifo_reset.895561340
Short name T1159
Test name
Test status
Simulation time 122260878888 ps
CPU time 181.64 seconds
Started Sep 04 10:47:13 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895561340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.895561340
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/223.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/224.uart_fifo_reset.595219123
Short name T1109
Test name
Test status
Simulation time 67839959449 ps
CPU time 70.81 seconds
Started Sep 04 10:47:15 AM UTC 24
Finished Sep 04 10:48:27 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595219123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.595219123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/224.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2513730305
Short name T250
Test name
Test status
Simulation time 20679651414 ps
CPU time 35.52 seconds
Started Sep 04 10:47:15 AM UTC 24
Finished Sep 04 10:47:51 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513730305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2513730305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/225.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/226.uart_fifo_reset.3158895958
Short name T1180
Test name
Test status
Simulation time 165670974527 ps
CPU time 360.36 seconds
Started Sep 04 10:47:16 AM UTC 24
Finished Sep 04 10:53:21 AM UTC 24
Peak memory 212304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158895958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3158895958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/226.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/227.uart_fifo_reset.1717215323
Short name T1092
Test name
Test status
Simulation time 111107849498 ps
CPU time 40.78 seconds
Started Sep 04 10:47:17 AM UTC 24
Finished Sep 04 10:47:59 AM UTC 24
Peak memory 208104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717215323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1717215323
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/227.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/228.uart_fifo_reset.4133849499
Short name T1105
Test name
Test status
Simulation time 110224673077 ps
CPU time 56.29 seconds
Started Sep 04 10:47:18 AM UTC 24
Finished Sep 04 10:48:16 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133849499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4133849499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/228.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2517203065
Short name T1096
Test name
Test status
Simulation time 16799141980 ps
CPU time 45.11 seconds
Started Sep 04 10:47:18 AM UTC 24
Finished Sep 04 10:48:04 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517203065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2517203065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/229.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_alert_test.669605358
Short name T518
Test name
Test status
Simulation time 14173055 ps
CPU time 0.83 seconds
Started Sep 04 10:24:23 AM UTC 24
Finished Sep 04 10:24:25 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669605358 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.669605358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_fifo_full.838913449
Short name T593
Test name
Test status
Simulation time 127096898322 ps
CPU time 254.57 seconds
Started Sep 04 10:24:01 AM UTC 24
Finished Sep 04 10:28:19 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838913449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.838913449
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.2892008469
Short name T159
Test name
Test status
Simulation time 164562054978 ps
CPU time 45.22 seconds
Started Sep 04 10:24:02 AM UTC 24
Finished Sep 04 10:24:49 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892008469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2892008469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_fifo_reset.3061221576
Short name T520
Test name
Test status
Simulation time 5557704950 ps
CPU time 24.81 seconds
Started Sep 04 10:24:04 AM UTC 24
Finished Sep 04 10:24:30 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061221576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3061221576
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_intr.271024463
Short name T555
Test name
Test status
Simulation time 106823527655 ps
CPU time 124.71 seconds
Started Sep 04 10:24:10 AM UTC 24
Finished Sep 04 10:26:17 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271024463 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.271024463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.51042827
Short name T637
Test name
Test status
Simulation time 68027899848 ps
CPU time 337.99 seconds
Started Sep 04 10:24:15 AM UTC 24
Finished Sep 04 10:29:57 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51042827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.51042827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_loopback.3938394425
Short name T526
Test name
Test status
Simulation time 6217900608 ps
CPU time 36.6 seconds
Started Sep 04 10:24:13 AM UTC 24
Finished Sep 04 10:24:52 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938394425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3938394425
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_noise_filter.1491013916
Short name T534
Test name
Test status
Simulation time 261772303284 ps
CPU time 60.02 seconds
Started Sep 04 10:24:10 AM UTC 24
Finished Sep 04 10:25:12 AM UTC 24
Peak memory 217560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491013916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1491013916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_perf.1286358524
Short name T975
Test name
Test status
Simulation time 18323563486 ps
CPU time 1172.66 seconds
Started Sep 04 10:24:14 AM UTC 24
Finished Sep 04 10:43:59 AM UTC 24
Peak memory 212472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286358524 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1286358524
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_rx_oversample.2534681990
Short name T521
Test name
Test status
Simulation time 6949953086 ps
CPU time 21.06 seconds
Started Sep 04 10:24:08 AM UTC 24
Finished Sep 04 10:24:30 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534681990 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2534681990
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.2564679100
Short name T150
Test name
Test status
Simulation time 52433724884 ps
CPU time 19.39 seconds
Started Sep 04 10:24:11 AM UTC 24
Finished Sep 04 10:24:32 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564679100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2564679100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.839975520
Short name T311
Test name
Test status
Simulation time 44993029013 ps
CPU time 17.39 seconds
Started Sep 04 10:24:11 AM UTC 24
Finished Sep 04 10:24:30 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839975520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.839975520
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_smoke.1823782859
Short name T508
Test name
Test status
Simulation time 294555315 ps
CPU time 2.29 seconds
Started Sep 04 10:24:00 AM UTC 24
Finished Sep 04 10:24:03 AM UTC 24
Peak memory 206864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823782859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1823782859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_stress_all.422937281
Short name T605
Test name
Test status
Simulation time 140989970319 ps
CPU time 271.78 seconds
Started Sep 04 10:24:18 AM UTC 24
Finished Sep 04 10:28:53 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422937281 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.422937281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.1159988481
Short name T91
Test name
Test status
Simulation time 1697725589 ps
CPU time 19.25 seconds
Started Sep 04 10:24:16 AM UTC 24
Finished Sep 04 10:24:36 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1159988481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all
_with_rand_reset.1159988481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.3314268595
Short name T516
Test name
Test status
Simulation time 1038985231 ps
CPU time 4.8 seconds
Started Sep 04 10:24:11 AM UTC 24
Finished Sep 04 10:24:17 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314268595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3314268595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/23.uart_tx_rx.1698225954
Short name T511
Test name
Test status
Simulation time 10318187965 ps
CPU time 9.12 seconds
Started Sep 04 10:24:00 AM UTC 24
Finished Sep 04 10:24:10 AM UTC 24
Peak memory 207608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698225954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1698225954
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/23.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3368246171
Short name T236
Test name
Test status
Simulation time 100176922828 ps
CPU time 103.72 seconds
Started Sep 04 10:47:18 AM UTC 24
Finished Sep 04 10:49:04 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368246171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3368246171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/230.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/231.uart_fifo_reset.4036483724
Short name T210
Test name
Test status
Simulation time 6184449196 ps
CPU time 7.63 seconds
Started Sep 04 10:47:19 AM UTC 24
Finished Sep 04 10:47:28 AM UTC 24
Peak memory 207348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036483724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.4036483724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/231.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/232.uart_fifo_reset.21025806
Short name T241
Test name
Test status
Simulation time 149081346131 ps
CPU time 48.87 seconds
Started Sep 04 10:47:19 AM UTC 24
Finished Sep 04 10:48:09 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21025806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.21025806
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/232.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/233.uart_fifo_reset.1095403081
Short name T1149
Test name
Test status
Simulation time 72647358463 ps
CPU time 142.76 seconds
Started Sep 04 10:47:22 AM UTC 24
Finished Sep 04 10:49:47 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095403081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1095403081
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/233.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/234.uart_fifo_reset.2045240399
Short name T1091
Test name
Test status
Simulation time 68061393339 ps
CPU time 31.78 seconds
Started Sep 04 10:47:22 AM UTC 24
Finished Sep 04 10:47:55 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045240399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2045240399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/234.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/235.uart_fifo_reset.2389553064
Short name T1086
Test name
Test status
Simulation time 19459268929 ps
CPU time 20.14 seconds
Started Sep 04 10:47:22 AM UTC 24
Finished Sep 04 10:47:44 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389553064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2389553064
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/235.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/236.uart_fifo_reset.1272007386
Short name T1097
Test name
Test status
Simulation time 94810313420 ps
CPU time 37.96 seconds
Started Sep 04 10:47:25 AM UTC 24
Finished Sep 04 10:48:05 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272007386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1272007386
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/236.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/237.uart_fifo_reset.3605336139
Short name T1156
Test name
Test status
Simulation time 55282450411 ps
CPU time 152.11 seconds
Started Sep 04 10:47:27 AM UTC 24
Finished Sep 04 10:50:02 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605336139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3605336139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/237.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/239.uart_fifo_reset.3259231673
Short name T1113
Test name
Test status
Simulation time 78789863275 ps
CPU time 62.45 seconds
Started Sep 04 10:47:29 AM UTC 24
Finished Sep 04 10:48:33 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259231673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3259231673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/239.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_alert_test.658591486
Short name T527
Test name
Test status
Simulation time 14052497 ps
CPU time 0.83 seconds
Started Sep 04 10:24:54 AM UTC 24
Finished Sep 04 10:24:56 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658591486 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.658591486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_fifo_full.2474132149
Short name T362
Test name
Test status
Simulation time 19327385545 ps
CPU time 75.14 seconds
Started Sep 04 10:24:31 AM UTC 24
Finished Sep 04 10:25:48 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474132149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2474132149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.1576525245
Short name T579
Test name
Test status
Simulation time 183306360389 ps
CPU time 179.3 seconds
Started Sep 04 10:24:31 AM UTC 24
Finished Sep 04 10:27:33 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576525245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1576525245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_fifo_reset.3082312135
Short name T561
Test name
Test status
Simulation time 84099421175 ps
CPU time 111.01 seconds
Started Sep 04 10:24:31 AM UTC 24
Finished Sep 04 10:26:25 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082312135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3082312135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_intr.877371300
Short name T525
Test name
Test status
Simulation time 15042714132 ps
CPU time 16 seconds
Started Sep 04 10:24:33 AM UTC 24
Finished Sep 04 10:24:51 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877371300 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.877371300
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.98687399
Short name T652
Test name
Test status
Simulation time 51176800273 ps
CPU time 321.06 seconds
Started Sep 04 10:24:49 AM UTC 24
Finished Sep 04 10:30:14 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98687399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.98687399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_loopback.2624220422
Short name T530
Test name
Test status
Simulation time 11321993929 ps
CPU time 17.93 seconds
Started Sep 04 10:24:41 AM UTC 24
Finished Sep 04 10:25:00 AM UTC 24
Peak memory 207628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624220422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2624220422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_noise_filter.2147809163
Short name T543
Test name
Test status
Simulation time 20689786364 ps
CPU time 56.99 seconds
Started Sep 04 10:24:36 AM UTC 24
Finished Sep 04 10:25:34 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147809163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2147809163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_perf.2014532373
Short name T640
Test name
Test status
Simulation time 11766713556 ps
CPU time 314.81 seconds
Started Sep 04 10:24:43 AM UTC 24
Finished Sep 04 10:30:02 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014532373 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2014532373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_rx_oversample.2463494471
Short name T522
Test name
Test status
Simulation time 2322772971 ps
CPU time 2.74 seconds
Started Sep 04 10:24:32 AM UTC 24
Finished Sep 04 10:24:36 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463494471 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2463494471
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.223011316
Short name T536
Test name
Test status
Simulation time 89731083599 ps
CPU time 36.7 seconds
Started Sep 04 10:24:37 AM UTC 24
Finished Sep 04 10:25:15 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223011316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.223011316
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.1228125941
Short name T523
Test name
Test status
Simulation time 4408222603 ps
CPU time 2.21 seconds
Started Sep 04 10:24:37 AM UTC 24
Finished Sep 04 10:24:40 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228125941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1228125941
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_smoke.671378855
Short name T519
Test name
Test status
Simulation time 497016219 ps
CPU time 2.07 seconds
Started Sep 04 10:24:25 AM UTC 24
Finished Sep 04 10:24:28 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671378855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.uart_smoke.671378855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.4132788097
Short name T92
Test name
Test status
Simulation time 9965350568 ps
CPU time 37.1 seconds
Started Sep 04 10:24:51 AM UTC 24
Finished Sep 04 10:25:30 AM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4132788097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all
_with_rand_reset.4132788097
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.4229684863
Short name T531
Test name
Test status
Simulation time 7215596353 ps
CPU time 20.18 seconds
Started Sep 04 10:24:40 AM UTC 24
Finished Sep 04 10:25:01 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229684863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4229684863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/24.uart_tx_rx.1370718198
Short name T532
Test name
Test status
Simulation time 22525287624 ps
CPU time 36.4 seconds
Started Sep 04 10:24:29 AM UTC 24
Finished Sep 04 10:25:07 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370718198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1370718198
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/24.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/241.uart_fifo_reset.773090945
Short name T1104
Test name
Test status
Simulation time 59838630576 ps
CPU time 39.64 seconds
Started Sep 04 10:47:32 AM UTC 24
Finished Sep 04 10:48:13 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773090945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.773090945
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/241.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1132423390
Short name T1163
Test name
Test status
Simulation time 137105871854 ps
CPU time 186.4 seconds
Started Sep 04 10:47:34 AM UTC 24
Finished Sep 04 10:50:43 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132423390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1132423390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/242.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/243.uart_fifo_reset.3775801160
Short name T1094
Test name
Test status
Simulation time 135054157301 ps
CPU time 19.04 seconds
Started Sep 04 10:47:39 AM UTC 24
Finished Sep 04 10:47:59 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775801160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3775801160
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/243.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/244.uart_fifo_reset.4081284420
Short name T1108
Test name
Test status
Simulation time 17296125996 ps
CPU time 34.87 seconds
Started Sep 04 10:47:44 AM UTC 24
Finished Sep 04 10:48:20 AM UTC 24
Peak memory 208440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081284420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4081284420
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/244.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/245.uart_fifo_reset.1631597164
Short name T1126
Test name
Test status
Simulation time 135096308782 ps
CPU time 74.26 seconds
Started Sep 04 10:47:44 AM UTC 24
Finished Sep 04 10:49:00 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631597164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1631597164
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/245.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3100055412
Short name T1118
Test name
Test status
Simulation time 158399530053 ps
CPU time 47.58 seconds
Started Sep 04 10:47:46 AM UTC 24
Finished Sep 04 10:48:35 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100055412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3100055412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/247.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/248.uart_fifo_reset.1327279415
Short name T1121
Test name
Test status
Simulation time 13259127602 ps
CPU time 50.02 seconds
Started Sep 04 10:47:47 AM UTC 24
Finished Sep 04 10:48:39 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327279415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1327279415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/248.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2672864963
Short name T1162
Test name
Test status
Simulation time 118647335273 ps
CPU time 162.04 seconds
Started Sep 04 10:47:49 AM UTC 24
Finished Sep 04 10:50:34 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672864963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2672864963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/249.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_alert_test.3459570066
Short name T540
Test name
Test status
Simulation time 51396187 ps
CPU time 0.81 seconds
Started Sep 04 10:25:27 AM UTC 24
Finished Sep 04 10:25:29 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459570066 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3459570066
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_fifo_full.2610874948
Short name T405
Test name
Test status
Simulation time 37147993188 ps
CPU time 98.54 seconds
Started Sep 04 10:24:59 AM UTC 24
Finished Sep 04 10:26:39 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610874948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2610874948
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.727520312
Short name T542
Test name
Test status
Simulation time 64465700630 ps
CPU time 30.82 seconds
Started Sep 04 10:25:01 AM UTC 24
Finished Sep 04 10:25:33 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727520312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.727520312
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_fifo_reset.339596738
Short name T544
Test name
Test status
Simulation time 10483424221 ps
CPU time 31.79 seconds
Started Sep 04 10:25:01 AM UTC 24
Finished Sep 04 10:25:34 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339596738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.339596738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_intr.3549456549
Short name T614
Test name
Test status
Simulation time 219686144239 ps
CPU time 241.11 seconds
Started Sep 04 10:25:08 AM UTC 24
Finished Sep 04 10:29:12 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549456549 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3549456549
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.3785190755
Short name T611
Test name
Test status
Simulation time 85223141167 ps
CPU time 225.06 seconds
Started Sep 04 10:25:15 AM UTC 24
Finished Sep 04 10:29:04 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785190755 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3785190755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_loopback.875611729
Short name T538
Test name
Test status
Simulation time 1588366670 ps
CPU time 6.5 seconds
Started Sep 04 10:25:13 AM UTC 24
Finished Sep 04 10:25:21 AM UTC 24
Peak memory 207004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875611729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_loopback.875611729
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_noise_filter.2034868227
Short name T557
Test name
Test status
Simulation time 140120642407 ps
CPU time 68.66 seconds
Started Sep 04 10:25:08 AM UTC 24
Finished Sep 04 10:26:18 AM UTC 24
Peak memory 209024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034868227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2034868227
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_perf.1345845361
Short name T588
Test name
Test status
Simulation time 25657020914 ps
CPU time 171.78 seconds
Started Sep 04 10:25:13 AM UTC 24
Finished Sep 04 10:28:08 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345845361 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1345845361
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_rx_oversample.3055825560
Short name T533
Test name
Test status
Simulation time 1925797822 ps
CPU time 4.05 seconds
Started Sep 04 10:25:02 AM UTC 24
Finished Sep 04 10:25:07 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055825560 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3055825560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.3191087651
Short name T386
Test name
Test status
Simulation time 144934199903 ps
CPU time 74.64 seconds
Started Sep 04 10:25:13 AM UTC 24
Finished Sep 04 10:26:30 AM UTC 24
Peak memory 208452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191087651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3191087651
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.2601869202
Short name T549
Test name
Test status
Simulation time 48962683620 ps
CPU time 45.02 seconds
Started Sep 04 10:25:08 AM UTC 24
Finished Sep 04 10:25:55 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601869202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2601869202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_smoke.420058190
Short name T529
Test name
Test status
Simulation time 503140392 ps
CPU time 1.54 seconds
Started Sep 04 10:24:57 AM UTC 24
Finished Sep 04 10:25:00 AM UTC 24
Peak memory 207824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420058190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.uart_smoke.420058190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_stress_all.341416909
Short name T1165
Test name
Test status
Simulation time 292252655201 ps
CPU time 1547.8 seconds
Started Sep 04 10:25:22 AM UTC 24
Finished Sep 04 10:51:26 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341416909 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.341416909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.3024375598
Short name T556
Test name
Test status
Simulation time 18572305865 ps
CPU time 58.72 seconds
Started Sep 04 10:25:17 AM UTC 24
Finished Sep 04 10:26:18 AM UTC 24
Peak memory 225232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3024375598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all
_with_rand_reset.3024375598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.2025795719
Short name T537
Test name
Test status
Simulation time 3378681310 ps
CPU time 1.95 seconds
Started Sep 04 10:25:13 AM UTC 24
Finished Sep 04 10:25:16 AM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025795719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2025795719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/25.uart_tx_rx.3186120285
Short name T535
Test name
Test status
Simulation time 8465663383 ps
CPU time 13.65 seconds
Started Sep 04 10:24:57 AM UTC 24
Finished Sep 04 10:25:12 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186120285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3186120285
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/25.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/250.uart_fifo_reset.3293033479
Short name T1115
Test name
Test status
Simulation time 20436650826 ps
CPU time 39.39 seconds
Started Sep 04 10:47:53 AM UTC 24
Finished Sep 04 10:48:33 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293033479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3293033479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/250.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/251.uart_fifo_reset.3354126223
Short name T1103
Test name
Test status
Simulation time 98761084263 ps
CPU time 19.22 seconds
Started Sep 04 10:47:53 AM UTC 24
Finished Sep 04 10:48:13 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354126223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3354126223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/251.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1618742140
Short name T1116
Test name
Test status
Simulation time 19987685433 ps
CPU time 37.61 seconds
Started Sep 04 10:47:55 AM UTC 24
Finished Sep 04 10:48:34 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618742140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1618742140
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/252.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/253.uart_fifo_reset.1340861940
Short name T1098
Test name
Test status
Simulation time 24936258315 ps
CPU time 9.53 seconds
Started Sep 04 10:47:56 AM UTC 24
Finished Sep 04 10:48:06 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340861940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1340861940
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/253.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/254.uart_fifo_reset.3331265993
Short name T1161
Test name
Test status
Simulation time 90418329655 ps
CPU time 148.91 seconds
Started Sep 04 10:48:00 AM UTC 24
Finished Sep 04 10:50:31 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331265993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3331265993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/254.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/256.uart_fifo_reset.3733850484
Short name T1154
Test name
Test status
Simulation time 58183625767 ps
CPU time 117.86 seconds
Started Sep 04 10:48:00 AM UTC 24
Finished Sep 04 10:50:00 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733850484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3733850484
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/256.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2904775346
Short name T1123
Test name
Test status
Simulation time 168073140630 ps
CPU time 42.92 seconds
Started Sep 04 10:48:02 AM UTC 24
Finished Sep 04 10:48:46 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904775346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2904775346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/257.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2377761704
Short name T1131
Test name
Test status
Simulation time 33420229568 ps
CPU time 58.3 seconds
Started Sep 04 10:48:05 AM UTC 24
Finished Sep 04 10:49:05 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377761704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2377761704
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/258.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/259.uart_fifo_reset.270897670
Short name T1114
Test name
Test status
Simulation time 87301664880 ps
CPU time 27.08 seconds
Started Sep 04 10:48:05 AM UTC 24
Finished Sep 04 10:48:33 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270897670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.270897670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/259.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_alert_test.3395326041
Short name T554
Test name
Test status
Simulation time 13166985 ps
CPU time 0.82 seconds
Started Sep 04 10:26:10 AM UTC 24
Finished Sep 04 10:26:12 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395326041 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3395326041
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_fifo_full.1391626663
Short name T548
Test name
Test status
Simulation time 25250675351 ps
CPU time 19.59 seconds
Started Sep 04 10:25:34 AM UTC 24
Finished Sep 04 10:25:55 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391626663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1391626663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.1050459260
Short name T570
Test name
Test status
Simulation time 168480227790 ps
CPU time 77.94 seconds
Started Sep 04 10:25:34 AM UTC 24
Finished Sep 04 10:26:54 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050459260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1050459260
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_intr.791944512
Short name T639
Test name
Test status
Simulation time 193830764239 ps
CPU time 260.96 seconds
Started Sep 04 10:25:35 AM UTC 24
Finished Sep 04 10:30:00 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791944512 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.791944512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.4217408503
Short name T603
Test name
Test status
Simulation time 228423617229 ps
CPU time 170.35 seconds
Started Sep 04 10:25:57 AM UTC 24
Finished Sep 04 10:28:50 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217408503 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4217408503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_loopback.1113717722
Short name T552
Test name
Test status
Simulation time 10733979322 ps
CPU time 7.08 seconds
Started Sep 04 10:25:56 AM UTC 24
Finished Sep 04 10:26:04 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113717722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1113717722
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_noise_filter.2167718223
Short name T546
Test name
Test status
Simulation time 893142545 ps
CPU time 1.78 seconds
Started Sep 04 10:25:42 AM UTC 24
Finished Sep 04 10:25:45 AM UTC 24
Peak memory 204320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167718223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2167718223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_perf.2069574112
Short name T1058
Test name
Test status
Simulation time 23092445437 ps
CPU time 1249.45 seconds
Started Sep 04 10:25:56 AM UTC 24
Finished Sep 04 10:46:58 AM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069574112 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2069574112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_rx_oversample.131892346
Short name T547
Test name
Test status
Simulation time 1796884530 ps
CPU time 13.9 seconds
Started Sep 04 10:25:35 AM UTC 24
Finished Sep 04 10:25:50 AM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131892346 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.131892346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.787630377
Short name T562
Test name
Test status
Simulation time 19902752862 ps
CPU time 39.52 seconds
Started Sep 04 10:25:49 AM UTC 24
Finished Sep 04 10:26:30 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787630377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.787630377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.2934230854
Short name T558
Test name
Test status
Simulation time 38122924395 ps
CPU time 34.36 seconds
Started Sep 04 10:25:46 AM UTC 24
Finished Sep 04 10:26:22 AM UTC 24
Peak memory 205024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934230854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2934230854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_smoke.2713871056
Short name T541
Test name
Test status
Simulation time 289411892 ps
CPU time 2.21 seconds
Started Sep 04 10:25:30 AM UTC 24
Finished Sep 04 10:25:33 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713871056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2713871056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.428968096
Short name T572
Test name
Test status
Simulation time 76106107105 ps
CPU time 66.46 seconds
Started Sep 04 10:25:59 AM UTC 24
Finished Sep 04 10:27:07 AM UTC 24
Peak memory 225440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=428968096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all_
with_rand_reset.428968096
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.216748633
Short name T550
Test name
Test status
Simulation time 1015563937 ps
CPU time 4.75 seconds
Started Sep 04 10:25:50 AM UTC 24
Finished Sep 04 10:25:56 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216748633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.216748633
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/26.uart_tx_rx.314841341
Short name T571
Test name
Test status
Simulation time 29648856267 ps
CPU time 91.49 seconds
Started Sep 04 10:25:31 AM UTC 24
Finished Sep 04 10:27:04 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314841341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.314841341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/26.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/260.uart_fifo_reset.1109784092
Short name T1139
Test name
Test status
Simulation time 42564679332 ps
CPU time 66.35 seconds
Started Sep 04 10:48:07 AM UTC 24
Finished Sep 04 10:49:15 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109784092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1109784092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/260.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1724114988
Short name T1120
Test name
Test status
Simulation time 15222249504 ps
CPU time 26.85 seconds
Started Sep 04 10:48:10 AM UTC 24
Finished Sep 04 10:48:38 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724114988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1724114988
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/261.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/263.uart_fifo_reset.472896332
Short name T1110
Test name
Test status
Simulation time 36299401992 ps
CPU time 14.09 seconds
Started Sep 04 10:48:12 AM UTC 24
Finished Sep 04 10:48:28 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472896332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.472896332
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/263.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/264.uart_fifo_reset.2007755221
Short name T200
Test name
Test status
Simulation time 143950212765 ps
CPU time 82.82 seconds
Started Sep 04 10:48:13 AM UTC 24
Finished Sep 04 10:49:37 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007755221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2007755221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/264.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/265.uart_fifo_reset.1879052543
Short name T1171
Test name
Test status
Simulation time 96607339268 ps
CPU time 226.67 seconds
Started Sep 04 10:48:14 AM UTC 24
Finished Sep 04 10:52:04 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879052543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1879052543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/265.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/266.uart_fifo_reset.150860934
Short name T1144
Test name
Test status
Simulation time 92419824769 ps
CPU time 78.05 seconds
Started Sep 04 10:48:14 AM UTC 24
Finished Sep 04 10:49:33 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150860934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.150860934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/266.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/267.uart_fifo_reset.3004049314
Short name T1122
Test name
Test status
Simulation time 8311522066 ps
CPU time 25.83 seconds
Started Sep 04 10:48:14 AM UTC 24
Finished Sep 04 10:48:41 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004049314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3004049314
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/267.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/268.uart_fifo_reset.4189753451
Short name T1127
Test name
Test status
Simulation time 55152052455 ps
CPU time 44.5 seconds
Started Sep 04 10:48:15 AM UTC 24
Finished Sep 04 10:49:01 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189753451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.4189753451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/268.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/269.uart_fifo_reset.1200591939
Short name T1117
Test name
Test status
Simulation time 15093192663 ps
CPU time 16.28 seconds
Started Sep 04 10:48:17 AM UTC 24
Finished Sep 04 10:48:34 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200591939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1200591939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/269.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_alert_test.670161895
Short name T568
Test name
Test status
Simulation time 14396127 ps
CPU time 0.83 seconds
Started Sep 04 10:26:47 AM UTC 24
Finished Sep 04 10:26:49 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670161895 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.670161895
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_fifo_full.314691268
Short name T581
Test name
Test status
Simulation time 95637054623 ps
CPU time 74.46 seconds
Started Sep 04 10:26:19 AM UTC 24
Finished Sep 04 10:27:35 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314691268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.314691268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.1603124085
Short name T151
Test name
Test status
Simulation time 78869355982 ps
CPU time 148.77 seconds
Started Sep 04 10:26:19 AM UTC 24
Finished Sep 04 10:28:51 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603124085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1603124085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_fifo_reset.4284281963
Short name T156
Test name
Test status
Simulation time 114300612484 ps
CPU time 119.68 seconds
Started Sep 04 10:26:22 AM UTC 24
Finished Sep 04 10:28:24 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284281963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4284281963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_intr.3021004149
Short name T575
Test name
Test status
Simulation time 38228295555 ps
CPU time 55.33 seconds
Started Sep 04 10:26:25 AM UTC 24
Finished Sep 04 10:27:21 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021004149 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3021004149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.117311514
Short name T616
Test name
Test status
Simulation time 61664488499 ps
CPU time 151.12 seconds
Started Sep 04 10:26:40 AM UTC 24
Finished Sep 04 10:29:14 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117311514 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.117311514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_loopback.1619795290
Short name T565
Test name
Test status
Simulation time 9736870351 ps
CPU time 13.13 seconds
Started Sep 04 10:26:32 AM UTC 24
Finished Sep 04 10:26:46 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619795290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1619795290
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_noise_filter.2172014618
Short name T391
Test name
Test status
Simulation time 100064012328 ps
CPU time 59.91 seconds
Started Sep 04 10:26:25 AM UTC 24
Finished Sep 04 10:27:26 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172014618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2172014618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_perf.538276651
Short name T831
Test name
Test status
Simulation time 18970955030 ps
CPU time 657.06 seconds
Started Sep 04 10:26:37 AM UTC 24
Finished Sep 04 10:37:42 AM UTC 24
Peak memory 212144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538276651 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.538276651
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_rx_oversample.3410604576
Short name T564
Test name
Test status
Simulation time 3256178693 ps
CPU time 18.1 seconds
Started Sep 04 10:26:24 AM UTC 24
Finished Sep 04 10:26:44 AM UTC 24
Peak memory 207480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410604576 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3410604576
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3420048384
Short name T749
Test name
Test status
Simulation time 188293846063 ps
CPU time 465.87 seconds
Started Sep 04 10:26:31 AM UTC 24
Finished Sep 04 10:34:22 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420048384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3420048384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.2413053080
Short name T566
Test name
Test status
Simulation time 6293734964 ps
CPU time 20.7 seconds
Started Sep 04 10:26:26 AM UTC 24
Finished Sep 04 10:26:48 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413053080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2413053080
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_smoke.498357725
Short name T560
Test name
Test status
Simulation time 5550677031 ps
CPU time 9.5 seconds
Started Sep 04 10:26:13 AM UTC 24
Finished Sep 04 10:26:24 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498357725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.uart_smoke.498357725
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_stress_all.265912456
Short name T586
Test name
Test status
Simulation time 50693756498 ps
CPU time 74.19 seconds
Started Sep 04 10:26:45 AM UTC 24
Finished Sep 04 10:28:01 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265912456 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.265912456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.4286525489
Short name T573
Test name
Test status
Simulation time 3403182470 ps
CPU time 25.36 seconds
Started Sep 04 10:26:42 AM UTC 24
Finished Sep 04 10:27:09 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4286525489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all
_with_rand_reset.4286525489
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.2396770850
Short name T370
Test name
Test status
Simulation time 11550893642 ps
CPU time 4.28 seconds
Started Sep 04 10:26:31 AM UTC 24
Finished Sep 04 10:26:36 AM UTC 24
Peak memory 208524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396770850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2396770850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/27.uart_tx_rx.328225295
Short name T559
Test name
Test status
Simulation time 805662749 ps
CPU time 4.18 seconds
Started Sep 04 10:26:18 AM UTC 24
Finished Sep 04 10:26:23 AM UTC 24
Peak memory 207216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328225295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.328225295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/27.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/270.uart_fifo_reset.2986801603
Short name T1148
Test name
Test status
Simulation time 160944774345 ps
CPU time 85.19 seconds
Started Sep 04 10:48:18 AM UTC 24
Finished Sep 04 10:49:45 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986801603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2986801603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/270.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/271.uart_fifo_reset.2285436245
Short name T1166
Test name
Test status
Simulation time 148708146572 ps
CPU time 185.93 seconds
Started Sep 04 10:48:19 AM UTC 24
Finished Sep 04 10:51:28 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285436245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2285436245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/271.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/272.uart_fifo_reset.3638009803
Short name T1135
Test name
Test status
Simulation time 137775215696 ps
CPU time 46 seconds
Started Sep 04 10:48:21 AM UTC 24
Finished Sep 04 10:49:09 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638009803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3638009803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/272.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/273.uart_fifo_reset.3199541742
Short name T1133
Test name
Test status
Simulation time 25501483758 ps
CPU time 35.73 seconds
Started Sep 04 10:48:28 AM UTC 24
Finished Sep 04 10:49:05 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199541742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3199541742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/273.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/274.uart_fifo_reset.775263344
Short name T1136
Test name
Test status
Simulation time 164897089629 ps
CPU time 42.93 seconds
Started Sep 04 10:48:28 AM UTC 24
Finished Sep 04 10:49:13 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775263344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.775263344
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/274.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2767621586
Short name T1141
Test name
Test status
Simulation time 21207866544 ps
CPU time 48.34 seconds
Started Sep 04 10:48:29 AM UTC 24
Finished Sep 04 10:49:19 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767621586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2767621586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/275.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2962293470
Short name T1155
Test name
Test status
Simulation time 47646043352 ps
CPU time 85.59 seconds
Started Sep 04 10:48:34 AM UTC 24
Finished Sep 04 10:50:01 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962293470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2962293470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/276.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2257627400
Short name T1150
Test name
Test status
Simulation time 33393419162 ps
CPU time 72.58 seconds
Started Sep 04 10:48:35 AM UTC 24
Finished Sep 04 10:49:49 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257627400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2257627400
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/279.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_alert_test.2199980704
Short name T580
Test name
Test status
Simulation time 43186180 ps
CPU time 0.83 seconds
Started Sep 04 10:27:32 AM UTC 24
Finished Sep 04 10:27:34 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199980704 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2199980704
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_fifo_full.1387831029
Short name T403
Test name
Test status
Simulation time 87335264661 ps
CPU time 274.59 seconds
Started Sep 04 10:26:51 AM UTC 24
Finished Sep 04 10:31:29 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387831029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1387831029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.2818746803
Short name T600
Test name
Test status
Simulation time 103276432113 ps
CPU time 113.67 seconds
Started Sep 04 10:26:52 AM UTC 24
Finished Sep 04 10:28:47 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818746803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2818746803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_fifo_reset.2607569491
Short name T194
Test name
Test status
Simulation time 49171684083 ps
CPU time 211.49 seconds
Started Sep 04 10:26:54 AM UTC 24
Finished Sep 04 10:30:29 AM UTC 24
Peak memory 208512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607569491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2607569491
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_intr.65320855
Short name T578
Test name
Test status
Simulation time 8911348027 ps
CPU time 30.95 seconds
Started Sep 04 10:26:59 AM UTC 24
Finished Sep 04 10:27:31 AM UTC 24
Peak memory 207980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65320855 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.65320855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.1081171883
Short name T674
Test name
Test status
Simulation time 104603048848 ps
CPU time 228.67 seconds
Started Sep 04 10:27:25 AM UTC 24
Finished Sep 04 10:31:16 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081171883 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1081171883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_loopback.3432134396
Short name T583
Test name
Test status
Simulation time 6435847781 ps
CPU time 13.68 seconds
Started Sep 04 10:27:21 AM UTC 24
Finished Sep 04 10:27:36 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432134396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3432134396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_noise_filter.1944879818
Short name T601
Test name
Test status
Simulation time 153173428926 ps
CPU time 100.88 seconds
Started Sep 04 10:27:05 AM UTC 24
Finished Sep 04 10:28:48 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944879818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1944879818
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_perf.2854357267
Short name T897
Test name
Test status
Simulation time 11843225056 ps
CPU time 784.12 seconds
Started Sep 04 10:27:22 AM UTC 24
Finished Sep 04 10:40:36 AM UTC 24
Peak memory 212240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854357267 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2854357267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_rx_oversample.1681742366
Short name T576
Test name
Test status
Simulation time 5996971048 ps
CPU time 27.41 seconds
Started Sep 04 10:26:55 AM UTC 24
Finished Sep 04 10:27:24 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681742366 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1681742366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.2573807099
Short name T609
Test name
Test status
Simulation time 70884887014 ps
CPU time 109.71 seconds
Started Sep 04 10:27:10 AM UTC 24
Finished Sep 04 10:29:02 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573807099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2573807099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.2564868551
Short name T574
Test name
Test status
Simulation time 2401162453 ps
CPU time 8.94 seconds
Started Sep 04 10:27:08 AM UTC 24
Finished Sep 04 10:27:18 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564868551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2564868551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_smoke.114130273
Short name T569
Test name
Test status
Simulation time 299394072 ps
CPU time 1.83 seconds
Started Sep 04 10:26:48 AM UTC 24
Finished Sep 04 10:26:51 AM UTC 24
Peak memory 206660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114130273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.uart_smoke.114130273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_stress_all.3564029455
Short name T937
Test name
Test status
Simulation time 440351319303 ps
CPU time 890.32 seconds
Started Sep 04 10:27:27 AM UTC 24
Finished Sep 04 10:42:27 AM UTC 24
Peak memory 212176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564029455 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3564029455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.1020258211
Short name T599
Test name
Test status
Simulation time 15516476425 ps
CPU time 72 seconds
Started Sep 04 10:27:27 AM UTC 24
Finished Sep 04 10:28:40 AM UTC 24
Peak memory 221888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1020258211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all
_with_rand_reset.1020258211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.4209266835
Short name T577
Test name
Test status
Simulation time 1081295016 ps
CPU time 5.45 seconds
Started Sep 04 10:27:19 AM UTC 24
Finished Sep 04 10:27:26 AM UTC 24
Peak memory 208068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209266835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4209266835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/28.uart_tx_rx.1973973242
Short name T387
Test name
Test status
Simulation time 32617109374 ps
CPU time 103.74 seconds
Started Sep 04 10:26:49 AM UTC 24
Finished Sep 04 10:28:35 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973973242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1973973242
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/28.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/280.uart_fifo_reset.75722090
Short name T1177
Test name
Test status
Simulation time 83550544381 ps
CPU time 257.34 seconds
Started Sep 04 10:48:35 AM UTC 24
Finished Sep 04 10:52:56 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75722090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.75722090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/280.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/281.uart_fifo_reset.2036996245
Short name T1125
Test name
Test status
Simulation time 11841831229 ps
CPU time 22.39 seconds
Started Sep 04 10:48:35 AM UTC 24
Finished Sep 04 10:48:58 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036996245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2036996245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/281.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/282.uart_fifo_reset.3250709129
Short name T1130
Test name
Test status
Simulation time 284073775485 ps
CPU time 26.74 seconds
Started Sep 04 10:48:35 AM UTC 24
Finished Sep 04 10:49:03 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250709129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3250709129
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/282.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3551547927
Short name T1134
Test name
Test status
Simulation time 41151116363 ps
CPU time 29.72 seconds
Started Sep 04 10:48:36 AM UTC 24
Finished Sep 04 10:49:07 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551547927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3551547927
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/283.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/284.uart_fifo_reset.4093972055
Short name T1179
Test name
Test status
Simulation time 156684657640 ps
CPU time 269.69 seconds
Started Sep 04 10:48:37 AM UTC 24
Finished Sep 04 10:53:10 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093972055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4093972055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/284.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3314387466
Short name T1138
Test name
Test status
Simulation time 72027902384 ps
CPU time 35.26 seconds
Started Sep 04 10:48:38 AM UTC 24
Finished Sep 04 10:49:15 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314387466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3314387466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/285.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/286.uart_fifo_reset.427301183
Short name T1168
Test name
Test status
Simulation time 119268520652 ps
CPU time 181.61 seconds
Started Sep 04 10:48:39 AM UTC 24
Finished Sep 04 10:51:43 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427301183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.427301183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/286.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/287.uart_fifo_reset.2430121120
Short name T1151
Test name
Test status
Simulation time 139025603867 ps
CPU time 69.34 seconds
Started Sep 04 10:48:40 AM UTC 24
Finished Sep 04 10:49:51 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430121120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2430121120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/287.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/288.uart_fifo_reset.2555697264
Short name T1170
Test name
Test status
Simulation time 121190301566 ps
CPU time 189.17 seconds
Started Sep 04 10:48:41 AM UTC 24
Finished Sep 04 10:51:53 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555697264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2555697264
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/288.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/289.uart_fifo_reset.768537276
Short name T1145
Test name
Test status
Simulation time 98491010844 ps
CPU time 45.44 seconds
Started Sep 04 10:48:47 AM UTC 24
Finished Sep 04 10:49:34 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768537276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.768537276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/289.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_alert_test.219958516
Short name T594
Test name
Test status
Simulation time 22575836 ps
CPU time 0.82 seconds
Started Sep 04 10:28:19 AM UTC 24
Finished Sep 04 10:28:21 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219958516 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.219958516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_fifo_full.391839330
Short name T377
Test name
Test status
Simulation time 48235974652 ps
CPU time 88.75 seconds
Started Sep 04 10:27:36 AM UTC 24
Finished Sep 04 10:29:07 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391839330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.391839330
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.3004056466
Short name T621
Test name
Test status
Simulation time 31982843469 ps
CPU time 111.4 seconds
Started Sep 04 10:27:37 AM UTC 24
Finished Sep 04 10:29:31 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004056466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3004056466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_fifo_reset.1443627513
Short name T185
Test name
Test status
Simulation time 4625151372 ps
CPU time 10.05 seconds
Started Sep 04 10:27:37 AM UTC 24
Finished Sep 04 10:27:48 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443627513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1443627513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_intr.3230647666
Short name T789
Test name
Test status
Simulation time 240213242376 ps
CPU time 493.08 seconds
Started Sep 04 10:27:51 AM UTC 24
Finished Sep 04 10:36:10 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230647666 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3230647666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.1256505881
Short name T747
Test name
Test status
Simulation time 152339115168 ps
CPU time 357.68 seconds
Started Sep 04 10:28:16 AM UTC 24
Finished Sep 04 10:34:18 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256505881 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1256505881
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_loopback.2180170478
Short name T590
Test name
Test status
Simulation time 3792859869 ps
CPU time 5.35 seconds
Started Sep 04 10:28:09 AM UTC 24
Finished Sep 04 10:28:15 AM UTC 24
Peak memory 207752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180170478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2180170478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_noise_filter.1919823475
Short name T647
Test name
Test status
Simulation time 70897274894 ps
CPU time 130 seconds
Started Sep 04 10:27:56 AM UTC 24
Finished Sep 04 10:30:09 AM UTC 24
Peak memory 209092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919823475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1919823475
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_perf.281780419
Short name T773
Test name
Test status
Simulation time 16408949236 ps
CPU time 414.68 seconds
Started Sep 04 10:28:10 AM UTC 24
Finished Sep 04 10:35:10 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281780419 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.281780419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_rx_oversample.793115324
Short name T595
Test name
Test status
Simulation time 6727749985 ps
CPU time 31.05 seconds
Started Sep 04 10:27:49 AM UTC 24
Finished Sep 04 10:28:22 AM UTC 24
Peak memory 207476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793115324 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.793115324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.2541631619
Short name T632
Test name
Test status
Simulation time 140555217872 ps
CPU time 101.31 seconds
Started Sep 04 10:28:05 AM UTC 24
Finished Sep 04 10:29:48 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541631619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2541631619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.344235387
Short name T589
Test name
Test status
Simulation time 2970059511 ps
CPU time 5.59 seconds
Started Sep 04 10:28:02 AM UTC 24
Finished Sep 04 10:28:09 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344235387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.344235387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_smoke.1428408694
Short name T587
Test name
Test status
Simulation time 6093659624 ps
CPU time 30.5 seconds
Started Sep 04 10:27:34 AM UTC 24
Finished Sep 04 10:28:06 AM UTC 24
Peak memory 208556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428408694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1428408694
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_stress_all.4013860373
Short name T762
Test name
Test status
Simulation time 234014689360 ps
CPU time 384.59 seconds
Started Sep 04 10:28:19 AM UTC 24
Finished Sep 04 10:34:48 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013860373 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.4013860373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.137445197
Short name T620
Test name
Test status
Simulation time 3633370444 ps
CPU time 71 seconds
Started Sep 04 10:28:16 AM UTC 24
Finished Sep 04 10:29:29 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=137445197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all_
with_rand_reset.137445197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.2131924087
Short name T592
Test name
Test status
Simulation time 9184524040 ps
CPU time 10.22 seconds
Started Sep 04 10:28:07 AM UTC 24
Finished Sep 04 10:28:18 AM UTC 24
Peak memory 208448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131924087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2131924087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/29.uart_tx_rx.1123601382
Short name T591
Test name
Test status
Simulation time 103697890318 ps
CPU time 38.93 seconds
Started Sep 04 10:27:35 AM UTC 24
Finished Sep 04 10:28:15 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123601382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1123601382
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/29.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/290.uart_fifo_reset.3916942663
Short name T1157
Test name
Test status
Simulation time 139479624861 ps
CPU time 69.83 seconds
Started Sep 04 10:48:56 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916942663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3916942663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/290.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/292.uart_fifo_reset.1106511684
Short name T242
Test name
Test status
Simulation time 30261328452 ps
CPU time 17.21 seconds
Started Sep 04 10:49:00 AM UTC 24
Finished Sep 04 10:49:18 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106511684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1106511684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/292.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/293.uart_fifo_reset.3734383967
Short name T1160
Test name
Test status
Simulation time 56530438617 ps
CPU time 84.46 seconds
Started Sep 04 10:49:01 AM UTC 24
Finished Sep 04 10:50:27 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734383967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3734383967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/293.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/294.uart_fifo_reset.3301918814
Short name T1142
Test name
Test status
Simulation time 37268465182 ps
CPU time 19.62 seconds
Started Sep 04 10:49:02 AM UTC 24
Finished Sep 04 10:49:23 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301918814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3301918814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/294.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2573051979
Short name T1158
Test name
Test status
Simulation time 32972600226 ps
CPU time 70.61 seconds
Started Sep 04 10:49:02 AM UTC 24
Finished Sep 04 10:50:14 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573051979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2573051979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/295.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3434927248
Short name T1147
Test name
Test status
Simulation time 53207385238 ps
CPU time 33.56 seconds
Started Sep 04 10:49:02 AM UTC 24
Finished Sep 04 10:49:37 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434927248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3434927248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/296.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/297.uart_fifo_reset.3165597812
Short name T1146
Test name
Test status
Simulation time 48987716679 ps
CPU time 30.87 seconds
Started Sep 04 10:49:04 AM UTC 24
Finished Sep 04 10:49:36 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165597812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3165597812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/297.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1387570669
Short name T252
Test name
Test status
Simulation time 94337283678 ps
CPU time 54.83 seconds
Started Sep 04 10:49:04 AM UTC 24
Finished Sep 04 10:50:00 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387570669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1387570669
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/298.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/299.uart_fifo_reset.4166033553
Short name T1172
Test name
Test status
Simulation time 108618309550 ps
CPU time 174.32 seconds
Started Sep 04 10:49:07 AM UTC 24
Finished Sep 04 10:52:04 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166033553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4166033553
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/299.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_alert_test.1813117831
Short name T40
Test name
Test status
Simulation time 41151541 ps
CPU time 0.82 seconds
Started Sep 04 10:06:58 AM UTC 24
Finished Sep 04 10:07:00 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813117831 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1813117831
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_fifo_full.2124934589
Short name T259
Test name
Test status
Simulation time 86706352080 ps
CPU time 96.12 seconds
Started Sep 04 10:06:23 AM UTC 24
Finished Sep 04 10:08:01 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124934589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2124934589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.2896236565
Short name T177
Test name
Test status
Simulation time 85452844878 ps
CPU time 126.12 seconds
Started Sep 04 10:06:27 AM UTC 24
Finished Sep 04 10:08:35 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896236565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2896236565
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_fifo_reset.2496265928
Short name T98
Test name
Test status
Simulation time 49007687094 ps
CPU time 94.22 seconds
Started Sep 04 10:06:27 AM UTC 24
Finished Sep 04 10:08:03 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496265928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2496265928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_intr.1936076850
Short name T257
Test name
Test status
Simulation time 16999241560 ps
CPU time 10.96 seconds
Started Sep 04 10:06:28 AM UTC 24
Finished Sep 04 10:06:40 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936076850 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1936076850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.951252597
Short name T319
Test name
Test status
Simulation time 111703811833 ps
CPU time 634.67 seconds
Started Sep 04 10:06:47 AM UTC 24
Finished Sep 04 10:17:30 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951252597 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.951252597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_loopback.3666290900
Short name T384
Test name
Test status
Simulation time 1254322310 ps
CPU time 6.69 seconds
Started Sep 04 10:06:46 AM UTC 24
Finished Sep 04 10:06:54 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666290900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3666290900
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_perf.2771262500
Short name T274
Test name
Test status
Simulation time 16030813111 ps
CPU time 250.52 seconds
Started Sep 04 10:06:46 AM UTC 24
Finished Sep 04 10:11:00 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771262500 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2771262500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_rx_oversample.793563555
Short name T76
Test name
Test status
Simulation time 5658846299 ps
CPU time 16.88 seconds
Started Sep 04 10:06:28 AM UTC 24
Finished Sep 04 10:06:46 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793563555 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.793563555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.2368285027
Short name T126
Test name
Test status
Simulation time 62340362806 ps
CPU time 84.35 seconds
Started Sep 04 10:06:41 AM UTC 24
Finished Sep 04 10:08:07 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368285027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2368285027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.390944649
Short name T318
Test name
Test status
Simulation time 1717662726 ps
CPU time 4.51 seconds
Started Sep 04 10:06:40 AM UTC 24
Finished Sep 04 10:06:46 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390944649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.390944649
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_sec_cm.3152685811
Short name T85
Test name
Test status
Simulation time 82323947 ps
CPU time 1.25 seconds
Started Sep 04 10:06:55 AM UTC 24
Finished Sep 04 10:06:57 AM UTC 24
Peak memory 239512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152685811 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3152685811
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_smoke.2024966793
Short name T74
Test name
Test status
Simulation time 134354212 ps
CPU time 1.16 seconds
Started Sep 04 10:06:20 AM UTC 24
Finished Sep 04 10:06:22 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024966793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2024966793
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.1112049112
Short name T33
Test name
Test status
Simulation time 4308741705 ps
CPU time 67.03 seconds
Started Sep 04 10:06:51 AM UTC 24
Finished Sep 04 10:08:00 AM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1112049112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_
with_rand_reset.1112049112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.3629797389
Short name T329
Test name
Test status
Simulation time 898304988 ps
CPU time 2.97 seconds
Started Sep 04 10:06:46 AM UTC 24
Finished Sep 04 10:06:50 AM UTC 24
Peak memory 207164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629797389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3629797389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/3.uart_tx_rx.144265645
Short name T381
Test name
Test status
Simulation time 14165572621 ps
CPU time 34.63 seconds
Started Sep 04 10:06:21 AM UTC 24
Finished Sep 04 10:06:57 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144265645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.144265645
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/3.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_alert_test.24868577
Short name T607
Test name
Test status
Simulation time 12961154 ps
CPU time 0.81 seconds
Started Sep 04 10:28:56 AM UTC 24
Finished Sep 04 10:28:57 AM UTC 24
Peak memory 204368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24868577 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.24868577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_fifo_full.3294878185
Short name T755
Test name
Test status
Simulation time 129237689308 ps
CPU time 364.27 seconds
Started Sep 04 10:28:22 AM UTC 24
Finished Sep 04 10:34:31 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294878185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3294878185
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.2676851995
Short name T140
Test name
Test status
Simulation time 113622742816 ps
CPU time 201.83 seconds
Started Sep 04 10:28:23 AM UTC 24
Finished Sep 04 10:31:48 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676851995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2676851995
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_fifo_reset.1769184267
Short name T617
Test name
Test status
Simulation time 228912362388 ps
CPU time 51.37 seconds
Started Sep 04 10:28:26 AM UTC 24
Finished Sep 04 10:29:18 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769184267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1769184267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_intr.836287742
Short name T613
Test name
Test status
Simulation time 13557927930 ps
CPU time 23.96 seconds
Started Sep 04 10:28:40 AM UTC 24
Finished Sep 04 10:29:05 AM UTC 24
Peak memory 207140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836287742 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.836287742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.316363841
Short name T780
Test name
Test status
Simulation time 164638856319 ps
CPU time 403.96 seconds
Started Sep 04 10:28:51 AM UTC 24
Finished Sep 04 10:35:41 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316363841 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.316363841
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_loopback.2223202383
Short name T610
Test name
Test status
Simulation time 8614432597 ps
CPU time 13.13 seconds
Started Sep 04 10:28:49 AM UTC 24
Finished Sep 04 10:29:03 AM UTC 24
Peak memory 208044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223202383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2223202383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_noise_filter.2092134329
Short name T651
Test name
Test status
Simulation time 153409189437 ps
CPU time 91.34 seconds
Started Sep 04 10:28:41 AM UTC 24
Finished Sep 04 10:30:14 AM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092134329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2092134329
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_perf.4043349071
Short name T735
Test name
Test status
Simulation time 20427175748 ps
CPU time 290.39 seconds
Started Sep 04 10:28:50 AM UTC 24
Finished Sep 04 10:33:44 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043349071 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.4043349071
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_rx_oversample.3683588222
Short name T606
Test name
Test status
Simulation time 2105159127 ps
CPU time 18.09 seconds
Started Sep 04 10:28:36 AM UTC 24
Finished Sep 04 10:28:55 AM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683588222 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3683588222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.644882472
Short name T163
Test name
Test status
Simulation time 55470365534 ps
CPU time 28.49 seconds
Started Sep 04 10:28:48 AM UTC 24
Finished Sep 04 10:29:18 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644882472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.644882472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.1367111073
Short name T612
Test name
Test status
Simulation time 5855196492 ps
CPU time 22.29 seconds
Started Sep 04 10:28:41 AM UTC 24
Finished Sep 04 10:29:04 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367111073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1367111073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_smoke.3989784353
Short name T597
Test name
Test status
Simulation time 5565564359 ps
CPU time 16.25 seconds
Started Sep 04 10:28:21 AM UTC 24
Finished Sep 04 10:28:39 AM UTC 24
Peak memory 207980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989784353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3989784353
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_stress_all.4225444902
Short name T392
Test name
Test status
Simulation time 48876183966 ps
CPU time 71.33 seconds
Started Sep 04 10:28:53 AM UTC 24
Finished Sep 04 10:30:06 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225444902 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.4225444902
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.1191901367
Short name T644
Test name
Test status
Simulation time 9165190807 ps
CPU time 69.68 seconds
Started Sep 04 10:28:53 AM UTC 24
Finished Sep 04 10:30:05 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1191901367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all
_with_rand_reset.1191901367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.4160997791
Short name T604
Test name
Test status
Simulation time 1891375210 ps
CPU time 2.44 seconds
Started Sep 04 10:28:49 AM UTC 24
Finished Sep 04 10:28:53 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160997791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.4160997791
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/30.uart_tx_rx.3634547389
Short name T628
Test name
Test status
Simulation time 70430429542 ps
CPU time 79.39 seconds
Started Sep 04 10:28:22 AM UTC 24
Finished Sep 04 10:29:44 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634547389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3634547389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/30.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_alert_test.178577144
Short name T622
Test name
Test status
Simulation time 34490277 ps
CPU time 0.79 seconds
Started Sep 04 10:29:32 AM UTC 24
Finished Sep 04 10:29:34 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178577144 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.178577144
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_fifo_full.559818336
Short name T624
Test name
Test status
Simulation time 40445905036 ps
CPU time 32.5 seconds
Started Sep 04 10:29:03 AM UTC 24
Finished Sep 04 10:29:37 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559818336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.559818336
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.980589652
Short name T638
Test name
Test status
Simulation time 49230309620 ps
CPU time 53.62 seconds
Started Sep 04 10:29:04 AM UTC 24
Finished Sep 04 10:29:59 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980589652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.980589652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_fifo_reset.4051496698
Short name T396
Test name
Test status
Simulation time 107745736536 ps
CPU time 275.95 seconds
Started Sep 04 10:29:05 AM UTC 24
Finished Sep 04 10:33:45 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051496698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.4051496698
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_intr.399516895
Short name T615
Test name
Test status
Simulation time 6164338721 ps
CPU time 5.65 seconds
Started Sep 04 10:29:06 AM UTC 24
Finished Sep 04 10:29:13 AM UTC 24
Peak memory 205220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399516895 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.399516895
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.13585679
Short name T824
Test name
Test status
Simulation time 128723149942 ps
CPU time 482.65 seconds
Started Sep 04 10:29:21 AM UTC 24
Finished Sep 04 10:37:29 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13585679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.13585679
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_loopback.3849571205
Short name T623
Test name
Test status
Simulation time 12224864373 ps
CPU time 15.49 seconds
Started Sep 04 10:29:18 AM UTC 24
Finished Sep 04 10:29:36 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849571205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3849571205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_noise_filter.3052044218
Short name T643
Test name
Test status
Simulation time 38425283802 ps
CPU time 55.7 seconds
Started Sep 04 10:29:07 AM UTC 24
Finished Sep 04 10:30:04 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052044218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3052044218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_perf.3543718302
Short name T810
Test name
Test status
Simulation time 16220081198 ps
CPU time 458.7 seconds
Started Sep 04 10:29:19 AM UTC 24
Finished Sep 04 10:37:04 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543718302 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3543718302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_rx_oversample.3174855656
Short name T630
Test name
Test status
Simulation time 4821817873 ps
CPU time 38.15 seconds
Started Sep 04 10:29:05 AM UTC 24
Finished Sep 04 10:29:45 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174855656 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3174855656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.3764543609
Short name T670
Test name
Test status
Simulation time 43623757476 ps
CPU time 113.41 seconds
Started Sep 04 10:29:13 AM UTC 24
Finished Sep 04 10:31:09 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764543609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3764543609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.711715501
Short name T618
Test name
Test status
Simulation time 6558234366 ps
CPU time 5.62 seconds
Started Sep 04 10:29:13 AM UTC 24
Finished Sep 04 10:29:20 AM UTC 24
Peak memory 205160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711715501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.711715501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_smoke.2731161134
Short name T608
Test name
Test status
Simulation time 453682239 ps
CPU time 1.72 seconds
Started Sep 04 10:28:58 AM UTC 24
Finished Sep 04 10:29:00 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731161134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2731161134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_stress_all.2082827174
Short name T646
Test name
Test status
Simulation time 6136450016 ps
CPU time 36.33 seconds
Started Sep 04 10:29:30 AM UTC 24
Finished Sep 04 10:30:07 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082827174 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2082827174
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1724032047
Short name T636
Test name
Test status
Simulation time 2313610058 ps
CPU time 31.34 seconds
Started Sep 04 10:29:23 AM UTC 24
Finished Sep 04 10:29:56 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1724032047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all
_with_rand_reset.1724032047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.1801396001
Short name T619
Test name
Test status
Simulation time 831974746 ps
CPU time 6.37 seconds
Started Sep 04 10:29:14 AM UTC 24
Finished Sep 04 10:29:22 AM UTC 24
Peak memory 207636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801396001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1801396001
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/31.uart_tx_rx.1190388257
Short name T691
Test name
Test status
Simulation time 74159483423 ps
CPU time 166.78 seconds
Started Sep 04 10:29:01 AM UTC 24
Finished Sep 04 10:31:50 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190388257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1190388257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/31.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_alert_test.922723664
Short name T641
Test name
Test status
Simulation time 14164627 ps
CPU time 0.83 seconds
Started Sep 04 10:30:00 AM UTC 24
Finished Sep 04 10:30:02 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922723664 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.922723664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_fifo_full.1177683462
Short name T713
Test name
Test status
Simulation time 152017102182 ps
CPU time 180.73 seconds
Started Sep 04 10:29:37 AM UTC 24
Finished Sep 04 10:32:41 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177683462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1177683462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.2919337664
Short name T650
Test name
Test status
Simulation time 16827895030 ps
CPU time 33.57 seconds
Started Sep 04 10:29:38 AM UTC 24
Finished Sep 04 10:30:13 AM UTC 24
Peak memory 208576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919337664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2919337664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_fifo_reset.2166409066
Short name T184
Test name
Test status
Simulation time 44826918969 ps
CPU time 37.08 seconds
Started Sep 04 10:29:39 AM UTC 24
Finished Sep 04 10:30:18 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166409066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2166409066
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_intr.3983557714
Short name T705
Test name
Test status
Simulation time 54162354795 ps
CPU time 146.55 seconds
Started Sep 04 10:29:44 AM UTC 24
Finished Sep 04 10:32:14 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983557714 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3983557714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.1047918582
Short name T930
Test name
Test status
Simulation time 78692957213 ps
CPU time 723.67 seconds
Started Sep 04 10:29:51 AM UTC 24
Finished Sep 04 10:42:03 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047918582 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1047918582
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_loopback.2883503643
Short name T645
Test name
Test status
Simulation time 5869339427 ps
CPU time 14.34 seconds
Started Sep 04 10:29:50 AM UTC 24
Finished Sep 04 10:30:05 AM UTC 24
Peak memory 207936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883503643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2883503643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_noise_filter.2163593281
Short name T660
Test name
Test status
Simulation time 17695032476 ps
CPU time 49.11 seconds
Started Sep 04 10:29:45 AM UTC 24
Finished Sep 04 10:30:36 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163593281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2163593281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_perf.2430957594
Short name T738
Test name
Test status
Simulation time 16996237538 ps
CPU time 243.07 seconds
Started Sep 04 10:29:51 AM UTC 24
Finished Sep 04 10:33:57 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430957594 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2430957594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_rx_oversample.2615803990
Short name T633
Test name
Test status
Simulation time 3250256649 ps
CPU time 6.92 seconds
Started Sep 04 10:29:41 AM UTC 24
Finished Sep 04 10:29:49 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615803990 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2615803990
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.1212340616
Short name T688
Test name
Test status
Simulation time 118022400578 ps
CPU time 112.72 seconds
Started Sep 04 10:29:48 AM UTC 24
Finished Sep 04 10:31:42 AM UTC 24
Peak memory 208412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212340616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1212340616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.1645988424
Short name T634
Test name
Test status
Simulation time 2030181149 ps
CPU time 3.1 seconds
Started Sep 04 10:29:45 AM UTC 24
Finished Sep 04 10:29:50 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645988424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1645988424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_smoke.1929475198
Short name T625
Test name
Test status
Simulation time 1003275841 ps
CPU time 1.85 seconds
Started Sep 04 10:29:35 AM UTC 24
Finished Sep 04 10:29:38 AM UTC 24
Peak memory 206436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929475198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1929475198
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_stress_all.1634419327
Short name T206
Test name
Test status
Simulation time 249203675264 ps
CPU time 640.3 seconds
Started Sep 04 10:29:58 AM UTC 24
Finished Sep 04 10:40:46 AM UTC 24
Peak memory 212468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634419327 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1634419327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2719228456
Short name T656
Test name
Test status
Simulation time 1076292966 ps
CPU time 23.09 seconds
Started Sep 04 10:29:57 AM UTC 24
Finished Sep 04 10:30:21 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2719228456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all
_with_rand_reset.2719228456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.600546160
Short name T648
Test name
Test status
Simulation time 6701736139 ps
CPU time 21.31 seconds
Started Sep 04 10:29:49 AM UTC 24
Finished Sep 04 10:30:11 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600546160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.600546160
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/32.uart_tx_rx.3457773807
Short name T626
Test name
Test status
Simulation time 697436958 ps
CPU time 1.5 seconds
Started Sep 04 10:29:36 AM UTC 24
Finished Sep 04 10:29:39 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457773807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3457773807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/32.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_alert_test.1361807812
Short name T654
Test name
Test status
Simulation time 16273232 ps
CPU time 0.85 seconds
Started Sep 04 10:30:15 AM UTC 24
Finished Sep 04 10:30:17 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361807812 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1361807812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_fifo_full.2423379159
Short name T658
Test name
Test status
Simulation time 33042753330 ps
CPU time 27.11 seconds
Started Sep 04 10:30:02 AM UTC 24
Finished Sep 04 10:30:31 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423379159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2423379159
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.54563923
Short name T173
Test name
Test status
Simulation time 43028231591 ps
CPU time 97.61 seconds
Started Sep 04 10:30:04 AM UTC 24
Finished Sep 04 10:31:44 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54563923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.54563923
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_fifo_reset.2904806634
Short name T685
Test name
Test status
Simulation time 97821918720 ps
CPU time 89.91 seconds
Started Sep 04 10:30:06 AM UTC 24
Finished Sep 04 10:31:37 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904806634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2904806634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_intr.2438616666
Short name T884
Test name
Test status
Simulation time 671543893828 ps
CPU time 591.83 seconds
Started Sep 04 10:30:06 AM UTC 24
Finished Sep 04 10:40:04 AM UTC 24
Peak memory 208136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438616666 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2438616666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.4054818540
Short name T673
Test name
Test status
Simulation time 33683391486 ps
CPU time 61.7 seconds
Started Sep 04 10:30:12 AM UTC 24
Finished Sep 04 10:31:15 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054818540 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.4054818540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_loopback.3363677910
Short name T657
Test name
Test status
Simulation time 8775958395 ps
CPU time 16.61 seconds
Started Sep 04 10:30:11 AM UTC 24
Finished Sep 04 10:30:29 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363677910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3363677910
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_noise_filter.460586498
Short name T669
Test name
Test status
Simulation time 53704664826 ps
CPU time 58.14 seconds
Started Sep 04 10:30:06 AM UTC 24
Finished Sep 04 10:31:05 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460586498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.460586498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_perf.1711084090
Short name T776
Test name
Test status
Simulation time 21058125236 ps
CPU time 313.18 seconds
Started Sep 04 10:30:12 AM UTC 24
Finished Sep 04 10:35:29 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711084090 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1711084090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_rx_oversample.254795463
Short name T659
Test name
Test status
Simulation time 4932142511 ps
CPU time 25.78 seconds
Started Sep 04 10:30:06 AM UTC 24
Finished Sep 04 10:30:33 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254795463 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.254795463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.4004633835
Short name T700
Test name
Test status
Simulation time 315186083418 ps
CPU time 118.02 seconds
Started Sep 04 10:30:08 AM UTC 24
Finished Sep 04 10:32:08 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004633835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.4004633835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.2380006792
Short name T649
Test name
Test status
Simulation time 4400768470 ps
CPU time 2.73 seconds
Started Sep 04 10:30:08 AM UTC 24
Finished Sep 04 10:30:12 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380006792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2380006792
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_smoke.3423528770
Short name T642
Test name
Test status
Simulation time 641240597 ps
CPU time 2.14 seconds
Started Sep 04 10:30:00 AM UTC 24
Finished Sep 04 10:30:03 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423528770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3423528770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_stress_all.1143129307
Short name T805
Test name
Test status
Simulation time 245615495304 ps
CPU time 386 seconds
Started Sep 04 10:30:15 AM UTC 24
Finished Sep 04 10:36:46 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143129307 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1143129307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.1034351778
Short name T671
Test name
Test status
Simulation time 3152775951 ps
CPU time 54.99 seconds
Started Sep 04 10:30:14 AM UTC 24
Finished Sep 04 10:31:11 AM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1034351778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all
_with_rand_reset.1034351778
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.1225340247
Short name T653
Test name
Test status
Simulation time 969219677 ps
CPU time 4.91 seconds
Started Sep 04 10:30:10 AM UTC 24
Finished Sep 04 10:30:16 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225340247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1225340247
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/33.uart_tx_rx.652376572
Short name T661
Test name
Test status
Simulation time 15211367280 ps
CPU time 35.98 seconds
Started Sep 04 10:30:02 AM UTC 24
Finished Sep 04 10:30:40 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652376572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.652376572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/33.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_alert_test.2115034021
Short name T666
Test name
Test status
Simulation time 12328200 ps
CPU time 0.82 seconds
Started Sep 04 10:30:55 AM UTC 24
Finished Sep 04 10:30:57 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115034021 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2115034021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_fifo_full.2911361747
Short name T677
Test name
Test status
Simulation time 34355566964 ps
CPU time 66.19 seconds
Started Sep 04 10:30:18 AM UTC 24
Finished Sep 04 10:31:26 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911361747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2911361747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.2359697627
Short name T160
Test name
Test status
Simulation time 97871262797 ps
CPU time 70.97 seconds
Started Sep 04 10:30:22 AM UTC 24
Finished Sep 04 10:31:34 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359697627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2359697627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_fifo_reset.3113885359
Short name T390
Test name
Test status
Simulation time 64679353274 ps
CPU time 205.58 seconds
Started Sep 04 10:30:22 AM UTC 24
Finished Sep 04 10:33:50 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113885359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3113885359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_intr.808109376
Short name T711
Test name
Test status
Simulation time 48838329986 ps
CPU time 127.42 seconds
Started Sep 04 10:30:30 AM UTC 24
Finished Sep 04 10:32:40 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808109376 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.808109376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.4007176764
Short name T775
Test name
Test status
Simulation time 43540023043 ps
CPU time 279.37 seconds
Started Sep 04 10:30:44 AM UTC 24
Finished Sep 04 10:35:28 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007176764 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.4007176764
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_loopback.2278954037
Short name T664
Test name
Test status
Simulation time 211257416 ps
CPU time 1.75 seconds
Started Sep 04 10:30:42 AM UTC 24
Finished Sep 04 10:30:45 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278954037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2278954037
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_noise_filter.2088431912
Short name T667
Test name
Test status
Simulation time 39996073616 ps
CPU time 28.3 seconds
Started Sep 04 10:30:32 AM UTC 24
Finished Sep 04 10:31:01 AM UTC 24
Peak memory 209032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088431912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2088431912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_perf.1692202982
Short name T968
Test name
Test status
Simulation time 15101768733 ps
CPU time 772.69 seconds
Started Sep 04 10:30:43 AM UTC 24
Finished Sep 04 10:43:45 AM UTC 24
Peak memory 212144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692202982 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1692202982
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2876914673
Short name T689
Test name
Test status
Simulation time 8223200852 ps
CPU time 71.07 seconds
Started Sep 04 10:30:30 AM UTC 24
Finished Sep 04 10:31:43 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876914673 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2876914673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.3438795207
Short name T715
Test name
Test status
Simulation time 63134218758 ps
CPU time 132.37 seconds
Started Sep 04 10:30:37 AM UTC 24
Finished Sep 04 10:32:52 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438795207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3438795207
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.3113815321
Short name T665
Test name
Test status
Simulation time 47617344838 ps
CPU time 17.98 seconds
Started Sep 04 10:30:34 AM UTC 24
Finished Sep 04 10:30:53 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113815321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3113815321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_smoke.3210958983
Short name T655
Test name
Test status
Simulation time 445106827 ps
CPU time 2.97 seconds
Started Sep 04 10:30:16 AM UTC 24
Finished Sep 04 10:30:20 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210958983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3210958983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_stress_all.621059291
Short name T892
Test name
Test status
Simulation time 169310755979 ps
CPU time 561.67 seconds
Started Sep 04 10:30:54 AM UTC 24
Finished Sep 04 10:40:22 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621059291 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.621059291
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.4294588737
Short name T707
Test name
Test status
Simulation time 14441776012 ps
CPU time 88.63 seconds
Started Sep 04 10:30:45 AM UTC 24
Finished Sep 04 10:32:16 AM UTC 24
Peak memory 225416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4294588737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all
_with_rand_reset.4294588737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.1625157458
Short name T663
Test name
Test status
Simulation time 521423470 ps
CPU time 1.53 seconds
Started Sep 04 10:30:40 AM UTC 24
Finished Sep 04 10:30:43 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625157458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1625157458
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/34.uart_tx_rx.2336515501
Short name T687
Test name
Test status
Simulation time 137964332531 ps
CPU time 81.42 seconds
Started Sep 04 10:30:17 AM UTC 24
Finished Sep 04 10:31:41 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336515501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2336515501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/34.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_alert_test.485295550
Short name T684
Test name
Test status
Simulation time 45046127 ps
CPU time 0.85 seconds
Started Sep 04 10:31:34 AM UTC 24
Finished Sep 04 10:31:36 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485295550 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.485295550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_fifo_full.2475956788
Short name T675
Test name
Test status
Simulation time 106332154361 ps
CPU time 14.31 seconds
Started Sep 04 10:31:03 AM UTC 24
Finished Sep 04 10:31:19 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475956788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2475956788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.3411126915
Short name T676
Test name
Test status
Simulation time 23266701251 ps
CPU time 17 seconds
Started Sep 04 10:31:06 AM UTC 24
Finished Sep 04 10:31:25 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411126915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3411126915
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_fifo_reset.57993285
Short name T683
Test name
Test status
Simulation time 33550539249 ps
CPU time 25.34 seconds
Started Sep 04 10:31:09 AM UTC 24
Finished Sep 04 10:31:36 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57993285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.57993285
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_intr.1072771388
Short name T679
Test name
Test status
Simulation time 11670323808 ps
CPU time 13.41 seconds
Started Sep 04 10:31:15 AM UTC 24
Finished Sep 04 10:31:30 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072771388 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1072771388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.1829623031
Short name T815
Test name
Test status
Simulation time 49246607832 ps
CPU time 340.87 seconds
Started Sep 04 10:31:30 AM UTC 24
Finished Sep 04 10:37:15 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829623031 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1829623031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_loopback.309756302
Short name T681
Test name
Test status
Simulation time 2231928643 ps
CPU time 5.92 seconds
Started Sep 04 10:31:27 AM UTC 24
Finished Sep 04 10:31:34 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309756302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_loopback.309756302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_noise_filter.3151520888
Short name T757
Test name
Test status
Simulation time 350038268855 ps
CPU time 195.39 seconds
Started Sep 04 10:31:17 AM UTC 24
Finished Sep 04 10:34:35 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151520888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3151520888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_perf.657866838
Short name T771
Test name
Test status
Simulation time 15933316679 ps
CPU time 216.63 seconds
Started Sep 04 10:31:28 AM UTC 24
Finished Sep 04 10:35:08 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657866838 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.657866838
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_rx_oversample.777798833
Short name T672
Test name
Test status
Simulation time 1197763225 ps
CPU time 1.78 seconds
Started Sep 04 10:31:11 AM UTC 24
Finished Sep 04 10:31:14 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777798833 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.777798833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.1747248109
Short name T690
Test name
Test status
Simulation time 122890705762 ps
CPU time 26.08 seconds
Started Sep 04 10:31:20 AM UTC 24
Finished Sep 04 10:31:47 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747248109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1747248109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.3171476235
Short name T678
Test name
Test status
Simulation time 2009268326 ps
CPU time 8.48 seconds
Started Sep 04 10:31:18 AM UTC 24
Finished Sep 04 10:31:27 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171476235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3171476235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_smoke.3897714726
Short name T668
Test name
Test status
Simulation time 511537944 ps
CPU time 2.43 seconds
Started Sep 04 10:30:58 AM UTC 24
Finished Sep 04 10:31:02 AM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897714726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3897714726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_stress_all.974371286
Short name T1174
Test name
Test status
Simulation time 265730424066 ps
CPU time 1222.62 seconds
Started Sep 04 10:31:32 AM UTC 24
Finished Sep 04 10:52:08 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974371286 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.974371286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.4156609514
Short name T701
Test name
Test status
Simulation time 7686914367 ps
CPU time 36.24 seconds
Started Sep 04 10:31:31 AM UTC 24
Finished Sep 04 10:32:09 AM UTC 24
Peak memory 219644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4156609514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all
_with_rand_reset.4156609514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.2150836615
Short name T697
Test name
Test status
Simulation time 7203300616 ps
CPU time 30.88 seconds
Started Sep 04 10:31:26 AM UTC 24
Finished Sep 04 10:31:58 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150836615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2150836615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/35.uart_tx_rx.313832466
Short name T680
Test name
Test status
Simulation time 20881455395 ps
CPU time 27.69 seconds
Started Sep 04 10:31:02 AM UTC 24
Finished Sep 04 10:31:31 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313832466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.313832466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/35.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_alert_test.2406569317
Short name T696
Test name
Test status
Simulation time 46979816 ps
CPU time 0.85 seconds
Started Sep 04 10:31:55 AM UTC 24
Finished Sep 04 10:31:57 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406569317 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2406569317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_fifo_full.3537512310
Short name T763
Test name
Test status
Simulation time 147544236093 ps
CPU time 189.86 seconds
Started Sep 04 10:31:36 AM UTC 24
Finished Sep 04 10:34:49 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537512310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3537512310
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.2655261443
Short name T695
Test name
Test status
Simulation time 98332184206 ps
CPU time 16.28 seconds
Started Sep 04 10:31:38 AM UTC 24
Finished Sep 04 10:31:55 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655261443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2655261443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_fifo_reset.1757989902
Short name T703
Test name
Test status
Simulation time 17091219999 ps
CPU time 32.02 seconds
Started Sep 04 10:31:39 AM UTC 24
Finished Sep 04 10:32:12 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757989902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1757989902
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_intr.3114498888
Short name T692
Test name
Test status
Simulation time 9376264730 ps
CPU time 8.51 seconds
Started Sep 04 10:31:42 AM UTC 24
Finished Sep 04 10:31:51 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114498888 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3114498888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.2738174815
Short name T875
Test name
Test status
Simulation time 78826876198 ps
CPU time 468.95 seconds
Started Sep 04 10:31:52 AM UTC 24
Finished Sep 04 10:39:47 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738174815 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2738174815
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_loopback.2426275564
Short name T694
Test name
Test status
Simulation time 1487385621 ps
CPU time 4.37 seconds
Started Sep 04 10:31:49 AM UTC 24
Finished Sep 04 10:31:55 AM UTC 24
Peak memory 207084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426275564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2426275564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_noise_filter.3274039835
Short name T710
Test name
Test status
Simulation time 15555139639 ps
CPU time 37.81 seconds
Started Sep 04 10:31:43 AM UTC 24
Finished Sep 04 10:32:22 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274039835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3274039835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_perf.2187828774
Short name T793
Test name
Test status
Simulation time 23475033768 ps
CPU time 262.15 seconds
Started Sep 04 10:31:51 AM UTC 24
Finished Sep 04 10:36:17 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187828774 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2187828774
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_rx_oversample.1179604596
Short name T699
Test name
Test status
Simulation time 6184423025 ps
CPU time 25.75 seconds
Started Sep 04 10:31:39 AM UTC 24
Finished Sep 04 10:32:06 AM UTC 24
Peak memory 208380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179604596 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1179604596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.2902518504
Short name T702
Test name
Test status
Simulation time 25380913034 ps
CPU time 23.9 seconds
Started Sep 04 10:31:45 AM UTC 24
Finished Sep 04 10:32:10 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902518504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2902518504
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1879821410
Short name T693
Test name
Test status
Simulation time 4247386498 ps
CPU time 6.49 seconds
Started Sep 04 10:31:44 AM UTC 24
Finished Sep 04 10:31:51 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879821410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1879821410
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_smoke.3159532730
Short name T686
Test name
Test status
Simulation time 976477165 ps
CPU time 1.55 seconds
Started Sep 04 10:31:35 AM UTC 24
Finished Sep 04 10:31:38 AM UTC 24
Peak memory 206396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159532730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3159532730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_stress_all.3100363134
Short name T393
Test name
Test status
Simulation time 60002184514 ps
CPU time 95.55 seconds
Started Sep 04 10:31:55 AM UTC 24
Finished Sep 04 10:33:33 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100363134 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3100363134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.51407940
Short name T726
Test name
Test status
Simulation time 18621370197 ps
CPU time 88.82 seconds
Started Sep 04 10:31:52 AM UTC 24
Finished Sep 04 10:33:23 AM UTC 24
Peak memory 219972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=51407940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all_w
ith_rand_reset.51407940
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.1198765676
Short name T706
Test name
Test status
Simulation time 6446185369 ps
CPU time 25.78 seconds
Started Sep 04 10:31:48 AM UTC 24
Finished Sep 04 10:32:15 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198765676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1198765676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/36.uart_tx_rx.468834192
Short name T761
Test name
Test status
Simulation time 80999150601 ps
CPU time 187.73 seconds
Started Sep 04 10:31:35 AM UTC 24
Finished Sep 04 10:34:46 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468834192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.468834192
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/36.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_alert_test.2509053251
Short name T712
Test name
Test status
Simulation time 10728695 ps
CPU time 0.85 seconds
Started Sep 04 10:32:39 AM UTC 24
Finished Sep 04 10:32:41 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509053251 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2509053251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_fifo_full.3422185109
Short name T153
Test name
Test status
Simulation time 104970550298 ps
CPU time 44.24 seconds
Started Sep 04 10:32:02 AM UTC 24
Finished Sep 04 10:32:47 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422185109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3422185109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.617532600
Short name T718
Test name
Test status
Simulation time 75429974193 ps
CPU time 54.66 seconds
Started Sep 04 10:32:04 AM UTC 24
Finished Sep 04 10:33:00 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617532600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.617532600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_fifo_reset.933144116
Short name T152
Test name
Test status
Simulation time 29349594568 ps
CPU time 30.14 seconds
Started Sep 04 10:32:07 AM UTC 24
Finished Sep 04 10:32:38 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933144116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.933144116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_intr.2022873321
Short name T725
Test name
Test status
Simulation time 237312043101 ps
CPU time 69.67 seconds
Started Sep 04 10:32:10 AM UTC 24
Finished Sep 04 10:33:21 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022873321 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2022873321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.1600924249
Short name T745
Test name
Test status
Simulation time 184748614335 ps
CPU time 115.58 seconds
Started Sep 04 10:32:20 AM UTC 24
Finished Sep 04 10:34:17 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600924249 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1600924249
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_loopback.4196651323
Short name T708
Test name
Test status
Simulation time 58276665 ps
CPU time 1.03 seconds
Started Sep 04 10:32:16 AM UTC 24
Finished Sep 04 10:32:18 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196651323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4196651323
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_noise_filter.3503102409
Short name T753
Test name
Test status
Simulation time 77353263461 ps
CPU time 137.28 seconds
Started Sep 04 10:32:11 AM UTC 24
Finished Sep 04 10:34:31 AM UTC 24
Peak memory 208908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503102409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3503102409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_perf.2938005934
Short name T880
Test name
Test status
Simulation time 12478368436 ps
CPU time 456.07 seconds
Started Sep 04 10:32:16 AM UTC 24
Finished Sep 04 10:39:58 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938005934 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2938005934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_rx_oversample.1434006814
Short name T704
Test name
Test status
Simulation time 2029137566 ps
CPU time 3.1 seconds
Started Sep 04 10:32:09 AM UTC 24
Finished Sep 04 10:32:13 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434006814 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1434006814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.3389665658
Short name T731
Test name
Test status
Simulation time 93589880215 ps
CPU time 74.24 seconds
Started Sep 04 10:32:14 AM UTC 24
Finished Sep 04 10:33:30 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389665658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3389665658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.2812437555
Short name T709
Test name
Test status
Simulation time 3159792764 ps
CPU time 5.95 seconds
Started Sep 04 10:32:13 AM UTC 24
Finished Sep 04 10:32:20 AM UTC 24
Peak memory 205024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812437555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2812437555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_smoke.3034045700
Short name T698
Test name
Test status
Simulation time 101072659 ps
CPU time 1.22 seconds
Started Sep 04 10:31:59 AM UTC 24
Finished Sep 04 10:32:01 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034045700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3034045700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_stress_all.1887857099
Short name T882
Test name
Test status
Simulation time 194711290588 ps
CPU time 451.28 seconds
Started Sep 04 10:32:23 AM UTC 24
Finished Sep 04 10:40:00 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887857099 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1887857099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.956188640
Short name T723
Test name
Test status
Simulation time 5204848256 ps
CPU time 54.04 seconds
Started Sep 04 10:32:21 AM UTC 24
Finished Sep 04 10:33:16 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=956188640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all_
with_rand_reset.956188640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.3349684760
Short name T717
Test name
Test status
Simulation time 6860466207 ps
CPU time 37.49 seconds
Started Sep 04 10:32:14 AM UTC 24
Finished Sep 04 10:32:53 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349684760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3349684760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/37.uart_tx_rx.719192657
Short name T404
Test name
Test status
Simulation time 107330659239 ps
CPU time 225.2 seconds
Started Sep 04 10:31:59 AM UTC 24
Finished Sep 04 10:35:47 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719192657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.719192657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/37.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_alert_test.585090293
Short name T727
Test name
Test status
Simulation time 44197000 ps
CPU time 0.84 seconds
Started Sep 04 10:33:22 AM UTC 24
Finished Sep 04 10:33:24 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585090293 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.585090293
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_fifo_full.1994169532
Short name T728
Test name
Test status
Simulation time 26418003583 ps
CPU time 40.67 seconds
Started Sep 04 10:32:42 AM UTC 24
Finished Sep 04 10:33:24 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994169532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1994169532
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.3255695693
Short name T781
Test name
Test status
Simulation time 68924632218 ps
CPU time 175.83 seconds
Started Sep 04 10:32:44 AM UTC 24
Finished Sep 04 10:35:43 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255695693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3255695693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_intr.1996440965
Short name T720
Test name
Test status
Simulation time 31594426021 ps
CPU time 16.25 seconds
Started Sep 04 10:32:52 AM UTC 24
Finished Sep 04 10:33:10 AM UTC 24
Peak memory 208976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996440965 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1996440965
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.1235887808
Short name T889
Test name
Test status
Simulation time 150156379296 ps
CPU time 414.97 seconds
Started Sep 04 10:33:17 AM UTC 24
Finished Sep 04 10:40:17 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235887808 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1235887808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_loopback.2144434430
Short name T733
Test name
Test status
Simulation time 7895859388 ps
CPU time 22.41 seconds
Started Sep 04 10:33:12 AM UTC 24
Finished Sep 04 10:33:35 AM UTC 24
Peak memory 207168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144434430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2144434430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_noise_filter.230174777
Short name T744
Test name
Test status
Simulation time 71265058217 ps
CPU time 73.09 seconds
Started Sep 04 10:32:54 AM UTC 24
Finished Sep 04 10:34:09 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230174777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.230174777
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_perf.4244504810
Short name T983
Test name
Test status
Simulation time 11657335594 ps
CPU time 656.79 seconds
Started Sep 04 10:33:13 AM UTC 24
Finished Sep 04 10:44:18 AM UTC 24
Peak memory 212148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244504810 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4244504810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_rx_oversample.3417755800
Short name T721
Test name
Test status
Simulation time 5389386376 ps
CPU time 17.4 seconds
Started Sep 04 10:32:52 AM UTC 24
Finished Sep 04 10:33:11 AM UTC 24
Peak memory 207864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417755800 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3417755800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.947152507
Short name T730
Test name
Test status
Simulation time 36334292203 ps
CPU time 27.25 seconds
Started Sep 04 10:33:02 AM UTC 24
Finished Sep 04 10:33:30 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947152507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.947152507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.2904484243
Short name T722
Test name
Test status
Simulation time 45359625235 ps
CPU time 10.66 seconds
Started Sep 04 10:33:00 AM UTC 24
Finished Sep 04 10:33:12 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904484243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2904484243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_smoke.4244906322
Short name T714
Test name
Test status
Simulation time 526871870 ps
CPU time 1.88 seconds
Started Sep 04 10:32:41 AM UTC 24
Finished Sep 04 10:32:44 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244906322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4244906322
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_stress_all.3537282171
Short name T944
Test name
Test status
Simulation time 193084316596 ps
CPU time 558.02 seconds
Started Sep 04 10:33:20 AM UTC 24
Finished Sep 04 10:42:45 AM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537282171 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3537282171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.189527265
Short name T746
Test name
Test status
Simulation time 3507429912 ps
CPU time 58.22 seconds
Started Sep 04 10:33:18 AM UTC 24
Finished Sep 04 10:34:18 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=189527265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all_
with_rand_reset.189527265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.3065881258
Short name T724
Test name
Test status
Simulation time 1291370763 ps
CPU time 5.68 seconds
Started Sep 04 10:33:11 AM UTC 24
Finished Sep 04 10:33:17 AM UTC 24
Peak memory 208544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065881258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3065881258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/38.uart_tx_rx.3861975154
Short name T719
Test name
Test status
Simulation time 24171505908 ps
CPU time 17.43 seconds
Started Sep 04 10:32:42 AM UTC 24
Finished Sep 04 10:33:01 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861975154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3861975154
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/38.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_alert_test.131816004
Short name T741
Test name
Test status
Simulation time 12563442 ps
CPU time 0.86 seconds
Started Sep 04 10:33:59 AM UTC 24
Finished Sep 04 10:34:01 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131816004 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.131816004
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_fifo_full.429893751
Short name T737
Test name
Test status
Simulation time 27747086073 ps
CPU time 27.94 seconds
Started Sep 04 10:33:25 AM UTC 24
Finished Sep 04 10:33:55 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429893751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.429893751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.1901603403
Short name T739
Test name
Test status
Simulation time 36141972808 ps
CPU time 27.81 seconds
Started Sep 04 10:33:29 AM UTC 24
Finished Sep 04 10:33:58 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901603403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1901603403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_fifo_reset.1881993325
Short name T228
Test name
Test status
Simulation time 114955820908 ps
CPU time 42.63 seconds
Started Sep 04 10:33:31 AM UTC 24
Finished Sep 04 10:34:15 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881993325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1881993325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_intr.3995626464
Short name T743
Test name
Test status
Simulation time 22867027867 ps
CPU time 31.02 seconds
Started Sep 04 10:33:34 AM UTC 24
Finished Sep 04 10:34:06 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995626464 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3995626464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.1161314452
Short name T964
Test name
Test status
Simulation time 84739751575 ps
CPU time 581.09 seconds
Started Sep 04 10:33:51 AM UTC 24
Finished Sep 04 10:43:40 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161314452 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1161314452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_loopback.1535592519
Short name T740
Test name
Test status
Simulation time 5243701393 ps
CPU time 12.73 seconds
Started Sep 04 10:33:45 AM UTC 24
Finished Sep 04 10:33:59 AM UTC 24
Peak memory 208064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535592519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1535592519
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_noise_filter.2710821639
Short name T388
Test name
Test status
Simulation time 34524497234 ps
CPU time 70.31 seconds
Started Sep 04 10:33:36 AM UTC 24
Finished Sep 04 10:34:48 AM UTC 24
Peak memory 217744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710821639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2710821639
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_perf.833532585
Short name T1173
Test name
Test status
Simulation time 23054597141 ps
CPU time 1083.14 seconds
Started Sep 04 10:33:50 AM UTC 24
Finished Sep 04 10:52:05 AM UTC 24
Peak memory 212468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833532585 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.833532585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_rx_oversample.2604202720
Short name T736
Test name
Test status
Simulation time 5787104083 ps
CPU time 17.85 seconds
Started Sep 04 10:33:31 AM UTC 24
Finished Sep 04 10:33:50 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604202720 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2604202720
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.1407142937
Short name T779
Test name
Test status
Simulation time 92109949086 ps
CPU time 114.11 seconds
Started Sep 04 10:33:43 AM UTC 24
Finished Sep 04 10:35:39 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407142937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1407142937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.4074488435
Short name T760
Test name
Test status
Simulation time 36435213270 ps
CPU time 63.92 seconds
Started Sep 04 10:33:36 AM UTC 24
Finished Sep 04 10:34:41 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074488435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.4074488435
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_smoke.1291911605
Short name T729
Test name
Test status
Simulation time 676881550 ps
CPU time 2.37 seconds
Started Sep 04 10:33:24 AM UTC 24
Finished Sep 04 10:33:28 AM UTC 24
Peak memory 207628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291911605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1291911605
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_stress_all.2386531077
Short name T1075
Test name
Test status
Simulation time 171461314114 ps
CPU time 790.74 seconds
Started Sep 04 10:33:59 AM UTC 24
Finished Sep 04 10:47:18 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386531077 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2386531077
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.1182010936
Short name T754
Test name
Test status
Simulation time 7401884399 ps
CPU time 34.05 seconds
Started Sep 04 10:33:55 AM UTC 24
Finished Sep 04 10:34:31 AM UTC 24
Peak memory 219852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1182010936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all
_with_rand_reset.1182010936
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.3694231770
Short name T748
Test name
Test status
Simulation time 6539101214 ps
CPU time 33.52 seconds
Started Sep 04 10:33:45 AM UTC 24
Finished Sep 04 10:34:20 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694231770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3694231770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/39.uart_tx_rx.3622355208
Short name T800
Test name
Test status
Simulation time 123519919005 ps
CPU time 195.06 seconds
Started Sep 04 10:33:24 AM UTC 24
Finished Sep 04 10:36:42 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622355208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3622355208
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/39.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_alert_test.338278524
Short name T407
Test name
Test status
Simulation time 13419575 ps
CPU time 0.85 seconds
Started Sep 04 10:07:46 AM UTC 24
Finished Sep 04 10:07:48 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338278524 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.338278524
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.6866234
Short name T115
Test name
Test status
Simulation time 26205549768 ps
CPU time 38.4 seconds
Started Sep 04 10:07:06 AM UTC 24
Finished Sep 04 10:07:46 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6866234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.6866234
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_fifo_reset.497609510
Short name T45
Test name
Test status
Simulation time 14049909668 ps
CPU time 13.65 seconds
Started Sep 04 10:07:09 AM UTC 24
Finished Sep 04 10:07:24 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497609510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.497609510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_intr.1032760046
Short name T22
Test name
Test status
Simulation time 21336200888 ps
CPU time 66.44 seconds
Started Sep 04 10:07:21 AM UTC 24
Finished Sep 04 10:08:30 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032760046 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1032760046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.2043335889
Short name T264
Test name
Test status
Simulation time 118510848577 ps
CPU time 309.95 seconds
Started Sep 04 10:07:35 AM UTC 24
Finished Sep 04 10:12:49 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043335889 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2043335889
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_loopback.3448594707
Short name T406
Test name
Test status
Simulation time 362816372 ps
CPU time 2.57 seconds
Started Sep 04 10:07:33 AM UTC 24
Finished Sep 04 10:07:36 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448594707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3448594707
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_noise_filter.443872786
Short name T261
Test name
Test status
Simulation time 16027417749 ps
CPU time 65.18 seconds
Started Sep 04 10:07:23 AM UTC 24
Finished Sep 04 10:08:31 AM UTC 24
Peak memory 208068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443872786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.443872786
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_rx_oversample.2347432806
Short name T409
Test name
Test status
Simulation time 5250927440 ps
CPU time 48.75 seconds
Started Sep 04 10:07:20 AM UTC 24
Finished Sep 04 10:08:11 AM UTC 24
Peak memory 207860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347432806 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2347432806
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.2284286
Short name T131
Test name
Test status
Simulation time 148187462776 ps
CPU time 169.87 seconds
Started Sep 04 10:07:25 AM UTC 24
Finished Sep 04 10:10:18 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2284286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.1991225477
Short name T300
Test name
Test status
Simulation time 77811679742 ps
CPU time 84.56 seconds
Started Sep 04 10:07:24 AM UTC 24
Finished Sep 04 10:08:51 AM UTC 24
Peak memory 207084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991225477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1991225477
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_sec_cm.3275367170
Short name T86
Test name
Test status
Simulation time 110796655 ps
CPU time 1.32 seconds
Started Sep 04 10:07:44 AM UTC 24
Finished Sep 04 10:07:46 AM UTC 24
Peak memory 240196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275367170 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3275367170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_smoke.2620612932
Short name T41
Test name
Test status
Simulation time 651630387 ps
CPU time 5.92 seconds
Started Sep 04 10:06:58 AM UTC 24
Finished Sep 04 10:07:05 AM UTC 24
Peak memory 207624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620612932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2620612932
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.1029714534
Short name T35
Test name
Test status
Simulation time 12926704853 ps
CPU time 79.31 seconds
Started Sep 04 10:07:37 AM UTC 24
Finished Sep 04 10:08:58 AM UTC 24
Peak memory 219832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1029714534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_
with_rand_reset.1029714534
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.205257645
Short name T47
Test name
Test status
Simulation time 2935517287 ps
CPU time 3.82 seconds
Started Sep 04 10:07:27 AM UTC 24
Finished Sep 04 10:07:32 AM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205257645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.205257645
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/4.uart_tx_rx.2355647938
Short name T46
Test name
Test status
Simulation time 41562046438 ps
CPU time 30.34 seconds
Started Sep 04 10:07:00 AM UTC 24
Finished Sep 04 10:07:32 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355647938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2355647938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/4.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_alert_test.1829551831
Short name T756
Test name
Test status
Simulation time 36972745 ps
CPU time 0.85 seconds
Started Sep 04 10:34:32 AM UTC 24
Finished Sep 04 10:34:34 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829551831 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1829551831
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_fifo_full.2925471557
Short name T863
Test name
Test status
Simulation time 113385527932 ps
CPU time 296.55 seconds
Started Sep 04 10:34:04 AM UTC 24
Finished Sep 04 10:39:04 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925471557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2925471557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.72227786
Short name T766
Test name
Test status
Simulation time 100549289840 ps
CPU time 45.12 seconds
Started Sep 04 10:34:07 AM UTC 24
Finished Sep 04 10:34:53 AM UTC 24
Peak memory 208452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72227786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.72227786
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_fifo_reset.3615045957
Short name T397
Test name
Test status
Simulation time 21889629015 ps
CPU time 25.55 seconds
Started Sep 04 10:34:10 AM UTC 24
Finished Sep 04 10:34:37 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615045957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3615045957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_intr.3490033209
Short name T765
Test name
Test status
Simulation time 45859077194 ps
CPU time 29.92 seconds
Started Sep 04 10:34:18 AM UTC 24
Finished Sep 04 10:34:49 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490033209 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3490033209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.2981240024
Short name T1046
Test name
Test status
Simulation time 92247477898 ps
CPU time 723.04 seconds
Started Sep 04 10:34:31 AM UTC 24
Finished Sep 04 10:46:42 AM UTC 24
Peak memory 212404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981240024 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2981240024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_loopback.2021227956
Short name T752
Test name
Test status
Simulation time 377323683 ps
CPU time 2.09 seconds
Started Sep 04 10:34:26 AM UTC 24
Finished Sep 04 10:34:30 AM UTC 24
Peak memory 207084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021227956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2021227956
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_noise_filter.3983410548
Short name T820
Test name
Test status
Simulation time 77597580462 ps
CPU time 176.04 seconds
Started Sep 04 10:34:19 AM UTC 24
Finished Sep 04 10:37:18 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983410548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3983410548
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_perf.1348086544
Short name T1183
Test name
Test status
Simulation time 30851518109 ps
CPU time 1637.09 seconds
Started Sep 04 10:34:31 AM UTC 24
Finished Sep 04 11:02:05 AM UTC 24
Peak memory 212244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348086544 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1348086544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_rx_oversample.1324288317
Short name T759
Test name
Test status
Simulation time 3552177393 ps
CPU time 23.21 seconds
Started Sep 04 10:34:16 AM UTC 24
Finished Sep 04 10:34:40 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324288317 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1324288317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.1835867429
Short name T808
Test name
Test status
Simulation time 69337226806 ps
CPU time 147.08 seconds
Started Sep 04 10:34:21 AM UTC 24
Finished Sep 04 10:36:51 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835867429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1835867429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.3857282234
Short name T750
Test name
Test status
Simulation time 4535844579 ps
CPU time 4.56 seconds
Started Sep 04 10:34:19 AM UTC 24
Finished Sep 04 10:34:25 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857282234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3857282234
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_smoke.854590307
Short name T742
Test name
Test status
Simulation time 692539468 ps
CPU time 2.53 seconds
Started Sep 04 10:34:00 AM UTC 24
Finished Sep 04 10:34:03 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854590307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.uart_smoke.854590307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_stress_all.3303718595
Short name T191
Test name
Test status
Simulation time 40487665033 ps
CPU time 78 seconds
Started Sep 04 10:34:32 AM UTC 24
Finished Sep 04 10:35:51 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303718595 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3303718595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.2512377266
Short name T777
Test name
Test status
Simulation time 12595197104 ps
CPU time 58.19 seconds
Started Sep 04 10:34:32 AM UTC 24
Finished Sep 04 10:35:32 AM UTC 24
Peak memory 219968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2512377266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all
_with_rand_reset.2512377266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.163027099
Short name T751
Test name
Test status
Simulation time 2524492659 ps
CPU time 4.12 seconds
Started Sep 04 10:34:23 AM UTC 24
Finished Sep 04 10:34:30 AM UTC 24
Peak memory 207616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163027099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.163027099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/40.uart_tx_rx.328808478
Short name T764
Test name
Test status
Simulation time 23437949071 ps
CPU time 46.05 seconds
Started Sep 04 10:34:02 AM UTC 24
Finished Sep 04 10:34:49 AM UTC 24
Peak memory 208556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328808478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.328808478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/40.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_alert_test.1696475273
Short name T772
Test name
Test status
Simulation time 20522460 ps
CPU time 0.86 seconds
Started Sep 04 10:35:07 AM UTC 24
Finished Sep 04 10:35:09 AM UTC 24
Peak memory 204132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696475273 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1696475273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_fifo_full.1101362131
Short name T934
Test name
Test status
Simulation time 70121158294 ps
CPU time 445.91 seconds
Started Sep 04 10:34:37 AM UTC 24
Finished Sep 04 10:42:09 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101362131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1101362131
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.873109113
Short name T395
Test name
Test status
Simulation time 120012375178 ps
CPU time 136.57 seconds
Started Sep 04 10:34:39 AM UTC 24
Finished Sep 04 10:36:58 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873109113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.873109113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_fifo_reset.2099307653
Short name T838
Test name
Test status
Simulation time 107179666883 ps
CPU time 196.13 seconds
Started Sep 04 10:34:41 AM UTC 24
Finished Sep 04 10:38:00 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099307653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2099307653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_intr.2315608870
Short name T769
Test name
Test status
Simulation time 6456917119 ps
CPU time 18.35 seconds
Started Sep 04 10:34:46 AM UTC 24
Finished Sep 04 10:35:06 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315608870 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2315608870
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.3462109090
Short name T926
Test name
Test status
Simulation time 95578214948 ps
CPU time 401.39 seconds
Started Sep 04 10:35:05 AM UTC 24
Finished Sep 04 10:41:51 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462109090 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3462109090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_loopback.2065815801
Short name T768
Test name
Test status
Simulation time 4304805449 ps
CPU time 13.45 seconds
Started Sep 04 10:34:51 AM UTC 24
Finished Sep 04 10:35:05 AM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065815801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2065815801
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_noise_filter.1528816825
Short name T792
Test name
Test status
Simulation time 123140616837 ps
CPU time 86.56 seconds
Started Sep 04 10:34:48 AM UTC 24
Finished Sep 04 10:36:17 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528816825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1528816825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_perf.1555836692
Short name T1087
Test name
Test status
Simulation time 15384221170 ps
CPU time 762.72 seconds
Started Sep 04 10:34:54 AM UTC 24
Finished Sep 04 10:47:45 AM UTC 24
Peak memory 212220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555836692 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1555836692
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_rx_oversample.2923561041
Short name T770
Test name
Test status
Simulation time 3184229576 ps
CPU time 22.31 seconds
Started Sep 04 10:34:42 AM UTC 24
Finished Sep 04 10:35:06 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923561041 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2923561041
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.3636959160
Short name T154
Test name
Test status
Simulation time 128368786897 ps
CPU time 61.81 seconds
Started Sep 04 10:34:50 AM UTC 24
Finished Sep 04 10:35:53 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636959160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3636959160
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.1912504090
Short name T790
Test name
Test status
Simulation time 36712341261 ps
CPU time 81 seconds
Started Sep 04 10:34:50 AM UTC 24
Finished Sep 04 10:36:12 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912504090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1912504090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_smoke.2106347695
Short name T758
Test name
Test status
Simulation time 488790573 ps
CPU time 2.21 seconds
Started Sep 04 10:34:35 AM UTC 24
Finished Sep 04 10:34:38 AM UTC 24
Peak memory 208052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106347695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2106347695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.1582377401
Short name T774
Test name
Test status
Simulation time 1421819831 ps
CPU time 13.22 seconds
Started Sep 04 10:35:06 AM UTC 24
Finished Sep 04 10:35:20 AM UTC 24
Peak memory 217740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1582377401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all
_with_rand_reset.1582377401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.434167667
Short name T767
Test name
Test status
Simulation time 7549978636 ps
CPU time 13.61 seconds
Started Sep 04 10:34:50 AM UTC 24
Finished Sep 04 10:35:04 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434167667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.434167667
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/41.uart_tx_rx.870659959
Short name T385
Test name
Test status
Simulation time 61821348660 ps
CPU time 103.58 seconds
Started Sep 04 10:34:36 AM UTC 24
Finished Sep 04 10:36:22 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870659959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.870659959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/41.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_alert_test.2631676275
Short name T787
Test name
Test status
Simulation time 35761340 ps
CPU time 0.81 seconds
Started Sep 04 10:35:57 AM UTC 24
Finished Sep 04 10:35:59 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631676275 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2631676275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_fifo_full.3223176028
Short name T806
Test name
Test status
Simulation time 237128475585 ps
CPU time 95.76 seconds
Started Sep 04 10:35:10 AM UTC 24
Finished Sep 04 10:36:48 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223176028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3223176028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.3820179078
Short name T837
Test name
Test status
Simulation time 72130630925 ps
CPU time 154.62 seconds
Started Sep 04 10:35:21 AM UTC 24
Finished Sep 04 10:37:58 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820179078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3820179078
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_fifo_reset.3742094323
Short name T398
Test name
Test status
Simulation time 44964654250 ps
CPU time 101.36 seconds
Started Sep 04 10:35:28 AM UTC 24
Finished Sep 04 10:37:12 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742094323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3742094323
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_intr.128144155
Short name T961
Test name
Test status
Simulation time 470940816467 ps
CPU time 470.19 seconds
Started Sep 04 10:35:33 AM UTC 24
Finished Sep 04 10:43:28 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128144155 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.128144155
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.1607500543
Short name T1176
Test name
Test status
Simulation time 140397878151 ps
CPU time 1006.48 seconds
Started Sep 04 10:35:50 AM UTC 24
Finished Sep 04 10:52:48 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607500543 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1607500543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_loopback.521847333
Short name T786
Test name
Test status
Simulation time 9302899673 ps
CPU time 9.95 seconds
Started Sep 04 10:35:48 AM UTC 24
Finished Sep 04 10:35:59 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521847333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.uart_loopback.521847333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_noise_filter.2751785054
Short name T784
Test name
Test status
Simulation time 65155218318 ps
CPU time 17.39 seconds
Started Sep 04 10:35:38 AM UTC 24
Finished Sep 04 10:35:56 AM UTC 24
Peak memory 205240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751785054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2751785054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_perf.1925074218
Short name T893
Test name
Test status
Simulation time 14739767483 ps
CPU time 272.16 seconds
Started Sep 04 10:35:48 AM UTC 24
Finished Sep 04 10:40:24 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925074218 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1925074218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_rx_oversample.612208950
Short name T782
Test name
Test status
Simulation time 6177131922 ps
CPU time 16.07 seconds
Started Sep 04 10:35:31 AM UTC 24
Finished Sep 04 10:35:48 AM UTC 24
Peak memory 207652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612208950 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.612208950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.1742352019
Short name T830
Test name
Test status
Simulation time 47546146211 ps
CPU time 117.21 seconds
Started Sep 04 10:35:42 AM UTC 24
Finished Sep 04 10:37:41 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742352019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1742352019
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.310955591
Short name T783
Test name
Test status
Simulation time 4423351353 ps
CPU time 8.75 seconds
Started Sep 04 10:35:40 AM UTC 24
Finished Sep 04 10:35:50 AM UTC 24
Peak memory 205020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310955591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.310955591
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_smoke.2350403238
Short name T778
Test name
Test status
Simulation time 5305607098 ps
CPU time 26.06 seconds
Started Sep 04 10:35:09 AM UTC 24
Finished Sep 04 10:35:37 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350403238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2350403238
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_stress_all.4027882457
Short name T839
Test name
Test status
Simulation time 244582497276 ps
CPU time 140.07 seconds
Started Sep 04 10:35:53 AM UTC 24
Finished Sep 04 10:38:16 AM UTC 24
Peak memory 219708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027882457 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.4027882457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.2220508573
Short name T801
Test name
Test status
Simulation time 6525566143 ps
CPU time 49.05 seconds
Started Sep 04 10:35:52 AM UTC 24
Finished Sep 04 10:36:43 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2220508573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all
_with_rand_reset.2220508573
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.4159454673
Short name T788
Test name
Test status
Simulation time 6627784708 ps
CPU time 24.14 seconds
Started Sep 04 10:35:43 AM UTC 24
Finished Sep 04 10:36:08 AM UTC 24
Peak memory 208024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159454673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4159454673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/42.uart_tx_rx.2068596549
Short name T812
Test name
Test status
Simulation time 91974437148 ps
CPU time 113.7 seconds
Started Sep 04 10:35:10 AM UTC 24
Finished Sep 04 10:37:06 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068596549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2068596549
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/42.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_alert_test.1657363159
Short name T804
Test name
Test status
Simulation time 15843208 ps
CPU time 0.86 seconds
Started Sep 04 10:36:44 AM UTC 24
Finished Sep 04 10:36:46 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657363159 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1657363159
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_fifo_full.78945712
Short name T836
Test name
Test status
Simulation time 66858245814 ps
CPU time 104.71 seconds
Started Sep 04 10:36:10 AM UTC 24
Finished Sep 04 10:37:56 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78945712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.78945712
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1731823982
Short name T794
Test name
Test status
Simulation time 10178142026 ps
CPU time 9.23 seconds
Started Sep 04 10:36:11 AM UTC 24
Finished Sep 04 10:36:21 AM UTC 24
Peak memory 208320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731823982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1731823982
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_fifo_reset.1193153073
Short name T803
Test name
Test status
Simulation time 39932941746 ps
CPU time 30.41 seconds
Started Sep 04 10:36:13 AM UTC 24
Finished Sep 04 10:36:45 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193153073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1193153073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_intr.2446308036
Short name T849
Test name
Test status
Simulation time 57005717758 ps
CPU time 145.89 seconds
Started Sep 04 10:36:18 AM UTC 24
Finished Sep 04 10:38:47 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446308036 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2446308036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.3541054044
Short name T871
Test name
Test status
Simulation time 73266432067 ps
CPU time 180.42 seconds
Started Sep 04 10:36:33 AM UTC 24
Finished Sep 04 10:39:37 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541054044 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3541054044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_loopback.107336152
Short name T802
Test name
Test status
Simulation time 9562727628 ps
CPU time 13.06 seconds
Started Sep 04 10:36:30 AM UTC 24
Finished Sep 04 10:36:45 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107336152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.uart_loopback.107336152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_noise_filter.281292871
Short name T811
Test name
Test status
Simulation time 58136016603 ps
CPU time 45.96 seconds
Started Sep 04 10:36:18 AM UTC 24
Finished Sep 04 10:37:06 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281292871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.281292871
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_perf.1768520114
Short name T848
Test name
Test status
Simulation time 11466246728 ps
CPU time 124.18 seconds
Started Sep 04 10:36:32 AM UTC 24
Finished Sep 04 10:38:39 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768520114 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1768520114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_rx_oversample.1423727200
Short name T795
Test name
Test status
Simulation time 3391398034 ps
CPU time 10.81 seconds
Started Sep 04 10:36:15 AM UTC 24
Finished Sep 04 10:36:27 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423727200 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1423727200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.3029594538
Short name T845
Test name
Test status
Simulation time 74769787348 ps
CPU time 126.2 seconds
Started Sep 04 10:36:23 AM UTC 24
Finished Sep 04 10:38:32 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029594538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3029594538
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.984917164
Short name T797
Test name
Test status
Simulation time 2780991780 ps
CPU time 7.81 seconds
Started Sep 04 10:36:22 AM UTC 24
Finished Sep 04 10:36:31 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984917164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.984917164
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_smoke.1079173447
Short name T796
Test name
Test status
Simulation time 11591189889 ps
CPU time 28.78 seconds
Started Sep 04 10:35:59 AM UTC 24
Finished Sep 04 10:36:29 AM UTC 24
Peak memory 208648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079173447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1079173447
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_stress_all.4148065746
Short name T895
Test name
Test status
Simulation time 293242164093 ps
CPU time 228.23 seconds
Started Sep 04 10:36:43 AM UTC 24
Finished Sep 04 10:40:34 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148065746 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.4148065746
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.61076998
Short name T814
Test name
Test status
Simulation time 3204139759 ps
CPU time 35.03 seconds
Started Sep 04 10:36:35 AM UTC 24
Finished Sep 04 10:37:11 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=61076998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all_w
ith_rand_reset.61076998
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.4166370221
Short name T798
Test name
Test status
Simulation time 1218583469 ps
CPU time 3.62 seconds
Started Sep 04 10:36:28 AM UTC 24
Finished Sep 04 10:36:33 AM UTC 24
Peak memory 208564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166370221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.4166370221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/43.uart_tx_rx.2956479373
Short name T799
Test name
Test status
Simulation time 32369654944 ps
CPU time 32.29 seconds
Started Sep 04 10:36:01 AM UTC 24
Finished Sep 04 10:36:34 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956479373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2956479373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/43.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_alert_test.3700017559
Short name T822
Test name
Test status
Simulation time 15317325 ps
CPU time 0.86 seconds
Started Sep 04 10:37:17 AM UTC 24
Finished Sep 04 10:37:19 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700017559 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3700017559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_fifo_full.4133991125
Short name T158
Test name
Test status
Simulation time 74372181711 ps
CPU time 70.09 seconds
Started Sep 04 10:36:46 AM UTC 24
Finished Sep 04 10:37:58 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133991125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4133991125
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.4050115090
Short name T821
Test name
Test status
Simulation time 17720006544 ps
CPU time 30.08 seconds
Started Sep 04 10:36:47 AM UTC 24
Finished Sep 04 10:37:19 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050115090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.4050115090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_fifo_reset.2476751702
Short name T230
Test name
Test status
Simulation time 154149282207 ps
CPU time 80.72 seconds
Started Sep 04 10:36:49 AM UTC 24
Finished Sep 04 10:38:12 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476751702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2476751702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_intr.116046067
Short name T819
Test name
Test status
Simulation time 16644223017 ps
CPU time 25.41 seconds
Started Sep 04 10:36:51 AM UTC 24
Finished Sep 04 10:37:18 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116046067 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.116046067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.879525945
Short name T1007
Test name
Test status
Simulation time 106471375782 ps
CPU time 474.27 seconds
Started Sep 04 10:37:12 AM UTC 24
Finished Sep 04 10:45:12 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879525945 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.879525945
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_loopback.393440110
Short name T826
Test name
Test status
Simulation time 6937775050 ps
CPU time 27.82 seconds
Started Sep 04 10:37:07 AM UTC 24
Finished Sep 04 10:37:36 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393440110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.uart_loopback.393440110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_noise_filter.3492837853
Short name T817
Test name
Test status
Simulation time 34357309048 ps
CPU time 17.03 seconds
Started Sep 04 10:36:59 AM UTC 24
Finished Sep 04 10:37:18 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492837853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3492837853
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_perf.2625922855
Short name T842
Test name
Test status
Simulation time 1663255864 ps
CPU time 74.07 seconds
Started Sep 04 10:37:07 AM UTC 24
Finished Sep 04 10:38:22 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625922855 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2625922855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_rx_oversample.981243171
Short name T813
Test name
Test status
Simulation time 4630812248 ps
CPU time 14.84 seconds
Started Sep 04 10:36:50 AM UTC 24
Finished Sep 04 10:37:06 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981243171 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.981243171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.265847974
Short name T818
Test name
Test status
Simulation time 7252575403 ps
CPU time 11.91 seconds
Started Sep 04 10:37:05 AM UTC 24
Finished Sep 04 10:37:18 AM UTC 24
Peak memory 208420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265847974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.265847974
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.1746916316
Short name T816
Test name
Test status
Simulation time 5487643531 ps
CPU time 10.62 seconds
Started Sep 04 10:37:04 AM UTC 24
Finished Sep 04 10:37:16 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746916316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1746916316
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_smoke.3989919974
Short name T807
Test name
Test status
Simulation time 459002851 ps
CPU time 2.94 seconds
Started Sep 04 10:36:46 AM UTC 24
Finished Sep 04 10:36:50 AM UTC 24
Peak memory 208392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989919974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3989919974
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_stress_all.2135019435
Short name T869
Test name
Test status
Simulation time 377684766796 ps
CPU time 127.22 seconds
Started Sep 04 10:37:16 AM UTC 24
Finished Sep 04 10:39:25 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135019435 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2135019435
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.1282759012
Short name T825
Test name
Test status
Simulation time 10969725176 ps
CPU time 15.28 seconds
Started Sep 04 10:37:13 AM UTC 24
Finished Sep 04 10:37:29 AM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1282759012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all
_with_rand_reset.1282759012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.3483811667
Short name T829
Test name
Test status
Simulation time 6306038748 ps
CPU time 30.25 seconds
Started Sep 04 10:37:07 AM UTC 24
Finished Sep 04 10:37:38 AM UTC 24
Peak memory 208564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483811667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3483811667
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/44.uart_tx_rx.2740894598
Short name T809
Test name
Test status
Simulation time 39459010490 ps
CPU time 16.37 seconds
Started Sep 04 10:36:46 AM UTC 24
Finished Sep 04 10:37:03 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740894598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2740894598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/44.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_alert_test.3016080317
Short name T834
Test name
Test status
Simulation time 12423965 ps
CPU time 0.81 seconds
Started Sep 04 10:37:45 AM UTC 24
Finished Sep 04 10:37:47 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016080317 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3016080317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_fifo_full.145291327
Short name T157
Test name
Test status
Simulation time 33853580850 ps
CPU time 25.65 seconds
Started Sep 04 10:37:19 AM UTC 24
Finished Sep 04 10:37:46 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145291327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.145291327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.2827612964
Short name T841
Test name
Test status
Simulation time 32714096856 ps
CPU time 58.97 seconds
Started Sep 04 10:37:19 AM UTC 24
Finished Sep 04 10:38:20 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827612964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2827612964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_fifo_reset.3495365173
Short name T906
Test name
Test status
Simulation time 132314469757 ps
CPU time 226.37 seconds
Started Sep 04 10:37:19 AM UTC 24
Finished Sep 04 10:41:09 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495365173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3495365173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_intr.3438295414
Short name T850
Test name
Test status
Simulation time 62452009174 ps
CPU time 86.24 seconds
Started Sep 04 10:37:22 AM UTC 24
Finished Sep 04 10:38:50 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438295414 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3438295414
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.2485881267
Short name T959
Test name
Test status
Simulation time 163976895720 ps
CPU time 337.1 seconds
Started Sep 04 10:37:42 AM UTC 24
Finished Sep 04 10:43:24 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485881267 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2485881267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_loopback.1652254215
Short name T833
Test name
Test status
Simulation time 2493608028 ps
CPU time 5.58 seconds
Started Sep 04 10:37:38 AM UTC 24
Finished Sep 04 10:37:45 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652254215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1652254215
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_noise_filter.854207762
Short name T899
Test name
Test status
Simulation time 175786587823 ps
CPU time 187.81 seconds
Started Sep 04 10:37:30 AM UTC 24
Finished Sep 04 10:40:41 AM UTC 24
Peak memory 208000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854207762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.854207762
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_perf.2436036854
Short name T1059
Test name
Test status
Simulation time 28709894483 ps
CPU time 552.95 seconds
Started Sep 04 10:37:39 AM UTC 24
Finished Sep 04 10:46:59 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436036854 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2436036854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_rx_oversample.1705000873
Short name T828
Test name
Test status
Simulation time 5278295759 ps
CPU time 16.78 seconds
Started Sep 04 10:37:19 AM UTC 24
Finished Sep 04 10:37:37 AM UTC 24
Peak memory 208012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705000873 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1705000873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.477448637
Short name T885
Test name
Test status
Simulation time 123533293549 ps
CPU time 144.88 seconds
Started Sep 04 10:37:37 AM UTC 24
Finished Sep 04 10:40:04 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477448637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.477448637
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.1753504065
Short name T827
Test name
Test status
Simulation time 2352096780 ps
CPU time 4.29 seconds
Started Sep 04 10:37:31 AM UTC 24
Finished Sep 04 10:37:36 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753504065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1753504065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_smoke.1137280829
Short name T823
Test name
Test status
Simulation time 102043305 ps
CPU time 1.47 seconds
Started Sep 04 10:37:18 AM UTC 24
Finished Sep 04 10:37:21 AM UTC 24
Peak memory 206364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137280829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1137280829
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_stress_all.2397818692
Short name T169
Test name
Test status
Simulation time 608083937916 ps
CPU time 167.82 seconds
Started Sep 04 10:37:43 AM UTC 24
Finished Sep 04 10:40:34 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397818692 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2397818692
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.3339006480
Short name T832
Test name
Test status
Simulation time 767959497 ps
CPU time 4.29 seconds
Started Sep 04 10:37:37 AM UTC 24
Finished Sep 04 10:37:42 AM UTC 24
Peak memory 208012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339006480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3339006480
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/45.uart_tx_rx.3030690218
Short name T874
Test name
Test status
Simulation time 80126045810 ps
CPU time 145.03 seconds
Started Sep 04 10:37:18 AM UTC 24
Finished Sep 04 10:39:46 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030690218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3030690218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/45.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_alert_test.3544537264
Short name T846
Test name
Test status
Simulation time 190064661 ps
CPU time 0.81 seconds
Started Sep 04 10:38:33 AM UTC 24
Finished Sep 04 10:38:35 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544537264 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3544537264
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_fifo_full.2701384625
Short name T929
Test name
Test status
Simulation time 89111816996 ps
CPU time 244.42 seconds
Started Sep 04 10:37:51 AM UTC 24
Finished Sep 04 10:41:59 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701384625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2701384625
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.3827139230
Short name T995
Test name
Test status
Simulation time 111081856184 ps
CPU time 448.19 seconds
Started Sep 04 10:37:58 AM UTC 24
Finished Sep 04 10:45:32 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827139230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3827139230
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_fifo_reset.580214836
Short name T166
Test name
Test status
Simulation time 46993992775 ps
CPU time 50 seconds
Started Sep 04 10:37:59 AM UTC 24
Finished Sep 04 10:38:50 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580214836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.580214836
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_intr.1955422385
Short name T840
Test name
Test status
Simulation time 22232488464 ps
CPU time 16.74 seconds
Started Sep 04 10:38:01 AM UTC 24
Finished Sep 04 10:38:19 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955422385 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1955422385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.600985911
Short name T1028
Test name
Test status
Simulation time 185161049489 ps
CPU time 444.53 seconds
Started Sep 04 10:38:26 AM UTC 24
Finished Sep 04 10:45:57 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600985911 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.600985911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_loopback.1442013780
Short name T851
Test name
Test status
Simulation time 6154079658 ps
CPU time 25.62 seconds
Started Sep 04 10:38:23 AM UTC 24
Finished Sep 04 10:38:50 AM UTC 24
Peak memory 207744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442013780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1442013780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_noise_filter.1457497975
Short name T853
Test name
Test status
Simulation time 62706277457 ps
CPU time 39.57 seconds
Started Sep 04 10:38:13 AM UTC 24
Finished Sep 04 10:38:54 AM UTC 24
Peak memory 208088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457497975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1457497975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_perf.1754146812
Short name T936
Test name
Test status
Simulation time 11858078479 ps
CPU time 235.9 seconds
Started Sep 04 10:38:24 AM UTC 24
Finished Sep 04 10:42:24 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754146812 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1754146812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_rx_oversample.3925831357
Short name T854
Test name
Test status
Simulation time 6102768905 ps
CPU time 53.9 seconds
Started Sep 04 10:38:00 AM UTC 24
Finished Sep 04 10:38:55 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925831357 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3925831357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.3039776774
Short name T852
Test name
Test status
Simulation time 21831711290 ps
CPU time 30.61 seconds
Started Sep 04 10:38:19 AM UTC 24
Finished Sep 04 10:38:51 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039776774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3039776774
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.2125742897
Short name T844
Test name
Test status
Simulation time 3140998651 ps
CPU time 11.3 seconds
Started Sep 04 10:38:16 AM UTC 24
Finished Sep 04 10:38:29 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125742897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2125742897
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_smoke.3406537743
Short name T835
Test name
Test status
Simulation time 124007281 ps
CPU time 1.26 seconds
Started Sep 04 10:37:47 AM UTC 24
Finished Sep 04 10:37:50 AM UTC 24
Peak memory 207036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406537743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3406537743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_stress_all.2653114095
Short name T887
Test name
Test status
Simulation time 100887603759 ps
CPU time 97.05 seconds
Started Sep 04 10:38:30 AM UTC 24
Finished Sep 04 10:40:08 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653114095 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2653114095
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.2591482305
Short name T859
Test name
Test status
Simulation time 4285392184 ps
CPU time 30.39 seconds
Started Sep 04 10:38:30 AM UTC 24
Finished Sep 04 10:39:01 AM UTC 24
Peak memory 219904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2591482305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all
_with_rand_reset.2591482305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.1973190396
Short name T843
Test name
Test status
Simulation time 1346321311 ps
CPU time 2.92 seconds
Started Sep 04 10:38:21 AM UTC 24
Finished Sep 04 10:38:25 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973190396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1973190396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/46.uart_tx_rx.1263328078
Short name T861
Test name
Test status
Simulation time 66464663569 ps
CPU time 73.64 seconds
Started Sep 04 10:37:47 AM UTC 24
Finished Sep 04 10:39:03 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263328078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1263328078
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/46.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_alert_test.279544501
Short name T864
Test name
Test status
Simulation time 25352505 ps
CPU time 0.82 seconds
Started Sep 04 10:39:04 AM UTC 24
Finished Sep 04 10:39:06 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279544501 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.279544501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_fifo_full.2997283532
Short name T888
Test name
Test status
Simulation time 61985842788 ps
CPU time 93.99 seconds
Started Sep 04 10:38:40 AM UTC 24
Finished Sep 04 10:40:16 AM UTC 24
Peak memory 208572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997283532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2997283532
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.3622895822
Short name T858
Test name
Test status
Simulation time 17538479767 ps
CPU time 11.84 seconds
Started Sep 04 10:38:47 AM UTC 24
Finished Sep 04 10:39:00 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622895822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3622895822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_fifo_reset.699402014
Short name T219
Test name
Test status
Simulation time 208494428985 ps
CPU time 119.12 seconds
Started Sep 04 10:38:50 AM UTC 24
Finished Sep 04 10:40:51 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699402014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.699402014
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_intr.2331823627
Short name T862
Test name
Test status
Simulation time 23154297311 ps
CPU time 10.51 seconds
Started Sep 04 10:38:51 AM UTC 24
Finished Sep 04 10:39:03 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331823627 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2331823627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.3296968682
Short name T1169
Test name
Test status
Simulation time 149460531093 ps
CPU time 759.47 seconds
Started Sep 04 10:39:01 AM UTC 24
Finished Sep 04 10:51:49 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296968682 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3296968682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_loopback.2773596333
Short name T867
Test name
Test status
Simulation time 4782881515 ps
CPU time 18.94 seconds
Started Sep 04 10:38:58 AM UTC 24
Finished Sep 04 10:39:18 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773596333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2773596333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_noise_filter.445325031
Short name T894
Test name
Test status
Simulation time 88571774702 ps
CPU time 92.13 seconds
Started Sep 04 10:38:52 AM UTC 24
Finished Sep 04 10:40:26 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445325031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.445325031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_perf.4083213489
Short name T1051
Test name
Test status
Simulation time 26861610976 ps
CPU time 461.27 seconds
Started Sep 04 10:39:00 AM UTC 24
Finished Sep 04 10:46:47 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083213489 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4083213489
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_rx_oversample.3296543701
Short name T855
Test name
Test status
Simulation time 1485009979 ps
CPU time 4.12 seconds
Started Sep 04 10:38:51 AM UTC 24
Finished Sep 04 10:38:56 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296543701 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3296543701
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.1378969077
Short name T902
Test name
Test status
Simulation time 66856282692 ps
CPU time 114.2 seconds
Started Sep 04 10:38:56 AM UTC 24
Finished Sep 04 10:40:53 AM UTC 24
Peak memory 208388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378969077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1378969077
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.2763549899
Short name T857
Test name
Test status
Simulation time 4518439612 ps
CPU time 2.58 seconds
Started Sep 04 10:38:55 AM UTC 24
Finished Sep 04 10:38:59 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763549899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2763549899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_smoke.4215388402
Short name T847
Test name
Test status
Simulation time 342068364 ps
CPU time 1.33 seconds
Started Sep 04 10:38:36 AM UTC 24
Finished Sep 04 10:38:38 AM UTC 24
Peak memory 206968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215388402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4215388402
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_stress_all.2777578215
Short name T932
Test name
Test status
Simulation time 271511088978 ps
CPU time 178.33 seconds
Started Sep 04 10:39:03 AM UTC 24
Finished Sep 04 10:42:04 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777578215 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2777578215
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.1614333981
Short name T878
Test name
Test status
Simulation time 2545774846 ps
CPU time 47.61 seconds
Started Sep 04 10:39:02 AM UTC 24
Finished Sep 04 10:39:51 AM UTC 24
Peak memory 217516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1614333981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all
_with_rand_reset.1614333981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.3414601698
Short name T860
Test name
Test status
Simulation time 686592526 ps
CPU time 3.24 seconds
Started Sep 04 10:38:58 AM UTC 24
Finished Sep 04 10:39:02 AM UTC 24
Peak memory 207476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414601698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3414601698
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/47.uart_tx_rx.2201887408
Short name T856
Test name
Test status
Simulation time 13918581417 ps
CPU time 17.08 seconds
Started Sep 04 10:38:39 AM UTC 24
Finished Sep 04 10:38:57 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201887408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2201887408
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/47.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_alert_test.3927885615
Short name T879
Test name
Test status
Simulation time 42827499 ps
CPU time 0.83 seconds
Started Sep 04 10:39:51 AM UTC 24
Finished Sep 04 10:39:53 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927885615 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3927885615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_fifo_full.2564755057
Short name T886
Test name
Test status
Simulation time 16288150507 ps
CPU time 56.73 seconds
Started Sep 04 10:39:06 AM UTC 24
Finished Sep 04 10:40:05 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564755057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2564755057
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.2342698909
Short name T915
Test name
Test status
Simulation time 36761959272 ps
CPU time 135.4 seconds
Started Sep 04 10:39:07 AM UTC 24
Finished Sep 04 10:41:25 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342698909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2342698909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_intr.999197458
Short name T967
Test name
Test status
Simulation time 255029270135 ps
CPU time 256.35 seconds
Started Sep 04 10:39:25 AM UTC 24
Finished Sep 04 10:43:44 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999197458 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.999197458
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.4265791324
Short name T987
Test name
Test status
Simulation time 145740580683 ps
CPU time 277.07 seconds
Started Sep 04 10:39:48 AM UTC 24
Finished Sep 04 10:44:29 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265791324 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4265791324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_loopback.1140807785
Short name T876
Test name
Test status
Simulation time 2293592071 ps
CPU time 1.55 seconds
Started Sep 04 10:39:46 AM UTC 24
Finished Sep 04 10:39:49 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140807785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1140807785
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_noise_filter.274098542
Short name T916
Test name
Test status
Simulation time 179710386759 ps
CPU time 119.24 seconds
Started Sep 04 10:39:27 AM UTC 24
Finished Sep 04 10:41:28 AM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274098542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.274098542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_perf.2390809083
Short name T990
Test name
Test status
Simulation time 5594167098 ps
CPU time 287.03 seconds
Started Sep 04 10:39:46 AM UTC 24
Finished Sep 04 10:44:37 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390809083 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2390809083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_rx_oversample.4003254561
Short name T873
Test name
Test status
Simulation time 3153838158 ps
CPU time 25.74 seconds
Started Sep 04 10:39:18 AM UTC 24
Finished Sep 04 10:39:45 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003254561 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.4003254561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.1239891052
Short name T904
Test name
Test status
Simulation time 144385643890 ps
CPU time 79.29 seconds
Started Sep 04 10:39:38 AM UTC 24
Finished Sep 04 10:40:59 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239891052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1239891052
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.304660490
Short name T872
Test name
Test status
Simulation time 3278233307 ps
CPU time 10.54 seconds
Started Sep 04 10:39:30 AM UTC 24
Finished Sep 04 10:39:41 AM UTC 24
Peak memory 205020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304660490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.304660490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_smoke.1984037505
Short name T865
Test name
Test status
Simulation time 518585951 ps
CPU time 1.8 seconds
Started Sep 04 10:39:04 AM UTC 24
Finished Sep 04 10:39:07 AM UTC 24
Peak memory 206376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984037505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1984037505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_stress_all.2116546055
Short name T1009
Test name
Test status
Simulation time 172273868933 ps
CPU time 332.49 seconds
Started Sep 04 10:39:50 AM UTC 24
Finished Sep 04 10:45:27 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116546055 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2116546055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.1634008248
Short name T900
Test name
Test status
Simulation time 5969036551 ps
CPU time 53.26 seconds
Started Sep 04 10:39:50 AM UTC 24
Finished Sep 04 10:40:45 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1634008248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all
_with_rand_reset.1634008248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.3091229119
Short name T877
Test name
Test status
Simulation time 823835094 ps
CPU time 6.13 seconds
Started Sep 04 10:39:42 AM UTC 24
Finished Sep 04 10:39:49 AM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091229119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3091229119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/48.uart_tx_rx.3970215409
Short name T883
Test name
Test status
Simulation time 32366001860 ps
CPU time 56.29 seconds
Started Sep 04 10:39:05 AM UTC 24
Finished Sep 04 10:40:03 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970215409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3970215409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/48.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_alert_test.4203469039
Short name T896
Test name
Test status
Simulation time 19563186 ps
CPU time 0.86 seconds
Started Sep 04 10:40:33 AM UTC 24
Finished Sep 04 10:40:35 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203469039 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.4203469039
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_fifo_full.1589600154
Short name T922
Test name
Test status
Simulation time 94446917468 ps
CPU time 96.37 seconds
Started Sep 04 10:40:00 AM UTC 24
Finished Sep 04 10:41:38 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589600154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1589600154
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.4060847527
Short name T905
Test name
Test status
Simulation time 16990426808 ps
CPU time 61.44 seconds
Started Sep 04 10:40:01 AM UTC 24
Finished Sep 04 10:41:05 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060847527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4060847527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_fifo_reset.195173378
Short name T909
Test name
Test status
Simulation time 142770170822 ps
CPU time 69.13 seconds
Started Sep 04 10:40:04 AM UTC 24
Finished Sep 04 10:41:15 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195173378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.195173378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_intr.4051094266
Short name T903
Test name
Test status
Simulation time 47749257277 ps
CPU time 46.42 seconds
Started Sep 04 10:40:05 AM UTC 24
Finished Sep 04 10:40:53 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051094266 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4051094266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.2588592728
Short name T1005
Test name
Test status
Simulation time 53342124982 ps
CPU time 282.89 seconds
Started Sep 04 10:40:23 AM UTC 24
Finished Sep 04 10:45:10 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588592728 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2588592728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_loopback.695686860
Short name T898
Test name
Test status
Simulation time 9434866494 ps
CPU time 19.25 seconds
Started Sep 04 10:40:19 AM UTC 24
Finished Sep 04 10:40:40 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695686860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.uart_loopback.695686860
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_noise_filter.1072777480
Short name T785
Test name
Test status
Simulation time 41136099647 ps
CPU time 23.69 seconds
Started Sep 04 10:40:06 AM UTC 24
Finished Sep 04 10:40:31 AM UTC 24
Peak memory 207560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072777480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1072777480
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_perf.2283544760
Short name T1181
Test name
Test status
Simulation time 17874347401 ps
CPU time 819.05 seconds
Started Sep 04 10:40:22 AM UTC 24
Finished Sep 04 10:54:11 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283544760 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2283544760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_rx_oversample.274374142
Short name T890
Test name
Test status
Simulation time 4447953192 ps
CPU time 11.87 seconds
Started Sep 04 10:40:05 AM UTC 24
Finished Sep 04 10:40:18 AM UTC 24
Peak memory 208208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274374142 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.274374142
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.2365454975
Short name T1050
Test name
Test status
Simulation time 218378086899 ps
CPU time 383.62 seconds
Started Sep 04 10:40:17 AM UTC 24
Finished Sep 04 10:46:45 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365454975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2365454975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.2314902605
Short name T891
Test name
Test status
Simulation time 48803403176 ps
CPU time 11.12 seconds
Started Sep 04 10:40:09 AM UTC 24
Finished Sep 04 10:40:22 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314902605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2314902605
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_smoke.1686498362
Short name T881
Test name
Test status
Simulation time 484830615 ps
CPU time 3.02 seconds
Started Sep 04 10:39:54 AM UTC 24
Finished Sep 04 10:39:58 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686498362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1686498362
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_stress_all.2717243190
Short name T1167
Test name
Test status
Simulation time 411459993871 ps
CPU time 660.24 seconds
Started Sep 04 10:40:28 AM UTC 24
Finished Sep 04 10:51:36 AM UTC 24
Peak memory 228776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717243190 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2717243190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.3896491735
Short name T911
Test name
Test status
Simulation time 10566010088 ps
CPU time 49.79 seconds
Started Sep 04 10:40:24 AM UTC 24
Finished Sep 04 10:41:16 AM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3896491735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all
_with_rand_reset.3896491735
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.4185013468
Short name T901
Test name
Test status
Simulation time 6003766119 ps
CPU time 31.37 seconds
Started Sep 04 10:40:18 AM UTC 24
Finished Sep 04 10:40:51 AM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185013468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4185013468
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/49.uart_tx_rx.493844115
Short name T401
Test name
Test status
Simulation time 52602278320 ps
CPU time 52.13 seconds
Started Sep 04 10:39:59 AM UTC 24
Finished Sep 04 10:40:54 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493844115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.493844115
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/49.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_alert_test.1647227237
Short name T411
Test name
Test status
Simulation time 11130886 ps
CPU time 0.82 seconds
Started Sep 04 10:08:28 AM UTC 24
Finished Sep 04 10:08:30 AM UTC 24
Peak memory 204444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647227237 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1647227237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_fifo_full.2806823031
Short name T116
Test name
Test status
Simulation time 41071030146 ps
CPU time 64.39 seconds
Started Sep 04 10:07:50 AM UTC 24
Finished Sep 04 10:08:56 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806823031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2806823031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_fifo_reset.910776596
Short name T114
Test name
Test status
Simulation time 14562499957 ps
CPU time 29.83 seconds
Started Sep 04 10:07:56 AM UTC 24
Finished Sep 04 10:08:28 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910776596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.910776596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_intr.2713881631
Short name T374
Test name
Test status
Simulation time 143757270546 ps
CPU time 171.77 seconds
Started Sep 04 10:08:01 AM UTC 24
Finished Sep 04 10:10:55 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713881631 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2713881631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.1767137452
Short name T355
Test name
Test status
Simulation time 212046019080 ps
CPU time 472.32 seconds
Started Sep 04 10:08:12 AM UTC 24
Finished Sep 04 10:16:10 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767137452 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1767137452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_loopback.1198049767
Short name T410
Test name
Test status
Simulation time 5175814376 ps
CPU time 11.79 seconds
Started Sep 04 10:08:08 AM UTC 24
Finished Sep 04 10:08:21 AM UTC 24
Peak memory 208136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198049767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1198049767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_perf.4197791622
Short name T297
Test name
Test status
Simulation time 25926720559 ps
CPU time 388.47 seconds
Started Sep 04 10:08:11 AM UTC 24
Finished Sep 04 10:14:45 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197791622 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.4197791622
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_rx_oversample.2712587546
Short name T408
Test name
Test status
Simulation time 1375493555 ps
CPU time 5.69 seconds
Started Sep 04 10:08:00 AM UTC 24
Finished Sep 04 10:08:06 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712587546 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2712587546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.3162554782
Short name T307
Test name
Test status
Simulation time 3556403309 ps
CPU time 6.6 seconds
Started Sep 04 10:08:03 AM UTC 24
Finished Sep 04 10:08:10 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162554782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3162554782
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_smoke.3838993696
Short name T271
Test name
Test status
Simulation time 686807744 ps
CPU time 1.79 seconds
Started Sep 04 10:07:47 AM UTC 24
Finished Sep 04 10:07:50 AM UTC 24
Peak memory 206248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838993696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3838993696
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.1397782795
Short name T34
Test name
Test status
Simulation time 716599602 ps
CPU time 13.12 seconds
Started Sep 04 10:08:13 AM UTC 24
Finished Sep 04 10:08:27 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1397782795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_
with_rand_reset.1397782795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.2607105590
Short name T351
Test name
Test status
Simulation time 727095144 ps
CPU time 4.35 seconds
Started Sep 04 10:08:07 AM UTC 24
Finished Sep 04 10:08:12 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607105590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2607105590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/5.uart_tx_rx.2136277543
Short name T289
Test name
Test status
Simulation time 44890754892 ps
CPU time 103.62 seconds
Started Sep 04 10:07:48 AM UTC 24
Finished Sep 04 10:09:34 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136277543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2136277543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/5.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/50.uart_fifo_reset.1233400682
Short name T198
Test name
Test status
Simulation time 122172210832 ps
CPU time 57.94 seconds
Started Sep 04 10:40:35 AM UTC 24
Finished Sep 04 10:41:35 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233400682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1233400682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/50.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.1837403408
Short name T928
Test name
Test status
Simulation time 4059641657 ps
CPU time 80.88 seconds
Started Sep 04 10:40:35 AM UTC 24
Finished Sep 04 10:41:58 AM UTC 24
Peak memory 219860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1837403408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all
_with_rand_reset.1837403408
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.2634448401
Short name T914
Test name
Test status
Simulation time 22108902795 ps
CPU time 41.31 seconds
Started Sep 04 10:40:37 AM UTC 24
Finished Sep 04 10:41:20 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2634448401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all
_with_rand_reset.2634448401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/52.uart_fifo_reset.1491351541
Short name T908
Test name
Test status
Simulation time 65292078514 ps
CPU time 31.11 seconds
Started Sep 04 10:40:41 AM UTC 24
Finished Sep 04 10:41:14 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491351541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1491351541
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/52.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.4139405600
Short name T913
Test name
Test status
Simulation time 6197928551 ps
CPU time 36.14 seconds
Started Sep 04 10:40:41 AM UTC 24
Finished Sep 04 10:41:19 AM UTC 24
Peak memory 217612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4139405600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all
_with_rand_reset.4139405600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/53.uart_fifo_reset.4177479815
Short name T239
Test name
Test status
Simulation time 65147696789 ps
CPU time 100.3 seconds
Started Sep 04 10:40:46 AM UTC 24
Finished Sep 04 10:42:28 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177479815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.4177479815
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/53.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.906832249
Short name T907
Test name
Test status
Simulation time 1107368515 ps
CPU time 22.42 seconds
Started Sep 04 10:40:47 AM UTC 24
Finished Sep 04 10:41:11 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=906832249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all_
with_rand_reset.906832249
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/54.uart_fifo_reset.493403542
Short name T187
Test name
Test status
Simulation time 137439076105 ps
CPU time 173.79 seconds
Started Sep 04 10:40:51 AM UTC 24
Finished Sep 04 10:43:48 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493403542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.493403542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/54.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.3947430336
Short name T933
Test name
Test status
Simulation time 6137421003 ps
CPU time 72.33 seconds
Started Sep 04 10:40:52 AM UTC 24
Finished Sep 04 10:42:07 AM UTC 24
Peak memory 224612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3947430336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all
_with_rand_reset.3947430336
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/55.uart_fifo_reset.183547558
Short name T912
Test name
Test status
Simulation time 19867750742 ps
CPU time 21.12 seconds
Started Sep 04 10:40:53 AM UTC 24
Finished Sep 04 10:41:16 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183547558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.183547558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/55.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.1077947966
Short name T910
Test name
Test status
Simulation time 910139791 ps
CPU time 20.5 seconds
Started Sep 04 10:40:53 AM UTC 24
Finished Sep 04 10:41:15 AM UTC 24
Peak memory 217648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1077947966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all
_with_rand_reset.1077947966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/56.uart_fifo_reset.2582654972
Short name T204
Test name
Test status
Simulation time 69106324114 ps
CPU time 20.33 seconds
Started Sep 04 10:40:55 AM UTC 24
Finished Sep 04 10:41:16 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582654972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2582654972
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/56.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.2084938192
Short name T923
Test name
Test status
Simulation time 3083615541 ps
CPU time 39.62 seconds
Started Sep 04 10:41:00 AM UTC 24
Finished Sep 04 10:41:41 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2084938192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all
_with_rand_reset.2084938192
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/57.uart_fifo_reset.1162617520
Short name T225
Test name
Test status
Simulation time 117628190767 ps
CPU time 125.33 seconds
Started Sep 04 10:41:06 AM UTC 24
Finished Sep 04 10:43:13 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162617520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1162617520
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/57.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.3571821091
Short name T921
Test name
Test status
Simulation time 2216943232 ps
CPU time 25.78 seconds
Started Sep 04 10:41:10 AM UTC 24
Finished Sep 04 10:41:37 AM UTC 24
Peak memory 221832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3571821091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all
_with_rand_reset.3571821091
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/58.uart_fifo_reset.1596824360
Short name T192
Test name
Test status
Simulation time 74570444438 ps
CPU time 144.25 seconds
Started Sep 04 10:41:12 AM UTC 24
Finished Sep 04 10:43:39 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596824360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1596824360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/58.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.969321280
Short name T938
Test name
Test status
Simulation time 4032304426 ps
CPU time 70.7 seconds
Started Sep 04 10:41:15 AM UTC 24
Finished Sep 04 10:42:27 AM UTC 24
Peak memory 224336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=969321280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all_
with_rand_reset.969321280
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/59.uart_fifo_reset.914436969
Short name T919
Test name
Test status
Simulation time 21528483395 ps
CPU time 18.9 seconds
Started Sep 04 10:41:16 AM UTC 24
Finished Sep 04 10:41:36 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914436969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.914436969
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/59.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.1974573747
Short name T917
Test name
Test status
Simulation time 5566996278 ps
CPU time 15.36 seconds
Started Sep 04 10:41:16 AM UTC 24
Finished Sep 04 10:41:32 AM UTC 24
Peak memory 219976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1974573747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all
_with_rand_reset.1974573747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_alert_test.2073486593
Short name T413
Test name
Test status
Simulation time 12692644 ps
CPU time 0.83 seconds
Started Sep 04 10:09:16 AM UTC 24
Finished Sep 04 10:09:18 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073486593 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2073486593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_fifo_full.2668935015
Short name T50
Test name
Test status
Simulation time 32180392219 ps
CPU time 31.85 seconds
Started Sep 04 10:08:31 AM UTC 24
Finished Sep 04 10:09:04 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668935015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2668935015
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.812835101
Short name T117
Test name
Test status
Simulation time 280849061957 ps
CPU time 144.72 seconds
Started Sep 04 10:08:32 AM UTC 24
Finished Sep 04 10:10:59 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812835101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.812835101
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_fifo_reset.3715975108
Short name T178
Test name
Test status
Simulation time 70407544681 ps
CPU time 223.51 seconds
Started Sep 04 10:08:35 AM UTC 24
Finished Sep 04 10:12:22 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715975108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3715975108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_intr.1011077974
Short name T99
Test name
Test status
Simulation time 97122772737 ps
CPU time 100.38 seconds
Started Sep 04 10:08:37 AM UTC 24
Finished Sep 04 10:10:19 AM UTC 24
Peak memory 208976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011077974 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1011077974
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.1179050294
Short name T278
Test name
Test status
Simulation time 62141226253 ps
CPU time 118.2 seconds
Started Sep 04 10:09:04 AM UTC 24
Finished Sep 04 10:11:05 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179050294 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1179050294
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_loopback.2869063553
Short name T412
Test name
Test status
Simulation time 86474396 ps
CPU time 1.04 seconds
Started Sep 04 10:08:59 AM UTC 24
Finished Sep 04 10:09:01 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869063553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2869063553
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_perf.3133847067
Short name T270
Test name
Test status
Simulation time 4391918205 ps
CPU time 295.37 seconds
Started Sep 04 10:09:02 AM UTC 24
Finished Sep 04 10:14:02 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133847067 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3133847067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_rx_oversample.3201948715
Short name T49
Test name
Test status
Simulation time 4992187464 ps
CPU time 13.38 seconds
Started Sep 04 10:08:36 AM UTC 24
Finished Sep 04 10:08:50 AM UTC 24
Peak memory 207760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201948715 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3201948715
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.2560046260
Short name T343
Test name
Test status
Simulation time 5447287974 ps
CPU time 3.17 seconds
Started Sep 04 10:08:52 AM UTC 24
Finished Sep 04 10:08:56 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560046260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2560046260
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_smoke.3856431768
Short name T301
Test name
Test status
Simulation time 892578395 ps
CPU time 4.28 seconds
Started Sep 04 10:08:28 AM UTC 24
Finished Sep 04 10:08:34 AM UTC 24
Peak memory 207972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856431768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3856431768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_stress_all.1474818840
Short name T732
Test name
Test status
Simulation time 39087398941 ps
CPU time 1446.26 seconds
Started Sep 04 10:09:14 AM UTC 24
Finished Sep 04 10:33:35 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474818840 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1474818840
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.2524541315
Short name T281
Test name
Test status
Simulation time 1966483294 ps
CPU time 5.41 seconds
Started Sep 04 10:08:57 AM UTC 24
Finished Sep 04 10:09:04 AM UTC 24
Peak memory 207168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524541315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2524541315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/6.uart_tx_rx.3124630800
Short name T294
Test name
Test status
Simulation time 98084326928 ps
CPU time 50.81 seconds
Started Sep 04 10:08:31 AM UTC 24
Finished Sep 04 10:09:23 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124630800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3124630800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/6.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/60.uart_fifo_reset.4022308891
Short name T920
Test name
Test status
Simulation time 36517663388 ps
CPU time 17.78 seconds
Started Sep 04 10:41:17 AM UTC 24
Finished Sep 04 10:41:36 AM UTC 24
Peak memory 208324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022308891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4022308891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/60.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.2282332556
Short name T924
Test name
Test status
Simulation time 5352997629 ps
CPU time 28.57 seconds
Started Sep 04 10:41:17 AM UTC 24
Finished Sep 04 10:41:47 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2282332556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all
_with_rand_reset.2282332556
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2915081009
Short name T220
Test name
Test status
Simulation time 97631053588 ps
CPU time 43.15 seconds
Started Sep 04 10:41:17 AM UTC 24
Finished Sep 04 10:42:02 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915081009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2915081009
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/61.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.2815224048
Short name T918
Test name
Test status
Simulation time 5173322905 ps
CPU time 12.05 seconds
Started Sep 04 10:41:20 AM UTC 24
Finished Sep 04 10:41:33 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2815224048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all
_with_rand_reset.2815224048
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/62.uart_fifo_reset.1776558592
Short name T956
Test name
Test status
Simulation time 127277767089 ps
CPU time 115.81 seconds
Started Sep 04 10:41:20 AM UTC 24
Finished Sep 04 10:43:18 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776558592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1776558592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/62.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.1094698450
Short name T927
Test name
Test status
Simulation time 12469993633 ps
CPU time 35.24 seconds
Started Sep 04 10:41:21 AM UTC 24
Finished Sep 04 10:41:58 AM UTC 24
Peak memory 223932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1094698450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all
_with_rand_reset.1094698450
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/63.uart_fifo_reset.253302679
Short name T942
Test name
Test status
Simulation time 33505367799 ps
CPU time 72.05 seconds
Started Sep 04 10:41:26 AM UTC 24
Finished Sep 04 10:42:39 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253302679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.253302679
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/63.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.1104210911
Short name T925
Test name
Test status
Simulation time 4586951651 ps
CPU time 19.18 seconds
Started Sep 04 10:41:29 AM UTC 24
Finished Sep 04 10:41:49 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1104210911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all
_with_rand_reset.1104210911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/64.uart_fifo_reset.3813443486
Short name T976
Test name
Test status
Simulation time 97281236607 ps
CPU time 147.25 seconds
Started Sep 04 10:41:34 AM UTC 24
Finished Sep 04 10:44:03 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813443486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3813443486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/64.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.1089994372
Short name T951
Test name
Test status
Simulation time 5775985678 ps
CPU time 84.02 seconds
Started Sep 04 10:41:34 AM UTC 24
Finished Sep 04 10:43:00 AM UTC 24
Peak memory 225476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1089994372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all
_with_rand_reset.1089994372
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/65.uart_fifo_reset.3786944416
Short name T223
Test name
Test status
Simulation time 10977287460 ps
CPU time 29.37 seconds
Started Sep 04 10:41:35 AM UTC 24
Finished Sep 04 10:42:05 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786944416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3786944416
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/65.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.1834104930
Short name T940
Test name
Test status
Simulation time 3359829075 ps
CPU time 52.88 seconds
Started Sep 04 10:41:36 AM UTC 24
Finished Sep 04 10:42:31 AM UTC 24
Peak memory 224004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1834104930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all
_with_rand_reset.1834104930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/66.uart_fifo_reset.2655915983
Short name T208
Test name
Test status
Simulation time 53717752555 ps
CPU time 51.37 seconds
Started Sep 04 10:41:37 AM UTC 24
Finished Sep 04 10:42:30 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655915983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2655915983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/66.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.850926332
Short name T954
Test name
Test status
Simulation time 19431673132 ps
CPU time 94.55 seconds
Started Sep 04 10:41:37 AM UTC 24
Finished Sep 04 10:43:14 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=850926332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all_
with_rand_reset.850926332
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.1872932007
Short name T941
Test name
Test status
Simulation time 2654963534 ps
CPU time 51.18 seconds
Started Sep 04 10:41:39 AM UTC 24
Finished Sep 04 10:42:32 AM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1872932007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all
_with_rand_reset.1872932007
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/68.uart_fifo_reset.705370903
Short name T224
Test name
Test status
Simulation time 46370207858 ps
CPU time 38.42 seconds
Started Sep 04 10:41:41 AM UTC 24
Finished Sep 04 10:42:21 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705370903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.705370903
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/68.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.1282446013
Short name T935
Test name
Test status
Simulation time 1074071521 ps
CPU time 19.99 seconds
Started Sep 04 10:41:47 AM UTC 24
Finished Sep 04 10:42:09 AM UTC 24
Peak memory 224020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1282446013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all
_with_rand_reset.1282446013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/69.uart_fifo_reset.4192122625
Short name T195
Test name
Test status
Simulation time 22039256987 ps
CPU time 27.48 seconds
Started Sep 04 10:41:49 AM UTC 24
Finished Sep 04 10:42:18 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192122625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4192122625
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/69.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.2493930845
Short name T931
Test name
Test status
Simulation time 1117796623 ps
CPU time 10.72 seconds
Started Sep 04 10:41:52 AM UTC 24
Finished Sep 04 10:42:03 AM UTC 24
Peak memory 217504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2493930845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all
_with_rand_reset.2493930845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_alert_test.3374877484
Short name T416
Test name
Test status
Simulation time 34035954 ps
CPU time 0.81 seconds
Started Sep 04 10:10:18 AM UTC 24
Finished Sep 04 10:10:20 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374877484 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3374877484
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_fifo_full.2692277762
Short name T119
Test name
Test status
Simulation time 80358565795 ps
CPU time 30.93 seconds
Started Sep 04 10:09:23 AM UTC 24
Finished Sep 04 10:09:55 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692277762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2692277762
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.3281531708
Short name T122
Test name
Test status
Simulation time 134939823202 ps
CPU time 399.09 seconds
Started Sep 04 10:09:24 AM UTC 24
Finished Sep 04 10:16:08 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281531708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3281531708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_fifo_reset.4161506043
Short name T269
Test name
Test status
Simulation time 22683679344 ps
CPU time 20.67 seconds
Started Sep 04 10:09:27 AM UTC 24
Finished Sep 04 10:09:49 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161506043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4161506043
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_intr.3988404727
Short name T276
Test name
Test status
Simulation time 36170762324 ps
CPU time 27.49 seconds
Started Sep 04 10:09:34 AM UTC 24
Finished Sep 04 10:10:03 AM UTC 24
Peak memory 208864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988404727 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3988404727
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.2746370643
Short name T444
Test name
Test status
Simulation time 174436038073 ps
CPU time 374.1 seconds
Started Sep 04 10:10:04 AM UTC 24
Finished Sep 04 10:16:23 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746370643 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2746370643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_loopback.15742089
Short name T415
Test name
Test status
Simulation time 4784415602 ps
CPU time 6.22 seconds
Started Sep 04 10:09:56 AM UTC 24
Finished Sep 04 10:10:03 AM UTC 24
Peak memory 207088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15742089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.uart_loopback.15742089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_noise_filter.4169035665
Short name T279
Test name
Test status
Simulation time 103022715484 ps
CPU time 325.34 seconds
Started Sep 04 10:09:38 AM UTC 24
Finished Sep 04 10:15:08 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169035665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4169035665
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_perf.943310755
Short name T528
Test name
Test status
Simulation time 15374207659 ps
CPU time 884.71 seconds
Started Sep 04 10:10:04 AM UTC 24
Finished Sep 04 10:24:58 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943310755 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.943310755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_rx_oversample.3169610525
Short name T414
Test name
Test status
Simulation time 2464131918 ps
CPU time 6.95 seconds
Started Sep 04 10:09:29 AM UTC 24
Finished Sep 04 10:09:37 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169610525 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3169610525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.1454418147
Short name T299
Test name
Test status
Simulation time 2511608831 ps
CPU time 6.44 seconds
Started Sep 04 10:09:40 AM UTC 24
Finished Sep 04 10:09:48 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454418147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1454418147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_smoke.2232138971
Short name T51
Test name
Test status
Simulation time 800865971 ps
CPU time 1.48 seconds
Started Sep 04 10:09:19 AM UTC 24
Finished Sep 04 10:09:21 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232138971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2232138971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.1385542585
Short name T38
Test name
Test status
Simulation time 3002408857 ps
CPU time 102.5 seconds
Started Sep 04 10:10:09 AM UTC 24
Finished Sep 04 10:11:53 AM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1385542585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_
with_rand_reset.1385542585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.3682690344
Short name T341
Test name
Test status
Simulation time 12719180672 ps
CPU time 39.4 seconds
Started Sep 04 10:09:49 AM UTC 24
Finished Sep 04 10:10:30 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682690344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3682690344
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/7.uart_tx_rx.3718700056
Short name T313
Test name
Test status
Simulation time 28585850502 ps
CPU time 64.05 seconds
Started Sep 04 10:09:22 AM UTC 24
Finished Sep 04 10:10:27 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718700056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3718700056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/7.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/70.uart_fifo_reset.1784883561
Short name T235
Test name
Test status
Simulation time 97685514349 ps
CPU time 150.53 seconds
Started Sep 04 10:41:59 AM UTC 24
Finished Sep 04 10:44:32 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784883561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1784883561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/70.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.3412228801
Short name T950
Test name
Test status
Simulation time 2063591058 ps
CPU time 57.98 seconds
Started Sep 04 10:41:59 AM UTC 24
Finished Sep 04 10:42:58 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3412228801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all
_with_rand_reset.3412228801
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/71.uart_fifo_reset.2854837817
Short name T217
Test name
Test status
Simulation time 110205717718 ps
CPU time 246.32 seconds
Started Sep 04 10:42:00 AM UTC 24
Finished Sep 04 10:46:09 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854837817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2854837817
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/71.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.721429229
Short name T949
Test name
Test status
Simulation time 11966579979 ps
CPU time 47.73 seconds
Started Sep 04 10:42:03 AM UTC 24
Finished Sep 04 10:42:52 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=721429229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all_
with_rand_reset.721429229
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/72.uart_fifo_reset.2032830713
Short name T1054
Test name
Test status
Simulation time 142997251424 ps
CPU time 283.02 seconds
Started Sep 04 10:42:04 AM UTC 24
Finished Sep 04 10:46:51 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032830713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2032830713
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/72.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.3794734968
Short name T962
Test name
Test status
Simulation time 3367991849 ps
CPU time 82.52 seconds
Started Sep 04 10:42:04 AM UTC 24
Finished Sep 04 10:43:29 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3794734968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all
_with_rand_reset.3794734968
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/73.uart_fifo_reset.1512516229
Short name T947
Test name
Test status
Simulation time 128880597129 ps
CPU time 43.37 seconds
Started Sep 04 10:42:05 AM UTC 24
Finished Sep 04 10:42:51 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512516229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1512516229
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/73.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.3727550859
Short name T943
Test name
Test status
Simulation time 8376012060 ps
CPU time 32.6 seconds
Started Sep 04 10:42:06 AM UTC 24
Finished Sep 04 10:42:41 AM UTC 24
Peak memory 223996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3727550859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all
_with_rand_reset.3727550859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/74.uart_fifo_reset.1121666757
Short name T946
Test name
Test status
Simulation time 30952111478 ps
CPU time 37.84 seconds
Started Sep 04 10:42:08 AM UTC 24
Finished Sep 04 10:42:48 AM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121666757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1121666757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/74.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.339827245
Short name T399
Test name
Test status
Simulation time 12727934750 ps
CPU time 69.35 seconds
Started Sep 04 10:42:09 AM UTC 24
Finished Sep 04 10:43:21 AM UTC 24
Peak memory 219708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=339827245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all_
with_rand_reset.339827245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/75.uart_fifo_reset.2971648672
Short name T197
Test name
Test status
Simulation time 115959476809 ps
CPU time 115.46 seconds
Started Sep 04 10:42:09 AM UTC 24
Finished Sep 04 10:44:08 AM UTC 24
Peak memory 208564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971648672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2971648672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/75.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.1805481708
Short name T939
Test name
Test status
Simulation time 390406193 ps
CPU time 9.49 seconds
Started Sep 04 10:42:20 AM UTC 24
Finished Sep 04 10:42:30 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1805481708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all
_with_rand_reset.1805481708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/76.uart_fifo_reset.3329033723
Short name T188
Test name
Test status
Simulation time 77377715429 ps
CPU time 130.84 seconds
Started Sep 04 10:42:22 AM UTC 24
Finished Sep 04 10:44:35 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329033723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3329033723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/76.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.934909399
Short name T952
Test name
Test status
Simulation time 2973148496 ps
CPU time 36.86 seconds
Started Sep 04 10:42:25 AM UTC 24
Finished Sep 04 10:43:03 AM UTC 24
Peak memory 217816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=934909399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all_
with_rand_reset.934909399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/77.uart_fifo_reset.3007253769
Short name T945
Test name
Test status
Simulation time 42982389112 ps
CPU time 17.56 seconds
Started Sep 04 10:42:28 AM UTC 24
Finished Sep 04 10:42:47 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007253769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3007253769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/77.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.465143921
Short name T966
Test name
Test status
Simulation time 19923801935 ps
CPU time 73 seconds
Started Sep 04 10:42:28 AM UTC 24
Finished Sep 04 10:43:43 AM UTC 24
Peak memory 219840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=465143921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all_
with_rand_reset.465143921
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/78.uart_fifo_reset.269602601
Short name T1089
Test name
Test status
Simulation time 139094966423 ps
CPU time 315.09 seconds
Started Sep 04 10:42:29 AM UTC 24
Finished Sep 04 10:47:48 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269602601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.269602601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/78.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.2570978114
Short name T948
Test name
Test status
Simulation time 4242124495 ps
CPU time 18.86 seconds
Started Sep 04 10:42:31 AM UTC 24
Finished Sep 04 10:42:51 AM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2570978114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all
_with_rand_reset.2570978114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/79.uart_fifo_reset.3547024298
Short name T196
Test name
Test status
Simulation time 41751091111 ps
CPU time 43 seconds
Started Sep 04 10:42:31 AM UTC 24
Finished Sep 04 10:43:15 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547024298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3547024298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/79.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.3792033270
Short name T958
Test name
Test status
Simulation time 56244071604 ps
CPU time 49.52 seconds
Started Sep 04 10:42:31 AM UTC 24
Finished Sep 04 10:43:22 AM UTC 24
Peak memory 224208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3792033270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all
_with_rand_reset.3792033270
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_alert_test.1269202267
Short name T419
Test name
Test status
Simulation time 44643310 ps
CPU time 0.82 seconds
Started Sep 04 10:11:05 AM UTC 24
Finished Sep 04 10:11:07 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269202267 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1269202267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_intr.2405543413
Short name T102
Test name
Test status
Simulation time 33079111558 ps
CPU time 32.3 seconds
Started Sep 04 10:10:32 AM UTC 24
Finished Sep 04 10:11:06 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405543413 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2405543413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.1090741775
Short name T629
Test name
Test status
Simulation time 152843249153 ps
CPU time 1108.18 seconds
Started Sep 04 10:11:04 AM UTC 24
Finished Sep 04 10:29:44 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090741775 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1090741775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_loopback.1962556528
Short name T418
Test name
Test status
Simulation time 4995379090 ps
CPU time 3.77 seconds
Started Sep 04 10:11:00 AM UTC 24
Finished Sep 04 10:11:05 AM UTC 24
Peak memory 208068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962556528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1962556528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_noise_filter.3149241451
Short name T324
Test name
Test status
Simulation time 154691045721 ps
CPU time 102.59 seconds
Started Sep 04 10:10:46 AM UTC 24
Finished Sep 04 10:12:30 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149241451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3149241451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_perf.1546186847
Short name T320
Test name
Test status
Simulation time 9032416003 ps
CPU time 290.32 seconds
Started Sep 04 10:11:01 AM UTC 24
Finished Sep 04 10:15:55 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546186847 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1546186847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_rx_oversample.316848909
Short name T417
Test name
Test status
Simulation time 2536626066 ps
CPU time 18.53 seconds
Started Sep 04 10:10:31 AM UTC 24
Finished Sep 04 10:10:51 AM UTC 24
Peak memory 207216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316848909 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.316848909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.3843009411
Short name T327
Test name
Test status
Simulation time 90393049615 ps
CPU time 236.03 seconds
Started Sep 04 10:10:56 AM UTC 24
Finished Sep 04 10:14:55 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843009411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3843009411
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.3247730016
Short name T326
Test name
Test status
Simulation time 37838744071 ps
CPU time 20.16 seconds
Started Sep 04 10:10:53 AM UTC 24
Finished Sep 04 10:11:14 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247730016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3247730016
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_smoke.1948244963
Short name T367
Test name
Test status
Simulation time 496744530 ps
CPU time 1.94 seconds
Started Sep 04 10:10:19 AM UTC 24
Finished Sep 04 10:10:22 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948244963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1948244963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1768336341
Short name T37
Test name
Test status
Simulation time 5271916047 ps
CPU time 39.61 seconds
Started Sep 04 10:11:04 AM UTC 24
Finished Sep 04 10:11:45 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1768336341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_
with_rand_reset.1768336341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2494079338
Short name T330
Test name
Test status
Simulation time 937942165 ps
CPU time 5.26 seconds
Started Sep 04 10:10:58 AM UTC 24
Finished Sep 04 10:11:04 AM UTC 24
Peak memory 208092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494079338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2494079338
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/8.uart_tx_rx.3740284197
Short name T285
Test name
Test status
Simulation time 27319506455 ps
CPU time 77.09 seconds
Started Sep 04 10:10:20 AM UTC 24
Finished Sep 04 10:11:39 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740284197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3740284197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/8.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/80.uart_fifo_reset.4224493326
Short name T974
Test name
Test status
Simulation time 56403356874 ps
CPU time 83.93 seconds
Started Sep 04 10:42:33 AM UTC 24
Finished Sep 04 10:43:59 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224493326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4224493326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/80.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.626218062
Short name T971
Test name
Test status
Simulation time 5933731074 ps
CPU time 71.14 seconds
Started Sep 04 10:42:40 AM UTC 24
Finished Sep 04 10:43:53 AM UTC 24
Peak memory 221692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=626218062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all_
with_rand_reset.626218062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/81.uart_fifo_reset.2622016255
Short name T996
Test name
Test status
Simulation time 74483190112 ps
CPU time 127.18 seconds
Started Sep 04 10:42:41 AM UTC 24
Finished Sep 04 10:44:51 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622016255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2622016255
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/81.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/82.uart_fifo_reset.1150535407
Short name T980
Test name
Test status
Simulation time 114875339671 ps
CPU time 78.64 seconds
Started Sep 04 10:42:48 AM UTC 24
Finished Sep 04 10:44:08 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150535407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1150535407
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/82.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.1281256320
Short name T955
Test name
Test status
Simulation time 1375623397 ps
CPU time 26.74 seconds
Started Sep 04 10:42:49 AM UTC 24
Finished Sep 04 10:43:17 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1281256320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all
_with_rand_reset.1281256320
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1099967524
Short name T972
Test name
Test status
Simulation time 88032558315 ps
CPU time 64.97 seconds
Started Sep 04 10:42:52 AM UTC 24
Finished Sep 04 10:43:58 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099967524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1099967524
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/83.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.358673570
Short name T953
Test name
Test status
Simulation time 1116826706 ps
CPU time 15.27 seconds
Started Sep 04 10:42:52 AM UTC 24
Finished Sep 04 10:43:08 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=358673570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all_
with_rand_reset.358673570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.546306929
Short name T960
Test name
Test status
Simulation time 2466631120 ps
CPU time 24.41 seconds
Started Sep 04 10:42:59 AM UTC 24
Finished Sep 04 10:43:25 AM UTC 24
Peak memory 217804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=546306929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all_
with_rand_reset.546306929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/85.uart_fifo_reset.2000640753
Short name T1025
Test name
Test status
Simulation time 90140620737 ps
CPU time 172.71 seconds
Started Sep 04 10:42:59 AM UTC 24
Finished Sep 04 10:45:54 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000640753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2000640753
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/85.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.501111225
Short name T957
Test name
Test status
Simulation time 1010292750 ps
CPU time 19.32 seconds
Started Sep 04 10:43:00 AM UTC 24
Finished Sep 04 10:43:21 AM UTC 24
Peak memory 217512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=501111225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all_
with_rand_reset.501111225
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/86.uart_fifo_reset.380541739
Short name T221
Test name
Test status
Simulation time 37593329869 ps
CPU time 22.01 seconds
Started Sep 04 10:43:04 AM UTC 24
Finished Sep 04 10:43:27 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380541739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.380541739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/86.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/87.uart_fifo_reset.3585684640
Short name T969
Test name
Test status
Simulation time 45537534006 ps
CPU time 30.13 seconds
Started Sep 04 10:43:14 AM UTC 24
Finished Sep 04 10:43:46 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585684640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3585684640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/87.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.1185491443
Short name T965
Test name
Test status
Simulation time 10442237020 ps
CPU time 27.2 seconds
Started Sep 04 10:43:14 AM UTC 24
Finished Sep 04 10:43:43 AM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1185491443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all
_with_rand_reset.1185491443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/88.uart_fifo_reset.2081749993
Short name T215
Test name
Test status
Simulation time 9376383312 ps
CPU time 20.38 seconds
Started Sep 04 10:43:16 AM UTC 24
Finished Sep 04 10:43:38 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081749993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2081749993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/88.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3289410845
Short name T978
Test name
Test status
Simulation time 11149850889 ps
CPU time 45.11 seconds
Started Sep 04 10:43:18 AM UTC 24
Finished Sep 04 10:44:04 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3289410845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all
_with_rand_reset.3289410845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2020806013
Short name T963
Test name
Test status
Simulation time 21417571986 ps
CPU time 16.72 seconds
Started Sep 04 10:43:20 AM UTC 24
Finished Sep 04 10:43:38 AM UTC 24
Peak memory 208548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020806013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2020806013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/89.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.203795457
Short name T988
Test name
Test status
Simulation time 16252070974 ps
CPU time 68.6 seconds
Started Sep 04 10:43:22 AM UTC 24
Finished Sep 04 10:44:32 AM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=203795457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all_
with_rand_reset.203795457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_alert_test.2001704301
Short name T420
Test name
Test status
Simulation time 93238678 ps
CPU time 0.81 seconds
Started Sep 04 10:11:46 AM UTC 24
Finished Sep 04 10:11:47 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001704301 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2001704301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_fifo_full.1948232126
Short name T124
Test name
Test status
Simulation time 32871327398 ps
CPU time 16.42 seconds
Started Sep 04 10:11:07 AM UTC 24
Finished Sep 04 10:11:25 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948232126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1948232126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.583741955
Short name T265
Test name
Test status
Simulation time 7952283710 ps
CPU time 21.39 seconds
Started Sep 04 10:11:07 AM UTC 24
Finished Sep 04 10:11:30 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583741955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.583741955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_fifo_reset.108771462
Short name T186
Test name
Test status
Simulation time 49229689947 ps
CPU time 88.42 seconds
Started Sep 04 10:11:15 AM UTC 24
Finished Sep 04 10:12:45 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108771462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.108771462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_intr.2377720832
Short name T322
Test name
Test status
Simulation time 11061140498 ps
CPU time 5.96 seconds
Started Sep 04 10:11:26 AM UTC 24
Finished Sep 04 10:11:33 AM UTC 24
Peak memory 208440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377720832 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2377720832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.1449612088
Short name T290
Test name
Test status
Simulation time 183763725944 ps
CPU time 170.78 seconds
Started Sep 04 10:11:42 AM UTC 24
Finished Sep 04 10:14:36 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449612088 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1449612088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_loopback.3258326795
Short name T421
Test name
Test status
Simulation time 5216606899 ps
CPU time 13.69 seconds
Started Sep 04 10:11:40 AM UTC 24
Finished Sep 04 10:11:55 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258326795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3258326795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_noise_filter.2460820466
Short name T296
Test name
Test status
Simulation time 23927276960 ps
CPU time 23.85 seconds
Started Sep 04 10:11:26 AM UTC 24
Finished Sep 04 10:11:51 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460820466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2460820466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_perf.1962464289
Short name T500
Test name
Test status
Simulation time 18039967131 ps
CPU time 709.89 seconds
Started Sep 04 10:11:40 AM UTC 24
Finished Sep 04 10:23:39 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962464289 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1962464289
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_rx_oversample.74171093
Short name T425
Test name
Test status
Simulation time 7033044296 ps
CPU time 76.07 seconds
Started Sep 04 10:11:21 AM UTC 24
Finished Sep 04 10:12:38 AM UTC 24
Peak memory 207496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74171093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.74171093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.591118647
Short name T165
Test name
Test status
Simulation time 66133390135 ps
CPU time 54.39 seconds
Started Sep 04 10:11:33 AM UTC 24
Finished Sep 04 10:12:29 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591118647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.591118647
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.556584542
Short name T282
Test name
Test status
Simulation time 6614215169 ps
CPU time 7.28 seconds
Started Sep 04 10:11:31 AM UTC 24
Finished Sep 04 10:11:39 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556584542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.556584542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_smoke.1812162699
Short name T337
Test name
Test status
Simulation time 5529816868 ps
CPU time 13.02 seconds
Started Sep 04 10:11:05 AM UTC 24
Finished Sep 04 10:11:19 AM UTC 24
Peak memory 208488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812162699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1812162699
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_stress_all.4066070551
Short name T145
Test name
Test status
Simulation time 265373306529 ps
CPU time 510.04 seconds
Started Sep 04 10:11:43 AM UTC 24
Finished Sep 04 10:20:20 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066070551 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4066070551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.3545155301
Short name T360
Test name
Test status
Simulation time 1002426554 ps
CPU time 5.57 seconds
Started Sep 04 10:11:35 AM UTC 24
Finished Sep 04 10:11:42 AM UTC 24
Peak memory 207168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545155301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3545155301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/9.uart_tx_rx.416470430
Short name T304
Test name
Test status
Simulation time 18107010622 ps
CPU time 16.45 seconds
Started Sep 04 10:11:07 AM UTC 24
Finished Sep 04 10:11:25 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416470430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.416470430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/9.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/90.uart_fifo_reset.727679437
Short name T1182
Test name
Test status
Simulation time 105212325078 ps
CPU time 772.68 seconds
Started Sep 04 10:43:22 AM UTC 24
Finished Sep 04 10:56:23 AM UTC 24
Peak memory 212220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727679437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.727679437
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/90.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.369028005
Short name T986
Test name
Test status
Simulation time 4914591240 ps
CPU time 62.11 seconds
Started Sep 04 10:43:23 AM UTC 24
Finished Sep 04 10:44:27 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=369028005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all_
with_rand_reset.369028005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/91.uart_fifo_reset.501812302
Short name T216
Test name
Test status
Simulation time 62895048805 ps
CPU time 70.4 seconds
Started Sep 04 10:43:24 AM UTC 24
Finished Sep 04 10:44:36 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501812302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.501812302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/91.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.2485780951
Short name T981
Test name
Test status
Simulation time 10469095401 ps
CPU time 49.6 seconds
Started Sep 04 10:43:25 AM UTC 24
Finished Sep 04 10:44:16 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2485780951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all
_with_rand_reset.2485780951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/92.uart_fifo_reset.2786240439
Short name T402
Test name
Test status
Simulation time 13286835541 ps
CPU time 28.02 seconds
Started Sep 04 10:43:28 AM UTC 24
Finished Sep 04 10:43:57 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786240439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2786240439
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/92.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.1299471392
Short name T979
Test name
Test status
Simulation time 6984524986 ps
CPU time 36.35 seconds
Started Sep 04 10:43:28 AM UTC 24
Finished Sep 04 10:44:06 AM UTC 24
Peak memory 217524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1299471392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all
_with_rand_reset.1299471392
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/93.uart_fifo_reset.1555114928
Short name T1003
Test name
Test status
Simulation time 112134779194 ps
CPU time 96.47 seconds
Started Sep 04 10:43:29 AM UTC 24
Finished Sep 04 10:45:08 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555114928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1555114928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/93.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.3889413770
Short name T970
Test name
Test status
Simulation time 4535725294 ps
CPU time 22.22 seconds
Started Sep 04 10:43:29 AM UTC 24
Finished Sep 04 10:43:53 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3889413770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all
_with_rand_reset.3889413770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/94.uart_fifo_reset.522873194
Short name T973
Test name
Test status
Simulation time 16632647728 ps
CPU time 18.61 seconds
Started Sep 04 10:43:38 AM UTC 24
Finished Sep 04 10:43:58 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522873194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.522873194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/94.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.2541783870
Short name T985
Test name
Test status
Simulation time 7087906267 ps
CPU time 46.48 seconds
Started Sep 04 10:43:38 AM UTC 24
Finished Sep 04 10:44:26 AM UTC 24
Peak memory 217804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2541783870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all
_with_rand_reset.2541783870
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/95.uart_fifo_reset.4270071825
Short name T226
Test name
Test status
Simulation time 39993235379 ps
CPU time 41.97 seconds
Started Sep 04 10:43:40 AM UTC 24
Finished Sep 04 10:44:23 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270071825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.4270071825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/95.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.613948930
Short name T977
Test name
Test status
Simulation time 9717812985 ps
CPU time 21.26 seconds
Started Sep 04 10:43:41 AM UTC 24
Finished Sep 04 10:44:04 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=613948930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all_
with_rand_reset.613948930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/96.uart_fifo_reset.3804366689
Short name T1031
Test name
Test status
Simulation time 79508869163 ps
CPU time 144.9 seconds
Started Sep 04 10:43:44 AM UTC 24
Finished Sep 04 10:46:11 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804366689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3804366689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/96.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.2848090184
Short name T249
Test name
Test status
Simulation time 10675937092 ps
CPU time 28.86 seconds
Started Sep 04 10:43:44 AM UTC 24
Finished Sep 04 10:44:14 AM UTC 24
Peak memory 223932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2848090184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all
_with_rand_reset.2848090184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/97.uart_fifo_reset.2574526847
Short name T1018
Test name
Test status
Simulation time 138893351980 ps
CPU time 115.64 seconds
Started Sep 04 10:43:45 AM UTC 24
Finished Sep 04 10:45:42 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574526847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2574526847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/97.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.1063516555
Short name T1000
Test name
Test status
Simulation time 5965129267 ps
CPU time 65.45 seconds
Started Sep 04 10:43:46 AM UTC 24
Finished Sep 04 10:44:53 AM UTC 24
Peak memory 219956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1063516555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all
_with_rand_reset.1063516555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2640116169
Short name T989
Test name
Test status
Simulation time 28857087450 ps
CPU time 48.46 seconds
Started Sep 04 10:43:46 AM UTC 24
Finished Sep 04 10:44:36 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640116169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2640116169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/98.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.405358849
Short name T1024
Test name
Test status
Simulation time 5906325290 ps
CPU time 121.22 seconds
Started Sep 04 10:43:47 AM UTC 24
Finished Sep 04 10:45:51 AM UTC 24
Peak memory 217796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=405358849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all_
with_rand_reset.405358849
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/99.uart_fifo_reset.1383533170
Short name T984
Test name
Test status
Simulation time 157949501623 ps
CPU time 34.96 seconds
Started Sep 04 10:43:49 AM UTC 24
Finished Sep 04 10:44:25 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383533170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1383533170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/99.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.278316925
Short name T982
Test name
Test status
Simulation time 1348261125 ps
CPU time 21.25 seconds
Started Sep 04 10:43:54 AM UTC 24
Finished Sep 04 10:44:17 AM UTC 24
Peak memory 217872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=278316925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all_
with_rand_reset.278316925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest
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