Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67490560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15439696

1

T1

12

T2

11

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	81623555	1			T1	453		T2	14013		T3	32
values[0x0]	632552	1			T1	7		T2	8		T3	8
values[0x1]	674149	1			T1	6		T2	6		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46806201	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36124055

1

T1

165

T2

7069

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	332342	1			T1	5		T2	46		T3	2
valid_sources[0x01]	296831	1			T2	43		T4	13		T7	2
valid_sources[0x02]	324515	1			T1	2		T2	43		T4	11
valid_sources[0x03]	290413	1			T2	50		T4	14		T7	2
valid_sources[0x04]	338647	1			T1	2		T2	53		T4	12
valid_sources[0x05]	301360	1			T1	1		T2	31		T4	9
valid_sources[0x06]	322991	1			T2	64		T3	1		T4	5
valid_sources[0x07]	306305	1			T2	45		T4	12		T7	7
valid_sources[0x08]	290913	1			T2	68		T4	17		T7	2
valid_sources[0x09]	318962	1			T2	47		T4	12		T7	2
valid_sources[0x0a]	307072	1			T1	4		T2	47		T4	13
valid_sources[0x0b]	293501	1			T1	2		T2	43		T4	9
valid_sources[0x0c]	356641	1			T1	3		T2	57		T4	10
valid_sources[0x0d]	312942	1			T1	5		T2	65		T4	13
valid_sources[0x0e]	330204	1			T2	48		T4	9		T7	5
valid_sources[0x0f]	283732	1			T1	2		T2	53		T4	8
valid_sources[0x10]	330612	1			T1	5		T2	73		T4	14
valid_sources[0x11]	315170	1			T2	49		T4	11		T8	13
valid_sources[0x12]	302988	1			T2	46		T4	6		T7	8
valid_sources[0x13]	348055	1			T2	75		T3	1		T4	15
valid_sources[0x14]	294404	1			T2	42		T4	15		T7	1
valid_sources[0x15]	309590	1			T1	8		T2	75		T4	9
valid_sources[0x16]	316619	1			T1	13		T2	52		T4	15
valid_sources[0x17]	309586	1			T1	3		T2	41		T4	15
valid_sources[0x18]	504960	1			T1	1		T2	96		T4	16
valid_sources[0x19]	326045	1			T1	3		T2	50		T4	9
valid_sources[0x1a]	304730	1			T1	5		T2	60		T4	12
valid_sources[0x1b]	389240	1			T1	3		T2	34		T4	5
valid_sources[0x1c]	307741	1			T1	3		T2	61		T4	14
valid_sources[0x1d]	286979	1			T1	1		T2	52		T4	4
valid_sources[0x1e]	307021	1			T2	59		T4	13		T7	2
valid_sources[0x1f]	299964	1			T1	3		T2	45		T4	21
valid_sources[0x20]	293661	1			T1	4		T2	77		T4	12
valid_sources[0x21]	316108	1			T1	2		T2	50		T4	11
valid_sources[0x22]	285768	1			T1	11		T2	43		T4	11
valid_sources[0x23]	319728	1			T2	58		T4	11		T8	13
valid_sources[0x24]	313997	1			T2	53		T4	12		T8	10
valid_sources[0x25]	343598	1			T1	4		T2	49		T4	18
valid_sources[0x26]	503879	1			T1	1		T2	77		T3	1
valid_sources[0x27]	302936	1			T2	49		T4	16		T7	8
valid_sources[0x28]	304339	1			T1	4		T2	47		T4	6
valid_sources[0x29]	286006	1			T1	6		T2	73		T4	5
valid_sources[0x2a]	343307	1			T1	1		T2	57		T4	13
valid_sources[0x2b]	296149	1			T2	60		T3	1		T4	16
valid_sources[0x2c]	375928	1			T2	72		T4	27		T8	4
valid_sources[0x2d]	316082	1			T2	85		T4	8		T7	10
valid_sources[0x2e]	296280	1			T2	56		T3	1		T4	12
valid_sources[0x2f]	306095	1			T2	33		T4	13		T7	3
valid_sources[0x30]	307841	1			T1	1		T2	30		T4	17
valid_sources[0x31]	310841	1			T1	2		T2	55		T4	12
valid_sources[0x32]	324715	1			T2	48		T4	19		T7	11
valid_sources[0x33]	306557	1			T2	38		T4	9		T7	2
valid_sources[0x34]	342536	1			T1	1		T2	60		T4	8
valid_sources[0x35]	304581	1			T2	71		T4	8		T7	3
valid_sources[0x36]	324997	1			T1	1		T2	69		T4	14
valid_sources[0x37]	300684	1			T2	67		T3	1		T4	15
valid_sources[0x38]	335052	1			T1	2		T2	57		T4	11
valid_sources[0x39]	358944	1			T1	4		T2	50		T4	15
valid_sources[0x3a]	319242	1			T1	1		T2	55		T4	16
valid_sources[0x3b]	311164	1			T2	55		T3	1		T4	14
valid_sources[0x3c]	322853	1			T2	41		T4	8		T7	9
valid_sources[0x3d]	317217	1			T2	77		T4	12		T7	10
valid_sources[0x3e]	304940	1			T2	41		T3	1		T4	15
valid_sources[0x3f]	351139	1			T1	3		T2	47		T4	16
valid_sources[0x40]	349681	1			T1	2		T2	44		T4	12
valid_sources[0x41]	351474	1			T1	3		T2	50		T4	8
valid_sources[0x42]	454253	1			T1	2		T2	37		T4	7
valid_sources[0x43]	348813	1			T1	1		T2	51		T4	6
valid_sources[0x44]	327621	1			T2	50		T4	19		T7	7
valid_sources[0x45]	326358	1			T2	49		T4	10		T7	2
valid_sources[0x46]	314644	1			T1	1		T2	51		T4	11
valid_sources[0x47]	352152	1			T1	1		T2	73		T4	12
valid_sources[0x48]	296513	1			T1	1		T2	58		T4	14
valid_sources[0x49]	320614	1			T1	5		T2	62		T4	15
valid_sources[0x4a]	301357	1			T1	1		T2	55		T3	1
valid_sources[0x4b]	334520	1			T2	63		T4	11		T7	9
valid_sources[0x4c]	310229	1			T2	48		T4	12		T8	6
valid_sources[0x4d]	289920	1			T1	6		T2	64		T4	11
valid_sources[0x4e]	309023	1			T2	48		T4	10		T6	1
valid_sources[0x4f]	319830	1			T2	62		T4	13		T7	5
valid_sources[0x50]	315395	1			T1	1		T2	50		T3	1
valid_sources[0x51]	307541	1			T1	1		T2	62		T3	2
valid_sources[0x52]	310377	1			T1	2		T2	50		T4	13
valid_sources[0x53]	305788	1			T1	4		T2	56		T4	10
valid_sources[0x54]	354111	1			T1	1		T2	56		T4	13
valid_sources[0x55]	297777	1			T2	52		T3	1		T4	12
valid_sources[0x56]	305783	1			T1	3		T2	66		T4	10
valid_sources[0x57]	296977	1			T1	4		T2	63		T4	9
valid_sources[0x58]	329892	1			T1	1		T2	45		T4	11
valid_sources[0x59]	322384	1			T2	63		T4	11		T7	15
valid_sources[0x5a]	304213	1			T1	3		T2	47		T4	13
valid_sources[0x5b]	330611	1			T2	65		T4	9		T7	7
valid_sources[0x5c]	311819	1			T1	1		T2	53		T4	13
valid_sources[0x5d]	309738	1			T2	60		T4	13		T7	2
valid_sources[0x5e]	281929	1			T2	56		T4	7		T7	2
valid_sources[0x5f]	412935	1			T1	1		T2	67		T4	8
valid_sources[0x60]	357096	1			T2	65		T3	1		T4	15
valid_sources[0x61]	302194	1			T1	8		T2	50		T4	8
valid_sources[0x62]	337772	1			T1	3		T2	44		T4	15
valid_sources[0x63]	315513	1			T2	64		T3	1		T4	15
valid_sources[0x64]	341941	1			T1	1		T2	56		T3	1
valid_sources[0x65]	310438	1			T2	43		T4	17		T7	7
valid_sources[0x66]	335491	1			T1	9		T2	71		T4	21
valid_sources[0x67]	296782	1			T2	72		T4	11		T7	1
valid_sources[0x68]	340918	1			T1	1		T2	66		T4	15
valid_sources[0x69]	322752	1			T1	2		T2	65		T3	1
valid_sources[0x6a]	292881	1			T1	1		T2	37		T4	13
valid_sources[0x6b]	292073	1			T2	58		T4	14		T7	11
valid_sources[0x6c]	315417	1			T2	35		T4	12		T7	2
valid_sources[0x6d]	414096	1			T2	35		T4	17		T7	5
valid_sources[0x6e]	348084	1			T2	56		T4	8		T7	6
valid_sources[0x6f]	305667	1			T1	1		T2	58		T4	12
valid_sources[0x70]	282775	1			T1	5		T2	52		T4	12
valid_sources[0x71]	300855	1			T1	10		T2	44		T4	14
valid_sources[0x72]	366044	1			T1	11		T2	68		T3	1
valid_sources[0x73]	291801	1			T1	1		T2	55		T3	1
valid_sources[0x74]	314366	1			T1	3		T2	54		T4	12
valid_sources[0x75]	302099	1			T2	72		T4	10		T7	3
valid_sources[0x76]	322306	1			T1	4		T2	64		T4	18
valid_sources[0x77]	320743	1			T2	61		T4	17		T7	8
valid_sources[0x78]	305867	1			T1	5		T2	62		T4	11
valid_sources[0x79]	318622	1			T2	41		T4	14		T8	7
valid_sources[0x7a]	293987	1			T1	3		T2	61		T4	14
valid_sources[0x7b]	348536	1			T1	1		T2	60		T4	12
valid_sources[0x7c]	301033	1			T2	50		T4	11		T8	12
valid_sources[0x7d]	311699	1			T2	62		T4	14		T7	3
valid_sources[0x7e]	313014	1			T1	4		T2	57		T4	6
valid_sources[0x7f]	375887	1			T1	2		T2	53		T4	15
valid_sources[0x80]	308419	1			T2	47		T4	14		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14600492

1

T1

8

T3

7

T4

5

values[0x0]

all_enables

biggest_size

445147

1

T1

2

T2

8

T3

7

values[0x1]

all_enables

biggest_size

394057

1

T1

2

T2

3

T3

2